1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "new_dynarec_config.h"
24 #include "linkage_offsets.h"
28 #define dynarec_local ESYM(dynarec_local)
29 #define add_jump_out ESYM(add_jump_out)
30 #define new_recompile_block ESYM(new_recompile_block)
31 #define ndrc_try_restore_block ESYM(ndrc_try_restore_block)
32 #define get_addr ESYM(get_addr)
33 #define get_addr_ht ESYM(get_addr_ht)
34 #define gen_interupt ESYM(gen_interupt)
35 #define invalidate_addr ESYM(invalidate_addr)
36 #define gteCheckStallRaw ESYM(gteCheckStallRaw)
37 #define psxException ESYM(psxException)
43 .type dynarec_local, %object
44 .size dynarec_local, LO_dynarec_local_size
46 .space LO_dynarec_local_size
48 #define DRC_VAR_(name, vname, size_) \
49 vname = dynarec_local + LO_##name; \
51 .type vname, %object; \
54 #define DRC_VAR(name, size_) \
55 DRC_VAR_(name, ESYM(name), size_)
57 DRC_VAR(next_interupt, 4)
58 DRC_VAR(cycle_count, 4)
59 DRC_VAR(last_count, 4)
60 DRC_VAR(pending_exception, 4)
62 DRC_VAR(branch_target, 4)
65 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
71 DRC_VAR(reg_cop0, 128)
72 DRC_VAR(reg_cop2d, 128)
73 DRC_VAR(reg_cop2c, 128)
77 @DRC_VAR(interrupt, 4)
78 @DRC_VAR(intCycle, 256)
81 DRC_VAR(inv_code_start, 4)
82 DRC_VAR(inv_code_end, 4)
86 DRC_VAR(zeromem_ptr, 4)
88 DRC_VAR(scratch_buf_ptr, 4)
89 DRC_VAR(ram_offset, 4)
93 #ifdef TEXRELS_FORBIDDEN
99 .word ESYM(hash_table)
114 .macro load_varadr reg var
115 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
116 movw \reg, #:lower16:(\var-(1678f+8))
117 movt \reg, #:upper16:(\var-(1678f+8))
120 #elif defined(HAVE_ARMV7) && !defined(__PIC__)
121 movw \reg, #:lower16:\var
122 movt \reg, #:upper16:\var
128 .macro load_varadr_ext reg var
129 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
130 movw \reg, #:lower16:(ptr_\var-(1678f+8))
131 movt \reg, #:upper16:(ptr_\var-(1678f+8))
135 load_varadr \reg \var
139 .macro mov_16 reg imm
143 mov \reg, #(\imm & 0x00ff)
144 orr \reg, #(\imm & 0xff00)
148 .macro mov_24 reg imm
150 movw \reg, #(\imm & 0xffff)
151 movt \reg, #(\imm >> 16)
153 mov \reg, #(\imm & 0x0000ff)
154 orr \reg, #(\imm & 0x00ff00)
155 orr \reg, #(\imm & 0xff0000)
159 /* r4 = virtual target address */
160 /* r5 = instruction to patch */
161 .macro dyna_linker_main
162 #ifndef NO_WRITE_EXEC
163 load_varadr_ext r3, jump_in
176 ldr r1, [r3, r2, lsl #2]
178 add r6, r5, r12, asr #6 /* old target */
184 ldr r3, [r1] /* ll_entry .vaddr */
185 ldrd r0, r1, [r0, #8] /* ll_entry .addr, .next */
189 moveq pc, r0 /* Stale i-cache */
191 b 1b /* jump_in may have dupes, continue search */
194 beq 3f /* r4 not in jump_in */
200 and r1, r7, #0xff000000
203 add r1, r1, r2, lsr #8
208 bl ndrc_try_restore_block
212 /* XXX: should be able to do better than this... */
220 FUNCTION(dyna_linker):
221 /* r0 = virtual target address */
222 /* r1 = instruction to patch */
229 bl new_recompile_block
236 mov r2, #(4<<2) /* Address error (fetch) */
237 .size dyna_linker, .-dyna_linker
239 FUNCTION(exec_pagefault):
240 /* r0 = instruction pointer */
241 /* r1 = fault address */
243 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
244 str r0, [fp, #LO_reg_cop0+56] /* EPC */
246 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
247 str r3, [fp, #LO_reg_cop0+48] /* Status */
248 str r2, [fp, #LO_reg_cop0+52] /* Cause */
253 .size exec_pagefault, .-exec_pagefault
255 /* Special dynamic linker for the case where a page fault
256 may occur in a branch delay slot */
257 FUNCTION(dyna_linker_ds):
258 /* r0 = virtual target address */
259 /* r1 = instruction to patch */
267 bl new_recompile_block
274 mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
277 .size dyna_linker_ds, .-dyna_linker_ds
281 FUNCTION(jump_vaddr_r0):
282 eor r2, r0, r0, lsl #16
284 .size jump_vaddr_r0, .-jump_vaddr_r0
285 FUNCTION(jump_vaddr_r1):
286 eor r2, r1, r1, lsl #16
289 .size jump_vaddr_r1, .-jump_vaddr_r1
290 FUNCTION(jump_vaddr_r2):
292 eor r2, r2, r2, lsl #16
294 .size jump_vaddr_r2, .-jump_vaddr_r2
295 FUNCTION(jump_vaddr_r3):
296 eor r2, r3, r3, lsl #16
299 .size jump_vaddr_r3, .-jump_vaddr_r3
300 FUNCTION(jump_vaddr_r4):
301 eor r2, r4, r4, lsl #16
304 .size jump_vaddr_r4, .-jump_vaddr_r4
305 FUNCTION(jump_vaddr_r5):
306 eor r2, r5, r5, lsl #16
309 .size jump_vaddr_r5, .-jump_vaddr_r5
310 FUNCTION(jump_vaddr_r6):
311 eor r2, r6, r6, lsl #16
314 .size jump_vaddr_r6, .-jump_vaddr_r6
315 FUNCTION(jump_vaddr_r8):
316 eor r2, r8, r8, lsl #16
319 .size jump_vaddr_r8, .-jump_vaddr_r8
320 FUNCTION(jump_vaddr_r9):
321 eor r2, r9, r9, lsl #16
324 .size jump_vaddr_r9, .-jump_vaddr_r9
325 FUNCTION(jump_vaddr_r10):
326 eor r2, r10, r10, lsl #16
329 .size jump_vaddr_r10, .-jump_vaddr_r10
330 FUNCTION(jump_vaddr_r12):
331 eor r2, r12, r12, lsl #16
334 .size jump_vaddr_r12, .-jump_vaddr_r12
335 FUNCTION(jump_vaddr_r7):
336 eor r2, r7, r7, lsl #16
338 .size jump_vaddr_r7, .-jump_vaddr_r7
339 FUNCTION(jump_vaddr):
340 load_varadr_ext r1, hash_table
342 and r2, r3, r2, lsr #12
349 str r10, [fp, #LO_cycle_count]
351 ldr r10, [fp, #LO_cycle_count]
353 .size jump_vaddr, .-jump_vaddr
357 FUNCTION(verify_code_ds):
358 str r8, [fp, #LO_branch_target] @ preserve HOST_BTREG?
359 FUNCTION(verify_code):
387 ldr r8, [fp, #LO_branch_target]
392 .size verify_code, .-verify_code
393 .size verify_code_ds, .-verify_code_ds
396 FUNCTION(cc_interrupt):
397 ldr r0, [fp, #LO_last_count]
400 str r1, [fp, #LO_pending_exception]
401 str r10, [fp, #LO_cycle] /* PCSX cycles */
402 @@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */
407 ldr r10, [fp, #LO_cycle]
408 ldr r0, [fp, #LO_next_interupt]
409 ldr r1, [fp, #LO_pending_exception]
410 ldr r2, [fp, #LO_stop]
411 str r0, [fp, #LO_last_count]
414 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
417 ldr r0, [fp, #LO_pcaddr]
420 .size cc_interrupt, .-cc_interrupt
423 FUNCTION(fp_exception):
426 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
428 str r0, [fp, #LO_reg_cop0+56] /* EPC */
431 str r1, [fp, #LO_reg_cop0+48] /* Status */
432 str r2, [fp, #LO_reg_cop0+52] /* Cause */
436 .size fp_exception, .-fp_exception
438 FUNCTION(fp_exception_ds):
439 mov r2, #0x90000000 /* Set high bit if delay slot */
441 .size fp_exception_ds, .-fp_exception_ds
444 FUNCTION(jump_break_ds):
448 FUNCTION(jump_break):
452 FUNCTION(jump_syscall_ds):
456 FUNCTION(jump_syscall):
461 ldr r3, [fp, #LO_last_count]
462 str r2, [fp, #LO_pcaddr]
464 str r10, [fp, #LO_cycle] /* PCSX cycles */
467 /* note: psxException might do recursive recompiler call from it's HLE code,
468 * so be ready for this */
469 FUNCTION(jump_to_new_pc):
470 ldr r1, [fp, #LO_next_interupt]
471 ldr r10, [fp, #LO_cycle]
472 ldr r0, [fp, #LO_pcaddr]
474 str r1, [fp, #LO_last_count]
477 .size jump_to_new_pc, .-jump_to_new_pc
480 FUNCTION(new_dyna_leave):
481 ldr r0, [fp, #LO_last_count]
484 str r10, [fp, #LO_cycle]
485 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
486 .size new_dyna_leave, .-new_dyna_leave
489 FUNCTION(invalidate_addr_r0):
490 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
491 b invalidate_addr_call
492 .size invalidate_addr_r0, .-invalidate_addr_r0
494 FUNCTION(invalidate_addr_r1):
495 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
497 b invalidate_addr_call
498 .size invalidate_addr_r1, .-invalidate_addr_r1
500 FUNCTION(invalidate_addr_r2):
501 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
503 b invalidate_addr_call
504 .size invalidate_addr_r2, .-invalidate_addr_r2
506 FUNCTION(invalidate_addr_r3):
507 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
509 b invalidate_addr_call
510 .size invalidate_addr_r3, .-invalidate_addr_r3
512 FUNCTION(invalidate_addr_r4):
513 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
515 b invalidate_addr_call
516 .size invalidate_addr_r4, .-invalidate_addr_r4
518 FUNCTION(invalidate_addr_r5):
519 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
521 b invalidate_addr_call
522 .size invalidate_addr_r5, .-invalidate_addr_r5
524 FUNCTION(invalidate_addr_r6):
525 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
527 b invalidate_addr_call
528 .size invalidate_addr_r6, .-invalidate_addr_r6
530 FUNCTION(invalidate_addr_r7):
531 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
533 b invalidate_addr_call
534 .size invalidate_addr_r7, .-invalidate_addr_r7
536 FUNCTION(invalidate_addr_r8):
537 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
539 b invalidate_addr_call
540 .size invalidate_addr_r8, .-invalidate_addr_r8
542 FUNCTION(invalidate_addr_r9):
543 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
545 b invalidate_addr_call
546 .size invalidate_addr_r9, .-invalidate_addr_r9
548 FUNCTION(invalidate_addr_r10):
549 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
551 b invalidate_addr_call
552 .size invalidate_addr_r10, .-invalidate_addr_r10
554 FUNCTION(invalidate_addr_r12):
555 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
557 .size invalidate_addr_r12, .-invalidate_addr_r12
559 invalidate_addr_call:
560 ldr r12, [fp, #LO_inv_code_start]
561 ldr lr, [fp, #LO_inv_code_end]
565 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
566 .size invalidate_addr_call, .-invalidate_addr_call
569 FUNCTION(new_dyna_start):
570 /* ip is stored to conform EABI alignment */
571 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
572 mov fp, r0 /* dynarec_local */
573 ldr r0, [fp, #LO_pcaddr]
575 ldr r1, [fp, #LO_next_interupt]
576 ldr r10, [fp, #LO_cycle]
577 str r1, [fp, #LO_last_count]
580 .size new_dyna_start, .-new_dyna_start
582 /* --------------------------------------- */
586 .macro pcsx_read_mem readop tab_shift
587 /* r0 = address, r1 = handler_tab, r2 = cycles */
589 lsr r3, #(20+\tab_shift)
590 ldr r12, [fp, #LO_last_count]
591 ldr r1, [r1, r3, lsl #2]
598 \readop r0, [r1, r3, lsl #\tab_shift]
601 str r2, [fp, #LO_cycle]
605 FUNCTION(jump_handler_read8):
606 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
607 pcsx_read_mem ldrbcc, 0
609 FUNCTION(jump_handler_read16):
610 add r1, #0x1000/4*4 @ shift to r16 part
611 pcsx_read_mem ldrhcc, 1
613 FUNCTION(jump_handler_read32):
614 pcsx_read_mem ldrcc, 2
617 .macro memhandler_post
618 ldr r0, [fp, #LO_next_interupt]
619 ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
620 str r0, [fp, #LO_last_count]
624 .macro pcsx_write_mem wrtop tab_shift
625 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
627 lsr r12, #(20+\tab_shift)
628 ldr r3, [r3, r12, lsl #2]
629 str r0, [fp, #LO_address] @ some handlers still need it..
631 mov r0, r2 @ cycle return in case of direct store
636 \wrtop r1, [r3, r12, lsl #\tab_shift]
639 ldr r12, [fp, #LO_last_count]
642 str r2, [fp, #LO_cycle]
644 str lr, [fp, #LO_saved_lr]
646 ldr lr, [fp, #LO_saved_lr]
652 FUNCTION(jump_handler_write8):
653 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
654 pcsx_write_mem strbcc, 0
656 FUNCTION(jump_handler_write16):
657 add r3, #0x1000/4*4 @ shift to r16 part
658 pcsx_write_mem strhcc, 1
660 FUNCTION(jump_handler_write32):
661 pcsx_write_mem strcc, 2
663 FUNCTION(jump_handler_write_h):
664 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
665 ldr r12, [fp, #LO_last_count]
666 str r0, [fp, #LO_address] @ some handlers still need it..
669 str r2, [fp, #LO_cycle]
671 str lr, [fp, #LO_saved_lr]
673 ldr lr, [fp, #LO_saved_lr]
678 FUNCTION(jump_handle_swl):
679 /* r0 = address, r1 = data, r2 = cycles */
680 ldr r3, [fp, #LO_mem_wtab]
682 ldr r3, [r3, r12, lsl #2]
703 lsreq r12, r1, #24 @ 0
713 FUNCTION(jump_handle_swr):
714 /* r0 = address, r1 = data, r2 = cycles */
715 ldr r3, [fp, #LO_mem_wtab]
717 ldr r3, [r3, r12, lsl #2]
739 .macro rcntx_read_mode0 num
740 /* r0 = address, r2 = cycles */
741 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
743 sub r0, r0, r3, lsl #16
748 FUNCTION(rcnt0_read_count_m0):
751 FUNCTION(rcnt1_read_count_m0):
754 FUNCTION(rcnt2_read_count_m0):
757 FUNCTION(rcnt0_read_count_m1):
758 /* r0 = address, r2 = cycles */
759 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
762 mul r0, r1, r2 @ /= 5
766 FUNCTION(rcnt1_read_count_m1):
767 /* r0 = address, r2 = cycles */
768 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
771 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
774 FUNCTION(rcnt2_read_count_m1):
775 /* r0 = address, r2 = cycles */
776 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
777 mov r0, r2, lsl #16-3
778 sub r0, r0, r3, lsl #16-3
782 FUNCTION(call_gteStall):
783 /* r0 = op_cycles, r1 = cycles */
784 ldr r2, [fp, #LO_last_count]
785 str lr, [fp, #LO_saved_lr]
787 str r1, [fp, #LO_cycle]
788 add r1, fp, #LO_psxRegs
790 ldr lr, [fp, #LO_saved_lr]
800 orr r1, r1, r1, lsl #8
802 orr r1, r1, r1, lsl #16 @ searched char in every byte
803 ldrb r0, [r0, #12] @ last byte
811 orr r3, r3, #0xff000000 @ EXCLUDE_REG
812 uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match)
814 sel r0, r12, r1 @ 0 if no match, else ff in some byte
820 clz r0, r0 @ 0, 8, 16, 24 or 32
823 sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1
824 sub r2, r12, r2, lsr #3
825 sub r3, r12, r3, lsr #3
832 #endif /* HAVE_ARMV6 */
834 @ vim:filetype=armasm