libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2010 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   uint64_t unneeded_reg[MAXBLOCK];
  88   uint64_t unneeded_reg_upper[MAXBLOCK];
  89   uint64_t branch_unneeded_reg[MAXBLOCK];
  90   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  91   uint64_t p32[MAXBLOCK];
  92   uint64_t pr32[MAXBLOCK];
  93   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  94   signed char regmap[MAXBLOCK][HOST_REGS];
  95   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  96   uint64_t constmap[MAXBLOCK][HOST_REGS];
  97   uint64_t known_value[HOST_REGS];
  98   u_int known_reg;
  99   struct regstat regs[MAXBLOCK];
 100   struct regstat branch_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124   u_int using_tlb;
 125   u_int stop_after_jal;
 126   extern u_char restore_candidate[512];
 127   extern int cycle_count;
 128
 129   /* registers that may be allocated */
 130   /* 1-31 gpr */
 131 #define HIREG 32 // hi
 132 #define LOREG 33 // lo
 133 #define FSREG 34 // FPU status (FCSR)
 134 #define CSREG 35 // Coprocessor status
 135 #define CCREG 36 // Cycle count
 136 #define INVCP 37 // Pointer to invalid_code
 137 #define TEMPREG 38
 138 #define FTEMP 38 // FPU/LDL/LDR temporary register
 139 #define PTEMP 39 // Prefetch temporary register
 140 #define TLREG 40 // TLB mapping offset
 141 #define RHASH 41 // Return address hash
 142 #define RHTBL 42 // Return address hash table address
 143 #define RTEMP 43 // JR/JALR address register
 144 #define MAXREG 43
 145 #define AGEN1 44 // Address generation temporary register
 146 #define AGEN2 45 // Address generation temporary register
 147 #define MGEN1 46 // Maptable address generation temporary register
 148 #define MGEN2 47 // Maptable address generation temporary register
 149 #define BTREG 48 // Branch target temporary register
 150
 151   /* instruction types */
 152 #define NOP 0     // No operation
 153 #define LOAD 1    // Load
 154 #define STORE 2   // Store
 155 #define LOADLR 3  // Unaligned load
 156 #define STORELR 4 // Unaligned store
 157 #define MOV 5     // Move
 158 #define ALU 6     // Arithmetic/logic
 159 #define MULTDIV 7 // Multiply/divide
 160 #define SHIFT 8   // Shift by register
 161 #define SHIFTIMM 9// Shift by immediate
 162 #define IMM16 10  // 16-bit immediate
 163 #define RJUMP 11  // Unconditional jump to register
 164 #define UJUMP 12  // Unconditional jump
 165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 166 #define SJUMP 14  // Conditional branch (regimm format)
 167 #define COP0 15   // Coprocessor 0
 168 #define COP1 16   // Coprocessor 1
 169 #define C1LS 17   // Coprocessor 1 load/store
 170 #define FJUMP 18  // Conditional branch (floating point)
 171 #define FLOAT 19  // Floating point unit
 172 #define FCONV 20  // Convert integer to float
 173 #define FCOMP 21  // Floating point compare (sets FSREG)
 174 #define SYSCALL 22// SYSCALL
 175 #define OTHER 23  // Other
 176 #define SPAN 24   // Branch/delay slot spans 2 pages
 177 #define NI 25     // Not implemented
 178 #define HLECALL 26// PCSX fake opcodes for HLE
 179 #define COP2 27   // Coprocessor 2 move
 180 #define C2LS 28   // Coprocessor 2 load/store
 181 #define C2OP 29   // Coprocessor 2 operation
 182
 183   /* stubs */
 184 #define CC_STUB 1
 185 #define FP_STUB 2
 186 #define LOADB_STUB 3
 187 #define LOADH_STUB 4
 188 #define LOADW_STUB 5
 189 #define LOADD_STUB 6
 190 #define LOADBU_STUB 7
 191 #define LOADHU_STUB 8
 192 #define STOREB_STUB 9
 193 #define STOREH_STUB 10
 194 #define STOREW_STUB 11
 195 #define STORED_STUB 12
 196 #define STORELR_STUB 13
 197 #define INVCODE_STUB 14
 198
 199   /* branch codes */
 200 #define TAKEN 1
 201 #define NOTTAKEN 2
 202 #define NULLDS 3
 203
 204 // asm linkage
 205 int new_recompile_block(int addr);
 206 void *get_addr_ht(u_int vaddr);
 207 void invalidate_block(u_int block);
 208 void invalidate_addr(u_int addr);
 209 void remove_hash(int vaddr);
 210 void jump_vaddr();
 211 void dyna_linker();
 212 void dyna_linker_ds();
 213 void verify_code();
 214 void verify_code_vm();
 215 void verify_code_ds();
 216 void cc_interrupt();
 217 void fp_exception();
 218 void fp_exception_ds();
 219 void jump_syscall();
 220 void jump_syscall_hle();
 221 void jump_eret();
 222 void jump_hlecall();
 223 void new_dyna_leave();
 224
 225 // TLB
 226 void TLBWI_new();
 227 void TLBWR_new();
 228 void read_nomem_new();
 229 void read_nomemb_new();
 230 void read_nomemh_new();
 231 void read_nomemd_new();
 232 void write_nomem_new();
 233 void write_nomemb_new();
 234 void write_nomemh_new();
 235 void write_nomemd_new();
 236 void write_rdram_new();
 237 void write_rdramb_new();
 238 void write_rdramh_new();
 239 void write_rdramd_new();
 240 extern u_int memory_map[1048576];
 241
 242 // Needed by assembler
 243 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 244 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 245 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 246 void load_all_regs(signed char i_regmap[]);
 247 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 248 void load_regs_entry(int t);
 249 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 250
 251 int tracedebug=0;
 252
 253 //#define DEBUG_CYCLE_COUNT 1
 254
 255 void nullf() {}
 256 //#define assem_debug printf
 257 //#define inv_debug printf
 258 #define assem_debug nullf
 259 #define inv_debug nullf
 260
 261 static void tlb_hacks()
 262 {
 263 #ifndef DISABLE_TLB
 264   // Goldeneye hack
 265   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 266   {
 267     u_int addr;
 268     int n;
 269     switch (ROM_HEADER->Country_code&0xFF)
 270     {
 271       case 0x45: // U
 272         addr=0x34b30;
 273         break;
 274       case 0x4A: // J
 275         addr=0x34b70;
 276         break;
 277       case 0x50: // E
 278         addr=0x329f0;
 279         break;
 280       default:
 281         // Unknown country code
 282         addr=0;
 283         break;
 284     }
 285     u_int rom_addr=(u_int)rom;
 286     #ifdef ROM_COPY
 287     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 288     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 289     if((void *)rom>(void *)0xffffffff) {
 290       munmap(ROM_COPY, 67108864);
 291       if(mmap(ROM_COPY, 12582912,
 292               PROT_READ | PROT_WRITE,
 293               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 294               -1, 0) <= 0) {printf("mmap() failed\n");}
 295       memcpy(ROM_COPY,rom,12582912);
 296       rom_addr=(u_int)ROM_COPY;
 297     }
 298     #endif
 299     if(addr) {
 300       for(n=0x7F000;n<0x80000;n++) {
 301         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 302       }
 303     }
 304   }
 305 #endif
 306 }
 307
 308 static u_int get_page(u_int vaddr)
 309 {
 310   u_int page=(vaddr^0x80000000)>>12;
 311 #ifndef DISABLE_TLB
 312   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 313 #endif
 314   if(page>2048) page=2048+(page&2047);
 315   return page;
 316 }
 317
 318 static u_int get_vpage(u_int vaddr)
 319 {
 320   u_int vpage=(vaddr^0x80000000)>>12;
 321 #ifndef DISABLE_TLB
 322   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 323 #endif
 324   if(vpage>2048) vpage=2048+(vpage&2047);
 325   return vpage;
 326 }
 327
 328 // Get address from virtual address
 329 // This is called from the recompiled JR/JALR instructions
 330 void *get_addr(u_int vaddr)
 331 {
 332   u_int page=get_page(vaddr);
 333   u_int vpage=get_vpage(vaddr);
 334   struct ll_entry *head;
 335   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 336   head=jump_in[page];
 337   while(head!=NULL) {
 338     if(head->vaddr==vaddr&&head->reg32==0) {
 339   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 340       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 341       ht_bin[3]=ht_bin[1];
 342       ht_bin[2]=ht_bin[0];
 343       ht_bin[1]=(int)head->addr;
 344       ht_bin[0]=vaddr;
 345       return head->addr;
 346     }
 347     head=head->next;
 348   }
 349   head=jump_dirty[vpage];
 350   while(head!=NULL) {
 351     if(head->vaddr==vaddr&&head->reg32==0) {
 352       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 353       // Don't restore blocks which are about to expire from the cache
 354       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 355       if(verify_dirty(head->addr)) {
 356         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 357         invalid_code[vaddr>>12]=0;
 358         memory_map[vaddr>>12]|=0x40000000;
 359         if(vpage<2048) {
 360 #ifndef DISABLE_TLB
 361           if(tlb_LUT_r[vaddr>>12]) {
 362             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 363             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 364           }
 365 #endif
 366           restore_candidate[vpage>>3]|=1<<(vpage&7);
 367         }
 368         else restore_candidate[page>>3]|=1<<(page&7);
 369         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 370         if(ht_bin[0]==vaddr) {
 371           ht_bin[1]=(int)head->addr; // Replace existing entry
 372         }
 373         else
 374         {
 375           ht_bin[3]=ht_bin[1];
 376           ht_bin[2]=ht_bin[0];
 377           ht_bin[1]=(int)head->addr;
 378           ht_bin[0]=vaddr;
 379         }
 380         return head->addr;
 381       }
 382     }
 383     head=head->next;
 384   }
 385   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 386   int r=new_recompile_block(vaddr);
 387   if(r==0) return get_addr(vaddr);
 388   // Execute in unmapped page, generate pagefault execption
 389   Status|=2;
 390   Cause=(vaddr<<31)|0x8;
 391   EPC=(vaddr&1)?vaddr-5:vaddr;
 392   BadVAddr=(vaddr&~1);
 393   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 394   EntryHi=BadVAddr&0xFFFFE000;
 395   return get_addr_ht(0x80000000);
 396 }
 397 // Look up address in hash table first
 398 void *get_addr_ht(u_int vaddr)
 399 {
 400   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 401   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 402   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 403   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 404   return get_addr(vaddr);
 405 }
 406
 407 void *get_addr_32(u_int vaddr,u_int flags)
 408 {
 409 #ifdef FORCE32
 410   return get_addr(vaddr);
 411 #endif
 412   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 413   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 414   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 415   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 416   u_int page=get_page(vaddr);
 417   u_int vpage=get_vpage(vaddr);
 418   struct ll_entry *head;
 419   head=jump_in[page];
 420   while(head!=NULL) {
 421     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 422       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 423       if(head->reg32==0) {
 424         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 425         if(ht_bin[0]==-1) {
 426           ht_bin[1]=(int)head->addr;
 427           ht_bin[0]=vaddr;
 428         }else if(ht_bin[2]==-1) {
 429           ht_bin[3]=(int)head->addr;
 430           ht_bin[2]=vaddr;
 431         }
 432         //ht_bin[3]=ht_bin[1];
 433         //ht_bin[2]=ht_bin[0];
 434         //ht_bin[1]=(int)head->addr;
 435         //ht_bin[0]=vaddr;
 436       }
 437       return head->addr;
 438     }
 439     head=head->next;
 440   }
 441   head=jump_dirty[vpage];
 442   while(head!=NULL) {
 443     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 444       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 445       // Don't restore blocks which are about to expire from the cache
 446       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 447       if(verify_dirty(head->addr)) {
 448         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 449         invalid_code[vaddr>>12]=0;
 450         memory_map[vaddr>>12]|=0x40000000;
 451         if(vpage<2048) {
 452 #ifndef DISABLE_TLB
 453           if(tlb_LUT_r[vaddr>>12]) {
 454             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 455             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 456           }
 457 #endif
 458           restore_candidate[vpage>>3]|=1<<(vpage&7);
 459         }
 460         else restore_candidate[page>>3]|=1<<(page&7);
 461         if(head->reg32==0) {
 462           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 463           if(ht_bin[0]==-1) {
 464             ht_bin[1]=(int)head->addr;
 465             ht_bin[0]=vaddr;
 466           }else if(ht_bin[2]==-1) {
 467             ht_bin[3]=(int)head->addr;
 468             ht_bin[2]=vaddr;
 469           }
 470           //ht_bin[3]=ht_bin[1];
 471           //ht_bin[2]=ht_bin[0];
 472           //ht_bin[1]=(int)head->addr;
 473           //ht_bin[0]=vaddr;
 474         }
 475         return head->addr;
 476       }
 477     }
 478     head=head->next;
 479   }
 480   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 481   int r=new_recompile_block(vaddr);
 482   if(r==0) return get_addr(vaddr);
 483   // Execute in unmapped page, generate pagefault execption
 484   Status|=2;
 485   Cause=(vaddr<<31)|0x8;
 486   EPC=(vaddr&1)?vaddr-5:vaddr;
 487   BadVAddr=(vaddr&~1);
 488   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 489   EntryHi=BadVAddr&0xFFFFE000;
 490   return get_addr_ht(0x80000000);
 491 }
 492
 493 void clear_all_regs(signed char regmap[])
 494 {
 495   int hr;
 496   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 497 }
 498
 499 signed char get_reg(signed char regmap[],int r)
 500 {
 501   int hr;
 502   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 503   return -1;
 504 }
 505
 506 // Find a register that is available for two consecutive cycles
 507 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 508 {
 509   int hr;
 510   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 511   return -1;
 512 }
 513
 514 int count_free_regs(signed char regmap[])
 515 {
 516   int count=0;
 517   int hr;
 518   for(hr=0;hr<HOST_REGS;hr++)
 519   {
 520     if(hr!=EXCLUDE_REG) {
 521       if(regmap[hr]<0) count++;
 522     }
 523   }
 524   return count;
 525 }
 526
 527 void dirty_reg(struct regstat *cur,signed char reg)
 528 {
 529   int hr;
 530   if(!reg) return;
 531   for (hr=0;hr<HOST_REGS;hr++) {
 532     if((cur->regmap[hr]&63)==reg) {
 533       cur->dirty|=1<<hr;
 534     }
 535   }
 536 }
 537
 538 // If we dirty the lower half of a 64 bit register which is now being
 539 // sign-extended, we need to dump the upper half.
 540 // Note: Do this only after completion of the instruction, because
 541 // some instructions may need to read the full 64-bit value even if
 542 // overwriting it (eg SLTI, DSRA32).
 543 static void flush_dirty_uppers(struct regstat *cur)
 544 {
 545   int hr,reg;
 546   for (hr=0;hr<HOST_REGS;hr++) {
 547     if((cur->dirty>>hr)&1) {
 548       reg=cur->regmap[hr];
 549       if(reg>=64)
 550         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 551     }
 552   }
 553 }
 554
 555 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 556 {
 557   int hr;
 558   if(!reg) return;
 559   for (hr=0;hr<HOST_REGS;hr++) {
 560     if(cur->regmap[hr]==reg) {
 561       cur->isconst|=1<<hr;
 562       cur->constmap[hr]=value;
 563     }
 564     else if((cur->regmap[hr]^64)==reg) {
 565       cur->isconst|=1<<hr;
 566       cur->constmap[hr]=value>>32;
 567     }
 568   }
 569 }
 570
 571 void clear_const(struct regstat *cur,signed char reg)
 572 {
 573   int hr;
 574   if(!reg) return;
 575   for (hr=0;hr<HOST_REGS;hr++) {
 576     if((cur->regmap[hr]&63)==reg) {
 577       cur->isconst&=~(1<<hr);
 578     }
 579   }
 580 }
 581
 582 int is_const(struct regstat *cur,signed char reg)
 583 {
 584   int hr;
 585   if(!reg) return 1;
 586   for (hr=0;hr<HOST_REGS;hr++) {
 587     if((cur->regmap[hr]&63)==reg) {
 588       return (cur->isconst>>hr)&1;
 589     }
 590   }
 591   return 0;
 592 }
 593 uint64_t get_const(struct regstat *cur,signed char reg)
 594 {
 595   int hr;
 596   if(!reg) return 0;
 597   for (hr=0;hr<HOST_REGS;hr++) {
 598     if(cur->regmap[hr]==reg) {
 599       return cur->constmap[hr];
 600     }
 601   }
 602   printf("Unknown constant in r%d\n",reg);
 603   exit(1);
 604 }
 605
 606 // Least soon needed registers
 607 // Look at the next ten instructions and see which registers
 608 // will be used.  Try not to reallocate these.
 609 void lsn(u_char hsn[], int i, int *preferred_reg)
 610 {
 611   int j;
 612   int b=-1;
 613   for(j=0;j<9;j++)
 614   {
 615     if(i+j>=slen) {
 616       j=slen-i-1;
 617       break;
 618     }
 619     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 620     {
 621       // Don't go past an unconditonal jump
 622       j++;
 623       break;
 624     }
 625   }
 626   for(;j>=0;j--)
 627   {
 628     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 629     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 630     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 631     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 632     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 633       // Stores can allocate zero
 634       hsn[rs1[i+j]]=j;
 635       hsn[rs2[i+j]]=j;
 636     }
 637     // On some architectures stores need invc_ptr
 638     #if defined(HOST_IMM8)
 639     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 640       hsn[INVCP]=j;
 641     }
 642     #endif
 643     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 644     {
 645       hsn[CCREG]=j;
 646       b=j;
 647     }
 648   }
 649   if(b>=0)
 650   {
 651     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 652     {
 653       // Follow first branch
 654       int t=(ba[i+b]-start)>>2;
 655       j=7-b;if(t+j>=slen) j=slen-t-1;
 656       for(;j>=0;j--)
 657       {
 658         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 659         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 660         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 661         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 662       }
 663     }
 664     // TODO: preferred register based on backward branch
 665   }
 666   // Delay slot should preferably not overwrite branch conditions or cycle count
 667   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 668     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 669     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 670     hsn[CCREG]=1;
 671     // ...or hash tables
 672     hsn[RHASH]=1;
 673     hsn[RHTBL]=1;
 674   }
 675   // Coprocessor load/store needs FTEMP, even if not declared
 676   if(itype[i]==C1LS||itype[i]==C2LS) {
 677     hsn[FTEMP]=0;
 678   }
 679   // Load L/R also uses FTEMP as a temporary register
 680   if(itype[i]==LOADLR) {
 681     hsn[FTEMP]=0;
 682   }
 683   // Also 64-bit SDL/SDR
 684   if(opcode[i]==0x2c||opcode[i]==0x2d) {
 685     hsn[FTEMP]=0;
 686   }
 687   // Don't remove the TLB registers either
 688   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 689     hsn[TLREG]=0;
 690   }
 691   // Don't remove the miniht registers
 692   if(itype[i]==UJUMP||itype[i]==RJUMP)
 693   {
 694     hsn[RHASH]=0;
 695     hsn[RHTBL]=0;
 696   }
 697 }
 698
 699 // We only want to allocate registers if we're going to use them again soon
 700 int needed_again(int r, int i)
 701 {
 702   int j;
 703   int b=-1;
 704   int rn=10;
 705   int hr;
 706   u_char hsn[MAXREG+1];
 707   int preferred_reg;
 708
 709   memset(hsn,10,sizeof(hsn));
 710   lsn(hsn,i,&preferred_reg);
 711
 712   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 713   {
 714     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 715       return 0; // Don't need any registers if exiting the block
 716   }
 717   for(j=0;j<9;j++)
 718   {
 719     if(i+j>=slen) {
 720       j=slen-i-1;
 721       break;
 722     }
 723     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 724     {
 725       // Don't go past an unconditonal jump
 726       j++;
 727       break;
 728     }
 729     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
 730     {
 731       break;
 732     }
 733   }
 734   for(;j>=1;j--)
 735   {
 736     if(rs1[i+j]==r) rn=j;
 737     if(rs2[i+j]==r) rn=j;
 738     if((unneeded_reg[i+j]>>r)&1) rn=10;
 739     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 740     {
 741       b=j;
 742     }
 743   }
 744   /*
 745   if(b>=0)
 746   {
 747     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 748     {
 749       // Follow first branch
 750       int o=rn;
 751       int t=(ba[i+b]-start)>>2;
 752       j=7-b;if(t+j>=slen) j=slen-t-1;
 753       for(;j>=0;j--)
 754       {
 755         if(!((unneeded_reg[t+j]>>r)&1)) {
 756           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 757           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 758         }
 759         else rn=o;
 760       }
 761     }
 762   }*/
 763   for(hr=0;hr<HOST_REGS;hr++) {
 764     if(hr!=EXCLUDE_REG) {
 765       if(rn<hsn[hr]) return 1;
 766     }
 767   }
 768   return 0;
 769 }
 770
 771 // Try to match register allocations at the end of a loop with those
 772 // at the beginning
 773 int loop_reg(int i, int r, int hr)
 774 {
 775   int j,k;
 776   for(j=0;j<9;j++)
 777   {
 778     if(i+j>=slen) {
 779       j=slen-i-1;
 780       break;
 781     }
 782     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 783     {
 784       // Don't go past an unconditonal jump
 785       j++;
 786       break;
 787     }
 788   }
 789   k=0;
 790   if(i>0){
 791     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 792       k--;
 793   }
 794   for(;k<j;k++)
 795   {
 796     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 797     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 798     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 799     {
 800       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 801       {
 802         int t=(ba[i+k]-start)>>2;
 803         int reg=get_reg(regs[t].regmap_entry,r);
 804         if(reg>=0) return reg;
 805         //reg=get_reg(regs[t+1].regmap_entry,r);
 806         //if(reg>=0) return reg;
 807       }
 808     }
 809   }
 810   return hr;
 811 }
 812
 813
 814 // Allocate every register, preserving source/target regs
 815 void alloc_all(struct regstat *cur,int i)
 816 {
 817   int hr;
 818
 819   for(hr=0;hr<HOST_REGS;hr++) {
 820     if(hr!=EXCLUDE_REG) {
 821       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 822          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 823       {
 824         cur->regmap[hr]=-1;
 825         cur->dirty&=~(1<<hr);
 826       }
 827       // Don't need zeros
 828       if((cur->regmap[hr]&63)==0)
 829       {
 830         cur->regmap[hr]=-1;
 831         cur->dirty&=~(1<<hr);
 832       }
 833     }
 834   }
 835 }
 836
 837
 838 void div64(int64_t dividend,int64_t divisor)
 839 {
 840   lo=dividend/divisor;
 841   hi=dividend%divisor;
 842   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 843   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 844 }
 845 void divu64(uint64_t dividend,uint64_t divisor)
 846 {
 847   lo=dividend/divisor;
 848   hi=dividend%divisor;
 849   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 850   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 851 }
 852
 853 void mult64(uint64_t m1,uint64_t m2)
 854 {
 855    unsigned long long int op1, op2, op3, op4;
 856    unsigned long long int result1, result2, result3, result4;
 857    unsigned long long int temp1, temp2, temp3, temp4;
 858    int sign = 0;
 859
 860    if (m1 < 0)
 861      {
 862     op2 = -m1;
 863     sign = 1 - sign;
 864      }
 865    else op2 = m1;
 866    if (m2 < 0)
 867      {
 868     op4 = -m2;
 869     sign = 1 - sign;
 870      }
 871    else op4 = m2;
 872
 873    op1 = op2 & 0xFFFFFFFF;
 874    op2 = (op2 >> 32) & 0xFFFFFFFF;
 875    op3 = op4 & 0xFFFFFFFF;
 876    op4 = (op4 >> 32) & 0xFFFFFFFF;
 877
 878    temp1 = op1 * op3;
 879    temp2 = (temp1 >> 32) + op1 * op4;
 880    temp3 = op2 * op3;
 881    temp4 = (temp3 >> 32) + op2 * op4;
 882
 883    result1 = temp1 & 0xFFFFFFFF;
 884    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 885    result3 = (result2 >> 32) + temp4;
 886    result4 = (result3 >> 32);
 887
 888    lo = result1 | (result2 << 32);
 889    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 890    if (sign)
 891      {
 892     hi = ~hi;
 893     if (!lo) hi++;
 894     else lo = ~lo + 1;
 895      }
 896 }
 897
 898 void multu64(uint64_t m1,uint64_t m2)
 899 {
 900    unsigned long long int op1, op2, op3, op4;
 901    unsigned long long int result1, result2, result3, result4;
 902    unsigned long long int temp1, temp2, temp3, temp4;
 903
 904    op1 = m1 & 0xFFFFFFFF;
 905    op2 = (m1 >> 32) & 0xFFFFFFFF;
 906    op3 = m2 & 0xFFFFFFFF;
 907    op4 = (m2 >> 32) & 0xFFFFFFFF;
 908
 909    temp1 = op1 * op3;
 910    temp2 = (temp1 >> 32) + op1 * op4;
 911    temp3 = op2 * op3;
 912    temp4 = (temp3 >> 32) + op2 * op4;
 913
 914    result1 = temp1 & 0xFFFFFFFF;
 915    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 916    result3 = (result2 >> 32) + temp4;
 917    result4 = (result3 >> 32);
 918
 919    lo = result1 | (result2 << 32);
 920    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 921
 922   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 923   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 924 }
 925
 926 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 927 {
 928   if(bits) {
 929     original<<=64-bits;
 930     original>>=64-bits;
 931     loaded<<=bits;
 932     original|=loaded;
 933   }
 934   else original=loaded;
 935   return original;
 936 }
 937 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 938 {
 939   if(bits^56) {
 940     original>>=64-(bits^56);
 941     original<<=64-(bits^56);
 942     loaded>>=bits^56;
 943     original|=loaded;
 944   }
 945   else original=loaded;
 946   return original;
 947 }
 948
 949 #ifdef __i386__
 950 #include "assem_x86.c"
 951 #endif
 952 #ifdef __x86_64__
 953 #include "assem_x64.c"
 954 #endif
 955 #ifdef __arm__
 956 #include "assem_arm.c"
 957 #endif
 958
 959 // Add virtual address mapping to linked list
 960 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 961 {
 962   struct ll_entry *new_entry;
 963   new_entry=malloc(sizeof(struct ll_entry));
 964   assert(new_entry!=NULL);
 965   new_entry->vaddr=vaddr;
 966   new_entry->reg32=0;
 967   new_entry->addr=addr;
 968   new_entry->next=*head;
 969   *head=new_entry;
 970 }
 971
 972 // Add virtual address mapping for 32-bit compiled block
 973 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 974 {
 975   ll_add(head,vaddr,addr);
 976 #ifndef FORCE32
 977   (*head)->reg32=reg32;
 978 #endif
 979 }
 980
 981 // Check if an address is already compiled
 982 // but don't return addresses which are about to expire from the cache
 983 void *check_addr(u_int vaddr)
 984 {
 985   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 986   if(ht_bin[0]==vaddr) {
 987     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 988       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 989   }
 990   if(ht_bin[2]==vaddr) {
 991     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 992       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
 993   }
 994   u_int page=get_page(vaddr);
 995   struct ll_entry *head;
 996   head=jump_in[page];
 997   while(head!=NULL) {
 998     if(head->vaddr==vaddr&&head->reg32==0) {
 999       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1000         // Update existing entry with current address
1001         if(ht_bin[0]==vaddr) {
1002           ht_bin[1]=(int)head->addr;
1003           return head->addr;
1004         }
1005         if(ht_bin[2]==vaddr) {
1006           ht_bin[3]=(int)head->addr;
1007           return head->addr;
1008         }
1009         // Insert into hash table with low priority.
1010         // Don't evict existing entries, as they are probably
1011         // addresses that are being accessed frequently.
1012         if(ht_bin[0]==-1) {
1013           ht_bin[1]=(int)head->addr;
1014           ht_bin[0]=vaddr;
1015         }else if(ht_bin[2]==-1) {
1016           ht_bin[3]=(int)head->addr;
1017           ht_bin[2]=vaddr;
1018         }
1019         return head->addr;
1020       }
1021     }
1022     head=head->next;
1023   }
1024   return 0;
1025 }
1026
1027 void remove_hash(int vaddr)
1028 {
1029   //printf("remove hash: %x\n",vaddr);
1030   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1031   if(ht_bin[2]==vaddr) {
1032     ht_bin[2]=ht_bin[3]=-1;
1033   }
1034   if(ht_bin[0]==vaddr) {
1035     ht_bin[0]=ht_bin[2];
1036     ht_bin[1]=ht_bin[3];
1037     ht_bin[2]=ht_bin[3]=-1;
1038   }
1039 }
1040
1041 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1042 {
1043   struct ll_entry *next;
1044   while(*head) {
1045     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1046        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1047     {
1048       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1049       remove_hash((*head)->vaddr);
1050       next=(*head)->next;
1051       free(*head);
1052       *head=next;
1053     }
1054     else
1055     {
1056       head=&((*head)->next);
1057     }
1058   }
1059 }
1060
1061 // Remove all entries from linked list
1062 void ll_clear(struct ll_entry **head)
1063 {
1064   struct ll_entry *cur;
1065   struct ll_entry *next;
1066   if(cur=*head) {
1067     *head=0;
1068     while(cur) {
1069       next=cur->next;
1070       free(cur);
1071       cur=next;
1072     }
1073   }
1074 }
1075
1076 // Dereference the pointers and remove if it matches
1077 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1078 {
1079   while(head) {
1080     int ptr=get_pointer(head->addr);
1081     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1082     if(((ptr>>shift)==(addr>>shift)) ||
1083        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1084     {
1085       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1086       kill_pointer(head->addr);
1087     }
1088     head=head->next;
1089   }
1090 }
1091
1092 // This is called when we write to a compiled block (see do_invstub)
1093 int invalidate_page(u_int page)
1094 {
1095   int modified=0;
1096   struct ll_entry *head;
1097   struct ll_entry *next;
1098   head=jump_in[page];
1099   jump_in[page]=0;
1100   while(head!=NULL) {
1101     inv_debug("INVALIDATE: %x\n",head->vaddr);
1102     remove_hash(head->vaddr);
1103     next=head->next;
1104     free(head);
1105     head=next;
1106   }
1107   head=jump_out[page];
1108   jump_out[page]=0;
1109   while(head!=NULL) {
1110     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1111     kill_pointer(head->addr);
1112     modified=1;
1113     next=head->next;
1114     free(head);
1115     head=next;
1116   }
1117   return modified;
1118 }
1119 void invalidate_block(u_int block)
1120 {
1121   int modified;
1122   u_int page=get_page(block<<12);
1123   u_int vpage=get_vpage(block<<12);
1124   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1125   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1126   u_int first,last;
1127   first=last=page;
1128   struct ll_entry *head;
1129   head=jump_dirty[vpage];
1130   //printf("page=%d vpage=%d\n",page,vpage);
1131   while(head!=NULL) {
1132     u_int start,end;
1133     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1134       get_bounds((int)head->addr,&start,&end);
1135       //printf("start: %x end: %x\n",start,end);
1136       if(page<2048&&start>=0x80000000&&end<0x80800000) {
1137         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1138           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1139           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1140         }
1141       }
1142 #ifndef DISABLE_TLB
1143       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1144         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1145           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1146           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1147         }
1148       }
1149 #endif
1150     }
1151     head=head->next;
1152   }
1153   //printf("first=%d last=%d\n",first,last);
1154   modified=invalidate_page(page);
1155   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1156   assert(last<page+5);
1157   // Invalidate the adjacent pages if a block crosses a 4K boundary
1158   while(first<page) {
1159     invalidate_page(first);
1160     first++;
1161   }
1162   for(first=page+1;first<last;first++) {
1163     invalidate_page(first);
1164   }
1165
1166   // Don't trap writes
1167   invalid_code[block]=1;
1168 #ifndef DISABLE_TLB
1169   // If there is a valid TLB entry for this page, remove write protect
1170   if(tlb_LUT_w[block]) {
1171     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1172     // CHECK: Is this right?
1173     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1174     u_int real_block=tlb_LUT_w[block]>>12;
1175     invalid_code[real_block]=1;
1176     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1177   }
1178   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1179 #endif
1180   #ifdef __arm__
1181   if(modified)
1182     __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1183   #endif
1184   #ifdef USE_MINI_HT
1185   memset(mini_ht,-1,sizeof(mini_ht));
1186   #endif
1187 }
1188 void invalidate_addr(u_int addr)
1189 {
1190   invalidate_block(addr>>12);
1191 }
1192 void invalidate_all_pages()
1193 {
1194   u_int page,n;
1195   for(page=0;page<4096;page++)
1196     invalidate_page(page);
1197   for(page=0;page<1048576;page++)
1198     if(!invalid_code[page]) {
1199       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1200       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1201     }
1202   #ifdef __arm__
1203   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1204   #endif
1205   #ifdef USE_MINI_HT
1206   memset(mini_ht,-1,sizeof(mini_ht));
1207   #endif
1208   #ifndef DISABLE_TLB
1209   // TLB
1210   for(page=0;page<0x100000;page++) {
1211     if(tlb_LUT_r[page]) {
1212       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1213       if(!tlb_LUT_w[page]||!invalid_code[page])
1214         memory_map[page]|=0x40000000; // Write protect
1215     }
1216     else memory_map[page]=-1;
1217     if(page==0x80000) page=0xC0000;
1218   }
1219   tlb_hacks();
1220   #endif
1221 }
1222
1223 // Add an entry to jump_out after making a link
1224 void add_link(u_int vaddr,void *src)
1225 {
1226   u_int page=get_page(vaddr);
1227   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1228   ll_add(jump_out+page,vaddr,src);
1229   //int ptr=get_pointer(src);
1230   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1231 }
1232
1233 // If a code block was found to be unmodified (bit was set in
1234 // restore_candidate) and it remains unmodified (bit is clear
1235 // in invalid_code) then move the entries for that 4K page from
1236 // the dirty list to the clean list.
1237 void clean_blocks(u_int page)
1238 {
1239   struct ll_entry *head;
1240   inv_debug("INV: clean_blocks page=%d\n",page);
1241   head=jump_dirty[page];
1242   while(head!=NULL) {
1243     if(!invalid_code[head->vaddr>>12]) {
1244       // Don't restore blocks which are about to expire from the cache
1245       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1246         u_int start,end;
1247         if(verify_dirty((int)head->addr)) {
1248           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1249           u_int i;
1250           u_int inv=0;
1251           get_bounds((int)head->addr,&start,&end);
1252           if(start-(u_int)rdram<0x800000) {
1253             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1254               inv|=invalid_code[i];
1255             }
1256           }
1257           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1258             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1259             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1260             if(addr<start||addr>=end) inv=1;
1261           }
1262           else if((signed int)head->vaddr>=(signed int)0x80800000) {
1263             inv=1;
1264           }
1265           if(!inv) {
1266             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1267             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1268               u_int ppage=page;
1269 #ifndef DISABLE_TLB
1270               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1271 #endif
1272               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1273               //printf("page=%x, addr=%x\n",page,head->vaddr);
1274               //assert(head->vaddr>>12==(page|0x80000));
1275               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1276               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1277               if(!head->reg32) {
1278                 if(ht_bin[0]==head->vaddr) {
1279                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1280                 }
1281                 if(ht_bin[2]==head->vaddr) {
1282                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1283                 }
1284               }
1285             }
1286           }
1287         }
1288       }
1289     }
1290     head=head->next;
1291   }
1292 }
1293
1294
1295 void mov_alloc(struct regstat *current,int i)
1296 {
1297   // Note: Don't need to actually alloc the source registers
1298   if((~current->is32>>rs1[i])&1) {
1299     //alloc_reg64(current,i,rs1[i]);
1300     alloc_reg64(current,i,rt1[i]);
1301     current->is32&=~(1LL<<rt1[i]);
1302   } else {
1303     //alloc_reg(current,i,rs1[i]);
1304     alloc_reg(current,i,rt1[i]);
1305     current->is32|=(1LL<<rt1[i]);
1306   }
1307   clear_const(current,rs1[i]);
1308   clear_const(current,rt1[i]);
1309   dirty_reg(current,rt1[i]);
1310 }
1311
1312 void shiftimm_alloc(struct regstat *current,int i)
1313 {
1314   clear_const(current,rs1[i]);
1315   clear_const(current,rt1[i]);
1316   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1317   {
1318     if(rt1[i]) {
1319       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1320       else lt1[i]=rs1[i];
1321       alloc_reg(current,i,rt1[i]);
1322       current->is32|=1LL<<rt1[i];
1323       dirty_reg(current,rt1[i]);
1324     }
1325   }
1326   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1327   {
1328     if(rt1[i]) {
1329       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1330       alloc_reg64(current,i,rt1[i]);
1331       current->is32&=~(1LL<<rt1[i]);
1332       dirty_reg(current,rt1[i]);
1333     }
1334   }
1335   if(opcode2[i]==0x3c) // DSLL32
1336   {
1337     if(rt1[i]) {
1338       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1339       alloc_reg64(current,i,rt1[i]);
1340       current->is32&=~(1LL<<rt1[i]);
1341       dirty_reg(current,rt1[i]);
1342     }
1343   }
1344   if(opcode2[i]==0x3e) // DSRL32
1345   {
1346     if(rt1[i]) {
1347       alloc_reg64(current,i,rs1[i]);
1348       if(imm[i]==32) {
1349         alloc_reg64(current,i,rt1[i]);
1350         current->is32&=~(1LL<<rt1[i]);
1351       } else {
1352         alloc_reg(current,i,rt1[i]);
1353         current->is32|=1LL<<rt1[i];
1354       }
1355       dirty_reg(current,rt1[i]);
1356     }
1357   }
1358   if(opcode2[i]==0x3f) // DSRA32
1359   {
1360     if(rt1[i]) {
1361       alloc_reg64(current,i,rs1[i]);
1362       alloc_reg(current,i,rt1[i]);
1363       current->is32|=1LL<<rt1[i];
1364       dirty_reg(current,rt1[i]);
1365     }
1366   }
1367 }
1368
1369 void shift_alloc(struct regstat *current,int i)
1370 {
1371   if(rt1[i]) {
1372     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1373     {
1374       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1375       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376       alloc_reg(current,i,rt1[i]);
1377       if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1378       current->is32|=1LL<<rt1[i];
1379     } else { // DSLLV/DSRLV/DSRAV
1380       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1381       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1382       alloc_reg64(current,i,rt1[i]);
1383       current->is32&=~(1LL<<rt1[i]);
1384       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1385         alloc_reg_temp(current,i,-1);
1386     }
1387     clear_const(current,rs1[i]);
1388     clear_const(current,rs2[i]);
1389     clear_const(current,rt1[i]);
1390     dirty_reg(current,rt1[i]);
1391   }
1392 }
1393
1394 void alu_alloc(struct regstat *current,int i)
1395 {
1396   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1397     if(rt1[i]) {
1398       if(rs1[i]&&rs2[i]) {
1399         alloc_reg(current,i,rs1[i]);
1400         alloc_reg(current,i,rs2[i]);
1401       }
1402       else {
1403         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1404         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1405       }
1406       alloc_reg(current,i,rt1[i]);
1407     }
1408     current->is32|=1LL<<rt1[i];
1409   }
1410   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1411     if(rt1[i]) {
1412       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1413       {
1414         alloc_reg64(current,i,rs1[i]);
1415         alloc_reg64(current,i,rs2[i]);
1416         alloc_reg(current,i,rt1[i]);
1417       } else {
1418         alloc_reg(current,i,rs1[i]);
1419         alloc_reg(current,i,rs2[i]);
1420         alloc_reg(current,i,rt1[i]);
1421       }
1422     }
1423     current->is32|=1LL<<rt1[i];
1424   }
1425   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1426     if(rt1[i]) {
1427       if(rs1[i]&&rs2[i]) {
1428         alloc_reg(current,i,rs1[i]);
1429         alloc_reg(current,i,rs2[i]);
1430       }
1431       else
1432       {
1433         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1434         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1435       }
1436       alloc_reg(current,i,rt1[i]);
1437       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1438       {
1439         if(!((current->uu>>rt1[i])&1)) {
1440           alloc_reg64(current,i,rt1[i]);
1441         }
1442         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1443           if(rs1[i]&&rs2[i]) {
1444             alloc_reg64(current,i,rs1[i]);
1445             alloc_reg64(current,i,rs2[i]);
1446           }
1447           else
1448           {
1449             // Is is really worth it to keep 64-bit values in registers?
1450             #ifdef NATIVE_64BIT
1451             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1452             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1453             #endif
1454           }
1455         }
1456         current->is32&=~(1LL<<rt1[i]);
1457       } else {
1458         current->is32|=1LL<<rt1[i];
1459       }
1460     }
1461   }
1462   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1463     if(rt1[i]) {
1464       if(rs1[i]&&rs2[i]) {
1465         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1466           alloc_reg64(current,i,rs1[i]);
1467           alloc_reg64(current,i,rs2[i]);
1468           alloc_reg64(current,i,rt1[i]);
1469         } else {
1470           alloc_reg(current,i,rs1[i]);
1471           alloc_reg(current,i,rs2[i]);
1472           alloc_reg(current,i,rt1[i]);
1473         }
1474       }
1475       else {
1476         alloc_reg(current,i,rt1[i]);
1477         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1478           // DADD used as move, or zeroing
1479           // If we have a 64-bit source, then make the target 64 bits too
1480           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1481             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1482             alloc_reg64(current,i,rt1[i]);
1483           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1484             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485             alloc_reg64(current,i,rt1[i]);
1486           }
1487           if(opcode2[i]>=0x2e&&rs2[i]) {
1488             // DSUB used as negation - 64-bit result
1489             // If we have a 32-bit register, extend it to 64 bits
1490             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1491             alloc_reg64(current,i,rt1[i]);
1492           }
1493         }
1494       }
1495       if(rs1[i]&&rs2[i]) {
1496         current->is32&=~(1LL<<rt1[i]);
1497       } else if(rs1[i]) {
1498         current->is32&=~(1LL<<rt1[i]);
1499         if((current->is32>>rs1[i])&1)
1500           current->is32|=1LL<<rt1[i];
1501       } else if(rs2[i]) {
1502         current->is32&=~(1LL<<rt1[i]);
1503         if((current->is32>>rs2[i])&1)
1504           current->is32|=1LL<<rt1[i];
1505       } else {
1506         current->is32|=1LL<<rt1[i];
1507       }
1508     }
1509   }
1510   clear_const(current,rs1[i]);
1511   clear_const(current,rs2[i]);
1512   clear_const(current,rt1[i]);
1513   dirty_reg(current,rt1[i]);
1514 }
1515
1516 void imm16_alloc(struct regstat *current,int i)
1517 {
1518   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519   else lt1[i]=rs1[i];
1520   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1521   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1522     current->is32&=~(1LL<<rt1[i]);
1523     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1524       // TODO: Could preserve the 32-bit flag if the immediate is zero
1525       alloc_reg64(current,i,rt1[i]);
1526       alloc_reg64(current,i,rs1[i]);
1527     }
1528     clear_const(current,rs1[i]);
1529     clear_const(current,rt1[i]);
1530   }
1531   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1532     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1533     current->is32|=1LL<<rt1[i];
1534     clear_const(current,rs1[i]);
1535     clear_const(current,rt1[i]);
1536   }
1537   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1538     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1539       if(rs1[i]!=rt1[i]) {
1540         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1541         alloc_reg64(current,i,rt1[i]);
1542         current->is32&=~(1LL<<rt1[i]);
1543       }
1544     }
1545     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1546     if(is_const(current,rs1[i])) {
1547       int v=get_const(current,rs1[i]);
1548       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1549       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1550       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1551     }
1552     else clear_const(current,rt1[i]);
1553   }
1554   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1555     if(is_const(current,rs1[i])) {
1556       int v=get_const(current,rs1[i]);
1557       set_const(current,rt1[i],v+imm[i]);
1558     }
1559     else clear_const(current,rt1[i]);
1560     current->is32|=1LL<<rt1[i];
1561   }
1562   else {
1563     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1564     current->is32|=1LL<<rt1[i];
1565   }
1566   dirty_reg(current,rt1[i]);
1567 }
1568
1569 void load_alloc(struct regstat *current,int i)
1570 {
1571   clear_const(current,rt1[i]);
1572   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1573   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1574   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1575   if(rt1[i]) {
1576     alloc_reg(current,i,rt1[i]);
1577     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1578     {
1579       current->is32&=~(1LL<<rt1[i]);
1580       alloc_reg64(current,i,rt1[i]);
1581     }
1582     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1583     {
1584       current->is32&=~(1LL<<rt1[i]);
1585       alloc_reg64(current,i,rt1[i]);
1586       alloc_all(current,i);
1587       alloc_reg64(current,i,FTEMP);
1588     }
1589     else current->is32|=1LL<<rt1[i];
1590     dirty_reg(current,rt1[i]);
1591     // If using TLB, need a register for pointer to the mapping table
1592     if(using_tlb) alloc_reg(current,i,TLREG);
1593     // LWL/LWR need a temporary register for the old value
1594     if(opcode[i]==0x22||opcode[i]==0x26)
1595     {
1596       alloc_reg(current,i,FTEMP);
1597       alloc_reg_temp(current,i,-1);
1598     }
1599   }
1600   else
1601   {
1602     // Load to r0 (dummy load)
1603     // but we still need a register to calculate the address
1604     alloc_reg_temp(current,i,-1);
1605   }
1606 }
1607
1608 void store_alloc(struct regstat *current,int i)
1609 {
1610   clear_const(current,rs2[i]);
1611   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1612   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1613   alloc_reg(current,i,rs2[i]);
1614   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1615     alloc_reg64(current,i,rs2[i]);
1616     if(rs2[i]) alloc_reg(current,i,FTEMP);
1617   }
1618   // If using TLB, need a register for pointer to the mapping table
1619   if(using_tlb) alloc_reg(current,i,TLREG);
1620   #if defined(HOST_IMM8)
1621   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1622   else alloc_reg(current,i,INVCP);
1623   #endif
1624   if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1625     alloc_reg(current,i,FTEMP);
1626   }
1627   // We need a temporary register for address generation
1628   alloc_reg_temp(current,i,-1);
1629 }
1630
1631 void c1ls_alloc(struct regstat *current,int i)
1632 {
1633   //clear_const(current,rs1[i]); // FIXME
1634   clear_const(current,rt1[i]);
1635   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1636   alloc_reg(current,i,CSREG); // Status
1637   alloc_reg(current,i,FTEMP);
1638   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1639     alloc_reg64(current,i,FTEMP);
1640   }
1641   // If using TLB, need a register for pointer to the mapping table
1642   if(using_tlb) alloc_reg(current,i,TLREG);
1643   #if defined(HOST_IMM8)
1644   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1645   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1646     alloc_reg(current,i,INVCP);
1647   #endif
1648   // We need a temporary register for address generation
1649   alloc_reg_temp(current,i,-1);
1650 }
1651
1652 void c2ls_alloc(struct regstat *current,int i)
1653 {
1654   clear_const(current,rt1[i]);
1655   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656   alloc_reg(current,i,FTEMP);
1657   // If using TLB, need a register for pointer to the mapping table
1658   if(using_tlb) alloc_reg(current,i,TLREG);
1659   #if defined(HOST_IMM8)
1660   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1662     alloc_reg(current,i,INVCP);
1663   #endif
1664   // We need a temporary register for address generation
1665   alloc_reg_temp(current,i,-1);
1666 }
1667
1668 #ifndef multdiv_alloc
1669 void multdiv_alloc(struct regstat *current,int i)
1670 {
1671   //  case 0x18: MULT
1672   //  case 0x19: MULTU
1673   //  case 0x1A: DIV
1674   //  case 0x1B: DIVU
1675   //  case 0x1C: DMULT
1676   //  case 0x1D: DMULTU
1677   //  case 0x1E: DDIV
1678   //  case 0x1F: DDIVU
1679   clear_const(current,rs1[i]);
1680   clear_const(current,rs2[i]);
1681   if(rs1[i]&&rs2[i])
1682   {
1683     if((opcode2[i]&4)==0) // 32-bit
1684     {
1685       current->u&=~(1LL<<HIREG);
1686       current->u&=~(1LL<<LOREG);
1687       alloc_reg(current,i,HIREG);
1688       alloc_reg(current,i,LOREG);
1689       alloc_reg(current,i,rs1[i]);
1690       alloc_reg(current,i,rs2[i]);
1691       current->is32|=1LL<<HIREG;
1692       current->is32|=1LL<<LOREG;
1693       dirty_reg(current,HIREG);
1694       dirty_reg(current,LOREG);
1695     }
1696     else // 64-bit
1697     {
1698       current->u&=~(1LL<<HIREG);
1699       current->u&=~(1LL<<LOREG);
1700       current->uu&=~(1LL<<HIREG);
1701       current->uu&=~(1LL<<LOREG);
1702       alloc_reg64(current,i,HIREG);
1703       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1704       alloc_reg64(current,i,rs1[i]);
1705       alloc_reg64(current,i,rs2[i]);
1706       alloc_all(current,i);
1707       current->is32&=~(1LL<<HIREG);
1708       current->is32&=~(1LL<<LOREG);
1709       dirty_reg(current,HIREG);
1710       dirty_reg(current,LOREG);
1711     }
1712   }
1713   else
1714   {
1715     // Multiply by zero is zero.
1716     // MIPS does not have a divide by zero exception.
1717     // The result is undefined, we return zero.
1718     alloc_reg(current,i,HIREG);
1719     alloc_reg(current,i,LOREG);
1720     current->is32|=1LL<<HIREG;
1721     current->is32|=1LL<<LOREG;
1722     dirty_reg(current,HIREG);
1723     dirty_reg(current,LOREG);
1724   }
1725 }
1726 #endif
1727
1728 void cop0_alloc(struct regstat *current,int i)
1729 {
1730   if(opcode2[i]==0) // MFC0
1731   {
1732     if(rt1[i]) {
1733       clear_const(current,rt1[i]);
1734       alloc_all(current,i);
1735       alloc_reg(current,i,rt1[i]);
1736       current->is32|=1LL<<rt1[i];
1737       dirty_reg(current,rt1[i]);
1738     }
1739   }
1740   else if(opcode2[i]==4) // MTC0
1741   {
1742     if(rs1[i]){
1743       clear_const(current,rs1[i]);
1744       alloc_reg(current,i,rs1[i]);
1745       alloc_all(current,i);
1746     }
1747     else {
1748       alloc_all(current,i); // FIXME: Keep r0
1749       current->u&=~1LL;
1750       alloc_reg(current,i,0);
1751     }
1752   }
1753   else
1754   {
1755     // TLBR/TLBWI/TLBWR/TLBP/ERET
1756     assert(opcode2[i]==0x10);
1757     alloc_all(current,i);
1758   }
1759 }
1760
1761 void cop1_alloc(struct regstat *current,int i)
1762 {
1763   alloc_reg(current,i,CSREG); // Load status
1764   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1765   {
1766     assert(rt1[i]);
1767     clear_const(current,rt1[i]);
1768     if(opcode2[i]==1) {
1769       alloc_reg64(current,i,rt1[i]); // DMFC1
1770       current->is32&=~(1LL<<rt1[i]);
1771     }else{
1772       alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1773       current->is32|=1LL<<rt1[i];
1774     }
1775     dirty_reg(current,rt1[i]);
1776     alloc_reg_temp(current,i,-1);
1777   }
1778   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1779   {
1780     if(rs1[i]){
1781       clear_const(current,rs1[i]);
1782       if(opcode2[i]==5)
1783         alloc_reg64(current,i,rs1[i]); // DMTC1
1784       else
1785         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1786       alloc_reg_temp(current,i,-1);
1787     }
1788     else {
1789       current->u&=~1LL;
1790       alloc_reg(current,i,0);
1791       alloc_reg_temp(current,i,-1);
1792     }
1793   }
1794 }
1795 void fconv_alloc(struct regstat *current,int i)
1796 {
1797   alloc_reg(current,i,CSREG); // Load status
1798   alloc_reg_temp(current,i,-1);
1799 }
1800 void float_alloc(struct regstat *current,int i)
1801 {
1802   alloc_reg(current,i,CSREG); // Load status
1803   alloc_reg_temp(current,i,-1);
1804 }
1805 void c2op_alloc(struct regstat *current,int i)
1806 {
1807   alloc_reg_temp(current,i,-1);
1808 }
1809 void fcomp_alloc(struct regstat *current,int i)
1810 {
1811   alloc_reg(current,i,CSREG); // Load status
1812   alloc_reg(current,i,FSREG); // Load flags
1813   dirty_reg(current,FSREG); // Flag will be modified
1814   alloc_reg_temp(current,i,-1);
1815 }
1816
1817 void syscall_alloc(struct regstat *current,int i)
1818 {
1819   alloc_cc(current,i);
1820   dirty_reg(current,CCREG);
1821   alloc_all(current,i);
1822   current->isconst=0;
1823 }
1824
1825 void delayslot_alloc(struct regstat *current,int i)
1826 {
1827   switch(itype[i]) {
1828     case UJUMP:
1829     case CJUMP:
1830     case SJUMP:
1831     case RJUMP:
1832     case FJUMP:
1833     case SYSCALL:
1834     case HLECALL:
1835     case SPAN:
1836       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1837       printf("Disabled speculative precompilation\n");
1838       stop_after_jal=1;
1839       break;
1840     case IMM16:
1841       imm16_alloc(current,i);
1842       break;
1843     case LOAD:
1844     case LOADLR:
1845       load_alloc(current,i);
1846       break;
1847     case STORE:
1848     case STORELR:
1849       store_alloc(current,i);
1850       break;
1851     case ALU:
1852       alu_alloc(current,i);
1853       break;
1854     case SHIFT:
1855       shift_alloc(current,i);
1856       break;
1857     case MULTDIV:
1858       multdiv_alloc(current,i);
1859       break;
1860     case SHIFTIMM:
1861       shiftimm_alloc(current,i);
1862       break;
1863     case MOV:
1864       mov_alloc(current,i);
1865       break;
1866     case COP0:
1867       cop0_alloc(current,i);
1868       break;
1869     case COP1:
1870     case COP2:
1871       cop1_alloc(current,i);
1872       break;
1873     case C1LS:
1874       c1ls_alloc(current,i);
1875       break;
1876     case C2LS:
1877       c2ls_alloc(current,i);
1878       break;
1879     case FCONV:
1880       fconv_alloc(current,i);
1881       break;
1882     case FLOAT:
1883       float_alloc(current,i);
1884       break;
1885     case FCOMP:
1886       fcomp_alloc(current,i);
1887       break;
1888     case C2OP:
1889       c2op_alloc(current,i);
1890       break;
1891   }
1892 }
1893
1894 // Special case where a branch and delay slot span two pages in virtual memory
1895 static void pagespan_alloc(struct regstat *current,int i)
1896 {
1897   current->isconst=0;
1898   current->wasconst=0;
1899   regs[i].wasconst=0;
1900   alloc_all(current,i);
1901   alloc_cc(current,i);
1902   dirty_reg(current,CCREG);
1903   if(opcode[i]==3) // JAL
1904   {
1905     alloc_reg(current,i,31);
1906     dirty_reg(current,31);
1907   }
1908   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1909   {
1910     alloc_reg(current,i,rs1[i]);
1911     if (rt1[i]!=0) {
1912       alloc_reg(current,i,rt1[i]);
1913       dirty_reg(current,rt1[i]);
1914     }
1915   }
1916   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1917   {
1918     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1919     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1920     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1921     {
1922       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1923       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1924     }
1925   }
1926   else
1927   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1928   {
1929     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1930     if(!((current->is32>>rs1[i])&1))
1931     {
1932       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1933     }
1934   }
1935   else
1936   if(opcode[i]==0x11) // BC1
1937   {
1938     alloc_reg(current,i,FSREG);
1939     alloc_reg(current,i,CSREG);
1940   }
1941   //else ...
1942 }
1943
1944 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1945 {
1946   stubs[stubcount][0]=type;
1947   stubs[stubcount][1]=addr;
1948   stubs[stubcount][2]=retaddr;
1949   stubs[stubcount][3]=a;
1950   stubs[stubcount][4]=b;
1951   stubs[stubcount][5]=c;
1952   stubs[stubcount][6]=d;
1953   stubs[stubcount][7]=e;
1954   stubcount++;
1955 }
1956
1957 // Write out a single register
1958 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1959 {
1960   int hr;
1961   for(hr=0;hr<HOST_REGS;hr++) {
1962     if(hr!=EXCLUDE_REG) {
1963       if((regmap[hr]&63)==r) {
1964         if((dirty>>hr)&1) {
1965           if(regmap[hr]<64) {
1966             emit_storereg(r,hr);
1967 #ifndef FORCE32
1968             if((is32>>regmap[hr])&1) {
1969               emit_sarimm(hr,31,hr);
1970               emit_storereg(r|64,hr);
1971             }
1972 #endif
1973           }else{
1974             emit_storereg(r|64,hr);
1975           }
1976         }
1977       }
1978     }
1979   }
1980 }
1981
1982 int mchecksum()
1983 {
1984   //if(!tracedebug) return 0;
1985   int i;
1986   int sum=0;
1987   for(i=0;i<2097152;i++) {
1988     unsigned int temp=sum;
1989     sum<<=1;
1990     sum|=(~temp)>>31;
1991     sum^=((u_int *)rdram)[i];
1992   }
1993   return sum;
1994 }
1995 int rchecksum()
1996 {
1997   int i;
1998   int sum=0;
1999   for(i=0;i<64;i++)
2000     sum^=((u_int *)reg)[i];
2001   return sum;
2002 }
2003 void rlist()
2004 {
2005   int i;
2006   printf("TRACE: ");
2007   for(i=0;i<32;i++)
2008     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2009   printf("\n");
2010 #ifndef DISABLE_COP1
2011   printf("TRACE: ");
2012   for(i=0;i<32;i++)
2013     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2014   printf("\n");
2015 #endif
2016 }
2017
2018 void enabletrace()
2019 {
2020   tracedebug=1;
2021 }
2022
2023 void memdebug(int i)
2024 {
2025   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2026   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2027   //rlist();
2028   //if(tracedebug) {
2029   //if(Count>=-2084597794) {
2030   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2031   //if(0) {
2032     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2033     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2034     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2035     rlist();
2036     #ifdef __i386__
2037     printf("TRACE: %x\n",(&i)[-1]);
2038     #endif
2039     #ifdef __arm__
2040     int j;
2041     printf("TRACE: %x \n",(&j)[10]);
2042     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2043     #endif
2044     //fflush(stdout);
2045   }
2046   //printf("TRACE: %x\n",(&i)[-1]);
2047 }
2048
2049 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2050 {
2051   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2052 }
2053
2054 void alu_assemble(int i,struct regstat *i_regs)
2055 {
2056   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2057     if(rt1[i]) {
2058       signed char s1,s2,t;
2059       t=get_reg(i_regs->regmap,rt1[i]);
2060       if(t>=0) {
2061         s1=get_reg(i_regs->regmap,rs1[i]);
2062         s2=get_reg(i_regs->regmap,rs2[i]);
2063         if(rs1[i]&&rs2[i]) {
2064           assert(s1>=0);
2065           assert(s2>=0);
2066           if(opcode2[i]&2) emit_sub(s1,s2,t);
2067           else emit_add(s1,s2,t);
2068         }
2069         else if(rs1[i]) {
2070           if(s1>=0) emit_mov(s1,t);
2071           else emit_loadreg(rs1[i],t);
2072         }
2073         else if(rs2[i]) {
2074           if(s2>=0) {
2075             if(opcode2[i]&2) emit_neg(s2,t);
2076             else emit_mov(s2,t);
2077           }
2078           else {
2079             emit_loadreg(rs2[i],t);
2080             if(opcode2[i]&2) emit_neg(t,t);
2081           }
2082         }
2083         else emit_zeroreg(t);
2084       }
2085     }
2086   }
2087   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2088     if(rt1[i]) {
2089       signed char s1l,s2l,s1h,s2h,tl,th;
2090       tl=get_reg(i_regs->regmap,rt1[i]);
2091       th=get_reg(i_regs->regmap,rt1[i]|64);
2092       if(tl>=0) {
2093         s1l=get_reg(i_regs->regmap,rs1[i]);
2094         s2l=get_reg(i_regs->regmap,rs2[i]);
2095         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2096         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2097         if(rs1[i]&&rs2[i]) {
2098           assert(s1l>=0);
2099           assert(s2l>=0);
2100           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2101           else emit_adds(s1l,s2l,tl);
2102           if(th>=0) {
2103             #ifdef INVERTED_CARRY
2104             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2105             #else
2106             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2107             #endif
2108             else emit_add(s1h,s2h,th);
2109           }
2110         }
2111         else if(rs1[i]) {
2112           if(s1l>=0) emit_mov(s1l,tl);
2113           else emit_loadreg(rs1[i],tl);
2114           if(th>=0) {
2115             if(s1h>=0) emit_mov(s1h,th);
2116             else emit_loadreg(rs1[i]|64,th);
2117           }
2118         }
2119         else if(rs2[i]) {
2120           if(s2l>=0) {
2121             if(opcode2[i]&2) emit_negs(s2l,tl);
2122             else emit_mov(s2l,tl);
2123           }
2124           else {
2125             emit_loadreg(rs2[i],tl);
2126             if(opcode2[i]&2) emit_negs(tl,tl);
2127           }
2128           if(th>=0) {
2129             #ifdef INVERTED_CARRY
2130             if(s2h>=0) emit_mov(s2h,th);
2131             else emit_loadreg(rs2[i]|64,th);
2132             if(opcode2[i]&2) {
2133               emit_adcimm(-1,th); // x86 has inverted carry flag
2134               emit_not(th,th);
2135             }
2136             #else
2137             if(opcode2[i]&2) {
2138               if(s2h>=0) emit_rscimm(s2h,0,th);
2139               else {
2140                 emit_loadreg(rs2[i]|64,th);
2141                 emit_rscimm(th,0,th);
2142               }
2143             }else{
2144               if(s2h>=0) emit_mov(s2h,th);
2145               else emit_loadreg(rs2[i]|64,th);
2146             }
2147             #endif
2148           }
2149         }
2150         else {
2151           emit_zeroreg(tl);
2152           if(th>=0) emit_zeroreg(th);
2153         }
2154       }
2155     }
2156   }
2157   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2158     if(rt1[i]) {
2159       signed char s1l,s1h,s2l,s2h,t;
2160       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2161       {
2162         t=get_reg(i_regs->regmap,rt1[i]);
2163         //assert(t>=0);
2164         if(t>=0) {
2165           s1l=get_reg(i_regs->regmap,rs1[i]);
2166           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2167           s2l=get_reg(i_regs->regmap,rs2[i]);
2168           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2169           if(rs2[i]==0) // rx<r0
2170           {
2171             assert(s1h>=0);
2172             if(opcode2[i]==0x2a) // SLT
2173               emit_shrimm(s1h,31,t);
2174             else // SLTU (unsigned can not be less than zero)
2175               emit_zeroreg(t);
2176           }
2177           else if(rs1[i]==0) // r0<rx
2178           {
2179             assert(s2h>=0);
2180             if(opcode2[i]==0x2a) // SLT
2181               emit_set_gz64_32(s2h,s2l,t);
2182             else // SLTU (set if not zero)
2183               emit_set_nz64_32(s2h,s2l,t);
2184           }
2185           else {
2186             assert(s1l>=0);assert(s1h>=0);
2187             assert(s2l>=0);assert(s2h>=0);
2188             if(opcode2[i]==0x2a) // SLT
2189               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2190             else // SLTU
2191               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2192           }
2193         }
2194       } else {
2195         t=get_reg(i_regs->regmap,rt1[i]);
2196         //assert(t>=0);
2197         if(t>=0) {
2198           s1l=get_reg(i_regs->regmap,rs1[i]);
2199           s2l=get_reg(i_regs->regmap,rs2[i]);
2200           if(rs2[i]==0) // rx<r0
2201           {
2202             assert(s1l>=0);
2203             if(opcode2[i]==0x2a) // SLT
2204               emit_shrimm(s1l,31,t);
2205             else // SLTU (unsigned can not be less than zero)
2206               emit_zeroreg(t);
2207           }
2208           else if(rs1[i]==0) // r0<rx
2209           {
2210             assert(s2l>=0);
2211             if(opcode2[i]==0x2a) // SLT
2212               emit_set_gz32(s2l,t);
2213             else // SLTU (set if not zero)
2214               emit_set_nz32(s2l,t);
2215           }
2216           else{
2217             assert(s1l>=0);assert(s2l>=0);
2218             if(opcode2[i]==0x2a) // SLT
2219               emit_set_if_less32(s1l,s2l,t);
2220             else // SLTU
2221               emit_set_if_carry32(s1l,s2l,t);
2222           }
2223         }
2224       }
2225     }
2226   }
2227   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2228     if(rt1[i]) {
2229       signed char s1l,s1h,s2l,s2h,th,tl;
2230       tl=get_reg(i_regs->regmap,rt1[i]);
2231       th=get_reg(i_regs->regmap,rt1[i]|64);
2232       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2233       {
2234         assert(tl>=0);
2235         if(tl>=0) {
2236           s1l=get_reg(i_regs->regmap,rs1[i]);
2237           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2238           s2l=get_reg(i_regs->regmap,rs2[i]);
2239           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2240           if(rs1[i]&&rs2[i]) {
2241             assert(s1l>=0);assert(s1h>=0);
2242             assert(s2l>=0);assert(s2h>=0);
2243             if(opcode2[i]==0x24) { // AND
2244               emit_and(s1l,s2l,tl);
2245               emit_and(s1h,s2h,th);
2246             } else
2247             if(opcode2[i]==0x25) { // OR
2248               emit_or(s1l,s2l,tl);
2249               emit_or(s1h,s2h,th);
2250             } else
2251             if(opcode2[i]==0x26) { // XOR
2252               emit_xor(s1l,s2l,tl);
2253               emit_xor(s1h,s2h,th);
2254             } else
2255             if(opcode2[i]==0x27) { // NOR
2256               emit_or(s1l,s2l,tl);
2257               emit_or(s1h,s2h,th);
2258               emit_not(tl,tl);
2259               emit_not(th,th);
2260             }
2261           }
2262           else
2263           {
2264             if(opcode2[i]==0x24) { // AND
2265               emit_zeroreg(tl);
2266               emit_zeroreg(th);
2267             } else
2268             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2269               if(rs1[i]){
2270                 if(s1l>=0) emit_mov(s1l,tl);
2271                 else emit_loadreg(rs1[i],tl);
2272                 if(s1h>=0) emit_mov(s1h,th);
2273                 else emit_loadreg(rs1[i]|64,th);
2274               }
2275               else
2276               if(rs2[i]){
2277                 if(s2l>=0) emit_mov(s2l,tl);
2278                 else emit_loadreg(rs2[i],tl);
2279                 if(s2h>=0) emit_mov(s2h,th);
2280                 else emit_loadreg(rs2[i]|64,th);
2281               }
2282               else{
2283                 emit_zeroreg(tl);
2284                 emit_zeroreg(th);
2285               }
2286             } else
2287             if(opcode2[i]==0x27) { // NOR
2288               if(rs1[i]){
2289                 if(s1l>=0) emit_not(s1l,tl);
2290                 else{
2291                   emit_loadreg(rs1[i],tl);
2292                   emit_not(tl,tl);
2293                 }
2294                 if(s1h>=0) emit_not(s1h,th);
2295                 else{
2296                   emit_loadreg(rs1[i]|64,th);
2297                   emit_not(th,th);
2298                 }
2299               }
2300               else
2301               if(rs2[i]){
2302                 if(s2l>=0) emit_not(s2l,tl);
2303                 else{
2304                   emit_loadreg(rs2[i],tl);
2305                   emit_not(tl,tl);
2306                 }
2307                 if(s2h>=0) emit_not(s2h,th);
2308                 else{
2309                   emit_loadreg(rs2[i]|64,th);
2310                   emit_not(th,th);
2311                 }
2312               }
2313               else {
2314                 emit_movimm(-1,tl);
2315                 emit_movimm(-1,th);
2316               }
2317             }
2318           }
2319         }
2320       }
2321       else
2322       {
2323         // 32 bit
2324         if(tl>=0) {
2325           s1l=get_reg(i_regs->regmap,rs1[i]);
2326           s2l=get_reg(i_regs->regmap,rs2[i]);
2327           if(rs1[i]&&rs2[i]) {
2328             assert(s1l>=0);
2329             assert(s2l>=0);
2330             if(opcode2[i]==0x24) { // AND
2331               emit_and(s1l,s2l,tl);
2332             } else
2333             if(opcode2[i]==0x25) { // OR
2334               emit_or(s1l,s2l,tl);
2335             } else
2336             if(opcode2[i]==0x26) { // XOR
2337               emit_xor(s1l,s2l,tl);
2338             } else
2339             if(opcode2[i]==0x27) { // NOR
2340               emit_or(s1l,s2l,tl);
2341               emit_not(tl,tl);
2342             }
2343           }
2344           else
2345           {
2346             if(opcode2[i]==0x24) { // AND
2347               emit_zeroreg(tl);
2348             } else
2349             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2350               if(rs1[i]){
2351                 if(s1l>=0) emit_mov(s1l,tl);
2352                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2353               }
2354               else
2355               if(rs2[i]){
2356                 if(s2l>=0) emit_mov(s2l,tl);
2357                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2358               }
2359               else emit_zeroreg(tl);
2360             } else
2361             if(opcode2[i]==0x27) { // NOR
2362               if(rs1[i]){
2363                 if(s1l>=0) emit_not(s1l,tl);
2364                 else {
2365                   emit_loadreg(rs1[i],tl);
2366                   emit_not(tl,tl);
2367                 }
2368               }
2369               else
2370               if(rs2[i]){
2371                 if(s2l>=0) emit_not(s2l,tl);
2372                 else {
2373                   emit_loadreg(rs2[i],tl);
2374                   emit_not(tl,tl);
2375                 }
2376               }
2377               else emit_movimm(-1,tl);
2378             }
2379           }
2380         }
2381       }
2382     }
2383   }
2384 }
2385
2386 void imm16_assemble(int i,struct regstat *i_regs)
2387 {
2388   if (opcode[i]==0x0f) { // LUI
2389     if(rt1[i]) {
2390       signed char t;
2391       t=get_reg(i_regs->regmap,rt1[i]);
2392       //assert(t>=0);
2393       if(t>=0) {
2394         if(!((i_regs->isconst>>t)&1))
2395           emit_movimm(imm[i]<<16,t);
2396       }
2397     }
2398   }
2399   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2400     if(rt1[i]) {
2401       signed char s,t;
2402       t=get_reg(i_regs->regmap,rt1[i]);
2403       s=get_reg(i_regs->regmap,rs1[i]);
2404       if(rs1[i]) {
2405         //assert(t>=0);
2406         //assert(s>=0);
2407         if(t>=0) {
2408           if(!((i_regs->isconst>>t)&1)) {
2409             if(s<0) {
2410               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2411               emit_addimm(t,imm[i],t);
2412             }else{
2413               if(!((i_regs->wasconst>>s)&1))
2414                 emit_addimm(s,imm[i],t);
2415               else
2416                 emit_movimm(constmap[i][s]+imm[i],t);
2417             }
2418           }
2419         }
2420       } else {
2421         if(t>=0) {
2422           if(!((i_regs->isconst>>t)&1))
2423             emit_movimm(imm[i],t);
2424         }
2425       }
2426     }
2427   }
2428   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2429     if(rt1[i]) {
2430       signed char sh,sl,th,tl;
2431       th=get_reg(i_regs->regmap,rt1[i]|64);
2432       tl=get_reg(i_regs->regmap,rt1[i]);
2433       sh=get_reg(i_regs->regmap,rs1[i]|64);
2434       sl=get_reg(i_regs->regmap,rs1[i]);
2435       if(tl>=0) {
2436         if(rs1[i]) {
2437           assert(sh>=0);
2438           assert(sl>=0);
2439           if(th>=0) {
2440             emit_addimm64_32(sh,sl,imm[i],th,tl);
2441           }
2442           else {
2443             emit_addimm(sl,imm[i],tl);
2444           }
2445         } else {
2446           emit_movimm(imm[i],tl);
2447           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2448         }
2449       }
2450     }
2451   }
2452   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2453     if(rt1[i]) {
2454       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2455       signed char sh,sl,t;
2456       t=get_reg(i_regs->regmap,rt1[i]);
2457       sh=get_reg(i_regs->regmap,rs1[i]|64);
2458       sl=get_reg(i_regs->regmap,rs1[i]);
2459       //assert(t>=0);
2460       if(t>=0) {
2461         if(rs1[i]>0) {
2462           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2463           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2464             if(opcode[i]==0x0a) { // SLTI
2465               if(sl<0) {
2466                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2467                 emit_slti32(t,imm[i],t);
2468               }else{
2469                 emit_slti32(sl,imm[i],t);
2470               }
2471             }
2472             else { // SLTIU
2473               if(sl<0) {
2474                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2475                 emit_sltiu32(t,imm[i],t);
2476               }else{
2477                 emit_sltiu32(sl,imm[i],t);
2478               }
2479             }
2480           }else{ // 64-bit
2481             assert(sl>=0);
2482             if(opcode[i]==0x0a) // SLTI
2483               emit_slti64_32(sh,sl,imm[i],t);
2484             else // SLTIU
2485               emit_sltiu64_32(sh,sl,imm[i],t);
2486           }
2487         }else{
2488           // SLTI(U) with r0 is just stupid,
2489           // nonetheless examples can be found
2490           if(opcode[i]==0x0a) // SLTI
2491             if(0<imm[i]) emit_movimm(1,t);
2492             else emit_zeroreg(t);
2493           else // SLTIU
2494           {
2495             if(imm[i]) emit_movimm(1,t);
2496             else emit_zeroreg(t);
2497           }
2498         }
2499       }
2500     }
2501   }
2502   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2503     if(rt1[i]) {
2504       signed char sh,sl,th,tl;
2505       th=get_reg(i_regs->regmap,rt1[i]|64);
2506       tl=get_reg(i_regs->regmap,rt1[i]);
2507       sh=get_reg(i_regs->regmap,rs1[i]|64);
2508       sl=get_reg(i_regs->regmap,rs1[i]);
2509       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2510         if(opcode[i]==0x0c) //ANDI
2511         {
2512           if(rs1[i]) {
2513             if(sl<0) {
2514               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2515               emit_andimm(tl,imm[i],tl);
2516             }else{
2517               if(!((i_regs->wasconst>>sl)&1))
2518                 emit_andimm(sl,imm[i],tl);
2519               else
2520                 emit_movimm(constmap[i][sl]&imm[i],tl);
2521             }
2522           }
2523           else
2524             emit_zeroreg(tl);
2525           if(th>=0) emit_zeroreg(th);
2526         }
2527         else
2528         {
2529           if(rs1[i]) {
2530             if(sl<0) {
2531               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2532             }
2533             if(th>=0) {
2534               if(sh<0) {
2535                 emit_loadreg(rs1[i]|64,th);
2536               }else{
2537                 emit_mov(sh,th);
2538               }
2539             }
2540             if(opcode[i]==0x0d) //ORI
2541             if(sl<0) {
2542               emit_orimm(tl,imm[i],tl);
2543             }else{
2544               if(!((i_regs->wasconst>>sl)&1))
2545                 emit_orimm(sl,imm[i],tl);
2546               else
2547                 emit_movimm(constmap[i][sl]|imm[i],tl);
2548             }
2549             if(opcode[i]==0x0e) //XORI
2550             if(sl<0) {
2551               emit_xorimm(tl,imm[i],tl);
2552             }else{
2553               if(!((i_regs->wasconst>>sl)&1))
2554                 emit_xorimm(sl,imm[i],tl);
2555               else
2556                 emit_movimm(constmap[i][sl]^imm[i],tl);
2557             }
2558           }
2559           else {
2560             emit_movimm(imm[i],tl);
2561             if(th>=0) emit_zeroreg(th);
2562           }
2563         }
2564       }
2565     }
2566   }
2567 }
2568
2569 void shiftimm_assemble(int i,struct regstat *i_regs)
2570 {
2571   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2572   {
2573     if(rt1[i]) {
2574       signed char s,t;
2575       t=get_reg(i_regs->regmap,rt1[i]);
2576       s=get_reg(i_regs->regmap,rs1[i]);
2577       //assert(t>=0);
2578       if(t>=0){
2579         if(rs1[i]==0)
2580         {
2581           emit_zeroreg(t);
2582         }
2583         else
2584         {
2585           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2586           if(imm[i]) {
2587             if(opcode2[i]==0) // SLL
2588             {
2589               emit_shlimm(s<0?t:s,imm[i],t);
2590             }
2591             if(opcode2[i]==2) // SRL
2592             {
2593               emit_shrimm(s<0?t:s,imm[i],t);
2594             }
2595             if(opcode2[i]==3) // SRA
2596             {
2597               emit_sarimm(s<0?t:s,imm[i],t);
2598             }
2599           }else{
2600             // Shift by zero
2601             if(s>=0 && s!=t) emit_mov(s,t);
2602           }
2603         }
2604       }
2605       //emit_storereg(rt1[i],t); //DEBUG
2606     }
2607   }
2608   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2609   {
2610     if(rt1[i]) {
2611       signed char sh,sl,th,tl;
2612       th=get_reg(i_regs->regmap,rt1[i]|64);
2613       tl=get_reg(i_regs->regmap,rt1[i]);
2614       sh=get_reg(i_regs->regmap,rs1[i]|64);
2615       sl=get_reg(i_regs->regmap,rs1[i]);
2616       if(tl>=0) {
2617         if(rs1[i]==0)
2618         {
2619           emit_zeroreg(tl);
2620           if(th>=0) emit_zeroreg(th);
2621         }
2622         else
2623         {
2624           assert(sl>=0);
2625           assert(sh>=0);
2626           if(imm[i]) {
2627             if(opcode2[i]==0x38) // DSLL
2628             {
2629               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2630               emit_shlimm(sl,imm[i],tl);
2631             }
2632             if(opcode2[i]==0x3a) // DSRL
2633             {
2634               emit_shrdimm(sl,sh,imm[i],tl);
2635               if(th>=0) emit_shrimm(sh,imm[i],th);
2636             }
2637             if(opcode2[i]==0x3b) // DSRA
2638             {
2639               emit_shrdimm(sl,sh,imm[i],tl);
2640               if(th>=0) emit_sarimm(sh,imm[i],th);
2641             }
2642           }else{
2643             // Shift by zero
2644             if(sl!=tl) emit_mov(sl,tl);
2645             if(th>=0&&sh!=th) emit_mov(sh,th);
2646           }
2647         }
2648       }
2649     }
2650   }
2651   if(opcode2[i]==0x3c) // DSLL32
2652   {
2653     if(rt1[i]) {
2654       signed char sl,tl,th;
2655       tl=get_reg(i_regs->regmap,rt1[i]);
2656       th=get_reg(i_regs->regmap,rt1[i]|64);
2657       sl=get_reg(i_regs->regmap,rs1[i]);
2658       if(th>=0||tl>=0){
2659         assert(tl>=0);
2660         assert(th>=0);
2661         assert(sl>=0);
2662         emit_mov(sl,th);
2663         emit_zeroreg(tl);
2664         if(imm[i]>32)
2665         {
2666           emit_shlimm(th,imm[i]&31,th);
2667         }
2668       }
2669     }
2670   }
2671   if(opcode2[i]==0x3e) // DSRL32
2672   {
2673     if(rt1[i]) {
2674       signed char sh,tl,th;
2675       tl=get_reg(i_regs->regmap,rt1[i]);
2676       th=get_reg(i_regs->regmap,rt1[i]|64);
2677       sh=get_reg(i_regs->regmap,rs1[i]|64);
2678       if(tl>=0){
2679         assert(sh>=0);
2680         emit_mov(sh,tl);
2681         if(th>=0) emit_zeroreg(th);
2682         if(imm[i]>32)
2683         {
2684           emit_shrimm(tl,imm[i]&31,tl);
2685         }
2686       }
2687     }
2688   }
2689   if(opcode2[i]==0x3f) // DSRA32
2690   {
2691     if(rt1[i]) {
2692       signed char sh,tl;
2693       tl=get_reg(i_regs->regmap,rt1[i]);
2694       sh=get_reg(i_regs->regmap,rs1[i]|64);
2695       if(tl>=0){
2696         assert(sh>=0);
2697         emit_mov(sh,tl);
2698         if(imm[i]>32)
2699         {
2700           emit_sarimm(tl,imm[i]&31,tl);
2701         }
2702       }
2703     }
2704   }
2705 }
2706
2707 #ifndef shift_assemble
2708 void shift_assemble(int i,struct regstat *i_regs)
2709 {
2710   printf("Need shift_assemble for this architecture.\n");
2711   exit(1);
2712 }
2713 #endif
2714
2715 void load_assemble(int i,struct regstat *i_regs)
2716 {
2717   int s,th,tl,addr,map=-1;
2718   int offset;
2719   int jaddr=0;
2720   int memtarget=0,c=0;
2721   u_int hr,reglist=0;
2722   th=get_reg(i_regs->regmap,rt1[i]|64);
2723   tl=get_reg(i_regs->regmap,rt1[i]);
2724   s=get_reg(i_regs->regmap,rs1[i]);
2725   offset=imm[i];
2726   for(hr=0;hr<HOST_REGS;hr++) {
2727     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2728   }
2729   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2730   if(s>=0) {
2731     c=(i_regs->wasconst>>s)&1;
2732     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2733     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2734   }
2735   //printf("load_assemble: c=%d\n",c);
2736   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2737   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2738 #ifdef PCSX
2739   if(tl<0) {
2740     if(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) {
2741       // could be FIFO, must perform the read
2742       assem_debug("(forced read)\n");
2743       tl=get_reg(i_regs->regmap,-1);
2744       assert(tl>=0);
2745     }
2746   }
2747   if(offset||s<0||c) addr=tl;
2748   else addr=s;
2749 #endif
2750   if(tl>=0) {
2751     //assert(tl>=0);
2752     //assert(rt1[i]);
2753     reglist&=~(1<<tl);
2754     if(th>=0) reglist&=~(1<<th);
2755     if(!using_tlb) {
2756       if(!c) {
2757 //#define R29_HACK 1
2758         #ifdef R29_HACK
2759         // Strmnnrmn's speed hack
2760         if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2761         #endif
2762         {
2763           emit_cmpimm(addr,0x800000);
2764           jaddr=(int)out;
2765           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2766           // Hint to branch predictor that the branch is unlikely to be taken
2767           if(rs1[i]>=28)
2768             emit_jno_unlikely(0);
2769           else
2770           #endif
2771           emit_jno(0);
2772         }
2773       }
2774     }else{ // using tlb
2775       int x=0;
2776       if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2777       if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2778       map=get_reg(i_regs->regmap,TLREG);
2779       assert(map>=0);
2780       map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2781       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2782     }
2783     if (opcode[i]==0x20) { // LB
2784       if(!c||memtarget) {
2785         #ifdef HOST_IMM_ADDR32
2786         if(c)
2787           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2788         else
2789         #endif
2790         {
2791           //emit_xorimm(addr,3,tl);
2792           //gen_tlb_addr_r(tl,map);
2793           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2794           int x=0;
2795 #ifdef BIG_ENDIAN_MIPS
2796           if(!c) emit_xorimm(addr,3,tl);
2797           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2798 #else
2799           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2800           else if (tl!=addr) emit_mov(addr,tl);
2801 #endif
2802           emit_movsbl_indexed_tlb(x,tl,map,tl);
2803         }
2804         if(jaddr)
2805           add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2806       }
2807       else
2808         inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2809     }
2810     if (opcode[i]==0x21) { // LH
2811       if(!c||memtarget) {
2812         #ifdef HOST_IMM_ADDR32
2813         if(c)
2814           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2815         else
2816         #endif
2817         {
2818           int x=0;
2819 #ifdef BIG_ENDIAN_MIPS
2820           if(!c) emit_xorimm(addr,2,tl);
2821           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2822 #else
2823           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2824           else if (tl!=addr) emit_mov(addr,tl);
2825 #endif
2826           //#ifdef
2827           //emit_movswl_indexed_tlb(x,tl,map,tl);
2828           //else
2829           if(map>=0) {
2830             gen_tlb_addr_r(tl,map);
2831             emit_movswl_indexed(x,tl,tl);
2832           }else
2833             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2834         }
2835         if(jaddr)
2836           add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2837       }
2838       else
2839         inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2840     }
2841     if (opcode[i]==0x23) { // LW
2842       if(!c||memtarget) {
2843         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2844         #ifdef HOST_IMM_ADDR32
2845         if(c)
2846           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2847         else
2848         #endif
2849         emit_readword_indexed_tlb(0,addr,map,tl);
2850         if(jaddr)
2851           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2852       }
2853       else
2854         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2855     }
2856     if (opcode[i]==0x24) { // LBU
2857       if(!c||memtarget) {
2858         #ifdef HOST_IMM_ADDR32
2859         if(c)
2860           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2861         else
2862         #endif
2863         {
2864           //emit_xorimm(addr,3,tl);
2865           //gen_tlb_addr_r(tl,map);
2866           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2867           int x=0;
2868 #ifdef BIG_ENDIAN_MIPS
2869           if(!c) emit_xorimm(addr,3,tl);
2870           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2871 #else
2872           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2873           else if (tl!=addr) emit_mov(addr,tl);
2874 #endif
2875           emit_movzbl_indexed_tlb(x,tl,map,tl);
2876         }
2877         if(jaddr)
2878           add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2879       }
2880       else
2881         inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2882     }
2883     if (opcode[i]==0x25) { // LHU
2884       if(!c||memtarget) {
2885         #ifdef HOST_IMM_ADDR32
2886         if(c)
2887           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2888         else
2889         #endif
2890         {
2891           int x=0;
2892 #ifdef BIG_ENDIAN_MIPS
2893           if(!c) emit_xorimm(addr,2,tl);
2894           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2895 #else
2896           if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2897           else if (tl!=addr) emit_mov(addr,tl);
2898 #endif
2899           //#ifdef
2900           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2901           //#else
2902           if(map>=0) {
2903             gen_tlb_addr_r(tl,map);
2904             emit_movzwl_indexed(x,tl,tl);
2905           }else
2906             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2907           if(jaddr)
2908             add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2909         }
2910       }
2911       else
2912         inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2913     }
2914     if (opcode[i]==0x27) { // LWU
2915       assert(th>=0);
2916       if(!c||memtarget) {
2917         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2918         #ifdef HOST_IMM_ADDR32
2919         if(c)
2920           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2921         else
2922         #endif
2923         emit_readword_indexed_tlb(0,addr,map,tl);
2924         if(jaddr)
2925           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2926       }
2927       else {
2928         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2929       }
2930       emit_zeroreg(th);
2931     }
2932     if (opcode[i]==0x37) { // LD
2933       if(!c||memtarget) {
2934         //gen_tlb_addr_r(tl,map);
2935         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2936         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2937         #ifdef HOST_IMM_ADDR32
2938         if(c)
2939           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2940         else
2941         #endif
2942         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2943         if(jaddr)
2944           add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2945       }
2946       else
2947         inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2948     }
2949     //emit_storereg(rt1[i],tl); // DEBUG
2950   }
2951   //if(opcode[i]==0x23)
2952   //if(opcode[i]==0x24)
2953   //if(opcode[i]==0x23||opcode[i]==0x24)
2954   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2955   {
2956     //emit_pusha();
2957     save_regs(0x100f);
2958         emit_readword((int)&last_count,ECX);
2959         #ifdef __i386__
2960         if(get_reg(i_regs->regmap,CCREG)<0)
2961           emit_loadreg(CCREG,HOST_CCREG);
2962         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2963         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2964         emit_writeword(HOST_CCREG,(int)&Count);
2965         #endif
2966         #ifdef __arm__
2967         if(get_reg(i_regs->regmap,CCREG)<0)
2968           emit_loadreg(CCREG,0);
2969         else
2970           emit_mov(HOST_CCREG,0);
2971         emit_add(0,ECX,0);
2972         emit_addimm(0,2*ccadj[i],0);
2973         emit_writeword(0,(int)&Count);
2974         #endif
2975     emit_call((int)memdebug);
2976     //emit_popa();
2977     restore_regs(0x100f);
2978   }/**/
2979 }
2980
2981 #ifndef loadlr_assemble
2982 void loadlr_assemble(int i,struct regstat *i_regs)
2983 {
2984   printf("Need loadlr_assemble for this architecture.\n");
2985   exit(1);
2986 }
2987 #endif
2988
2989 void store_assemble(int i,struct regstat *i_regs)
2990 {
2991   int s,th,tl,map=-1;
2992   int addr,temp;
2993   int offset;
2994   int jaddr=0,jaddr2,type;
2995   int memtarget=0,c=0;
2996   int agr=AGEN1+(i&1);
2997   u_int hr,reglist=0;
2998   th=get_reg(i_regs->regmap,rs2[i]|64);
2999   tl=get_reg(i_regs->regmap,rs2[i]);
3000   s=get_reg(i_regs->regmap,rs1[i]);
3001   temp=get_reg(i_regs->regmap,agr);
3002   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3003   offset=imm[i];
3004   if(s>=0) {
3005     c=(i_regs->wasconst>>s)&1;
3006     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3007     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3008   }
3009   assert(tl>=0);
3010   assert(temp>=0);
3011   for(hr=0;hr<HOST_REGS;hr++) {
3012     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3013   }
3014   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3015   if(offset||s<0||c) addr=temp;
3016   else addr=s;
3017   if(!using_tlb) {
3018     if(!c) {
3019       #ifdef R29_HACK
3020       // Strmnnrmn's speed hack
3021       memtarget=1;
3022       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3023       #endif
3024       emit_cmpimm(addr,0x800000);
3025       #ifdef DESTRUCTIVE_SHIFT
3026       if(s==addr) emit_mov(s,temp);
3027       #endif
3028       #ifdef R29_HACK
3029       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3030       #endif
3031       {
3032         jaddr=(int)out;
3033         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3034         // Hint to branch predictor that the branch is unlikely to be taken
3035         if(rs1[i]>=28)
3036           emit_jno_unlikely(0);
3037         else
3038         #endif
3039         emit_jno(0);
3040       }
3041     }
3042   }else{ // using tlb
3043     int x=0;
3044     if (opcode[i]==0x28) x=3; // SB
3045     if (opcode[i]==0x29) x=2; // SH
3046     map=get_reg(i_regs->regmap,TLREG);
3047     assert(map>=0);
3048     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3049     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3050   }
3051
3052   if (opcode[i]==0x28) { // SB
3053     if(!c||memtarget) {
3054       int x=0;
3055 #ifdef BIG_ENDIAN_MIPS
3056       if(!c) emit_xorimm(addr,3,temp);
3057       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3058 #else
3059       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3060       else if (addr!=temp) emit_mov(addr,temp);
3061 #endif
3062       //gen_tlb_addr_w(temp,map);
3063       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3064       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3065     }
3066     type=STOREB_STUB;
3067   }
3068   if (opcode[i]==0x29) { // SH
3069     if(!c||memtarget) {
3070       int x=0;
3071 #ifdef BIG_ENDIAN_MIPS
3072       if(!c) emit_xorimm(addr,2,temp);
3073       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3074 #else
3075       if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3076       else if (addr!=temp) emit_mov(addr,temp);
3077 #endif
3078       //#ifdef
3079       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3080       //#else
3081       if(map>=0) {
3082         gen_tlb_addr_w(temp,map);
3083         emit_writehword_indexed(tl,x,temp);
3084       }else
3085         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3086     }
3087     type=STOREH_STUB;
3088   }
3089   if (opcode[i]==0x2B) { // SW
3090     if(!c||memtarget)
3091       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3092       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3093     type=STOREW_STUB;
3094   }
3095   if (opcode[i]==0x3F) { // SD
3096     if(!c||memtarget) {
3097       if(rs2[i]) {
3098         assert(th>=0);
3099         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3100         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3101         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3102       }else{
3103         // Store zero
3104         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3105         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3106         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3107       }
3108     }
3109     type=STORED_STUB;
3110   }
3111   if(!using_tlb&&(!c||memtarget))
3112     // addr could be a temp, make sure it survives STORE*_STUB
3113     reglist|=1<<addr;
3114   if(jaddr) {
3115     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3116   } else if(!memtarget) {
3117     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3118   }
3119   if(!using_tlb) {
3120     if(!c||memtarget) {
3121       #ifdef DESTRUCTIVE_SHIFT
3122       // The x86 shift operation is 'destructive'; it overwrites the
3123       // source register, so we need to make a copy first and use that.
3124       addr=temp;
3125       #endif
3126       #if defined(HOST_IMM8)
3127       int ir=get_reg(i_regs->regmap,INVCP);
3128       assert(ir>=0);
3129       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3130       #else
3131       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3132       #endif
3133       jaddr2=(int)out;
3134       emit_jne(0);
3135       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3136     }
3137   }
3138   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3139   //if(opcode[i]==0x2B || opcode[i]==0x28)
3140   //if(opcode[i]==0x2B || opcode[i]==0x29)
3141   //if(opcode[i]==0x2B)
3142   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3143   {
3144     //emit_pusha();
3145     save_regs(0x100f);
3146         emit_readword((int)&last_count,ECX);
3147         #ifdef __i386__
3148         if(get_reg(i_regs->regmap,CCREG)<0)
3149           emit_loadreg(CCREG,HOST_CCREG);
3150         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3151         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3152         emit_writeword(HOST_CCREG,(int)&Count);
3153         #endif
3154         #ifdef __arm__
3155         if(get_reg(i_regs->regmap,CCREG)<0)
3156           emit_loadreg(CCREG,0);
3157         else
3158           emit_mov(HOST_CCREG,0);
3159         emit_add(0,ECX,0);
3160         emit_addimm(0,2*ccadj[i],0);
3161         emit_writeword(0,(int)&Count);
3162         #endif
3163     emit_call((int)memdebug);
3164     //emit_popa();
3165     restore_regs(0x100f);
3166   }/**/
3167 }
3168
3169 void storelr_assemble(int i,struct regstat *i_regs)
3170 {
3171   int s,th,tl;
3172   int temp;
3173   int temp2;
3174   int offset;
3175   int jaddr=0,jaddr2;
3176   int case1,case2,case3;
3177   int done0,done1,done2;
3178   int memtarget,c=0;
3179   u_int hr,reglist=0;
3180   th=get_reg(i_regs->regmap,rs2[i]|64);
3181   tl=get_reg(i_regs->regmap,rs2[i]);
3182   s=get_reg(i_regs->regmap,rs1[i]);
3183   temp=get_reg(i_regs->regmap,-1);
3184   offset=imm[i];
3185   if(s>=0) {
3186     c=(i_regs->isconst>>s)&1;
3187     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3188     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3189   }
3190   assert(tl>=0);
3191   for(hr=0;hr<HOST_REGS;hr++) {
3192     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3193   }
3194   if(tl>=0) {
3195     assert(temp>=0);
3196     if(!using_tlb) {
3197       if(!c) {
3198         emit_cmpimm(s<0||offset?temp:s,0x800000);
3199         if(!offset&&s!=temp) emit_mov(s,temp);
3200         jaddr=(int)out;
3201         emit_jno(0);
3202       }
3203       else
3204       {
3205         if(!memtarget||!rs1[i]) {
3206           jaddr=(int)out;
3207           emit_jmp(0);
3208         }
3209       }
3210       if((u_int)rdram!=0x80000000)
3211         emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3212     }else{ // using tlb
3213       int map=get_reg(i_regs->regmap,TLREG);
3214       assert(map>=0);
3215       map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3216       if(!c&&!offset&&s>=0) emit_mov(s,temp);
3217       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3218       if(!jaddr&&!memtarget) {
3219         jaddr=(int)out;
3220         emit_jmp(0);
3221       }
3222       gen_tlb_addr_w(temp,map);
3223     }
3224
3225     if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3226       temp2=get_reg(i_regs->regmap,FTEMP);
3227       if(!rs2[i]) temp2=th=tl;
3228     }
3229
3230 #ifndef BIG_ENDIAN_MIPS
3231     emit_xorimm(temp,3,temp);
3232 #endif
3233     emit_testimm(temp,2);
3234     case2=(int)out;
3235     emit_jne(0);
3236     emit_testimm(temp,1);
3237     case1=(int)out;
3238     emit_jne(0);
3239     // 0
3240     if (opcode[i]==0x2A) { // SWL
3241       emit_writeword_indexed(tl,0,temp);
3242     }
3243     if (opcode[i]==0x2E) { // SWR
3244       emit_writebyte_indexed(tl,3,temp);
3245     }
3246     if (opcode[i]==0x2C) { // SDL
3247       emit_writeword_indexed(th,0,temp);
3248       if(rs2[i]) emit_mov(tl,temp2);
3249     }
3250     if (opcode[i]==0x2D) { // SDR
3251       emit_writebyte_indexed(tl,3,temp);
3252       if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3253     }
3254     done0=(int)out;
3255     emit_jmp(0);
3256     // 1
3257     set_jump_target(case1,(int)out);
3258     if (opcode[i]==0x2A) { // SWL
3259       // Write 3 msb into three least significant bytes
3260       if(rs2[i]) emit_rorimm(tl,8,tl);
3261       emit_writehword_indexed(tl,-1,temp);
3262       if(rs2[i]) emit_rorimm(tl,16,tl);
3263       emit_writebyte_indexed(tl,1,temp);
3264       if(rs2[i]) emit_rorimm(tl,8,tl);
3265     }
3266     if (opcode[i]==0x2E) { // SWR
3267       // Write two lsb into two most significant bytes
3268       emit_writehword_indexed(tl,1,temp);
3269     }
3270     if (opcode[i]==0x2C) { // SDL
3271       if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3272       // Write 3 msb into three least significant bytes
3273       if(rs2[i]) emit_rorimm(th,8,th);
3274       emit_writehword_indexed(th,-1,temp);
3275       if(rs2[i]) emit_rorimm(th,16,th);
3276       emit_writebyte_indexed(th,1,temp);
3277       if(rs2[i]) emit_rorimm(th,8,th);
3278     }
3279     if (opcode[i]==0x2D) { // SDR
3280       if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3281       // Write two lsb into two most significant bytes
3282       emit_writehword_indexed(tl,1,temp);
3283     }
3284     done1=(int)out;
3285     emit_jmp(0);
3286     // 2
3287     set_jump_target(case2,(int)out);
3288     emit_testimm(temp,1);
3289     case3=(int)out;
3290     emit_jne(0);
3291     if (opcode[i]==0x2A) { // SWL
3292       // Write two msb into two least significant bytes
3293       if(rs2[i]) emit_rorimm(tl,16,tl);
3294       emit_writehword_indexed(tl,-2,temp);
3295       if(rs2[i]) emit_rorimm(tl,16,tl);
3296     }
3297     if (opcode[i]==0x2E) { // SWR
3298       // Write 3 lsb into three most significant bytes
3299       emit_writebyte_indexed(tl,-1,temp);
3300       if(rs2[i]) emit_rorimm(tl,8,tl);
3301       emit_writehword_indexed(tl,0,temp);
3302       if(rs2[i]) emit_rorimm(tl,24,tl);
3303     }
3304     if (opcode[i]==0x2C) { // SDL
3305       if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3306       // Write two msb into two least significant bytes
3307       if(rs2[i]) emit_rorimm(th,16,th);
3308       emit_writehword_indexed(th,-2,temp);
3309       if(rs2[i]) emit_rorimm(th,16,th);
3310     }
3311     if (opcode[i]==0x2D) { // SDR
3312       if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3313       // Write 3 lsb into three most significant bytes
3314       emit_writebyte_indexed(tl,-1,temp);
3315       if(rs2[i]) emit_rorimm(tl,8,tl);
3316       emit_writehword_indexed(tl,0,temp);
3317       if(rs2[i]) emit_rorimm(tl,24,tl);
3318     }
3319     done2=(int)out;
3320     emit_jmp(0);
3321     // 3
3322     set_jump_target(case3,(int)out);
3323     if (opcode[i]==0x2A) { // SWL
3324       // Write msb into least significant byte
3325       if(rs2[i]) emit_rorimm(tl,24,tl);
3326       emit_writebyte_indexed(tl,-3,temp);
3327       if(rs2[i]) emit_rorimm(tl,8,tl);
3328     }
3329     if (opcode[i]==0x2E) { // SWR
3330       // Write entire word
3331       emit_writeword_indexed(tl,-3,temp);
3332     }
3333     if (opcode[i]==0x2C) { // SDL
3334       if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3335       // Write msb into least significant byte
3336       if(rs2[i]) emit_rorimm(th,24,th);
3337       emit_writebyte_indexed(th,-3,temp);
3338       if(rs2[i]) emit_rorimm(th,8,th);
3339     }
3340     if (opcode[i]==0x2D) { // SDR
3341       if(rs2[i]) emit_mov(th,temp2);
3342       // Write entire word
3343       emit_writeword_indexed(tl,-3,temp);
3344     }
3345     set_jump_target(done0,(int)out);
3346     set_jump_target(done1,(int)out);
3347     set_jump_target(done2,(int)out);
3348     if (opcode[i]==0x2C) { // SDL
3349       emit_testimm(temp,4);
3350       done0=(int)out;
3351       emit_jne(0);
3352       emit_andimm(temp,~3,temp);
3353       emit_writeword_indexed(temp2,4,temp);
3354       set_jump_target(done0,(int)out);
3355     }
3356     if (opcode[i]==0x2D) { // SDR
3357       emit_testimm(temp,4);
3358       done0=(int)out;
3359       emit_jeq(0);
3360       emit_andimm(temp,~3,temp);
3361       emit_writeword_indexed(temp2,-4,temp);
3362       set_jump_target(done0,(int)out);
3363     }
3364     if(!c||!memtarget)
3365       add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3366   }
3367   if(!using_tlb) {
3368     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3369     #if defined(HOST_IMM8)
3370     int ir=get_reg(i_regs->regmap,INVCP);
3371     assert(ir>=0);
3372     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3373     #else
3374     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3375     #endif
3376     jaddr2=(int)out;
3377     emit_jne(0);
3378     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3379   }
3380   /*
3381     emit_pusha();
3382     //save_regs(0x100f);
3383         emit_readword((int)&last_count,ECX);
3384         if(get_reg(i_regs->regmap,CCREG)<0)
3385           emit_loadreg(CCREG,HOST_CCREG);
3386         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3387         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3388         emit_writeword(HOST_CCREG,(int)&Count);
3389     emit_call((int)memdebug);
3390     emit_popa();
3391     //restore_regs(0x100f);
3392   /**/
3393 }
3394
3395 void c1ls_assemble(int i,struct regstat *i_regs)
3396 {
3397 #ifndef DISABLE_COP1
3398   int s,th,tl;
3399   int temp,ar;
3400   int map=-1;
3401   int offset;
3402   int c=0;
3403   int jaddr,jaddr2=0,jaddr3,type;
3404   int agr=AGEN1+(i&1);
3405   u_int hr,reglist=0;
3406   th=get_reg(i_regs->regmap,FTEMP|64);
3407   tl=get_reg(i_regs->regmap,FTEMP);
3408   s=get_reg(i_regs->regmap,rs1[i]);
3409   temp=get_reg(i_regs->regmap,agr);
3410   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3411   offset=imm[i];
3412   assert(tl>=0);
3413   assert(rs1[i]>0);
3414   assert(temp>=0);
3415   for(hr=0;hr<HOST_REGS;hr++) {
3416     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3417   }
3418   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3419   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3420   {
3421     // Loads use a temporary register which we need to save
3422     reglist|=1<<temp;
3423   }
3424   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3425     ar=temp;
3426   else // LWC1/LDC1
3427     ar=tl;
3428   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3429   //else c=(i_regs->wasconst>>s)&1;
3430   if(s>=0) c=(i_regs->wasconst>>s)&1;
3431   // Check cop1 unusable
3432   if(!cop1_usable) {
3433     signed char rs=get_reg(i_regs->regmap,CSREG);
3434     assert(rs>=0);
3435     emit_testimm(rs,0x20000000);
3436     jaddr=(int)out;
3437     emit_jeq(0);
3438     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3439     cop1_usable=1;
3440   }
3441   if (opcode[i]==0x39) { // SWC1 (get float address)
3442     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3443   }
3444   if (opcode[i]==0x3D) { // SDC1 (get double address)
3445     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3446   }
3447   // Generate address + offset
3448   if(!using_tlb) {
3449     if(!c)
3450       emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3451   }
3452   else
3453   {
3454     map=get_reg(i_regs->regmap,TLREG);
3455     assert(map>=0);
3456     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3457       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3458     }
3459     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3460       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3461     }
3462   }
3463   if (opcode[i]==0x39) { // SWC1 (read float)
3464     emit_readword_indexed(0,tl,tl);
3465   }
3466   if (opcode[i]==0x3D) { // SDC1 (read double)
3467     emit_readword_indexed(4,tl,th);
3468     emit_readword_indexed(0,tl,tl);
3469   }
3470   if (opcode[i]==0x31) { // LWC1 (get target address)
3471     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3472   }
3473   if (opcode[i]==0x35) { // LDC1 (get target address)
3474     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3475   }
3476   if(!using_tlb) {
3477     if(!c) {
3478       jaddr2=(int)out;
3479       emit_jno(0);
3480     }
3481     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3482       jaddr2=(int)out;
3483       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3484     }
3485     #ifdef DESTRUCTIVE_SHIFT
3486     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3487       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3488     }
3489     #endif
3490   }else{
3491     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3492       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3493     }
3494     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3495       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3496     }
3497   }
3498   if (opcode[i]==0x31) { // LWC1
3499     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3500     //gen_tlb_addr_r(ar,map);
3501     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3502     #ifdef HOST_IMM_ADDR32
3503     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3504     else
3505     #endif
3506     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3507     type=LOADW_STUB;
3508   }
3509   if (opcode[i]==0x35) { // LDC1
3510     assert(th>=0);
3511     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3512     //gen_tlb_addr_r(ar,map);
3513     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3514     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3515     #ifdef HOST_IMM_ADDR32
3516     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3517     else
3518     #endif
3519     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3520     type=LOADD_STUB;
3521   }
3522   if (opcode[i]==0x39) { // SWC1
3523     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3524     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3525     type=STOREW_STUB;
3526   }
3527   if (opcode[i]==0x3D) { // SDC1
3528     assert(th>=0);
3529     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3530     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3531     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3532     type=STORED_STUB;
3533   }
3534   if(!using_tlb) {
3535     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3536       #ifndef DESTRUCTIVE_SHIFT
3537       temp=offset||c||s<0?ar:s;
3538       #endif
3539       #if defined(HOST_IMM8)
3540       int ir=get_reg(i_regs->regmap,INVCP);
3541       assert(ir>=0);
3542       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3543       #else
3544       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3545       #endif
3546       jaddr3=(int)out;
3547       emit_jne(0);
3548       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3549     }
3550   }
3551   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3552   if (opcode[i]==0x31) { // LWC1 (write float)
3553     emit_writeword_indexed(tl,0,temp);
3554   }
3555   if (opcode[i]==0x35) { // LDC1 (write double)
3556     emit_writeword_indexed(th,4,temp);
3557     emit_writeword_indexed(tl,0,temp);
3558   }
3559   //if(opcode[i]==0x39)
3560   /*if(opcode[i]==0x39||opcode[i]==0x31)
3561   {
3562     emit_pusha();
3563         emit_readword((int)&last_count,ECX);
3564         if(get_reg(i_regs->regmap,CCREG)<0)
3565           emit_loadreg(CCREG,HOST_CCREG);
3566         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3567         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3568         emit_writeword(HOST_CCREG,(int)&Count);
3569     emit_call((int)memdebug);
3570     emit_popa();
3571   }/**/
3572 #else
3573   cop1_unusable(i, i_regs);
3574 #endif
3575 }
3576
3577 void c2ls_assemble(int i,struct regstat *i_regs)
3578 {
3579   int s,tl;
3580   int ar;
3581   int offset;
3582   int c=0;
3583   int jaddr,jaddr2=0,jaddr3,type;
3584   int agr=AGEN1+(i&1);
3585   u_int hr,reglist=0;
3586   u_int copr=(source[i]>>16)&0x1f;
3587   s=get_reg(i_regs->regmap,rs1[i]);
3588   tl=get_reg(i_regs->regmap,FTEMP);
3589   offset=imm[i];
3590   assert(rs1[i]>0);
3591   assert(tl>=0);
3592   assert(!using_tlb);
3593
3594   for(hr=0;hr<HOST_REGS;hr++) {
3595     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3596   }
3597   if(i_regs->regmap[HOST_CCREG]==CCREG)
3598     reglist&=~(1<<HOST_CCREG);
3599
3600   // get the address
3601   if (opcode[i]==0x3a) { // SWC2
3602     ar=get_reg(i_regs->regmap,agr);
3603     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3604     reglist|=1<<ar;
3605   } else { // LWC2
3606     ar=tl;
3607   }
3608   if (!offset&&!c&&s>=0) ar=s;
3609   assert(ar>=0);
3610
3611   if (opcode[i]==0x3a) { // SWC2
3612     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3613   }
3614   if(s>=0) c=(i_regs->wasconst>>s)&1;
3615   if(!c) {
3616     emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3617     jaddr2=(int)out;
3618     emit_jno(0);
3619   }
3620   else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3621     jaddr2=(int)out;
3622     emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3623   }
3624   if (opcode[i]==0x32) { // LWC2
3625     #ifdef HOST_IMM_ADDR32
3626     if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3627     else
3628     #endif
3629     emit_readword_indexed(0,ar,tl);
3630     type=LOADW_STUB;
3631   }
3632   if (opcode[i]==0x3a) { // SWC2
3633 #ifdef DESTRUCTIVE_SHIFT
3634     if(!offset&&!c&&s>=0) emit_mov(s,ar);
3635 #endif
3636     emit_writeword_indexed(tl,0,ar);
3637     type=STOREW_STUB;
3638   }
3639   if(jaddr2)
3640     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3641   if (opcode[i]==0x3a) { // SWC2
3642 #if defined(HOST_IMM8)
3643     int ir=get_reg(i_regs->regmap,INVCP);
3644     assert(ir>=0);
3645     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3646 #else
3647     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3648 #endif
3649     jaddr3=(int)out;
3650     emit_jne(0);
3651     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3652   }
3653   if (opcode[i]==0x32) { // LWC2
3654     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3655   }
3656 }
3657
3658 #ifndef multdiv_assemble
3659 void multdiv_assemble(int i,struct regstat *i_regs)
3660 {
3661   printf("Need multdiv_assemble for this architecture.\n");
3662   exit(1);
3663 }
3664 #endif
3665
3666 void mov_assemble(int i,struct regstat *i_regs)
3667 {
3668   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3669   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3670   assert(rt1[i]>0);
3671   if(rt1[i]) {
3672     signed char sh,sl,th,tl;
3673     th=get_reg(i_regs->regmap,rt1[i]|64);
3674     tl=get_reg(i_regs->regmap,rt1[i]);
3675     //assert(tl>=0);
3676     if(tl>=0) {
3677       sh=get_reg(i_regs->regmap,rs1[i]|64);
3678       sl=get_reg(i_regs->regmap,rs1[i]);
3679       if(sl>=0) emit_mov(sl,tl);
3680       else emit_loadreg(rs1[i],tl);
3681       if(th>=0) {
3682         if(sh>=0) emit_mov(sh,th);
3683         else emit_loadreg(rs1[i]|64,th);
3684       }
3685     }
3686   }
3687 }
3688
3689 #ifndef fconv_assemble
3690 void fconv_assemble(int i,struct regstat *i_regs)
3691 {
3692   printf("Need fconv_assemble for this architecture.\n");
3693   exit(1);
3694 }
3695 #endif
3696
3697 #if 0
3698 void float_assemble(int i,struct regstat *i_regs)
3699 {
3700   printf("Need float_assemble for this architecture.\n");
3701   exit(1);
3702 }
3703 #endif
3704
3705 void syscall_assemble(int i,struct regstat *i_regs)
3706 {
3707   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3708   assert(ccreg==HOST_CCREG);
3709   assert(!is_delayslot);
3710   emit_movimm(start+i*4,EAX); // Get PC
3711   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3712   emit_jmp((int)jump_syscall_hle); // XXX
3713 }
3714
3715 void hlecall_assemble(int i,struct regstat *i_regs)
3716 {
3717   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3718   assert(ccreg==HOST_CCREG);
3719   assert(!is_delayslot);
3720   emit_movimm(start+i*4+4,0); // Get PC
3721   emit_movimm((int)psxHLEt[source[i]&7],1);
3722   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3723   emit_jmp((int)jump_hlecall);
3724 }
3725
3726 void ds_assemble(int i,struct regstat *i_regs)
3727 {
3728   is_delayslot=1;
3729   switch(itype[i]) {
3730     case ALU:
3731       alu_assemble(i,i_regs);break;
3732     case IMM16:
3733       imm16_assemble(i,i_regs);break;
3734     case SHIFT:
3735       shift_assemble(i,i_regs);break;
3736     case SHIFTIMM:
3737       shiftimm_assemble(i,i_regs);break;
3738     case LOAD:
3739       load_assemble(i,i_regs);break;
3740     case LOADLR:
3741       loadlr_assemble(i,i_regs);break;
3742     case STORE:
3743       store_assemble(i,i_regs);break;
3744     case STORELR:
3745       storelr_assemble(i,i_regs);break;
3746     case COP0:
3747       cop0_assemble(i,i_regs);break;
3748     case COP1:
3749       cop1_assemble(i,i_regs);break;
3750     case C1LS:
3751       c1ls_assemble(i,i_regs);break;
3752     case COP2:
3753       cop2_assemble(i,i_regs);break;
3754     case C2LS:
3755       c2ls_assemble(i,i_regs);break;
3756     case C2OP:
3757       c2op_assemble(i,i_regs);break;
3758     case FCONV:
3759       fconv_assemble(i,i_regs);break;
3760     case FLOAT:
3761       float_assemble(i,i_regs);break;
3762     case FCOMP:
3763       fcomp_assemble(i,i_regs);break;
3764     case MULTDIV:
3765       multdiv_assemble(i,i_regs);break;
3766     case MOV:
3767       mov_assemble(i,i_regs);break;
3768     case SYSCALL:
3769     case HLECALL:
3770     case SPAN:
3771     case UJUMP:
3772     case RJUMP:
3773     case CJUMP:
3774     case SJUMP:
3775     case FJUMP:
3776       printf("Jump in the delay slot.  This is probably a bug.\n");
3777   }
3778   is_delayslot=0;
3779 }
3780
3781 // Is the branch target a valid internal jump?
3782 int internal_branch(uint64_t i_is32,int addr)
3783 {
3784   if(addr&1) return 0; // Indirect (register) jump
3785   if(addr>=start && addr<start+slen*4-4)
3786   {
3787     int t=(addr-start)>>2;
3788     // Delay slots are not valid branch targets
3789     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3790     // 64 -> 32 bit transition requires a recompile
3791     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3792     {
3793       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3794       else printf("optimizable: yes\n");
3795     }*/
3796     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3797     if(requires_32bit[t]&~i_is32) return 0;
3798     else return 1;
3799   }
3800   return 0;
3801 }
3802
3803 #ifndef wb_invalidate
3804 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3805   uint64_t u,uint64_t uu)
3806 {
3807   int hr;
3808   for(hr=0;hr<HOST_REGS;hr++) {
3809     if(hr!=EXCLUDE_REG) {
3810       if(pre[hr]!=entry[hr]) {
3811         if(pre[hr]>=0) {
3812           if((dirty>>hr)&1) {
3813             if(get_reg(entry,pre[hr])<0) {
3814               if(pre[hr]<64) {
3815                 if(!((u>>pre[hr])&1)) {
3816                   emit_storereg(pre[hr],hr);
3817                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3818                     emit_sarimm(hr,31,hr);
3819                     emit_storereg(pre[hr]|64,hr);
3820                   }
3821                 }
3822               }else{
3823                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3824                   emit_storereg(pre[hr],hr);
3825                 }
3826               }
3827             }
3828           }
3829         }
3830       }
3831     }
3832   }
3833   // Move from one register to another (no writeback)
3834   for(hr=0;hr<HOST_REGS;hr++) {
3835     if(hr!=EXCLUDE_REG) {
3836       if(pre[hr]!=entry[hr]) {
3837         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3838           int nr;
3839           if((nr=get_reg(entry,pre[hr]))>=0) {
3840             emit_mov(hr,nr);
3841           }
3842         }
3843       }
3844     }
3845   }
3846 }
3847 #endif
3848
3849 // Load the specified registers
3850 // This only loads the registers given as arguments because
3851 // we don't want to load things that will be overwritten
3852 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3853 {
3854   int hr;
3855   // Load 32-bit regs
3856   for(hr=0;hr<HOST_REGS;hr++) {
3857     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3858       if(entry[hr]!=regmap[hr]) {
3859         if(regmap[hr]==rs1||regmap[hr]==rs2)
3860         {
3861           if(regmap[hr]==0) {
3862             emit_zeroreg(hr);
3863           }
3864           else
3865           {
3866             emit_loadreg(regmap[hr],hr);
3867           }
3868         }
3869       }
3870     }
3871   }
3872   //Load 64-bit regs
3873   for(hr=0;hr<HOST_REGS;hr++) {
3874     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3875       if(entry[hr]!=regmap[hr]) {
3876         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3877         {
3878           assert(regmap[hr]!=64);
3879           if((is32>>(regmap[hr]&63))&1) {
3880             int lr=get_reg(regmap,regmap[hr]-64);
3881             if(lr>=0)
3882               emit_sarimm(lr,31,hr);
3883             else
3884               emit_loadreg(regmap[hr],hr);
3885           }
3886           else
3887           {
3888             emit_loadreg(regmap[hr],hr);
3889           }
3890         }
3891       }
3892     }
3893   }
3894 }
3895
3896 // Load registers prior to the start of a loop
3897 // so that they are not loaded within the loop
3898 static void loop_preload(signed char pre[],signed char entry[])
3899 {
3900   int hr;
3901   for(hr=0;hr<HOST_REGS;hr++) {
3902     if(hr!=EXCLUDE_REG) {
3903       if(pre[hr]!=entry[hr]) {
3904         if(entry[hr]>=0) {
3905           if(get_reg(pre,entry[hr])<0) {
3906             assem_debug("loop preload:\n");
3907             //printf("loop preload: %d\n",hr);
3908             if(entry[hr]==0) {
3909               emit_zeroreg(hr);
3910             }
3911             else if(entry[hr]<TEMPREG)
3912             {
3913               emit_loadreg(entry[hr],hr);
3914             }
3915             else if(entry[hr]-64<TEMPREG)
3916             {
3917               emit_loadreg(entry[hr],hr);
3918             }
3919           }
3920         }
3921       }
3922     }
3923   }
3924 }
3925
3926 // Generate address for load/store instruction
3927 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3928 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3929 {
3930   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3931     int ra;
3932     int agr=AGEN1+(i&1);
3933     int mgr=MGEN1+(i&1);
3934     if(itype[i]==LOAD) {
3935       ra=get_reg(i_regs->regmap,rt1[i]);
3936       //if(rt1[i]) assert(ra>=0);
3937     }
3938     if(itype[i]==LOADLR) {
3939       ra=get_reg(i_regs->regmap,FTEMP);
3940     }
3941     if(itype[i]==STORE||itype[i]==STORELR) {
3942       ra=get_reg(i_regs->regmap,agr);
3943       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3944     }
3945     if(itype[i]==C1LS||itype[i]==C2LS) {
3946       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3947         ra=get_reg(i_regs->regmap,FTEMP);
3948       else { // SWC1/SDC1
3949         ra=get_reg(i_regs->regmap,agr);
3950         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3951       }
3952     }
3953     int rs=get_reg(i_regs->regmap,rs1[i]);
3954     int rm=get_reg(i_regs->regmap,TLREG);
3955     if(ra>=0) {
3956       int offset=imm[i];
3957       int c=(i_regs->wasconst>>rs)&1;
3958       if(rs1[i]==0) {
3959         // Using r0 as a base address
3960         /*if(rm>=0) {
3961           if(!entry||entry[rm]!=mgr) {
3962             generate_map_const(offset,rm);
3963           } // else did it in the previous cycle
3964         }*/
3965         if(!entry||entry[ra]!=agr) {
3966           if (opcode[i]==0x22||opcode[i]==0x26) {
3967             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3968           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3969             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3970           }else{
3971             emit_movimm(offset,ra);
3972           }
3973         } // else did it in the previous cycle
3974       }
3975       else if(rs<0) {
3976         if(!entry||entry[ra]!=rs1[i])
3977           emit_loadreg(rs1[i],ra);
3978         //if(!entry||entry[ra]!=rs1[i])
3979         //  printf("poor load scheduling!\n");
3980       }
3981       else if(c) {
3982         if(rm>=0) {
3983           if(!entry||entry[rm]!=mgr) {
3984             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
3985               // Stores to memory go thru the mapper to detect self-modifying
3986               // code, loads don't.
3987               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3988                  (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3989                 generate_map_const(constmap[i][rs]+offset,rm);
3990             }else{
3991               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3992                 generate_map_const(constmap[i][rs]+offset,rm);
3993             }
3994           }
3995         }
3996         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3997           if(!entry||entry[ra]!=agr) {
3998             if (opcode[i]==0x22||opcode[i]==0x26) {
3999               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4000             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4001               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4002             }else{
4003               #ifdef HOST_IMM_ADDR32
4004               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4005                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4006               #endif
4007               emit_movimm(constmap[i][rs]+offset,ra);
4008             }
4009           } // else did it in the previous cycle
4010         } // else load_consts already did it
4011       }
4012       if(offset&&!c&&rs1[i]) {
4013         if(rs>=0) {
4014           emit_addimm(rs,offset,ra);
4015         }else{
4016           emit_addimm(ra,offset,ra);
4017         }
4018       }
4019     }
4020   }
4021   // Preload constants for next instruction
4022   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4023     int agr,ra;
4024     #ifndef HOST_IMM_ADDR32
4025     // Mapper entry
4026     agr=MGEN1+((i+1)&1);
4027     ra=get_reg(i_regs->regmap,agr);
4028     if(ra>=0) {
4029       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4030       int offset=imm[i+1];
4031       int c=(regs[i+1].wasconst>>rs)&1;
4032       if(c) {
4033         if(itype[i+1]==STORE||itype[i+1]==STORELR
4034            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4035           // Stores to memory go thru the mapper to detect self-modifying
4036           // code, loads don't.
4037           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4038              (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
4039             generate_map_const(constmap[i+1][rs]+offset,ra);
4040         }else{
4041           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4042             generate_map_const(constmap[i+1][rs]+offset,ra);
4043         }
4044       }
4045       /*else if(rs1[i]==0) {
4046         generate_map_const(offset,ra);
4047       }*/
4048     }
4049     #endif
4050     // Actual address
4051     agr=AGEN1+((i+1)&1);
4052     ra=get_reg(i_regs->regmap,agr);
4053     if(ra>=0) {
4054       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4055       int offset=imm[i+1];
4056       int c=(regs[i+1].wasconst>>rs)&1;
4057       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4058         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4059           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4060         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4061           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4062         }else{
4063           #ifdef HOST_IMM_ADDR32
4064           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4065              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4066           #endif
4067           emit_movimm(constmap[i+1][rs]+offset,ra);
4068         }
4069       }
4070       else if(rs1[i+1]==0) {
4071         // Using r0 as a base address
4072         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4073           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4074         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4075           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4076         }else{
4077           emit_movimm(offset,ra);
4078         }
4079       }
4080     }
4081   }
4082 }
4083
4084 int get_final_value(int hr, int i, int *value)
4085 {
4086   int reg=regs[i].regmap[hr];
4087   while(i<slen-1) {
4088     if(regs[i+1].regmap[hr]!=reg) break;
4089     if(!((regs[i+1].isconst>>hr)&1)) break;
4090     if(bt[i+1]) break;
4091     i++;
4092   }
4093   if(i<slen-1) {
4094     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4095       *value=constmap[i][hr];
4096       return 1;
4097     }
4098     if(!bt[i+1]) {
4099       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4100         // Load in delay slot, out-of-order execution
4101         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4102         {
4103           #ifdef HOST_IMM_ADDR32
4104           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4105           #endif
4106           // Precompute load address
4107           *value=constmap[i][hr]+imm[i+2];
4108           return 1;
4109         }
4110       }
4111       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4112       {
4113         #ifdef HOST_IMM_ADDR32
4114         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4115         #endif
4116         // Precompute load address
4117         *value=constmap[i][hr]+imm[i+1];
4118         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4119         return 1;
4120       }
4121     }
4122   }
4123   *value=constmap[i][hr];
4124   //printf("c=%x\n",(int)constmap[i][hr]);
4125   if(i==slen-1) return 1;
4126   if(reg<64) {
4127     return !((unneeded_reg[i+1]>>reg)&1);
4128   }else{
4129     return !((unneeded_reg_upper[i+1]>>reg)&1);
4130   }
4131 }
4132
4133 // Load registers with known constants
4134 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4135 {
4136   int hr;
4137   // Load 32-bit regs
4138   for(hr=0;hr<HOST_REGS;hr++) {
4139     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4140       //if(entry[hr]!=regmap[hr]) {
4141       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4142         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4143           int value;
4144           if(get_final_value(hr,i,&value)) {
4145             if(value==0) {
4146               emit_zeroreg(hr);
4147             }
4148             else {
4149               emit_movimm(value,hr);
4150             }
4151           }
4152         }
4153       }
4154     }
4155   }
4156   // Load 64-bit regs
4157   for(hr=0;hr<HOST_REGS;hr++) {
4158     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4159       //if(entry[hr]!=regmap[hr]) {
4160       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4161         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4162           if((is32>>(regmap[hr]&63))&1) {
4163             int lr=get_reg(regmap,regmap[hr]-64);
4164             assert(lr>=0);
4165             emit_sarimm(lr,31,hr);
4166           }
4167           else
4168           {
4169             int value;
4170             if(get_final_value(hr,i,&value)) {
4171               if(value==0) {
4172                 emit_zeroreg(hr);
4173               }
4174               else {
4175                 emit_movimm(value,hr);
4176               }
4177             }
4178           }
4179         }
4180       }
4181     }
4182   }
4183 }
4184 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4185 {
4186   int hr;
4187   // Load 32-bit regs
4188   for(hr=0;hr<HOST_REGS;hr++) {
4189     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4190       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4191         int value=constmap[i][hr];
4192         if(value==0) {
4193           emit_zeroreg(hr);
4194         }
4195         else {
4196           emit_movimm(value,hr);
4197         }
4198       }
4199     }
4200   }
4201   // Load 64-bit regs
4202   for(hr=0;hr<HOST_REGS;hr++) {
4203     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4204       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4205         if((is32>>(regmap[hr]&63))&1) {
4206           int lr=get_reg(regmap,regmap[hr]-64);
4207           assert(lr>=0);
4208           emit_sarimm(lr,31,hr);
4209         }
4210         else
4211         {
4212           int value=constmap[i][hr];
4213           if(value==0) {
4214             emit_zeroreg(hr);
4215           }
4216           else {
4217             emit_movimm(value,hr);
4218           }
4219         }
4220       }
4221     }
4222   }
4223 }
4224
4225 // Write out all dirty registers (except cycle count)
4226 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4227 {
4228   int hr;
4229   for(hr=0;hr<HOST_REGS;hr++) {
4230     if(hr!=EXCLUDE_REG) {
4231       if(i_regmap[hr]>0) {
4232         if(i_regmap[hr]!=CCREG) {
4233           if((i_dirty>>hr)&1) {
4234             if(i_regmap[hr]<64) {
4235               emit_storereg(i_regmap[hr],hr);
4236 #ifndef FORCE32
4237               if( ((i_is32>>i_regmap[hr])&1) ) {
4238                 #ifdef DESTRUCTIVE_WRITEBACK
4239                 emit_sarimm(hr,31,hr);
4240                 emit_storereg(i_regmap[hr]|64,hr);
4241                 #else
4242                 emit_sarimm(hr,31,HOST_TEMPREG);
4243                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4244                 #endif
4245               }
4246 #endif
4247             }else{
4248               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4249                 emit_storereg(i_regmap[hr],hr);
4250               }
4251             }
4252           }
4253         }
4254       }
4255     }
4256   }
4257 }
4258 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4259 // This writes the registers not written by store_regs_bt
4260 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4261 {
4262   int hr;
4263   int t=(addr-start)>>2;
4264   for(hr=0;hr<HOST_REGS;hr++) {
4265     if(hr!=EXCLUDE_REG) {
4266       if(i_regmap[hr]>0) {
4267         if(i_regmap[hr]!=CCREG) {
4268           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4269             if((i_dirty>>hr)&1) {
4270               if(i_regmap[hr]<64) {
4271                 emit_storereg(i_regmap[hr],hr);
4272 #ifndef FORCE32
4273                 if( ((i_is32>>i_regmap[hr])&1) ) {
4274                   #ifdef DESTRUCTIVE_WRITEBACK
4275                   emit_sarimm(hr,31,hr);
4276                   emit_storereg(i_regmap[hr]|64,hr);
4277                   #else
4278                   emit_sarimm(hr,31,HOST_TEMPREG);
4279                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4280                   #endif
4281                 }
4282 #endif
4283               }else{
4284                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4285                   emit_storereg(i_regmap[hr],hr);
4286                 }
4287               }
4288             }
4289           }
4290         }
4291       }
4292     }
4293   }
4294 }
4295
4296 // Load all registers (except cycle count)
4297 void load_all_regs(signed char i_regmap[])
4298 {
4299   int hr;
4300   for(hr=0;hr<HOST_REGS;hr++) {
4301     if(hr!=EXCLUDE_REG) {
4302       if(i_regmap[hr]==0) {
4303         emit_zeroreg(hr);
4304       }
4305       else
4306       if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4307       {
4308         emit_loadreg(i_regmap[hr],hr);
4309       }
4310     }
4311   }
4312 }
4313
4314 // Load all current registers also needed by next instruction
4315 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4316 {
4317   int hr;
4318   for(hr=0;hr<HOST_REGS;hr++) {
4319     if(hr!=EXCLUDE_REG) {
4320       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4321         if(i_regmap[hr]==0) {
4322           emit_zeroreg(hr);
4323         }
4324         else
4325         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4326         {
4327           emit_loadreg(i_regmap[hr],hr);
4328         }
4329       }
4330     }
4331   }
4332 }
4333
4334 // Load all regs, storing cycle count if necessary
4335 void load_regs_entry(int t)
4336 {
4337   int hr;
4338   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4339   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4340   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4341     emit_storereg(CCREG,HOST_CCREG);
4342   }
4343   // Load 32-bit regs
4344   for(hr=0;hr<HOST_REGS;hr++) {
4345     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4346       if(regs[t].regmap_entry[hr]==0) {
4347         emit_zeroreg(hr);
4348       }
4349       else if(regs[t].regmap_entry[hr]!=CCREG)
4350       {
4351         emit_loadreg(regs[t].regmap_entry[hr],hr);
4352       }
4353     }
4354   }
4355   // Load 64-bit regs
4356   for(hr=0;hr<HOST_REGS;hr++) {
4357     if(regs[t].regmap_entry[hr]>=64) {
4358       assert(regs[t].regmap_entry[hr]!=64);
4359       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4360         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4361         if(lr<0) {
4362           emit_loadreg(regs[t].regmap_entry[hr],hr);
4363         }
4364         else
4365         {
4366           emit_sarimm(lr,31,hr);
4367         }
4368       }
4369       else
4370       {
4371         emit_loadreg(regs[t].regmap_entry[hr],hr);
4372       }
4373     }
4374   }
4375 }
4376
4377 // Store dirty registers prior to branch
4378 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4379 {
4380   if(internal_branch(i_is32,addr))
4381   {
4382     int t=(addr-start)>>2;
4383     int hr;
4384     for(hr=0;hr<HOST_REGS;hr++) {
4385       if(hr!=EXCLUDE_REG) {
4386         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4387           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4388             if((i_dirty>>hr)&1) {
4389               if(i_regmap[hr]<64) {
4390                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4391                   emit_storereg(i_regmap[hr],hr);
4392                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4393                     #ifdef DESTRUCTIVE_WRITEBACK
4394                     emit_sarimm(hr,31,hr);
4395                     emit_storereg(i_regmap[hr]|64,hr);
4396                     #else
4397                     emit_sarimm(hr,31,HOST_TEMPREG);
4398                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4399                     #endif
4400                   }
4401                 }
4402               }else{
4403                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4404                   emit_storereg(i_regmap[hr],hr);
4405                 }
4406               }
4407             }
4408           }
4409         }
4410       }
4411     }
4412   }
4413   else
4414   {
4415     // Branch out of this block, write out all dirty regs
4416     wb_dirtys(i_regmap,i_is32,i_dirty);
4417   }
4418 }
4419
4420 // Load all needed registers for branch target
4421 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4422 {
4423   //if(addr>=start && addr<(start+slen*4))
4424   if(internal_branch(i_is32,addr))
4425   {
4426     int t=(addr-start)>>2;
4427     int hr;
4428     // Store the cycle count before loading something else
4429     if(i_regmap[HOST_CCREG]!=CCREG) {
4430       assert(i_regmap[HOST_CCREG]==-1);
4431     }
4432     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4433       emit_storereg(CCREG,HOST_CCREG);
4434     }
4435     // Load 32-bit regs
4436     for(hr=0;hr<HOST_REGS;hr++) {
4437       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<64) {
4438         #ifdef DESTRUCTIVE_WRITEBACK
4439         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4440         #else
4441         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4442         #endif
4443           if(regs[t].regmap_entry[hr]==0) {
4444             emit_zeroreg(hr);
4445           }
4446           else if(regs[t].regmap_entry[hr]!=CCREG)
4447           {
4448             emit_loadreg(regs[t].regmap_entry[hr],hr);
4449           }
4450         }
4451       }
4452     }
4453     //Load 64-bit regs
4454     for(hr=0;hr<HOST_REGS;hr++) {
4455       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64) {
4456         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4457           assert(regs[t].regmap_entry[hr]!=64);
4458           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4459             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4460             if(lr<0) {
4461               emit_loadreg(regs[t].regmap_entry[hr],hr);
4462             }
4463             else
4464             {
4465               emit_sarimm(lr,31,hr);
4466             }
4467           }
4468           else
4469           {
4470             emit_loadreg(regs[t].regmap_entry[hr],hr);
4471           }
4472         }
4473         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4474           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4475           assert(lr>=0);
4476           emit_sarimm(lr,31,hr);
4477         }
4478       }
4479     }
4480   }
4481 }
4482
4483 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4484 {
4485   if(addr>=start && addr<start+slen*4-4)
4486   {
4487     int t=(addr-start)>>2;
4488     int hr;
4489     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4490     for(hr=0;hr<HOST_REGS;hr++)
4491     {
4492       if(hr!=EXCLUDE_REG)
4493       {
4494         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4495         {
4496           if(regs[t].regmap_entry[hr]!=-1)
4497           {
4498             return 0;
4499           }
4500           else
4501           if((i_dirty>>hr)&1)
4502           {
4503             if(i_regmap[hr]<64)
4504             {
4505               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4506                 return 0;
4507             }
4508             else
4509             {
4510               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4511                 return 0;
4512             }
4513           }
4514         }
4515         else // Same register but is it 32-bit or dirty?
4516         if(i_regmap[hr]>=0)
4517         {
4518           if(!((regs[t].dirty>>hr)&1))
4519           {
4520             if((i_dirty>>hr)&1)
4521             {
4522               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4523               {
4524                 //printf("%x: dirty no match\n",addr);
4525                 return 0;
4526               }
4527             }
4528           }
4529           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4530           {
4531             //printf("%x: is32 no match\n",addr);
4532             return 0;
4533           }
4534         }
4535       }
4536     }
4537     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4538     if(requires_32bit[t]&~i_is32) return 0;
4539     // Delay slots are not valid branch targets
4540     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4541     // Delay slots require additional processing, so do not match
4542     if(is_ds[t]) return 0;
4543   }
4544   else
4545   {
4546     int hr;
4547     for(hr=0;hr<HOST_REGS;hr++)
4548     {
4549       if(hr!=EXCLUDE_REG)
4550       {
4551         if(i_regmap[hr]>=0)
4552         {
4553           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4554           {
4555             if((i_dirty>>hr)&1)
4556             {
4557               return 0;
4558             }
4559           }
4560         }
4561       }
4562     }
4563   }
4564   return 1;
4565 }
4566
4567 // Used when a branch jumps into the delay slot of another branch
4568 void ds_assemble_entry(int i)
4569 {
4570   int t=(ba[i]-start)>>2;
4571   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4572   assem_debug("Assemble delay slot at %x\n",ba[i]);
4573   assem_debug("<->\n");
4574   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4575     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4576   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4577   address_generation(t,&regs[t],regs[t].regmap_entry);
4578   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4579     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4580   cop1_usable=0;
4581   is_delayslot=0;
4582   switch(itype[t]) {
4583     case ALU:
4584       alu_assemble(t,&regs[t]);break;
4585     case IMM16:
4586       imm16_assemble(t,&regs[t]);break;
4587     case SHIFT:
4588       shift_assemble(t,&regs[t]);break;
4589     case SHIFTIMM:
4590       shiftimm_assemble(t,&regs[t]);break;
4591     case LOAD:
4592       load_assemble(t,&regs[t]);break;
4593     case LOADLR:
4594       loadlr_assemble(t,&regs[t]);break;
4595     case STORE:
4596       store_assemble(t,&regs[t]);break;
4597     case STORELR:
4598       storelr_assemble(t,&regs[t]);break;
4599     case COP0:
4600       cop0_assemble(t,&regs[t]);break;
4601     case COP1:
4602       cop1_assemble(t,&regs[t]);break;
4603     case C1LS:
4604       c1ls_assemble(t,&regs[t]);break;
4605     case COP2:
4606       cop2_assemble(t,&regs[t]);break;
4607     case C2LS:
4608       c2ls_assemble(t,&regs[t]);break;
4609     case C2OP:
4610       c2op_assemble(t,&regs[t]);break;
4611     case FCONV:
4612       fconv_assemble(t,&regs[t]);break;
4613     case FLOAT:
4614       float_assemble(t,&regs[t]);break;
4615     case FCOMP:
4616       fcomp_assemble(t,&regs[t]);break;
4617     case MULTDIV:
4618       multdiv_assemble(t,&regs[t]);break;
4619     case MOV:
4620       mov_assemble(t,&regs[t]);break;
4621     case SYSCALL:
4622     case HLECALL:
4623     case SPAN:
4624     case UJUMP:
4625     case RJUMP:
4626     case CJUMP:
4627     case SJUMP:
4628     case FJUMP:
4629       printf("Jump in the delay slot.  This is probably a bug.\n");
4630   }
4631   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4632   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4633   if(internal_branch(regs[t].is32,ba[i]+4))
4634     assem_debug("branch: internal\n");
4635   else
4636     assem_debug("branch: external\n");
4637   assert(internal_branch(regs[t].is32,ba[i]+4));
4638   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4639   emit_jmp(0);
4640 }
4641
4642 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4643 {
4644   int count;
4645   int jaddr;
4646   int idle=0;
4647   if(itype[i]==RJUMP)
4648   {
4649     *adj=0;
4650   }
4651   //if(ba[i]>=start && ba[i]<(start+slen*4))
4652   if(internal_branch(branch_regs[i].is32,ba[i]))
4653   {
4654     int t=(ba[i]-start)>>2;
4655     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4656     else *adj=ccadj[t];
4657   }
4658   else
4659   {
4660     *adj=0;
4661   }
4662   count=ccadj[i];
4663   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4664     // Idle loop
4665     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4666     idle=(int)out;
4667     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4668     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4669     jaddr=(int)out;
4670     emit_jmp(0);
4671   }
4672   else if(*adj==0||invert) {
4673     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4674     jaddr=(int)out;
4675     emit_jns(0);
4676   }
4677   else
4678   {
4679     emit_cmpimm(HOST_CCREG,-2*(count+2));
4680     jaddr=(int)out;
4681     emit_jns(0);
4682   }
4683   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4684 }
4685
4686 void do_ccstub(int n)
4687 {
4688   literal_pool(256);
4689   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4690   set_jump_target(stubs[n][1],(int)out);
4691   int i=stubs[n][4];
4692   if(stubs[n][6]==NULLDS) {
4693     // Delay slot instruction is nullified ("likely" branch)
4694     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4695   }
4696   else if(stubs[n][6]!=TAKEN) {
4697     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4698   }
4699   else {
4700     if(internal_branch(branch_regs[i].is32,ba[i]))
4701       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4702   }
4703   if(stubs[n][5]!=-1)
4704   {
4705     // Save PC as return address
4706     emit_movimm(stubs[n][5],EAX);
4707     emit_writeword(EAX,(int)&pcaddr);
4708   }
4709   else
4710   {
4711     // Return address depends on which way the branch goes
4712     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4713     {
4714       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4715       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4716       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4717       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4718       if(rs1[i]==0)
4719       {
4720         s1l=s2l;s1h=s2h;
4721         s2l=s2h=-1;
4722       }
4723       else if(rs2[i]==0)
4724       {
4725         s2l=s2h=-1;
4726       }
4727       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4728         s1h=s2h=-1;
4729       }
4730       assert(s1l>=0);
4731       #ifdef DESTRUCTIVE_WRITEBACK
4732       if(rs1[i]) {
4733         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4734           emit_loadreg(rs1[i],s1l);
4735       }
4736       else {
4737         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4738           emit_loadreg(rs2[i],s1l);
4739       }
4740       if(s2l>=0)
4741         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4742           emit_loadreg(rs2[i],s2l);
4743       #endif
4744       int hr=0;
4745       int addr,alt,ntaddr;
4746       while(hr<HOST_REGS)
4747       {
4748         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4749            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4750            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4751         {
4752           addr=hr++;break;
4753         }
4754         hr++;
4755       }
4756       while(hr<HOST_REGS)
4757       {
4758         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4759            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4760            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4761         {
4762           alt=hr++;break;
4763         }
4764         hr++;
4765       }
4766       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4767       {
4768         while(hr<HOST_REGS)
4769         {
4770           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4771              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4772              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4773           {
4774             ntaddr=hr;break;
4775           }
4776           hr++;
4777         }
4778         assert(hr<HOST_REGS);
4779       }
4780       if((opcode[i]&0x2f)==4) // BEQ
4781       {
4782         #ifdef HAVE_CMOV_IMM
4783         if(s1h<0) {
4784           if(s2l>=0) emit_cmp(s1l,s2l);
4785           else emit_test(s1l,s1l);
4786           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4787         }
4788         else
4789         #endif
4790         {
4791           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4792           if(s1h>=0) {
4793             if(s2h>=0) emit_cmp(s1h,s2h);
4794             else emit_test(s1h,s1h);
4795             emit_cmovne_reg(alt,addr);
4796           }
4797           if(s2l>=0) emit_cmp(s1l,s2l);
4798           else emit_test(s1l,s1l);
4799           emit_cmovne_reg(alt,addr);
4800         }
4801       }
4802       if((opcode[i]&0x2f)==5) // BNE
4803       {
4804         #ifdef HAVE_CMOV_IMM
4805         if(s1h<0) {
4806           if(s2l>=0) emit_cmp(s1l,s2l);
4807           else emit_test(s1l,s1l);
4808           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4809         }
4810         else
4811         #endif
4812         {
4813           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4814           if(s1h>=0) {
4815             if(s2h>=0) emit_cmp(s1h,s2h);
4816             else emit_test(s1h,s1h);
4817             emit_cmovne_reg(alt,addr);
4818           }
4819           if(s2l>=0) emit_cmp(s1l,s2l);
4820           else emit_test(s1l,s1l);
4821           emit_cmovne_reg(alt,addr);
4822         }
4823       }
4824       if((opcode[i]&0x2f)==6) // BLEZ
4825       {
4826         //emit_movimm(ba[i],alt);
4827         //emit_movimm(start+i*4+8,addr);
4828         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4829         emit_cmpimm(s1l,1);
4830         if(s1h>=0) emit_mov(addr,ntaddr);
4831         emit_cmovl_reg(alt,addr);
4832         if(s1h>=0) {
4833           emit_test(s1h,s1h);
4834           emit_cmovne_reg(ntaddr,addr);
4835           emit_cmovs_reg(alt,addr);
4836         }
4837       }
4838       if((opcode[i]&0x2f)==7) // BGTZ
4839       {
4840         //emit_movimm(ba[i],addr);
4841         //emit_movimm(start+i*4+8,ntaddr);
4842         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4843         emit_cmpimm(s1l,1);
4844         if(s1h>=0) emit_mov(addr,alt);
4845         emit_cmovl_reg(ntaddr,addr);
4846         if(s1h>=0) {
4847           emit_test(s1h,s1h);
4848           emit_cmovne_reg(alt,addr);
4849           emit_cmovs_reg(ntaddr,addr);
4850         }
4851       }
4852       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4853       {
4854         //emit_movimm(ba[i],alt);
4855         //emit_movimm(start+i*4+8,addr);
4856         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4857         if(s1h>=0) emit_test(s1h,s1h);
4858         else emit_test(s1l,s1l);
4859         emit_cmovs_reg(alt,addr);
4860       }
4861       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4862       {
4863         //emit_movimm(ba[i],addr);
4864         //emit_movimm(start+i*4+8,alt);
4865         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4866         if(s1h>=0) emit_test(s1h,s1h);
4867         else emit_test(s1l,s1l);
4868         emit_cmovs_reg(alt,addr);
4869       }
4870       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4871         if(source[i]&0x10000) // BC1T
4872         {
4873           //emit_movimm(ba[i],alt);
4874           //emit_movimm(start+i*4+8,addr);
4875           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4876           emit_testimm(s1l,0x800000);
4877           emit_cmovne_reg(alt,addr);
4878         }
4879         else // BC1F
4880         {
4881           //emit_movimm(ba[i],addr);
4882           //emit_movimm(start+i*4+8,alt);
4883           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4884           emit_testimm(s1l,0x800000);
4885           emit_cmovne_reg(alt,addr);
4886         }
4887       }
4888       emit_writeword(addr,(int)&pcaddr);
4889     }
4890     else
4891     if(itype[i]==RJUMP)
4892     {
4893       int r=get_reg(branch_regs[i].regmap,rs1[i]);
4894       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4895         r=get_reg(branch_regs[i].regmap,RTEMP);
4896       }
4897       emit_writeword(r,(int)&pcaddr);
4898     }
4899     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4900   }
4901   // Update cycle count
4902   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4903   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4904   emit_call((int)cc_interrupt);
4905   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4906   if(stubs[n][6]==TAKEN) {
4907     if(internal_branch(branch_regs[i].is32,ba[i]))
4908       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4909     else if(itype[i]==RJUMP) {
4910       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4911         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4912       else
4913         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4914     }
4915   }else if(stubs[n][6]==NOTTAKEN) {
4916     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4917     else load_all_regs(branch_regs[i].regmap);
4918   }else if(stubs[n][6]==NULLDS) {
4919     // Delay slot instruction is nullified ("likely" branch)
4920     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4921     else load_all_regs(regs[i].regmap);
4922   }else{
4923     load_all_regs(branch_regs[i].regmap);
4924   }
4925   emit_jmp(stubs[n][2]); // return address
4926
4927   /* This works but uses a lot of memory...
4928   emit_readword((int)&last_count,ECX);
4929   emit_add(HOST_CCREG,ECX,EAX);
4930   emit_writeword(EAX,(int)&Count);
4931   emit_call((int)gen_interupt);
4932   emit_readword((int)&Count,HOST_CCREG);
4933   emit_readword((int)&next_interupt,EAX);
4934   emit_readword((int)&pending_exception,EBX);
4935   emit_writeword(EAX,(int)&last_count);
4936   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4937   emit_test(EBX,EBX);
4938   int jne_instr=(int)out;
4939   emit_jne(0);
4940   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4941   load_all_regs(branch_regs[i].regmap);
4942   emit_jmp(stubs[n][2]); // return address
4943   set_jump_target(jne_instr,(int)out);
4944   emit_readword((int)&pcaddr,EAX);
4945   // Call get_addr_ht instead of doing the hash table here.
4946   // This code is executed infrequently and takes up a lot of space
4947   // so smaller is better.
4948   emit_storereg(CCREG,HOST_CCREG);
4949   emit_pushreg(EAX);
4950   emit_call((int)get_addr_ht);
4951   emit_loadreg(CCREG,HOST_CCREG);
4952   emit_addimm(ESP,4,ESP);
4953   emit_jmpreg(EAX);*/
4954 }
4955
4956 add_to_linker(int addr,int target,int ext)
4957 {
4958   link_addr[linkcount][0]=addr;
4959   link_addr[linkcount][1]=target;
4960   link_addr[linkcount][2]=ext;
4961   linkcount++;
4962 }
4963
4964 void ujump_assemble(int i,struct regstat *i_regs)
4965 {
4966   signed char *i_regmap=i_regs->regmap;
4967   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4968   address_generation(i+1,i_regs,regs[i].regmap_entry);
4969   #ifdef REG_PREFETCH
4970   int temp=get_reg(branch_regs[i].regmap,PTEMP);
4971   if(rt1[i]==31&&temp>=0)
4972   {
4973     int return_address=start+i*4+8;
4974     if(get_reg(branch_regs[i].regmap,31)>0)
4975     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
4976   }
4977   #endif
4978   ds_assemble(i+1,i_regs);
4979   uint64_t bc_unneeded=branch_regs[i].u;
4980   uint64_t bc_unneeded_upper=branch_regs[i].uu;
4981   bc_unneeded|=1|(1LL<<rt1[i]);
4982   bc_unneeded_upper|=1|(1LL<<rt1[i]);
4983   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4984                 bc_unneeded,bc_unneeded_upper);
4985   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4986   if(rt1[i]==31) {
4987     int rt;
4988     unsigned int return_address;
4989     assert(rt1[i+1]!=31);
4990     assert(rt2[i+1]!=31);
4991     rt=get_reg(branch_regs[i].regmap,31);
4992     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4993     //assert(rt>=0);
4994     return_address=start+i*4+8;
4995     if(rt>=0) {
4996       #ifdef USE_MINI_HT
4997       if(internal_branch(branch_regs[i].is32,return_address)) {
4998         int temp=rt+1;
4999         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5000            branch_regs[i].regmap[temp]>=0)
5001         {
5002           temp=get_reg(branch_regs[i].regmap,-1);
5003         }
5004         #ifdef HOST_TEMPREG
5005         if(temp<0) temp=HOST_TEMPREG;
5006         #endif
5007         if(temp>=0) do_miniht_insert(return_address,rt,temp);
5008         else emit_movimm(return_address,rt);
5009       }
5010       else
5011       #endif
5012       {
5013         #ifdef REG_PREFETCH
5014         if(temp>=0)
5015         {
5016           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5017         }
5018         #endif
5019         emit_movimm(return_address,rt); // PC into link register
5020         #ifdef IMM_PREFETCH
5021         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5022         #endif
5023       }
5024     }
5025   }
5026   int cc,adj;
5027   cc=get_reg(branch_regs[i].regmap,CCREG);
5028   assert(cc==HOST_CCREG);
5029   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5030   #ifdef REG_PREFETCH
5031   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5032   #endif
5033   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5034   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5035   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5036   if(internal_branch(branch_regs[i].is32,ba[i]))
5037     assem_debug("branch: internal\n");
5038   else
5039     assem_debug("branch: external\n");
5040   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5041     ds_assemble_entry(i);
5042   }
5043   else {
5044     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5045     emit_jmp(0);
5046   }
5047 }
5048
5049 void rjump_assemble(int i,struct regstat *i_regs)
5050 {
5051   signed char *i_regmap=i_regs->regmap;
5052   int temp;
5053   int rs,cc,adj;
5054   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5055   assert(rs>=0);
5056   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5057     // Delay slot abuse, make a copy of the branch address register
5058     temp=get_reg(branch_regs[i].regmap,RTEMP);
5059     assert(temp>=0);
5060     assert(regs[i].regmap[temp]==RTEMP);
5061     emit_mov(rs,temp);
5062     rs=temp;
5063   }
5064   address_generation(i+1,i_regs,regs[i].regmap_entry);
5065   #ifdef REG_PREFETCH
5066   if(rt1[i]==31)
5067   {
5068     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5069       int return_address=start+i*4+8;
5070       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5071     }
5072   }
5073   #endif
5074   #ifdef USE_MINI_HT
5075   if(rs1[i]==31) {
5076     int rh=get_reg(regs[i].regmap,RHASH);
5077     if(rh>=0) do_preload_rhash(rh);
5078   }
5079   #endif
5080   ds_assemble(i+1,i_regs);
5081   uint64_t bc_unneeded=branch_regs[i].u;
5082   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5083   bc_unneeded|=1|(1LL<<rt1[i]);
5084   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5085   bc_unneeded&=~(1LL<<rs1[i]);
5086   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5087                 bc_unneeded,bc_unneeded_upper);
5088   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5089   if(rt1[i]!=0) {
5090     int rt,return_address;
5091     assert(rt1[i+1]!=rt1[i]);
5092     assert(rt2[i+1]!=rt1[i]);
5093     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5094     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5095     assert(rt>=0);
5096     return_address=start+i*4+8;
5097     #ifdef REG_PREFETCH
5098     if(temp>=0)
5099     {
5100       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5101     }
5102     #endif
5103     emit_movimm(return_address,rt); // PC into link register
5104     #ifdef IMM_PREFETCH
5105     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5106     #endif
5107   }
5108   cc=get_reg(branch_regs[i].regmap,CCREG);
5109   assert(cc==HOST_CCREG);
5110   #ifdef USE_MINI_HT
5111   int rh=get_reg(branch_regs[i].regmap,RHASH);
5112   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5113   if(rs1[i]==31) {
5114     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5115     do_preload_rhtbl(ht);
5116     do_rhash(rs,rh);
5117   }
5118   #endif
5119   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5120   #ifdef DESTRUCTIVE_WRITEBACK
5121   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5122     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5123       emit_loadreg(rs1[i],rs);
5124     }
5125   }
5126   #endif
5127   #ifdef REG_PREFETCH
5128   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5129   #endif
5130   #ifdef USE_MINI_HT
5131   if(rs1[i]==31) {
5132     do_miniht_load(ht,rh);
5133   }
5134   #endif
5135   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5136   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5137   //assert(adj==0);
5138   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5139   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5140   emit_jns(0);
5141   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5142   #ifdef USE_MINI_HT
5143   if(rs1[i]==31) {
5144     do_miniht_jump(rs,rh,ht);
5145   }
5146   else
5147   #endif
5148   {
5149     //if(rs!=EAX) emit_mov(rs,EAX);
5150     //emit_jmp((int)jump_vaddr_eax);
5151     emit_jmp(jump_vaddr_reg[rs]);
5152   }
5153   /* Check hash table
5154   temp=!rs;
5155   emit_mov(rs,temp);
5156   emit_shrimm(rs,16,rs);
5157   emit_xor(temp,rs,rs);
5158   emit_movzwl_reg(rs,rs);
5159   emit_shlimm(rs,4,rs);
5160   emit_cmpmem_indexed((int)hash_table,rs,temp);
5161   emit_jne((int)out+14);
5162   emit_readword_indexed((int)hash_table+4,rs,rs);
5163   emit_jmpreg(rs);
5164   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5165   emit_addimm_no_flags(8,rs);
5166   emit_jeq((int)out-17);
5167   // No hit on hash table, call compiler
5168   emit_pushreg(temp);
5169 //DEBUG >
5170 #ifdef DEBUG_CYCLE_COUNT
5171   emit_readword((int)&last_count,ECX);
5172   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5173   emit_readword((int)&next_interupt,ECX);
5174   emit_writeword(HOST_CCREG,(int)&Count);
5175   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5176   emit_writeword(ECX,(int)&last_count);
5177 #endif
5178 //DEBUG <
5179   emit_storereg(CCREG,HOST_CCREG);
5180   emit_call((int)get_addr);
5181   emit_loadreg(CCREG,HOST_CCREG);
5182   emit_addimm(ESP,4,ESP);
5183   emit_jmpreg(EAX);*/
5184   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5185   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5186   #endif
5187 }
5188
5189 void cjump_assemble(int i,struct regstat *i_regs)
5190 {
5191   signed char *i_regmap=i_regs->regmap;
5192   int cc;
5193   int match;
5194   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5195   assem_debug("match=%d\n",match);
5196   int s1h,s1l,s2h,s2l;
5197   int prev_cop1_usable=cop1_usable;
5198   int unconditional=0,nop=0;
5199   int only32=0;
5200   int ooo=1;
5201   int invert=0;
5202   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5203   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5204   if(likely[i]) ooo=0;
5205   if(!match) invert=1;
5206   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5207   if(i>(ba[i]-start)>>2) invert=1;
5208   #endif
5209
5210   if(ooo)
5211     if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5212        (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5213   {
5214     // Write-after-read dependency prevents out of order execution
5215     // First test branch condition, then execute delay slot, then branch
5216     ooo=0;
5217   }
5218
5219   if(ooo) {
5220     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5221     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5222     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5223     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5224   }
5225   else {
5226     s1l=get_reg(i_regmap,rs1[i]);
5227     s1h=get_reg(i_regmap,rs1[i]|64);
5228     s2l=get_reg(i_regmap,rs2[i]);
5229     s2h=get_reg(i_regmap,rs2[i]|64);
5230   }
5231   if(rs1[i]==0&&rs2[i]==0)
5232   {
5233     if(opcode[i]&1) nop=1;
5234     else unconditional=1;
5235     //assert(opcode[i]!=5);
5236     //assert(opcode[i]!=7);
5237     //assert(opcode[i]!=0x15);
5238     //assert(opcode[i]!=0x17);
5239   }
5240   else if(rs1[i]==0)
5241   {
5242     s1l=s2l;s1h=s2h;
5243     s2l=s2h=-1;
5244     only32=(regs[i].was32>>rs2[i])&1;
5245   }
5246   else if(rs2[i]==0)
5247   {
5248     s2l=s2h=-1;
5249     only32=(regs[i].was32>>rs1[i])&1;
5250   }
5251   else {
5252     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5253   }
5254
5255   if(ooo) {
5256     // Out of order execution (delay slot first)
5257     //printf("OOOE\n");
5258     address_generation(i+1,i_regs,regs[i].regmap_entry);
5259     ds_assemble(i+1,i_regs);
5260     int adj;
5261     uint64_t bc_unneeded=branch_regs[i].u;
5262     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5263     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5264     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5265     bc_unneeded|=1;
5266     bc_unneeded_upper|=1;
5267     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5268                   bc_unneeded,bc_unneeded_upper);
5269     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5270     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5271     cc=get_reg(branch_regs[i].regmap,CCREG);
5272     assert(cc==HOST_CCREG);
5273     if(unconditional)
5274       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5275     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5276     //assem_debug("cycle count (adj)\n");
5277     if(unconditional) {
5278       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5279       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5280         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5281         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5282         if(internal)
5283           assem_debug("branch: internal\n");
5284         else
5285           assem_debug("branch: external\n");
5286         if(internal&&is_ds[(ba[i]-start)>>2]) {
5287           ds_assemble_entry(i);
5288         }
5289         else {
5290           add_to_linker((int)out,ba[i],internal);
5291           emit_jmp(0);
5292         }
5293         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5294         if(((u_int)out)&7) emit_addnop(0);
5295         #endif
5296       }
5297     }
5298     else if(nop) {
5299       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5300       int jaddr=(int)out;
5301       emit_jns(0);
5302       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5303     }
5304     else {
5305       int taken=0,nottaken=0,nottaken1=0;
5306       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5307       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5308       if(!only32)
5309       {
5310         assert(s1h>=0);
5311         if(opcode[i]==4) // BEQ
5312         {
5313           if(s2h>=0) emit_cmp(s1h,s2h);
5314           else emit_test(s1h,s1h);
5315           nottaken1=(int)out;
5316           emit_jne(1);
5317         }
5318         if(opcode[i]==5) // BNE
5319         {
5320           if(s2h>=0) emit_cmp(s1h,s2h);
5321           else emit_test(s1h,s1h);
5322           if(invert) taken=(int)out;
5323           else add_to_linker((int)out,ba[i],internal);
5324           emit_jne(0);
5325         }
5326         if(opcode[i]==6) // BLEZ
5327         {
5328           emit_test(s1h,s1h);
5329           if(invert) taken=(int)out;
5330           else add_to_linker((int)out,ba[i],internal);
5331           emit_js(0);
5332           nottaken1=(int)out;
5333           emit_jne(1);
5334         }
5335         if(opcode[i]==7) // BGTZ
5336         {
5337           emit_test(s1h,s1h);
5338           nottaken1=(int)out;
5339           emit_js(1);
5340           if(invert) taken=(int)out;
5341           else add_to_linker((int)out,ba[i],internal);
5342           emit_jne(0);
5343         }
5344       } // if(!only32)
5345
5346       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5347       assert(s1l>=0);
5348       if(opcode[i]==4) // BEQ
5349       {
5350         if(s2l>=0) emit_cmp(s1l,s2l);
5351         else emit_test(s1l,s1l);
5352         if(invert){
5353           nottaken=(int)out;
5354           emit_jne(1);
5355         }else{
5356           add_to_linker((int)out,ba[i],internal);
5357           emit_jeq(0);
5358         }
5359       }
5360       if(opcode[i]==5) // BNE
5361       {
5362         if(s2l>=0) emit_cmp(s1l,s2l);
5363         else emit_test(s1l,s1l);
5364         if(invert){
5365           nottaken=(int)out;
5366           emit_jeq(1);
5367         }else{
5368           add_to_linker((int)out,ba[i],internal);
5369           emit_jne(0);
5370         }
5371       }
5372       if(opcode[i]==6) // BLEZ
5373       {
5374         emit_cmpimm(s1l,1);
5375         if(invert){
5376           nottaken=(int)out;
5377           emit_jge(1);
5378         }else{
5379           add_to_linker((int)out,ba[i],internal);
5380           emit_jl(0);
5381         }
5382       }
5383       if(opcode[i]==7) // BGTZ
5384       {
5385         emit_cmpimm(s1l,1);
5386         if(invert){
5387           nottaken=(int)out;
5388           emit_jl(1);
5389         }else{
5390           add_to_linker((int)out,ba[i],internal);
5391           emit_jge(0);
5392         }
5393       }
5394       if(invert) {
5395         if(taken) set_jump_target(taken,(int)out);
5396         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5397         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5398           if(adj) {
5399             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5400             add_to_linker((int)out,ba[i],internal);
5401           }else{
5402             emit_addnop(13);
5403             add_to_linker((int)out,ba[i],internal*2);
5404           }
5405           emit_jmp(0);
5406         }else
5407         #endif
5408         {
5409           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5410           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5411           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5412           if(internal)
5413             assem_debug("branch: internal\n");
5414           else
5415             assem_debug("branch: external\n");
5416           if(internal&&is_ds[(ba[i]-start)>>2]) {
5417             ds_assemble_entry(i);
5418           }
5419           else {
5420             add_to_linker((int)out,ba[i],internal);
5421             emit_jmp(0);
5422           }
5423         }
5424         set_jump_target(nottaken,(int)out);
5425       }
5426
5427       if(nottaken1) set_jump_target(nottaken1,(int)out);
5428       if(adj) {
5429         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5430       }
5431     } // (!unconditional)
5432   } // if(ooo)
5433   else
5434   {
5435     // In-order execution (branch first)
5436     //if(likely[i]) printf("IOL\n");
5437     //else
5438     //printf("IOE\n");
5439     int taken=0,nottaken=0,nottaken1=0;
5440     if(!unconditional&&!nop) {
5441       if(!only32)
5442       {
5443         assert(s1h>=0);
5444         if((opcode[i]&0x2f)==4) // BEQ
5445         {
5446           if(s2h>=0) emit_cmp(s1h,s2h);
5447           else emit_test(s1h,s1h);
5448           nottaken1=(int)out;
5449           emit_jne(2);
5450         }
5451         if((opcode[i]&0x2f)==5) // BNE
5452         {
5453           if(s2h>=0) emit_cmp(s1h,s2h);
5454           else emit_test(s1h,s1h);
5455           taken=(int)out;
5456           emit_jne(1);
5457         }
5458         if((opcode[i]&0x2f)==6) // BLEZ
5459         {
5460           emit_test(s1h,s1h);
5461           taken=(int)out;
5462           emit_js(1);
5463           nottaken1=(int)out;
5464           emit_jne(2);
5465         }
5466         if((opcode[i]&0x2f)==7) // BGTZ
5467         {
5468           emit_test(s1h,s1h);
5469           nottaken1=(int)out;
5470           emit_js(2);
5471           taken=(int)out;
5472           emit_jne(1);
5473         }
5474       } // if(!only32)
5475
5476       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5477       assert(s1l>=0);
5478       if((opcode[i]&0x2f)==4) // BEQ
5479       {
5480         if(s2l>=0) emit_cmp(s1l,s2l);
5481         else emit_test(s1l,s1l);
5482         nottaken=(int)out;
5483         emit_jne(2);
5484       }
5485       if((opcode[i]&0x2f)==5) // BNE
5486       {
5487         if(s2l>=0) emit_cmp(s1l,s2l);
5488         else emit_test(s1l,s1l);
5489         nottaken=(int)out;
5490         emit_jeq(2);
5491       }
5492       if((opcode[i]&0x2f)==6) // BLEZ
5493       {
5494         emit_cmpimm(s1l,1);
5495         nottaken=(int)out;
5496         emit_jge(2);
5497       }
5498       if((opcode[i]&0x2f)==7) // BGTZ
5499       {
5500         emit_cmpimm(s1l,1);
5501         nottaken=(int)out;
5502         emit_jl(2);
5503       }
5504     } // if(!unconditional)
5505     int adj;
5506     uint64_t ds_unneeded=branch_regs[i].u;
5507     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5508     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5509     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5510     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5511     ds_unneeded|=1;
5512     ds_unneeded_upper|=1;
5513     // branch taken
5514     if(!nop) {
5515       if(taken) set_jump_target(taken,(int)out);
5516       assem_debug("1:\n");
5517       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5518                     ds_unneeded,ds_unneeded_upper);
5519       // load regs
5520       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5521       address_generation(i+1,&branch_regs[i],0);
5522       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5523       ds_assemble(i+1,&branch_regs[i]);
5524       cc=get_reg(branch_regs[i].regmap,CCREG);
5525       if(cc==-1) {
5526         emit_loadreg(CCREG,cc=HOST_CCREG);
5527         // CHECK: Is the following instruction (fall thru) allocated ok?
5528       }
5529       assert(cc==HOST_CCREG);
5530       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5531       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5532       assem_debug("cycle count (adj)\n");
5533       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5534       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5535       if(internal)
5536         assem_debug("branch: internal\n");
5537       else
5538         assem_debug("branch: external\n");
5539       if(internal&&is_ds[(ba[i]-start)>>2]) {
5540         ds_assemble_entry(i);
5541       }
5542       else {
5543         add_to_linker((int)out,ba[i],internal);
5544         emit_jmp(0);
5545       }
5546     }
5547     // branch not taken
5548     cop1_usable=prev_cop1_usable;
5549     if(!unconditional) {
5550       if(nottaken1) set_jump_target(nottaken1,(int)out);
5551       set_jump_target(nottaken,(int)out);
5552       assem_debug("2:\n");
5553       if(!likely[i]) {
5554         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5555                       ds_unneeded,ds_unneeded_upper);
5556         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5557         address_generation(i+1,&branch_regs[i],0);
5558         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5559         ds_assemble(i+1,&branch_regs[i]);
5560       }
5561       cc=get_reg(branch_regs[i].regmap,CCREG);
5562       if(cc==-1&&!likely[i]) {
5563         // Cycle count isn't in a register, temporarily load it then write it out
5564         emit_loadreg(CCREG,HOST_CCREG);
5565         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5566         int jaddr=(int)out;
5567         emit_jns(0);
5568         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5569         emit_storereg(CCREG,HOST_CCREG);
5570       }
5571       else{
5572         cc=get_reg(i_regmap,CCREG);
5573         assert(cc==HOST_CCREG);
5574         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5575         int jaddr=(int)out;
5576         emit_jns(0);
5577         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5578       }
5579     }
5580   }
5581 }
5582
5583 void sjump_assemble(int i,struct regstat *i_regs)
5584 {
5585   signed char *i_regmap=i_regs->regmap;
5586   int cc;
5587   int match;
5588   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5589   assem_debug("smatch=%d\n",match);
5590   int s1h,s1l;
5591   int prev_cop1_usable=cop1_usable;
5592   int unconditional=0,nevertaken=0;
5593   int only32=0;
5594   int ooo=1;
5595   int invert=0;
5596   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5597   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5598   if(likely[i]) ooo=0;
5599   if(!match) invert=1;
5600   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5601   if(i>(ba[i]-start)>>2) invert=1;
5602   #endif
5603
5604   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5605   assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5606
5607   if(ooo)
5608     if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5609   {
5610     // Write-after-read dependency prevents out of order execution
5611     // First test branch condition, then execute delay slot, then branch
5612     ooo=0;
5613   }
5614   // TODO: Conditional branches w/link must execute in-order so that
5615   // condition test and write to r31 occur before cycle count test
5616
5617   if(ooo) {
5618     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5619     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5620   }
5621   else {
5622     s1l=get_reg(i_regmap,rs1[i]);
5623     s1h=get_reg(i_regmap,rs1[i]|64);
5624   }
5625   if(rs1[i]==0)
5626   {
5627     if(opcode2[i]&1) unconditional=1;
5628     else nevertaken=1;
5629     // These are never taken (r0 is never less than zero)
5630     //assert(opcode2[i]!=0);
5631     //assert(opcode2[i]!=2);
5632     //assert(opcode2[i]!=0x10);
5633     //assert(opcode2[i]!=0x12);
5634   }
5635   else {
5636     only32=(regs[i].was32>>rs1[i])&1;
5637   }
5638
5639   if(ooo) {
5640     // Out of order execution (delay slot first)
5641     //printf("OOOE\n");
5642     address_generation(i+1,i_regs,regs[i].regmap_entry);
5643     ds_assemble(i+1,i_regs);
5644     int adj;
5645     uint64_t bc_unneeded=branch_regs[i].u;
5646     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5647     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5648     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5649     bc_unneeded|=1;
5650     bc_unneeded_upper|=1;
5651     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5652                   bc_unneeded,bc_unneeded_upper);
5653     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5654     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5655     if(rt1[i]==31) {
5656       int rt,return_address;
5657       assert(rt1[i+1]!=31);
5658       assert(rt2[i+1]!=31);
5659       rt=get_reg(branch_regs[i].regmap,31);
5660       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5661       if(rt>=0) {
5662         // Save the PC even if the branch is not taken
5663         return_address=start+i*4+8;
5664         emit_movimm(return_address,rt); // PC into link register
5665         #ifdef IMM_PREFETCH
5666         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5667         #endif
5668       }
5669     }
5670     cc=get_reg(branch_regs[i].regmap,CCREG);
5671     assert(cc==HOST_CCREG);
5672     if(unconditional)
5673       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5674     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5675     assem_debug("cycle count (adj)\n");
5676     if(unconditional) {
5677       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5678       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5679         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5680         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5681         if(internal)
5682           assem_debug("branch: internal\n");
5683         else
5684           assem_debug("branch: external\n");
5685         if(internal&&is_ds[(ba[i]-start)>>2]) {
5686           ds_assemble_entry(i);
5687         }
5688         else {
5689           add_to_linker((int)out,ba[i],internal);
5690           emit_jmp(0);
5691         }
5692         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5693         if(((u_int)out)&7) emit_addnop(0);
5694         #endif
5695       }
5696     }
5697     else if(nevertaken) {
5698       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5699       int jaddr=(int)out;
5700       emit_jns(0);
5701       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5702     }
5703     else {
5704       int nottaken=0;
5705       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5706       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5707       if(!only32)
5708       {
5709         assert(s1h>=0);
5710         if(opcode2[i]==0) // BLTZ
5711         {
5712           emit_test(s1h,s1h);
5713           if(invert){
5714             nottaken=(int)out;
5715             emit_jns(1);
5716           }else{
5717             add_to_linker((int)out,ba[i],internal);
5718             emit_js(0);
5719           }
5720         }
5721         if(opcode2[i]==1) // BGEZ
5722         {
5723           emit_test(s1h,s1h);
5724           if(invert){
5725             nottaken=(int)out;
5726             emit_js(1);
5727           }else{
5728             add_to_linker((int)out,ba[i],internal);
5729             emit_jns(0);
5730           }
5731         }
5732       } // if(!only32)
5733       else
5734       {
5735         assert(s1l>=0);
5736         if(opcode2[i]==0) // BLTZ
5737         {
5738           emit_test(s1l,s1l);
5739           if(invert){
5740             nottaken=(int)out;
5741             emit_jns(1);
5742           }else{
5743             add_to_linker((int)out,ba[i],internal);
5744             emit_js(0);
5745           }
5746         }
5747         if(opcode2[i]==1) // BGEZ
5748         {
5749           emit_test(s1l,s1l);
5750           if(invert){
5751             nottaken=(int)out;
5752             emit_js(1);
5753           }else{
5754             add_to_linker((int)out,ba[i],internal);
5755             emit_jns(0);
5756           }
5757         }
5758       } // if(!only32)
5759
5760       if(invert) {
5761         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5762         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5763           if(adj) {
5764             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5765             add_to_linker((int)out,ba[i],internal);
5766           }else{
5767             emit_addnop(13);
5768             add_to_linker((int)out,ba[i],internal*2);
5769           }
5770           emit_jmp(0);
5771         }else
5772         #endif
5773         {
5774           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5775           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5776           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5777           if(internal)
5778             assem_debug("branch: internal\n");
5779           else
5780             assem_debug("branch: external\n");
5781           if(internal&&is_ds[(ba[i]-start)>>2]) {
5782             ds_assemble_entry(i);
5783           }
5784           else {
5785             add_to_linker((int)out,ba[i],internal);
5786             emit_jmp(0);
5787           }
5788         }
5789         set_jump_target(nottaken,(int)out);
5790       }
5791
5792       if(adj) {
5793         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5794       }
5795     } // (!unconditional)
5796   } // if(ooo)
5797   else
5798   {
5799     // In-order execution (branch first)
5800     //printf("IOE\n");
5801     int nottaken=0;
5802     if(!unconditional) {
5803       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5804       if(!only32)
5805       {
5806         assert(s1h>=0);
5807         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5808         {
5809           emit_test(s1h,s1h);
5810           nottaken=(int)out;
5811           emit_jns(1);
5812         }
5813         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5814         {
5815           emit_test(s1h,s1h);
5816           nottaken=(int)out;
5817           emit_js(1);
5818         }
5819       } // if(!only32)
5820       else
5821       {
5822         assert(s1l>=0);
5823         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5824         {
5825           emit_test(s1l,s1l);
5826           nottaken=(int)out;
5827           emit_jns(1);
5828         }
5829         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5830         {
5831           emit_test(s1l,s1l);
5832           nottaken=(int)out;
5833           emit_js(1);
5834         }
5835       }
5836     } // if(!unconditional)
5837     int adj;
5838     uint64_t ds_unneeded=branch_regs[i].u;
5839     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5840     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5841     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5842     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5843     ds_unneeded|=1;
5844     ds_unneeded_upper|=1;
5845     // branch taken
5846     if(!nevertaken) {
5847       //assem_debug("1:\n");
5848       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5849                     ds_unneeded,ds_unneeded_upper);
5850       // load regs
5851       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5852       address_generation(i+1,&branch_regs[i],0);
5853       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5854       ds_assemble(i+1,&branch_regs[i]);
5855       cc=get_reg(branch_regs[i].regmap,CCREG);
5856       if(cc==-1) {
5857         emit_loadreg(CCREG,cc=HOST_CCREG);
5858         // CHECK: Is the following instruction (fall thru) allocated ok?
5859       }
5860       assert(cc==HOST_CCREG);
5861       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5862       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5863       assem_debug("cycle count (adj)\n");
5864       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5865       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5866       if(internal)
5867         assem_debug("branch: internal\n");
5868       else
5869         assem_debug("branch: external\n");
5870       if(internal&&is_ds[(ba[i]-start)>>2]) {
5871         ds_assemble_entry(i);
5872       }
5873       else {
5874         add_to_linker((int)out,ba[i],internal);
5875         emit_jmp(0);
5876       }
5877     }
5878     // branch not taken
5879     cop1_usable=prev_cop1_usable;
5880     if(!unconditional) {
5881       set_jump_target(nottaken,(int)out);
5882       assem_debug("1:\n");
5883       if(!likely[i]) {
5884         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5885                       ds_unneeded,ds_unneeded_upper);
5886         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5887         address_generation(i+1,&branch_regs[i],0);
5888         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5889         ds_assemble(i+1,&branch_regs[i]);
5890       }
5891       cc=get_reg(branch_regs[i].regmap,CCREG);
5892       if(cc==-1&&!likely[i]) {
5893         // Cycle count isn't in a register, temporarily load it then write it out
5894         emit_loadreg(CCREG,HOST_CCREG);
5895         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5896         int jaddr=(int)out;
5897         emit_jns(0);
5898         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5899         emit_storereg(CCREG,HOST_CCREG);
5900       }
5901       else{
5902         cc=get_reg(i_regmap,CCREG);
5903         assert(cc==HOST_CCREG);
5904         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5905         int jaddr=(int)out;
5906         emit_jns(0);
5907         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5908       }
5909     }
5910   }
5911 }
5912
5913 void fjump_assemble(int i,struct regstat *i_regs)
5914 {
5915   signed char *i_regmap=i_regs->regmap;
5916   int cc;
5917   int match;
5918   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5919   assem_debug("fmatch=%d\n",match);
5920   int fs,cs;
5921   int eaddr;
5922   int ooo=1;
5923   int invert=0;
5924   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5925   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5926   if(likely[i]) ooo=0;
5927   if(!match) invert=1;
5928   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5929   if(i>(ba[i]-start)>>2) invert=1;
5930   #endif
5931
5932   if(ooo)
5933     if(itype[i+1]==FCOMP)
5934   {
5935     // Write-after-read dependency prevents out of order execution
5936     // First test branch condition, then execute delay slot, then branch
5937     ooo=0;
5938   }
5939
5940   if(ooo) {
5941     fs=get_reg(branch_regs[i].regmap,FSREG);
5942     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5943   }
5944   else {
5945     fs=get_reg(i_regmap,FSREG);
5946   }
5947
5948   // Check cop1 unusable
5949   if(!cop1_usable) {
5950     cs=get_reg(i_regmap,CSREG);
5951     assert(cs>=0);
5952     emit_testimm(cs,0x20000000);
5953     eaddr=(int)out;
5954     emit_jeq(0);
5955     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5956     cop1_usable=1;
5957   }
5958
5959   if(ooo) {
5960     // Out of order execution (delay slot first)
5961     //printf("OOOE\n");
5962     ds_assemble(i+1,i_regs);
5963     int adj;
5964     uint64_t bc_unneeded=branch_regs[i].u;
5965     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5966     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5967     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5968     bc_unneeded|=1;
5969     bc_unneeded_upper|=1;
5970     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5971                   bc_unneeded,bc_unneeded_upper);
5972     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5973     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5974     cc=get_reg(branch_regs[i].regmap,CCREG);
5975     assert(cc==HOST_CCREG);
5976     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5977     assem_debug("cycle count (adj)\n");
5978     if(1) {
5979       int nottaken=0;
5980       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5981       if(1) {
5982         assert(fs>=0);
5983         emit_testimm(fs,0x800000);
5984         if(source[i]&0x10000) // BC1T
5985         {
5986           if(invert){
5987             nottaken=(int)out;
5988             emit_jeq(1);
5989           }else{
5990             add_to_linker((int)out,ba[i],internal);
5991             emit_jne(0);
5992           }
5993         }
5994         else // BC1F
5995           if(invert){
5996             nottaken=(int)out;
5997             emit_jne(1);
5998           }else{
5999             add_to_linker((int)out,ba[i],internal);
6000             emit_jeq(0);
6001           }
6002         {
6003         }
6004       } // if(!only32)
6005
6006       if(invert) {
6007         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6008         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6009         else if(match) emit_addnop(13);
6010         #endif
6011         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6012         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6013         if(internal)
6014           assem_debug("branch: internal\n");
6015         else
6016           assem_debug("branch: external\n");
6017         if(internal&&is_ds[(ba[i]-start)>>2]) {
6018           ds_assemble_entry(i);
6019         }
6020         else {
6021           add_to_linker((int)out,ba[i],internal);
6022           emit_jmp(0);
6023         }
6024         set_jump_target(nottaken,(int)out);
6025       }
6026
6027       if(adj) {
6028         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6029       }
6030     } // (!unconditional)
6031   } // if(ooo)
6032   else
6033   {
6034     // In-order execution (branch first)
6035     //printf("IOE\n");
6036     int nottaken=0;
6037     if(1) {
6038       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6039       if(1) {
6040         assert(fs>=0);
6041         emit_testimm(fs,0x800000);
6042         if(source[i]&0x10000) // BC1T
6043         {
6044           nottaken=(int)out;
6045           emit_jeq(1);
6046         }
6047         else // BC1F
6048         {
6049           nottaken=(int)out;
6050           emit_jne(1);
6051         }
6052       }
6053     } // if(!unconditional)
6054     int adj;
6055     uint64_t ds_unneeded=branch_regs[i].u;
6056     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6057     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6058     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6059     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6060     ds_unneeded|=1;
6061     ds_unneeded_upper|=1;
6062     // branch taken
6063     //assem_debug("1:\n");
6064     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6065                   ds_unneeded,ds_unneeded_upper);
6066     // load regs
6067     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6068     address_generation(i+1,&branch_regs[i],0);
6069     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6070     ds_assemble(i+1,&branch_regs[i]);
6071     cc=get_reg(branch_regs[i].regmap,CCREG);
6072     if(cc==-1) {
6073       emit_loadreg(CCREG,cc=HOST_CCREG);
6074       // CHECK: Is the following instruction (fall thru) allocated ok?
6075     }
6076     assert(cc==HOST_CCREG);
6077     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6078     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6079     assem_debug("cycle count (adj)\n");
6080     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6081     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6082     if(internal)
6083       assem_debug("branch: internal\n");
6084     else
6085       assem_debug("branch: external\n");
6086     if(internal&&is_ds[(ba[i]-start)>>2]) {
6087       ds_assemble_entry(i);
6088     }
6089     else {
6090       add_to_linker((int)out,ba[i],internal);
6091       emit_jmp(0);
6092     }
6093
6094     // branch not taken
6095     if(1) { // <- FIXME (don't need this)
6096       set_jump_target(nottaken,(int)out);
6097       assem_debug("1:\n");
6098       if(!likely[i]) {
6099         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6100                       ds_unneeded,ds_unneeded_upper);
6101         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6102         address_generation(i+1,&branch_regs[i],0);
6103         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6104         ds_assemble(i+1,&branch_regs[i]);
6105       }
6106       cc=get_reg(branch_regs[i].regmap,CCREG);
6107       if(cc==-1&&!likely[i]) {
6108         // Cycle count isn't in a register, temporarily load it then write it out
6109         emit_loadreg(CCREG,HOST_CCREG);
6110         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6111         int jaddr=(int)out;
6112         emit_jns(0);
6113         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6114         emit_storereg(CCREG,HOST_CCREG);
6115       }
6116       else{
6117         cc=get_reg(i_regmap,CCREG);
6118         assert(cc==HOST_CCREG);
6119         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6120         int jaddr=(int)out;
6121         emit_jns(0);
6122         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6123       }
6124     }
6125   }
6126 }
6127
6128 static void pagespan_assemble(int i,struct regstat *i_regs)
6129 {
6130   int s1l=get_reg(i_regs->regmap,rs1[i]);
6131   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6132   int s2l=get_reg(i_regs->regmap,rs2[i]);
6133   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6134   void *nt_branch=NULL;
6135   int taken=0;
6136   int nottaken=0;
6137   int unconditional=0;
6138   if(rs1[i]==0)
6139   {
6140     s1l=s2l;s1h=s2h;
6141     s2l=s2h=-1;
6142   }
6143   else if(rs2[i]==0)
6144   {
6145     s2l=s2h=-1;
6146   }
6147   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6148     s1h=s2h=-1;
6149   }
6150   int hr=0;
6151   int addr,alt,ntaddr;
6152   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6153   else {
6154     while(hr<HOST_REGS)
6155     {
6156       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6157          (i_regs->regmap[hr]&63)!=rs1[i] &&
6158          (i_regs->regmap[hr]&63)!=rs2[i] )
6159       {
6160         addr=hr++;break;
6161       }
6162       hr++;
6163     }
6164   }
6165   while(hr<HOST_REGS)
6166   {
6167     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6168        (i_regs->regmap[hr]&63)!=rs1[i] &&
6169        (i_regs->regmap[hr]&63)!=rs2[i] )
6170     {
6171       alt=hr++;break;
6172     }
6173     hr++;
6174   }
6175   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6176   {
6177     while(hr<HOST_REGS)
6178     {
6179       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6180          (i_regs->regmap[hr]&63)!=rs1[i] &&
6181          (i_regs->regmap[hr]&63)!=rs2[i] )
6182       {
6183         ntaddr=hr;break;
6184       }
6185       hr++;
6186     }
6187   }
6188   assert(hr<HOST_REGS);
6189   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6190     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6191   }
6192   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6193   if(opcode[i]==2) // J
6194   {
6195     unconditional=1;
6196   }
6197   if(opcode[i]==3) // JAL
6198   {
6199     // TODO: mini_ht
6200     int rt=get_reg(i_regs->regmap,31);
6201     emit_movimm(start+i*4+8,rt);
6202     unconditional=1;
6203   }
6204   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6205   {
6206     emit_mov(s1l,addr);
6207     if(opcode2[i]==9) // JALR
6208     {
6209       int rt=get_reg(i_regs->regmap,rt1[i]);
6210       emit_movimm(start+i*4+8,rt);
6211     }
6212   }
6213   if((opcode[i]&0x3f)==4) // BEQ
6214   {
6215     if(rs1[i]==rs2[i])
6216     {
6217       unconditional=1;
6218     }
6219     else
6220     #ifdef HAVE_CMOV_IMM
6221     if(s1h<0) {
6222       if(s2l>=0) emit_cmp(s1l,s2l);
6223       else emit_test(s1l,s1l);
6224       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6225     }
6226     else
6227     #endif
6228     {
6229       assert(s1l>=0);
6230       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6231       if(s1h>=0) {
6232         if(s2h>=0) emit_cmp(s1h,s2h);
6233         else emit_test(s1h,s1h);
6234         emit_cmovne_reg(alt,addr);
6235       }
6236       if(s2l>=0) emit_cmp(s1l,s2l);
6237       else emit_test(s1l,s1l);
6238       emit_cmovne_reg(alt,addr);
6239     }
6240   }
6241   if((opcode[i]&0x3f)==5) // BNE
6242   {
6243     #ifdef HAVE_CMOV_IMM
6244     if(s1h<0) {
6245       if(s2l>=0) emit_cmp(s1l,s2l);
6246       else emit_test(s1l,s1l);
6247       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6248     }
6249     else
6250     #endif
6251     {
6252       assert(s1l>=0);
6253       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6254       if(s1h>=0) {
6255         if(s2h>=0) emit_cmp(s1h,s2h);
6256         else emit_test(s1h,s1h);
6257         emit_cmovne_reg(alt,addr);
6258       }
6259       if(s2l>=0) emit_cmp(s1l,s2l);
6260       else emit_test(s1l,s1l);
6261       emit_cmovne_reg(alt,addr);
6262     }
6263   }
6264   if((opcode[i]&0x3f)==0x14) // BEQL
6265   {
6266     if(s1h>=0) {
6267       if(s2h>=0) emit_cmp(s1h,s2h);
6268       else emit_test(s1h,s1h);
6269       nottaken=(int)out;
6270       emit_jne(0);
6271     }
6272     if(s2l>=0) emit_cmp(s1l,s2l);
6273     else emit_test(s1l,s1l);
6274     if(nottaken) set_jump_target(nottaken,(int)out);
6275     nottaken=(int)out;
6276     emit_jne(0);
6277   }
6278   if((opcode[i]&0x3f)==0x15) // BNEL
6279   {
6280     if(s1h>=0) {
6281       if(s2h>=0) emit_cmp(s1h,s2h);
6282       else emit_test(s1h,s1h);
6283       taken=(int)out;
6284       emit_jne(0);
6285     }
6286     if(s2l>=0) emit_cmp(s1l,s2l);
6287     else emit_test(s1l,s1l);
6288     nottaken=(int)out;
6289     emit_jeq(0);
6290     if(taken) set_jump_target(taken,(int)out);
6291   }
6292   if((opcode[i]&0x3f)==6) // BLEZ
6293   {
6294     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6295     emit_cmpimm(s1l,1);
6296     if(s1h>=0) emit_mov(addr,ntaddr);
6297     emit_cmovl_reg(alt,addr);
6298     if(s1h>=0) {
6299       emit_test(s1h,s1h);
6300       emit_cmovne_reg(ntaddr,addr);
6301       emit_cmovs_reg(alt,addr);
6302     }
6303   }
6304   if((opcode[i]&0x3f)==7) // BGTZ
6305   {
6306     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6307     emit_cmpimm(s1l,1);
6308     if(s1h>=0) emit_mov(addr,alt);
6309     emit_cmovl_reg(ntaddr,addr);
6310     if(s1h>=0) {
6311       emit_test(s1h,s1h);
6312       emit_cmovne_reg(alt,addr);
6313       emit_cmovs_reg(ntaddr,addr);
6314     }
6315   }
6316   if((opcode[i]&0x3f)==0x16) // BLEZL
6317   {
6318     assert((opcode[i]&0x3f)!=0x16);
6319   }
6320   if((opcode[i]&0x3f)==0x17) // BGTZL
6321   {
6322     assert((opcode[i]&0x3f)!=0x17);
6323   }
6324   assert(opcode[i]!=1); // BLTZ/BGEZ
6325
6326   //FIXME: Check CSREG
6327   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6328     if((source[i]&0x30000)==0) // BC1F
6329     {
6330       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6331       emit_testimm(s1l,0x800000);
6332       emit_cmovne_reg(alt,addr);
6333     }
6334     if((source[i]&0x30000)==0x10000) // BC1T
6335     {
6336       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6337       emit_testimm(s1l,0x800000);
6338       emit_cmovne_reg(alt,addr);
6339     }
6340     if((source[i]&0x30000)==0x20000) // BC1FL
6341     {
6342       emit_testimm(s1l,0x800000);
6343       nottaken=(int)out;
6344       emit_jne(0);
6345     }
6346     if((source[i]&0x30000)==0x30000) // BC1TL
6347     {
6348       emit_testimm(s1l,0x800000);
6349       nottaken=(int)out;
6350       emit_jeq(0);
6351     }
6352   }
6353
6354   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6355   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6356   if(likely[i]||unconditional)
6357   {
6358     emit_movimm(ba[i],HOST_BTREG);
6359   }
6360   else if(addr!=HOST_BTREG)
6361   {
6362     emit_mov(addr,HOST_BTREG);
6363   }
6364   void *branch_addr=out;
6365   emit_jmp(0);
6366   int target_addr=start+i*4+5;
6367   void *stub=out;
6368   void *compiled_target_addr=check_addr(target_addr);
6369   emit_extjump_ds((int)branch_addr,target_addr);
6370   if(compiled_target_addr) {
6371     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6372     add_link(target_addr,stub);
6373   }
6374   else set_jump_target((int)branch_addr,(int)stub);
6375   if(likely[i]) {
6376     // Not-taken path
6377     set_jump_target((int)nottaken,(int)out);
6378     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6379     void *branch_addr=out;
6380     emit_jmp(0);
6381     int target_addr=start+i*4+8;
6382     void *stub=out;
6383     void *compiled_target_addr=check_addr(target_addr);
6384     emit_extjump_ds((int)branch_addr,target_addr);
6385     if(compiled_target_addr) {
6386       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6387       add_link(target_addr,stub);
6388     }
6389     else set_jump_target((int)branch_addr,(int)stub);
6390   }
6391 }
6392
6393 // Assemble the delay slot for the above
6394 static void pagespan_ds()
6395 {
6396   assem_debug("initial delay slot:\n");
6397   u_int vaddr=start+1;
6398   u_int page=get_page(vaddr);
6399   u_int vpage=get_vpage(vaddr);
6400   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6401   do_dirty_stub_ds();
6402   ll_add(jump_in+page,vaddr,(void *)out);
6403   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6404   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6405     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6406   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6407     emit_writeword(HOST_BTREG,(int)&branch_target);
6408   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6409   address_generation(0,&regs[0],regs[0].regmap_entry);
6410   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6411     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6412   cop1_usable=0;
6413   is_delayslot=0;
6414   switch(itype[0]) {
6415     case ALU:
6416       alu_assemble(0,&regs[0]);break;
6417     case IMM16:
6418       imm16_assemble(0,&regs[0]);break;
6419     case SHIFT:
6420       shift_assemble(0,&regs[0]);break;
6421     case SHIFTIMM:
6422       shiftimm_assemble(0,&regs[0]);break;
6423     case LOAD:
6424       load_assemble(0,&regs[0]);break;
6425     case LOADLR:
6426       loadlr_assemble(0,&regs[0]);break;
6427     case STORE:
6428       store_assemble(0,&regs[0]);break;
6429     case STORELR:
6430       storelr_assemble(0,&regs[0]);break;
6431     case COP0:
6432       cop0_assemble(0,&regs[0]);break;
6433     case COP1:
6434       cop1_assemble(0,&regs[0]);break;
6435     case C1LS:
6436       c1ls_assemble(0,&regs[0]);break;
6437     case COP2:
6438       cop2_assemble(0,&regs[0]);break;
6439     case C2LS:
6440       c2ls_assemble(0,&regs[0]);break;
6441     case C2OP:
6442       c2op_assemble(0,&regs[0]);break;
6443     case FCONV:
6444       fconv_assemble(0,&regs[0]);break;
6445     case FLOAT:
6446       float_assemble(0,&regs[0]);break;
6447     case FCOMP:
6448       fcomp_assemble(0,&regs[0]);break;
6449     case MULTDIV:
6450       multdiv_assemble(0,&regs[0]);break;
6451     case MOV:
6452       mov_assemble(0,&regs[0]);break;
6453     case SYSCALL:
6454     case HLECALL:
6455     case SPAN:
6456     case UJUMP:
6457     case RJUMP:
6458     case CJUMP:
6459     case SJUMP:
6460     case FJUMP:
6461       printf("Jump in the delay slot.  This is probably a bug.\n");
6462   }
6463   int btaddr=get_reg(regs[0].regmap,BTREG);
6464   if(btaddr<0) {
6465     btaddr=get_reg(regs[0].regmap,-1);
6466     emit_readword((int)&branch_target,btaddr);
6467   }
6468   assert(btaddr!=HOST_CCREG);
6469   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6470 #ifdef HOST_IMM8
6471   emit_movimm(start+4,HOST_TEMPREG);
6472   emit_cmp(btaddr,HOST_TEMPREG);
6473 #else
6474   emit_cmpimm(btaddr,start+4);
6475 #endif
6476   int branch=(int)out;
6477   emit_jeq(0);
6478   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6479   emit_jmp(jump_vaddr_reg[btaddr]);
6480   set_jump_target(branch,(int)out);
6481   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6482   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6483 }
6484
6485 // Basic liveness analysis for MIPS registers
6486 void unneeded_registers(int istart,int iend,int r)
6487 {
6488   int i;
6489   uint64_t u,uu,b,bu;
6490   uint64_t temp_u,temp_uu;
6491   uint64_t tdep;
6492   if(iend==slen-1) {
6493     u=1;uu=1;
6494   }else{
6495     u=unneeded_reg[iend+1];
6496     uu=unneeded_reg_upper[iend+1];
6497     u=1;uu=1;
6498   }
6499   for (i=iend;i>=istart;i--)
6500   {
6501     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6502     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6503     {
6504       // If subroutine call, flag return address as a possible branch target
6505       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6506
6507       if(ba[i]<start || ba[i]>=(start+slen*4))
6508       {
6509         // Branch out of this block, flush all regs
6510         u=1;
6511         uu=1;
6512         /* Hexagon hack
6513         if(itype[i]==UJUMP&&rt1[i]==31)
6514         {
6515           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6516         }
6517         if(itype[i]==RJUMP&&rs1[i]==31)
6518         {
6519           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6520         }
6521         if(start>0x80000400&&start<0x80800000) {
6522           if(itype[i]==UJUMP&&rt1[i]==31)
6523           {
6524             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6525             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6526           }
6527           if(itype[i]==RJUMP&&rs1[i]==31)
6528           {
6529             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6530             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6531           }
6532         }*/
6533         branch_unneeded_reg[i]=u;
6534         branch_unneeded_reg_upper[i]=uu;
6535         // Merge in delay slot
6536         tdep=(~uu>>rt1[i+1])&1;
6537         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6538         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6539         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6540         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6541         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6542         u|=1;uu|=1;
6543         // If branch is "likely" (and conditional)
6544         // then we skip the delay slot on the fall-thru path
6545         if(likely[i]) {
6546           if(i<slen-1) {
6547             u&=unneeded_reg[i+2];
6548             uu&=unneeded_reg_upper[i+2];
6549           }
6550           else
6551           {
6552             u=1;
6553             uu=1;
6554           }
6555         }
6556       }
6557       else
6558       {
6559         // Internal branch, flag target
6560         bt[(ba[i]-start)>>2]=1;
6561         if(ba[i]<=start+i*4) {
6562           // Backward branch
6563           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6564           {
6565             // Unconditional branch
6566             temp_u=1;temp_uu=1;
6567           } else {
6568             // Conditional branch (not taken case)
6569             temp_u=unneeded_reg[i+2];
6570             temp_uu=unneeded_reg_upper[i+2];
6571           }
6572           // Merge in delay slot
6573           tdep=(~temp_uu>>rt1[i+1])&1;
6574           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6575           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6576           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6577           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6578           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6579           temp_u|=1;temp_uu|=1;
6580           // If branch is "likely" (and conditional)
6581           // then we skip the delay slot on the fall-thru path
6582           if(likely[i]) {
6583             if(i<slen-1) {
6584               temp_u&=unneeded_reg[i+2];
6585               temp_uu&=unneeded_reg_upper[i+2];
6586             }
6587             else
6588             {
6589               temp_u=1;
6590               temp_uu=1;
6591             }
6592           }
6593           tdep=(~temp_uu>>rt1[i])&1;
6594           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6595           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6596           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6597           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6598           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6599           temp_u|=1;temp_uu|=1;
6600           unneeded_reg[i]=temp_u;
6601           unneeded_reg_upper[i]=temp_uu;
6602           // Only go three levels deep.  This recursion can take an
6603           // excessive amount of time if there are a lot of nested loops.
6604           if(r<2) {
6605             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6606           }else{
6607             unneeded_reg[(ba[i]-start)>>2]=1;
6608             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6609           }
6610         } /*else*/ if(1) {
6611           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6612           {
6613             // Unconditional branch
6614             u=unneeded_reg[(ba[i]-start)>>2];
6615             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6616             branch_unneeded_reg[i]=u;
6617             branch_unneeded_reg_upper[i]=uu;
6618         //u=1;
6619         //uu=1;
6620         //branch_unneeded_reg[i]=u;
6621         //branch_unneeded_reg_upper[i]=uu;
6622             // Merge in delay slot
6623             tdep=(~uu>>rt1[i+1])&1;
6624             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6625             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6626             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6627             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6628             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6629             u|=1;uu|=1;
6630           } else {
6631             // Conditional branch
6632             b=unneeded_reg[(ba[i]-start)>>2];
6633             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6634             branch_unneeded_reg[i]=b;
6635             branch_unneeded_reg_upper[i]=bu;
6636         //b=1;
6637         //bu=1;
6638         //branch_unneeded_reg[i]=b;
6639         //branch_unneeded_reg_upper[i]=bu;
6640             // Branch delay slot
6641             tdep=(~uu>>rt1[i+1])&1;
6642             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6643             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6644             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6645             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6646             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6647             b|=1;bu|=1;
6648             // If branch is "likely" then we skip the
6649             // delay slot on the fall-thru path
6650             if(likely[i]) {
6651               u=b;
6652               uu=bu;
6653               if(i<slen-1) {
6654                 u&=unneeded_reg[i+2];
6655                 uu&=unneeded_reg_upper[i+2];
6656         //u=1;
6657         //uu=1;
6658               }
6659             } else {
6660               u&=b;
6661               uu&=bu;
6662         //u=1;
6663         //uu=1;
6664             }
6665             if(i<slen-1) {
6666               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6667               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6668         //branch_unneeded_reg[i]=1;
6669         //branch_unneeded_reg_upper[i]=1;
6670             } else {
6671               branch_unneeded_reg[i]=1;
6672               branch_unneeded_reg_upper[i]=1;
6673             }
6674           }
6675         }
6676       }
6677     }
6678     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
6679     {
6680       // SYSCALL instruction (software interrupt)
6681       u=1;
6682       uu=1;
6683     }
6684     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6685     {
6686       // ERET instruction (return from interrupt)
6687       u=1;
6688       uu=1;
6689     }
6690     //u=uu=1; // DEBUG
6691     tdep=(~uu>>rt1[i])&1;
6692     // Written registers are unneeded
6693     u|=1LL<<rt1[i];
6694     u|=1LL<<rt2[i];
6695     uu|=1LL<<rt1[i];
6696     uu|=1LL<<rt2[i];
6697     // Accessed registers are needed
6698     u&=~(1LL<<rs1[i]);
6699     u&=~(1LL<<rs2[i]);
6700     uu&=~(1LL<<us1[i]);
6701     uu&=~(1LL<<us2[i]);
6702     // Source-target dependencies
6703     uu&=~(tdep<<dep1[i]);
6704     uu&=~(tdep<<dep2[i]);
6705     // R0 is always unneeded
6706     u|=1;uu|=1;
6707     // Save it
6708     unneeded_reg[i]=u;
6709     unneeded_reg_upper[i]=uu;
6710     /*
6711     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6712     printf("U:");
6713     int r;
6714     for(r=1;r<=CCREG;r++) {
6715       if((unneeded_reg[i]>>r)&1) {
6716         if(r==HIREG) printf(" HI");
6717         else if(r==LOREG) printf(" LO");
6718         else printf(" r%d",r);
6719       }
6720     }
6721     printf(" UU:");
6722     for(r=1;r<=CCREG;r++) {
6723       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6724         if(r==HIREG) printf(" HI");
6725         else if(r==LOREG) printf(" LO");
6726         else printf(" r%d",r);
6727       }
6728     }
6729     printf("\n");*/
6730   }
6731 #ifdef FORCE32
6732   for (i=iend;i>=istart;i--)
6733   {
6734     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6735   }
6736 #endif
6737 }
6738
6739 // Identify registers which are likely to contain 32-bit values
6740 // This is used to predict whether any branches will jump to a
6741 // location with 64-bit values in registers.
6742 static void provisional_32bit()
6743 {
6744   int i,j;
6745   uint64_t is32=1;
6746   uint64_t lastbranch=1;
6747
6748   for(i=0;i<slen;i++)
6749   {
6750     if(i>0) {
6751       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6752         if(i>1) is32=lastbranch;
6753         else is32=1;
6754       }
6755     }
6756     if(i>1)
6757     {
6758       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6759         if(likely[i-2]) {
6760           if(i>2) is32=lastbranch;
6761           else is32=1;
6762         }
6763       }
6764       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6765       {
6766         if(rs1[i-2]==0||rs2[i-2]==0)
6767         {
6768           if(rs1[i-2]) {
6769             is32|=1LL<<rs1[i-2];
6770           }
6771           if(rs2[i-2]) {
6772             is32|=1LL<<rs2[i-2];
6773           }
6774         }
6775       }
6776     }
6777     // If something jumps here with 64-bit values
6778     // then promote those registers to 64 bits
6779     if(bt[i])
6780     {
6781       uint64_t temp_is32=is32;
6782       for(j=i-1;j>=0;j--)
6783       {
6784         if(ba[j]==start+i*4)
6785           //temp_is32&=branch_regs[j].is32;
6786           temp_is32&=p32[j];
6787       }
6788       for(j=i;j<slen;j++)
6789       {
6790         if(ba[j]==start+i*4)
6791           temp_is32=1;
6792       }
6793       is32=temp_is32;
6794     }
6795     int type=itype[i];
6796     int op=opcode[i];
6797     int op2=opcode2[i];
6798     int rt=rt1[i];
6799     int s1=rs1[i];
6800     int s2=rs2[i];
6801     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6802       // Branches don't write registers, consider the delay slot instead.
6803       type=itype[i+1];
6804       op=opcode[i+1];
6805       op2=opcode2[i+1];
6806       rt=rt1[i+1];
6807       s1=rs1[i+1];
6808       s2=rs2[i+1];
6809       lastbranch=is32;
6810     }
6811     switch(type) {
6812       case LOAD:
6813         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6814            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6815           is32&=~(1LL<<rt);
6816         else
6817           is32|=1LL<<rt;
6818         break;
6819       case STORE:
6820       case STORELR:
6821         break;
6822       case LOADLR:
6823         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6824         if(op==0x22) is32|=1LL<<rt; // LWL
6825         break;
6826       case IMM16:
6827         if (op==0x08||op==0x09|| // ADDI/ADDIU
6828             op==0x0a||op==0x0b|| // SLTI/SLTIU
6829             op==0x0c|| // ANDI
6830             op==0x0f)  // LUI
6831         {
6832           is32|=1LL<<rt;
6833         }
6834         if(op==0x18||op==0x19) { // DADDI/DADDIU
6835           is32&=~(1LL<<rt);
6836           //if(imm[i]==0)
6837           //  is32|=((is32>>s1)&1LL)<<rt;
6838         }
6839         if(op==0x0d||op==0x0e) { // ORI/XORI
6840           uint64_t sr=((is32>>s1)&1LL);
6841           is32&=~(1LL<<rt);
6842           is32|=sr<<rt;
6843         }
6844         break;
6845       case UJUMP:
6846         break;
6847       case RJUMP:
6848         break;
6849       case CJUMP:
6850         break;
6851       case SJUMP:
6852         break;
6853       case FJUMP:
6854         break;
6855       case ALU:
6856         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6857           is32|=1LL<<rt;
6858         }
6859         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6860           is32|=1LL<<rt;
6861         }
6862         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6863           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6864           is32&=~(1LL<<rt);
6865           is32|=sr<<rt;
6866         }
6867         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6868           if(s1==0&&s2==0) {
6869             is32|=1LL<<rt;
6870           }
6871           else if(s2==0) {
6872             uint64_t sr=((is32>>s1)&1LL);
6873             is32&=~(1LL<<rt);
6874             is32|=sr<<rt;
6875           }
6876           else if(s1==0) {
6877             uint64_t sr=((is32>>s2)&1LL);
6878             is32&=~(1LL<<rt);
6879             is32|=sr<<rt;
6880           }
6881           else {
6882             is32&=~(1LL<<rt);
6883           }
6884         }
6885         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6886           if(s1==0&&s2==0) {
6887             is32|=1LL<<rt;
6888           }
6889           else if(s2==0) {
6890             uint64_t sr=((is32>>s1)&1LL);
6891             is32&=~(1LL<<rt);
6892             is32|=sr<<rt;
6893           }
6894           else {
6895             is32&=~(1LL<<rt);
6896           }
6897         }
6898         break;
6899       case MULTDIV:
6900         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6901           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6902         }
6903         else {
6904           is32|=(1LL<<HIREG)|(1LL<<LOREG);
6905         }
6906         break;
6907       case MOV:
6908         {
6909           uint64_t sr=((is32>>s1)&1LL);
6910           is32&=~(1LL<<rt);
6911           is32|=sr<<rt;
6912         }
6913         break;
6914       case SHIFT:
6915         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6916         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6917         break;
6918       case SHIFTIMM:
6919         is32|=1LL<<rt;
6920         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6921         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6922         break;
6923       case COP0:
6924         if(op2==0) is32|=1LL<<rt; // MFC0
6925         break;
6926       case COP1:
6927       case COP2:
6928         if(op2==0) is32|=1LL<<rt; // MFC1
6929         if(op2==1) is32&=~(1LL<<rt); // DMFC1
6930         if(op2==2) is32|=1LL<<rt; // CFC1
6931         break;
6932       case C1LS:
6933       case C2LS:
6934         break;
6935       case FLOAT:
6936       case FCONV:
6937         break;
6938       case FCOMP:
6939         break;
6940       case C2OP:
6941       case SYSCALL:
6942       case HLECALL:
6943         break;
6944       default:
6945         break;
6946     }
6947     is32|=1;
6948     p32[i]=is32;
6949
6950     if(i>0)
6951     {
6952       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6953       {
6954         if(rt1[i-1]==31) // JAL/JALR
6955         {
6956           // Subroutine call will return here, don't alloc any registers
6957           is32=1;
6958         }
6959         else if(i+1<slen)
6960         {
6961           // Internal branch will jump here, match registers to caller
6962           is32=0x3FFFFFFFFLL;
6963         }
6964       }
6965     }
6966   }
6967 }
6968
6969 // Identify registers which may be assumed to contain 32-bit values
6970 // and where optimizations will rely on this.
6971 // This is used to determine whether backward branches can safely
6972 // jump to a location with 64-bit values in registers.
6973 static void provisional_r32()
6974 {
6975   u_int r32=0;
6976   int i;
6977
6978   for (i=slen-1;i>=0;i--)
6979   {
6980     int hr;
6981     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6982     {
6983       if(ba[i]<start || ba[i]>=(start+slen*4))
6984       {
6985         // Branch out of this block, don't need anything
6986         r32=0;
6987       }
6988       else
6989       {
6990         // Internal branch
6991         // Need whatever matches the target
6992         // (and doesn't get overwritten by the delay slot instruction)
6993         r32=0;
6994         int t=(ba[i]-start)>>2;
6995         if(ba[i]>start+i*4) {
6996           // Forward branch
6997           //if(!(requires_32bit[t]&~regs[i].was32))
6998           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6999           if(!(pr32[t]&~regs[i].was32))
7000             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7001         }else{
7002           // Backward branch
7003           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7004             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7005         }
7006       }
7007       // Conditional branch may need registers for following instructions
7008       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7009       {
7010         if(i<slen-2) {
7011           //r32|=requires_32bit[i+2];
7012           r32|=pr32[i+2];
7013           r32&=regs[i].was32;
7014           // Mark this address as a branch target since it may be called
7015           // upon return from interrupt
7016           //bt[i+2]=1;
7017         }
7018       }
7019       // Merge in delay slot
7020       if(!likely[i]) {
7021         // These are overwritten unless the branch is "likely"
7022         // and the delay slot is nullified if not taken
7023         r32&=~(1LL<<rt1[i+1]);
7024         r32&=~(1LL<<rt2[i+1]);
7025       }
7026       // Assume these are needed (delay slot)
7027       if(us1[i+1]>0)
7028       {
7029         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7030       }
7031       if(us2[i+1]>0)
7032       {
7033         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7034       }
7035       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7036       {
7037         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7038       }
7039       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7040       {
7041         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7042       }
7043     }
7044     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
7045     {
7046       // SYSCALL instruction (software interrupt)
7047       r32=0;
7048     }
7049     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7050     {
7051       // ERET instruction (return from interrupt)
7052       r32=0;
7053     }
7054     // Check 32 bits
7055     r32&=~(1LL<<rt1[i]);
7056     r32&=~(1LL<<rt2[i]);
7057     if(us1[i]>0)
7058     {
7059       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7060     }
7061     if(us2[i]>0)
7062     {
7063       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7064     }
7065     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7066     {
7067       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7068     }
7069     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7070     {
7071       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7072     }
7073     //requires_32bit[i]=r32;
7074     pr32[i]=r32;
7075
7076     // Dirty registers which are 32-bit, require 32-bit input
7077     // as they will be written as 32-bit values
7078     for(hr=0;hr<HOST_REGS;hr++)
7079     {
7080       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7081         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7082           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7083           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7084           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7085         }
7086       }
7087     }
7088   }
7089 }
7090
7091 // Write back dirty registers as soon as we will no longer modify them,
7092 // so that we don't end up with lots of writes at the branches.
7093 void clean_registers(int istart,int iend,int wr)
7094 {
7095   int i;
7096   int r;
7097   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7098   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7099   if(iend==slen-1) {
7100     will_dirty_i=will_dirty_next=0;
7101     wont_dirty_i=wont_dirty_next=0;
7102   }else{
7103     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7104     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7105   }
7106   for (i=iend;i>=istart;i--)
7107   {
7108     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7109     {
7110       if(ba[i]<start || ba[i]>=(start+slen*4))
7111       {
7112         // Branch out of this block, flush all regs
7113         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7114         {
7115           // Unconditional branch
7116           will_dirty_i=0;
7117           wont_dirty_i=0;
7118           // Merge in delay slot (will dirty)
7119           for(r=0;r<HOST_REGS;r++) {
7120             if(r!=EXCLUDE_REG) {
7121               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7122               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7123               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7124               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7125               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7126               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7127               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7128               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7129               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7130               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7131               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7132               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7133               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7134               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7135             }
7136           }
7137         }
7138         else
7139         {
7140           // Conditional branch
7141           will_dirty_i=0;
7142           wont_dirty_i=wont_dirty_next;
7143           // Merge in delay slot (will dirty)
7144           for(r=0;r<HOST_REGS;r++) {
7145             if(r!=EXCLUDE_REG) {
7146               if(!likely[i]) {
7147                 // Might not dirty if likely branch is not taken
7148                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7149                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7150                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7151                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7152                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7153                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7154                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7155                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7156                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7157                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7158                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7159                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7160                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7161                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7162               }
7163             }
7164           }
7165         }
7166         // Merge in delay slot (wont dirty)
7167         for(r=0;r<HOST_REGS;r++) {
7168           if(r!=EXCLUDE_REG) {
7169             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7170             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7171             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7172             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7173             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7174             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7175             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7176             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7177             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7178             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7179           }
7180         }
7181         if(wr) {
7182           #ifndef DESTRUCTIVE_WRITEBACK
7183           branch_regs[i].dirty&=wont_dirty_i;
7184           #endif
7185           branch_regs[i].dirty|=will_dirty_i;
7186         }
7187       }
7188       else
7189       {
7190         // Internal branch
7191         if(ba[i]<=start+i*4) {
7192           // Backward branch
7193           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7194           {
7195             // Unconditional branch
7196             temp_will_dirty=0;
7197             temp_wont_dirty=0;
7198             // Merge in delay slot (will dirty)
7199             for(r=0;r<HOST_REGS;r++) {
7200               if(r!=EXCLUDE_REG) {
7201                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7202                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7203                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7204                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7205                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7206                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7207                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7208                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7209                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7210                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7211                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7212                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7213                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7214                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7215               }
7216             }
7217           } else {
7218             // Conditional branch (not taken case)
7219             temp_will_dirty=will_dirty_next;
7220             temp_wont_dirty=wont_dirty_next;
7221             // Merge in delay slot (will dirty)
7222             for(r=0;r<HOST_REGS;r++) {
7223               if(r!=EXCLUDE_REG) {
7224                 if(!likely[i]) {
7225                   // Will not dirty if likely branch is not taken
7226                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7227                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7228                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7229                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7230                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7231                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7232                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7233                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7234                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7235                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7236                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7237                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7238                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7239                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7240                 }
7241               }
7242             }
7243           }
7244           // Merge in delay slot (wont dirty)
7245           for(r=0;r<HOST_REGS;r++) {
7246             if(r!=EXCLUDE_REG) {
7247               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7248               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7249               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7250               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7251               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7252               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7253               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7254               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7255               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7256               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7257             }
7258           }
7259           // Deal with changed mappings
7260           if(i<iend) {
7261             for(r=0;r<HOST_REGS;r++) {
7262               if(r!=EXCLUDE_REG) {
7263                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7264                   temp_will_dirty&=~(1<<r);
7265                   temp_wont_dirty&=~(1<<r);
7266                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7267                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7268                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7269                   } else {
7270                     temp_will_dirty|=1<<r;
7271                     temp_wont_dirty|=1<<r;
7272                   }
7273                 }
7274               }
7275             }
7276           }
7277           if(wr) {
7278             will_dirty[i]=temp_will_dirty;
7279             wont_dirty[i]=temp_wont_dirty;
7280             clean_registers((ba[i]-start)>>2,i-1,0);
7281           }else{
7282             // Limit recursion.  It can take an excessive amount
7283             // of time if there are a lot of nested loops.
7284             will_dirty[(ba[i]-start)>>2]=0;
7285             wont_dirty[(ba[i]-start)>>2]=-1;
7286           }
7287         }
7288         /*else*/ if(1)
7289         {
7290           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7291           {
7292             // Unconditional branch
7293             will_dirty_i=0;
7294             wont_dirty_i=0;
7295           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7296             for(r=0;r<HOST_REGS;r++) {
7297               if(r!=EXCLUDE_REG) {
7298                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7299                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7300                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7301                 }
7302               }
7303             }
7304           //}
7305             // Merge in delay slot
7306             for(r=0;r<HOST_REGS;r++) {
7307               if(r!=EXCLUDE_REG) {
7308                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7309                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7310                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7311                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7312                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7313                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7314                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7315                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7316                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7317                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7318                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7319                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7320                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7321                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7322               }
7323             }
7324           } else {
7325             // Conditional branch
7326             will_dirty_i=will_dirty_next;
7327             wont_dirty_i=wont_dirty_next;
7328           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7329             for(r=0;r<HOST_REGS;r++) {
7330               if(r!=EXCLUDE_REG) {
7331                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7332                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7333                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7334                 }
7335                 else
7336                 {
7337                   will_dirty_i&=~(1<<r);
7338                 }
7339                 // Treat delay slot as part of branch too
7340                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7341                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7342                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7343                 }
7344                 else
7345                 {
7346                   will_dirty[i+1]&=~(1<<r);
7347                 }*/
7348               }
7349             }
7350           //}
7351             // Merge in delay slot
7352             for(r=0;r<HOST_REGS;r++) {
7353               if(r!=EXCLUDE_REG) {
7354                 if(!likely[i]) {
7355                   // Might not dirty if likely branch is not taken
7356                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7357                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7358                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7359                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7360                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7361                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7362                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7363                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7364                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7365                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7366                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7367                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7368                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7369                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7370                 }
7371               }
7372             }
7373           }
7374           // Merge in delay slot
7375           for(r=0;r<HOST_REGS;r++) {
7376             if(r!=EXCLUDE_REG) {
7377               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7378               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7379               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7380               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7381               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7382               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7383               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7384               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7385               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7386               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7387             }
7388           }
7389           if(wr) {
7390             #ifndef DESTRUCTIVE_WRITEBACK
7391             branch_regs[i].dirty&=wont_dirty_i;
7392             #endif
7393             branch_regs[i].dirty|=will_dirty_i;
7394           }
7395         }
7396       }
7397     }
7398     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
7399     {
7400       // SYSCALL instruction (software interrupt)
7401       will_dirty_i=0;
7402       wont_dirty_i=0;
7403     }
7404     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7405     {
7406       // ERET instruction (return from interrupt)
7407       will_dirty_i=0;
7408       wont_dirty_i=0;
7409     }
7410     will_dirty_next=will_dirty_i;
7411     wont_dirty_next=wont_dirty_i;
7412     for(r=0;r<HOST_REGS;r++) {
7413       if(r!=EXCLUDE_REG) {
7414         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7415         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7416         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7417         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7418         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7419         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7420         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7421         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7422         if(i>istart) {
7423           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7424           {
7425             // Don't store a register immediately after writing it,
7426             // may prevent dual-issue.
7427             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7428             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7429           }
7430         }
7431       }
7432     }
7433     // Save it
7434     will_dirty[i]=will_dirty_i;
7435     wont_dirty[i]=wont_dirty_i;
7436     // Mark registers that won't be dirtied as not dirty
7437     if(wr) {
7438       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7439       for(r=0;r<HOST_REGS;r++) {
7440         if((will_dirty_i>>r)&1) {
7441           printf(" r%d",r);
7442         }
7443       }
7444       printf("\n");*/
7445
7446       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7447         regs[i].dirty|=will_dirty_i;
7448         #ifndef DESTRUCTIVE_WRITEBACK
7449         regs[i].dirty&=wont_dirty_i;
7450         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7451         {
7452           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7453             for(r=0;r<HOST_REGS;r++) {
7454               if(r!=EXCLUDE_REG) {
7455                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7456                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7457                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7458               }
7459             }
7460           }
7461         }
7462         else
7463         {
7464           if(i<iend) {
7465             for(r=0;r<HOST_REGS;r++) {
7466               if(r!=EXCLUDE_REG) {
7467                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7468                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7469                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7470               }
7471             }
7472           }
7473         }
7474         #endif
7475       //}
7476     }
7477     // Deal with changed mappings
7478     temp_will_dirty=will_dirty_i;
7479     temp_wont_dirty=wont_dirty_i;
7480     for(r=0;r<HOST_REGS;r++) {
7481       if(r!=EXCLUDE_REG) {
7482         int nr;
7483         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7484           if(wr) {
7485             #ifndef DESTRUCTIVE_WRITEBACK
7486             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7487             #endif
7488             regs[i].wasdirty|=will_dirty_i&(1<<r);
7489           }
7490         }
7491         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7492           // Register moved to a different register
7493           will_dirty_i&=~(1<<r);
7494           wont_dirty_i&=~(1<<r);
7495           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7496           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7497           if(wr) {
7498             #ifndef DESTRUCTIVE_WRITEBACK
7499             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7500             #endif
7501             regs[i].wasdirty|=will_dirty_i&(1<<r);
7502           }
7503         }
7504         else {
7505           will_dirty_i&=~(1<<r);
7506           wont_dirty_i&=~(1<<r);
7507           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7508             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7509             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7510           } else {
7511             wont_dirty_i|=1<<r;
7512             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7513           }
7514         }
7515       }
7516     }
7517   }
7518 }
7519
7520   /* disassembly */
7521 void disassemble_inst(int i)
7522 {
7523     if (bt[i]) printf("*"); else printf(" ");
7524     switch(itype[i]) {
7525       case UJUMP:
7526         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7527       case CJUMP:
7528         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7529       case SJUMP:
7530         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7531       case FJUMP:
7532         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7533       case RJUMP:
7534         if (rt1[i]!=31)
7535           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7536         else
7537           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7538         break;
7539       case SPAN:
7540         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7541       case IMM16:
7542         if(opcode[i]==0xf) //LUI
7543           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7544         else
7545           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7546         break;
7547       case LOAD:
7548       case LOADLR:
7549         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7550         break;
7551       case STORE:
7552       case STORELR:
7553         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7554         break;
7555       case ALU:
7556       case SHIFT:
7557         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7558         break;
7559       case MULTDIV:
7560         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7561         break;
7562       case SHIFTIMM:
7563         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7564         break;
7565       case MOV:
7566         if((opcode2[i]&0x1d)==0x10)
7567           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7568         else if((opcode2[i]&0x1d)==0x11)
7569           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7570         else
7571           printf (" %x: %s\n",start+i*4,insn[i]);
7572         break;
7573       case COP0:
7574         if(opcode2[i]==0)
7575           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7576         else if(opcode2[i]==4)
7577           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7578         else printf (" %x: %s\n",start+i*4,insn[i]);
7579         break;
7580       case COP1:
7581         if(opcode2[i]<3)
7582           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7583         else if(opcode2[i]>3)
7584           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7585         else printf (" %x: %s\n",start+i*4,insn[i]);
7586         break;
7587       case COP2:
7588         if(opcode2[i]<3)
7589           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7590         else if(opcode2[i]>3)
7591           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7592         else printf (" %x: %s\n",start+i*4,insn[i]);
7593         break;
7594       case C1LS:
7595         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7596         break;
7597       case C2LS:
7598         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7599         break;
7600       default:
7601         //printf (" %s %8x\n",insn[i],source[i]);
7602         printf (" %x: %s\n",start+i*4,insn[i]);
7603     }
7604 }
7605
7606 void new_dynarec_init()
7607 {
7608   printf("Init new dynarec\n");
7609   out=(u_char *)BASE_ADDR;
7610   if (mmap (out, 1<<TARGET_SIZE_2,
7611             PROT_READ | PROT_WRITE | PROT_EXEC,
7612             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7613             -1, 0) <= 0) {printf("mmap() failed\n");}
7614 #ifdef MUPEN64
7615   rdword=&readmem_dword;
7616   fake_pc.f.r.rs=&readmem_dword;
7617   fake_pc.f.r.rt=&readmem_dword;
7618   fake_pc.f.r.rd=&readmem_dword;
7619 #endif
7620   int n;
7621   for(n=0x80000;n<0x80800;n++)
7622     invalid_code[n]=1;
7623   for(n=0;n<65536;n++)
7624     hash_table[n][0]=hash_table[n][2]=-1;
7625   memset(mini_ht,-1,sizeof(mini_ht));
7626   memset(restore_candidate,0,sizeof(restore_candidate));
7627   copy=shadow;
7628   expirep=16384; // Expiry pointer, +2 blocks
7629   pending_exception=0;
7630   literalcount=0;
7631 #ifdef HOST_IMM8
7632   // Copy this into local area so we don't have to put it in every literal pool
7633   invc_ptr=invalid_code;
7634 #endif
7635   stop_after_jal=0;
7636   // TLB
7637   using_tlb=0;
7638   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7639     memory_map[n]=-1;
7640   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7641     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7642   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7643     memory_map[n]=-1;
7644 #ifdef MUPEN64
7645   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7646     writemem[n] = write_nomem_new;
7647     writememb[n] = write_nomemb_new;
7648     writememh[n] = write_nomemh_new;
7649 #ifndef FORCE32
7650     writememd[n] = write_nomemd_new;
7651 #endif
7652     readmem[n] = read_nomem_new;
7653     readmemb[n] = read_nomemb_new;
7654     readmemh[n] = read_nomemh_new;
7655 #ifndef FORCE32
7656     readmemd[n] = read_nomemd_new;
7657 #endif
7658   }
7659   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7660     writemem[n] = write_rdram_new;
7661     writememb[n] = write_rdramb_new;
7662     writememh[n] = write_rdramh_new;
7663 #ifndef FORCE32
7664     writememd[n] = write_rdramd_new;
7665 #endif
7666   }
7667   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7668     writemem[n] = write_nomem_new;
7669     writememb[n] = write_nomemb_new;
7670     writememh[n] = write_nomemh_new;
7671 #ifndef FORCE32
7672     writememd[n] = write_nomemd_new;
7673 #endif
7674     readmem[n] = read_nomem_new;
7675     readmemb[n] = read_nomemb_new;
7676     readmemh[n] = read_nomemh_new;
7677 #ifndef FORCE32
7678     readmemd[n] = read_nomemd_new;
7679 #endif
7680   }
7681 #endif
7682   tlb_hacks();
7683   arch_init();
7684 }
7685
7686 void new_dynarec_cleanup()
7687 {
7688   int n;
7689   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7690   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7691   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7692   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7693   #ifdef ROM_COPY
7694   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7695   #endif
7696 }
7697
7698 int new_recompile_block(int addr)
7699 {
7700 /*
7701   if(addr==0x800cd050) {
7702     int block;
7703     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7704     int n;
7705     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7706   }
7707 */
7708   //if(Count==365117028) tracedebug=1;
7709   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7710   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7711   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7712   //if(debug)
7713   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7714   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7715   /*if(Count>=312978186) {
7716     rlist();
7717   }*/
7718   //rlist();
7719   start = (u_int)addr&~3;
7720   //assert(((u_int)addr&1)==0);
7721 #ifdef PCSX
7722   if (Config.HLE && start == 0x80001000) {
7723     // XXX: is this enough? Maybe check hleSoftCall?
7724     u_int beginning=(u_int)out;
7725     u_int page=get_page(start);
7726     ll_add(jump_in+page,start,out);
7727     invalid_code[start>>12]=0;
7728     emit_movimm(start,0);
7729     emit_writeword(0,(int)&pcaddr);
7730     emit_jmp((int)new_dyna_leave);
7731 #ifdef __arm__
7732     __clear_cache((void *)beginning,out);
7733 #endif
7734     return 0;
7735   }
7736   else if ((u_int)addr < 0x00200000) {
7737     // used for BIOS calls mostly?
7738     source = (u_int *)((u_int)rdram+start-0);
7739     pagelimit = 0x00200000;
7740   }
7741   else
7742 #endif
7743 #ifdef MUPEN64
7744   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7745     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7746     pagelimit = 0xa4001000;
7747   }
7748   else
7749 #endif
7750   if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
7751     source = (u_int *)((u_int)rdram+start-0x80000000);
7752     pagelimit = 0x80800000;
7753   }
7754 #ifndef DISABLE_TLB
7755   else if ((signed int)addr >= (signed int)0xC0000000) {
7756     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7757     //if(tlb_LUT_r[start>>12])
7758       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7759     if((signed int)memory_map[start>>12]>=0) {
7760       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7761       pagelimit=(start+4096)&0xFFFFF000;
7762       int map=memory_map[start>>12];
7763       int i;
7764       for(i=0;i<5;i++) {
7765         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7766         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7767       }
7768       assem_debug("pagelimit=%x\n",pagelimit);
7769       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7770     }
7771     else {
7772       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7773       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7774       return 1; // Caller will invoke exception handler
7775     }
7776     //printf("source= %x\n",(int)source);
7777   }
7778 #endif
7779   else {
7780     printf("Compile at bogus memory address: %x \n", (int)addr);
7781     exit(1);
7782   }
7783
7784   /* Pass 1: disassemble */
7785   /* Pass 2: register dependencies, branch targets */
7786   /* Pass 3: register allocation */
7787   /* Pass 4: branch dependencies */
7788   /* Pass 5: pre-alloc */
7789   /* Pass 6: optimize clean/dirty state */
7790   /* Pass 7: flag 32-bit registers */
7791   /* Pass 8: assembly */
7792   /* Pass 9: linker */
7793   /* Pass 10: garbage collection / free memory */
7794
7795   int i,j;
7796   int done=0;
7797   unsigned int type,op,op2;
7798
7799   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7800
7801   /* Pass 1 disassembly */
7802
7803   for(i=0;!done;i++) {
7804     bt[i]=0;likely[i]=0;op2=0;
7805     opcode[i]=op=source[i]>>26;
7806     switch(op)
7807     {
7808       case 0x00: strcpy(insn[i],"special"); type=NI;
7809         op2=source[i]&0x3f;
7810         switch(op2)
7811         {
7812           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7813           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7814           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7815           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7816           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7817           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7818           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7819           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7820           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7821           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7822           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7823           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7824           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7825           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7826           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7827           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7828           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7829           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7830           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7831           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7832           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7833           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7834           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7835           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7836           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7837           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7838           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7839           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7840           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7841           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7842           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7843           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7844           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7845           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7846           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7847           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7848           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7849           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7850           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7851           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7852           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7853           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7854           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7855           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7856           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7857           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7858           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7859           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7860           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7861           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7862           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7863           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7864         }
7865         break;
7866       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7867         op2=(source[i]>>16)&0x1f;
7868         switch(op2)
7869         {
7870           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7871           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7872           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7873           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7874           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7875           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7876           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7877           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7878           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7879           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7880           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7881           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7882           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7883           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7884         }
7885         break;
7886       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7887       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7888       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7889       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7890       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7891       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7892       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7893       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7894       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7895       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7896       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7897       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7898       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7899       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7900       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7901         op2=(source[i]>>21)&0x1f;
7902         switch(op2)
7903         {
7904           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7905           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7906           case 0x10: strcpy(insn[i],"tlb"); type=NI;
7907           switch(source[i]&0x3f)
7908           {
7909             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7910             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7911             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7912             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7913             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7914           }
7915         }
7916         break;
7917       case 0x11: strcpy(insn[i],"cop1"); type=NI;
7918         op2=(source[i]>>21)&0x1f;
7919         switch(op2)
7920         {
7921           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7922           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7923           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7924           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7925           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7926           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7927           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7928           switch((source[i]>>16)&0x3)
7929           {
7930             case 0x00: strcpy(insn[i],"BC1F"); break;
7931             case 0x01: strcpy(insn[i],"BC1T"); break;
7932             case 0x02: strcpy(insn[i],"BC1FL"); break;
7933             case 0x03: strcpy(insn[i],"BC1TL"); break;
7934           }
7935           break;
7936           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7937           switch(source[i]&0x3f)
7938           {
7939             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7940             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7941             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7942             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7943             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7944             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7945             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7946             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7947             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7948             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7949             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7950             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7951             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7952             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7953             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7954             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7955             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7956             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7957             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7958             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7959             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7960             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7961             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7962             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7963             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7964             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7965             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7966             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7967             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7968             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7969             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7970             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7971             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7972             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7973             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7974           }
7975           break;
7976           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7977           switch(source[i]&0x3f)
7978           {
7979             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7980             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7981             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7982             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7983             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7984             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7985             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7986             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7987             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7988             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7989             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7990             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7991             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7992             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7993             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7994             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7995             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7996             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7997             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7998             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7999             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8000             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8001             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8002             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8003             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8004             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8005             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8006             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8007             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8008             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8009             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8010             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8011             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8012             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8013             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8014           }
8015           break;
8016           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8017           switch(source[i]&0x3f)
8018           {
8019             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8020             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8021           }
8022           break;
8023           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8024           switch(source[i]&0x3f)
8025           {
8026             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8027             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8028           }
8029           break;
8030         }
8031         break;
8032       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8033       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8034       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8035       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8036       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8037       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8038       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8039       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8040       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8041       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8042       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8043       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8044       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8045       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8046       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8047       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8048       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8049       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8050       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8051       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8052       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8053       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8054       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8055       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8056       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8057       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8058       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8059       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8060       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8061       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8062       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8063       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8064       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8065       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8066 #ifdef PCSX
8067       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8068         op2=(source[i]>>21)&0x1f;
8069         switch(op2)
8070         {
8071           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8072           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8073           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8074           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8075           default:
8076             if (gte_handlers[source[i]&0x3f]!=NULL) {
8077               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8078               type=C2OP;
8079             }
8080             break;
8081         }
8082         break;
8083       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8084       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8085       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8086 #endif
8087       default: strcpy(insn[i],"???"); type=NI;
8088         printf("NI %08x @%08x\n", source[i], addr + i*4);
8089         break;
8090     }
8091     itype[i]=type;
8092     opcode2[i]=op2;
8093     /* Get registers/immediates */
8094     lt1[i]=0;
8095     us1[i]=0;
8096     us2[i]=0;
8097     dep1[i]=0;
8098     dep2[i]=0;
8099     switch(type) {
8100       case LOAD:
8101         rs1[i]=(source[i]>>21)&0x1f;
8102         rs2[i]=0;
8103         rt1[i]=(source[i]>>16)&0x1f;
8104         rt2[i]=0;
8105         imm[i]=(short)source[i];
8106         break;
8107       case STORE:
8108       case STORELR:
8109         rs1[i]=(source[i]>>21)&0x1f;
8110         rs2[i]=(source[i]>>16)&0x1f;
8111         rt1[i]=0;
8112         rt2[i]=0;
8113         imm[i]=(short)source[i];
8114         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8115         break;
8116       case LOADLR:
8117         // LWL/LWR only load part of the register,
8118         // therefore the target register must be treated as a source too
8119         rs1[i]=(source[i]>>21)&0x1f;
8120         rs2[i]=(source[i]>>16)&0x1f;
8121         rt1[i]=(source[i]>>16)&0x1f;
8122         rt2[i]=0;
8123         imm[i]=(short)source[i];
8124         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8125         if(op==0x26) dep1[i]=rt1[i]; // LWR
8126         break;
8127       case IMM16:
8128         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8129         else rs1[i]=(source[i]>>21)&0x1f;
8130         rs2[i]=0;
8131         rt1[i]=(source[i]>>16)&0x1f;
8132         rt2[i]=0;
8133         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8134           imm[i]=(unsigned short)source[i];
8135         }else{
8136           imm[i]=(short)source[i];
8137         }
8138         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8139         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8140         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8141         break;
8142       case UJUMP:
8143         rs1[i]=0;
8144         rs2[i]=0;
8145         rt1[i]=0;
8146         rt2[i]=0;
8147         // The JAL instruction writes to r31.
8148         if (op&1) {
8149           rt1[i]=31;
8150         }
8151         rs2[i]=CCREG;
8152         break;
8153       case RJUMP:
8154         rs1[i]=(source[i]>>21)&0x1f;
8155         rs2[i]=0;
8156         rt1[i]=0;
8157         rt2[i]=0;
8158         // The JALR instruction writes to rd.
8159         if (op2&1) {
8160           rt1[i]=(source[i]>>11)&0x1f;
8161         }
8162         rs2[i]=CCREG;
8163         break;
8164       case CJUMP:
8165         rs1[i]=(source[i]>>21)&0x1f;
8166         rs2[i]=(source[i]>>16)&0x1f;
8167         rt1[i]=0;
8168         rt2[i]=0;
8169         if(op&2) { // BGTZ/BLEZ
8170           rs2[i]=0;
8171         }
8172         us1[i]=rs1[i];
8173         us2[i]=rs2[i];
8174         likely[i]=op>>4;
8175         break;
8176       case SJUMP:
8177         rs1[i]=(source[i]>>21)&0x1f;
8178         rs2[i]=CCREG;
8179         rt1[i]=0;
8180         rt2[i]=0;
8181         us1[i]=rs1[i];
8182         if(op2&0x10) { // BxxAL
8183           rt1[i]=31;
8184           // NOTE: If the branch is not taken, r31 is still overwritten
8185         }
8186         likely[i]=(op2&2)>>1;
8187         break;
8188       case FJUMP:
8189         rs1[i]=FSREG;
8190         rs2[i]=CSREG;
8191         rt1[i]=0;
8192         rt2[i]=0;
8193         likely[i]=((source[i])>>17)&1;
8194         break;
8195       case ALU:
8196         rs1[i]=(source[i]>>21)&0x1f; // source
8197         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8198         rt1[i]=(source[i]>>11)&0x1f; // destination
8199         rt2[i]=0;
8200         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8201           us1[i]=rs1[i];us2[i]=rs2[i];
8202         }
8203         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8204           dep1[i]=rs1[i];dep2[i]=rs2[i];
8205         }
8206         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8207           dep1[i]=rs1[i];dep2[i]=rs2[i];
8208         }
8209         break;
8210       case MULTDIV:
8211         rs1[i]=(source[i]>>21)&0x1f; // source
8212         rs2[i]=(source[i]>>16)&0x1f; // divisor
8213         rt1[i]=HIREG;
8214         rt2[i]=LOREG;
8215         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8216           us1[i]=rs1[i];us2[i]=rs2[i];
8217         }
8218         break;
8219       case MOV:
8220         rs1[i]=0;
8221         rs2[i]=0;
8222         rt1[i]=0;
8223         rt2[i]=0;
8224         if(op2==0x10) rs1[i]=HIREG; // MFHI
8225         if(op2==0x11) rt1[i]=HIREG; // MTHI
8226         if(op2==0x12) rs1[i]=LOREG; // MFLO
8227         if(op2==0x13) rt1[i]=LOREG; // MTLO
8228         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8229         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8230         dep1[i]=rs1[i];
8231         break;
8232       case SHIFT:
8233         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8234         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8235         rt1[i]=(source[i]>>11)&0x1f; // destination
8236         rt2[i]=0;
8237         // DSLLV/DSRLV/DSRAV are 64-bit
8238         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8239         break;
8240       case SHIFTIMM:
8241         rs1[i]=(source[i]>>16)&0x1f;
8242         rs2[i]=0;
8243         rt1[i]=(source[i]>>11)&0x1f;
8244         rt2[i]=0;
8245         imm[i]=(source[i]>>6)&0x1f;
8246         // DSxx32 instructions
8247         if(op2>=0x3c) imm[i]|=0x20;
8248         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8249         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8250         break;
8251       case COP0:
8252         rs1[i]=0;
8253         rs2[i]=0;
8254         rt1[i]=0;
8255         rt2[i]=0;
8256         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8257         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8258         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8259         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8260         break;
8261       case COP1:
8262       case COP2:
8263         rs1[i]=0;
8264         rs2[i]=0;
8265         rt1[i]=0;
8266         rt2[i]=0;
8267         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8268         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8269         if(op2==5) us1[i]=rs1[i]; // DMTC1
8270         rs2[i]=CSREG;
8271         break;
8272       case C1LS:
8273         rs1[i]=(source[i]>>21)&0x1F;
8274         rs2[i]=CSREG;
8275         rt1[i]=0;
8276         rt2[i]=0;
8277         imm[i]=(short)source[i];
8278         break;
8279       case C2LS:
8280         rs1[i]=(source[i]>>21)&0x1F;
8281         rs2[i]=0;
8282         rt1[i]=0;
8283         rt2[i]=0;
8284         imm[i]=(short)source[i];
8285         break;
8286       case FLOAT:
8287       case FCONV:
8288         rs1[i]=0;
8289         rs2[i]=CSREG;
8290         rt1[i]=0;
8291         rt2[i]=0;
8292         break;
8293       case FCOMP:
8294         rs1[i]=FSREG;
8295         rs2[i]=CSREG;
8296         rt1[i]=FSREG;
8297         rt2[i]=0;
8298         break;
8299       case SYSCALL:
8300       case HLECALL:
8301         rs1[i]=CCREG;
8302         rs2[i]=0;
8303         rt1[i]=0;
8304         rt2[i]=0;
8305         break;
8306       default:
8307         rs1[i]=0;
8308         rs2[i]=0;
8309         rt1[i]=0;
8310         rt2[i]=0;
8311     }
8312     /* Calculate branch target addresses */
8313     if(type==UJUMP)
8314       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8315     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8316       ba[i]=start+i*4+8; // Ignore never taken branch
8317     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8318       ba[i]=start+i*4+8; // Ignore never taken branch
8319     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8320       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8321     else ba[i]=-1;
8322     /* Is this the end of the block? */
8323     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8324       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8325         done=1;
8326         // Does the block continue due to a branch?
8327         for(j=i-1;j>=0;j--)
8328         {
8329           if(ba[j]==start+i*4+4) done=j=0;
8330           if(ba[j]==start+i*4+8) done=j=0;
8331         }
8332       }
8333       else {
8334         if(stop_after_jal) done=1;
8335         // Stop on BREAK
8336         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8337       }
8338       // Don't recompile stuff that's already compiled
8339       if(check_addr(start+i*4+4)) done=1;
8340       // Don't get too close to the limit
8341       if(i>MAXBLOCK/2) done=1;
8342     }
8343     if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
8344     if(itype[i-1]==HLECALL) done=1;
8345     assert(i<MAXBLOCK-1);
8346     if(start+i*4==pagelimit-4) done=1;
8347     assert(start+i*4<pagelimit);
8348     if (i==MAXBLOCK-1) done=1;
8349     // Stop if we're compiling junk
8350     if(itype[i]==NI&&opcode[i]==0x11) {
8351       done=stop_after_jal=1;
8352       printf("Disabled speculative precompilation\n");
8353     }
8354   }
8355   slen=i;
8356   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8357     if(start+i*4==pagelimit) {
8358       itype[i-1]=SPAN;
8359     }
8360   }
8361   assert(slen>0);
8362
8363   /* Pass 2 - Register dependencies and branch targets */
8364
8365   unneeded_registers(0,slen-1,0);
8366
8367   /* Pass 3 - Register allocation */
8368
8369   struct regstat current; // Current register allocations/status
8370   current.is32=1;
8371   current.dirty=0;
8372   current.u=unneeded_reg[0];
8373   current.uu=unneeded_reg_upper[0];
8374   clear_all_regs(current.regmap);
8375   alloc_reg(&current,0,CCREG);
8376   dirty_reg(&current,CCREG);
8377   current.isconst=0;
8378   current.wasconst=0;
8379   int ds=0;
8380   int cc=0;
8381   int hr;
8382
8383   provisional_32bit();
8384
8385   if((u_int)addr&1) {
8386     // First instruction is delay slot
8387     cc=-1;
8388     bt[1]=1;
8389     ds=1;
8390     unneeded_reg[0]=1;
8391     unneeded_reg_upper[0]=1;
8392     current.regmap[HOST_BTREG]=BTREG;
8393   }
8394
8395   for(i=0;i<slen;i++)
8396   {
8397     if(bt[i])
8398     {
8399       int hr;
8400       for(hr=0;hr<HOST_REGS;hr++)
8401       {
8402         // Is this really necessary?
8403         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8404       }
8405       current.isconst=0;
8406     }
8407     if(i>1)
8408     {
8409       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8410       {
8411         if(rs1[i-2]==0||rs2[i-2]==0)
8412         {
8413           if(rs1[i-2]) {
8414             current.is32|=1LL<<rs1[i-2];
8415             int hr=get_reg(current.regmap,rs1[i-2]|64);
8416             if(hr>=0) current.regmap[hr]=-1;
8417           }
8418           if(rs2[i-2]) {
8419             current.is32|=1LL<<rs2[i-2];
8420             int hr=get_reg(current.regmap,rs2[i-2]|64);
8421             if(hr>=0) current.regmap[hr]=-1;
8422           }
8423         }
8424       }
8425     }
8426     // If something jumps here with 64-bit values
8427     // then promote those registers to 64 bits
8428     if(bt[i])
8429     {
8430       uint64_t temp_is32=current.is32;
8431       for(j=i-1;j>=0;j--)
8432       {
8433         if(ba[j]==start+i*4)
8434           temp_is32&=branch_regs[j].is32;
8435       }
8436       for(j=i;j<slen;j++)
8437       {
8438         if(ba[j]==start+i*4)
8439           //temp_is32=1;
8440           temp_is32&=p32[j];
8441       }
8442       if(temp_is32!=current.is32) {
8443         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8444         #ifdef DESTRUCTIVE_WRITEBACK
8445         for(hr=0;hr<HOST_REGS;hr++)
8446         {
8447           int r=current.regmap[hr];
8448           if(r>0&&r<64)
8449           {
8450             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8451               temp_is32|=1LL<<r;
8452               //printf("restore %d\n",r);
8453             }
8454           }
8455         }
8456         #endif
8457         current.is32=temp_is32;
8458       }
8459     }
8460 #ifdef FORCE32
8461     memset(p32, 0xff, sizeof(p32));
8462     current.is32=-1LL;
8463 #endif
8464
8465     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8466     regs[i].wasconst=current.isconst;
8467     regs[i].was32=current.is32;
8468     regs[i].wasdirty=current.dirty;
8469     #ifdef DESTRUCTIVE_WRITEBACK
8470     // To change a dirty register from 32 to 64 bits, we must write
8471     // it out during the previous cycle (for branches, 2 cycles)
8472     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8473     {
8474       uint64_t temp_is32=current.is32;
8475       for(j=i-1;j>=0;j--)
8476       {
8477         if(ba[j]==start+i*4+4)
8478           temp_is32&=branch_regs[j].is32;
8479       }
8480       for(j=i;j<slen;j++)
8481       {
8482         if(ba[j]==start+i*4+4)
8483           //temp_is32=1;
8484           temp_is32&=p32[j];
8485       }
8486       if(temp_is32!=current.is32) {
8487         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8488         for(hr=0;hr<HOST_REGS;hr++)
8489         {
8490           int r=current.regmap[hr];
8491           if(r>0)
8492           {
8493             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8494               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8495               {
8496                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8497                 {
8498                   //printf("dump %d/r%d\n",hr,r);
8499                   current.regmap[hr]=-1;
8500                   if(get_reg(current.regmap,r|64)>=0)
8501                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8502                 }
8503               }
8504             }
8505           }
8506         }
8507       }
8508     }
8509     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8510     {
8511       uint64_t temp_is32=current.is32;
8512       for(j=i-1;j>=0;j--)
8513       {
8514         if(ba[j]==start+i*4+8)
8515           temp_is32&=branch_regs[j].is32;
8516       }
8517       for(j=i;j<slen;j++)
8518       {
8519         if(ba[j]==start+i*4+8)
8520           //temp_is32=1;
8521           temp_is32&=p32[j];
8522       }
8523       if(temp_is32!=current.is32) {
8524         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8525         for(hr=0;hr<HOST_REGS;hr++)
8526         {
8527           int r=current.regmap[hr];
8528           if(r>0)
8529           {
8530             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8531               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8532               {
8533                 //printf("dump %d/r%d\n",hr,r);
8534                 current.regmap[hr]=-1;
8535                 if(get_reg(current.regmap,r|64)>=0)
8536                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8537               }
8538             }
8539           }
8540         }
8541       }
8542     }
8543     #endif
8544     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8545       if(i+1<slen) {
8546         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8547         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8548         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8549         current.u|=1;
8550         current.uu|=1;
8551       } else {
8552         current.u=1;
8553         current.uu=1;
8554       }
8555     } else {
8556       if(i+1<slen) {
8557         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8558         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8559         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8560         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8561         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8562         current.u|=1;
8563         current.uu|=1;
8564       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8565     }
8566     is_ds[i]=ds;
8567     if(ds) {
8568       ds=0; // Skip delay slot, already allocated as part of branch
8569       // ...but we need to alloc it in case something jumps here
8570       if(i+1<slen) {
8571         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8572         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8573       }else{
8574         current.u=branch_unneeded_reg[i-1];
8575         current.uu=branch_unneeded_reg_upper[i-1];
8576       }
8577       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8578       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8579       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8580       current.u|=1;
8581       current.uu|=1;
8582       struct regstat temp;
8583       memcpy(&temp,&current,sizeof(current));
8584       temp.wasdirty=temp.dirty;
8585       temp.was32=temp.is32;
8586       // TODO: Take into account unconditional branches, as below
8587       delayslot_alloc(&temp,i);
8588       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8589       regs[i].wasdirty=temp.wasdirty;
8590       regs[i].was32=temp.was32;
8591       regs[i].dirty=temp.dirty;
8592       regs[i].is32=temp.is32;
8593       regs[i].isconst=0;
8594       regs[i].wasconst=0;
8595       current.isconst=0;
8596       // Create entry (branch target) regmap
8597       for(hr=0;hr<HOST_REGS;hr++)
8598       {
8599         int r=temp.regmap[hr];
8600         if(r>=0) {
8601           if(r!=regmap_pre[i][hr]) {
8602             regs[i].regmap_entry[hr]=-1;
8603           }
8604           else
8605           {
8606             if(r<64){
8607               if((current.u>>r)&1) {
8608                 regs[i].regmap_entry[hr]=-1;
8609                 regs[i].regmap[hr]=-1;
8610                 //Don't clear regs in the delay slot as the branch might need them
8611                 //current.regmap[hr]=-1;
8612               }else
8613                 regs[i].regmap_entry[hr]=r;
8614             }
8615             else {
8616               if((current.uu>>(r&63))&1) {
8617                 regs[i].regmap_entry[hr]=-1;
8618                 regs[i].regmap[hr]=-1;
8619                 //Don't clear regs in the delay slot as the branch might need them
8620                 //current.regmap[hr]=-1;
8621               }else
8622                 regs[i].regmap_entry[hr]=r;
8623             }
8624           }
8625         } else {
8626           // First instruction expects CCREG to be allocated
8627           if(i==0&&hr==HOST_CCREG)
8628             regs[i].regmap_entry[hr]=CCREG;
8629           else
8630             regs[i].regmap_entry[hr]=-1;
8631         }
8632       }
8633     }
8634     else { // Not delay slot
8635       switch(itype[i]) {
8636         case UJUMP:
8637           //current.isconst=0; // DEBUG
8638           //current.wasconst=0; // DEBUG
8639           //regs[i].wasconst=0; // DEBUG
8640           clear_const(&current,rt1[i]);
8641           alloc_cc(&current,i);
8642           dirty_reg(&current,CCREG);
8643           if (rt1[i]==31) {
8644             alloc_reg(&current,i,31);
8645             dirty_reg(&current,31);
8646             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8647             #ifdef REG_PREFETCH
8648             alloc_reg(&current,i,PTEMP);
8649             #endif
8650             //current.is32|=1LL<<rt1[i];
8651           }
8652           delayslot_alloc(&current,i+1);
8653           //current.isconst=0; // DEBUG
8654           ds=1;
8655           //printf("i=%d, isconst=%x\n",i,current.isconst);
8656           break;
8657         case RJUMP:
8658           //current.isconst=0;
8659           //current.wasconst=0;
8660           //regs[i].wasconst=0;
8661           clear_const(&current,rs1[i]);
8662           clear_const(&current,rt1[i]);
8663           alloc_cc(&current,i);
8664           dirty_reg(&current,CCREG);
8665           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8666             alloc_reg(&current,i,rs1[i]);
8667             if (rt1[i]!=0) {
8668               alloc_reg(&current,i,rt1[i]);
8669               dirty_reg(&current,rt1[i]);
8670               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8671               #ifdef REG_PREFETCH
8672               alloc_reg(&current,i,PTEMP);
8673               #endif
8674             }
8675             #ifdef USE_MINI_HT
8676             if(rs1[i]==31) { // JALR
8677               alloc_reg(&current,i,RHASH);
8678               #ifndef HOST_IMM_ADDR32
8679               alloc_reg(&current,i,RHTBL);
8680               #endif
8681             }
8682             #endif
8683             delayslot_alloc(&current,i+1);
8684           } else {
8685             // The delay slot overwrites our source register,
8686             // allocate a temporary register to hold the old value.
8687             current.isconst=0;
8688             current.wasconst=0;
8689             regs[i].wasconst=0;
8690             delayslot_alloc(&current,i+1);
8691             current.isconst=0;
8692             alloc_reg(&current,i,RTEMP);
8693           }
8694           //current.isconst=0; // DEBUG
8695           ds=1;
8696           break;
8697         case CJUMP:
8698           //current.isconst=0;
8699           //current.wasconst=0;
8700           //regs[i].wasconst=0;
8701           clear_const(&current,rs1[i]);
8702           clear_const(&current,rs2[i]);
8703           if((opcode[i]&0x3E)==4) // BEQ/BNE
8704           {
8705             alloc_cc(&current,i);
8706             dirty_reg(&current,CCREG);
8707             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8708             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8709             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8710             {
8711               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8712               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8713             }
8714             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8715                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8716               // The delay slot overwrites one of our conditions.
8717               // Allocate the branch condition registers instead.
8718               // Note that such a sequence of instructions could
8719               // be considered a bug since the branch can not be
8720               // re-executed if an exception occurs.
8721               current.isconst=0;
8722               current.wasconst=0;
8723               regs[i].wasconst=0;
8724               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8725               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8726               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8727               {
8728                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8729                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8730               }
8731             }
8732             else delayslot_alloc(&current,i+1);
8733           }
8734           else
8735           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8736           {
8737             alloc_cc(&current,i);
8738             dirty_reg(&current,CCREG);
8739             alloc_reg(&current,i,rs1[i]);
8740             if(!(current.is32>>rs1[i]&1))
8741             {
8742               alloc_reg64(&current,i,rs1[i]);
8743             }
8744             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8745               // The delay slot overwrites one of our conditions.
8746               // Allocate the branch condition registers instead.
8747               // Note that such a sequence of instructions could
8748               // be considered a bug since the branch can not be
8749               // re-executed if an exception occurs.
8750               current.isconst=0;
8751               current.wasconst=0;
8752               regs[i].wasconst=0;
8753               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8754               if(!((current.is32>>rs1[i])&1))
8755               {
8756                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8757               }
8758             }
8759             else delayslot_alloc(&current,i+1);
8760           }
8761           else
8762           // Don't alloc the delay slot yet because we might not execute it
8763           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8764           {
8765             current.isconst=0;
8766             current.wasconst=0;
8767             regs[i].wasconst=0;
8768             alloc_cc(&current,i);
8769             dirty_reg(&current,CCREG);
8770             alloc_reg(&current,i,rs1[i]);
8771             alloc_reg(&current,i,rs2[i]);
8772             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8773             {
8774               alloc_reg64(&current,i,rs1[i]);
8775               alloc_reg64(&current,i,rs2[i]);
8776             }
8777           }
8778           else
8779           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8780           {
8781             current.isconst=0;
8782             current.wasconst=0;
8783             regs[i].wasconst=0;
8784             alloc_cc(&current,i);
8785             dirty_reg(&current,CCREG);
8786             alloc_reg(&current,i,rs1[i]);
8787             if(!(current.is32>>rs1[i]&1))
8788             {
8789               alloc_reg64(&current,i,rs1[i]);
8790             }
8791           }
8792           ds=1;
8793           //current.isconst=0;
8794           break;
8795         case SJUMP:
8796           //current.isconst=0;
8797           //current.wasconst=0;
8798           //regs[i].wasconst=0;
8799           clear_const(&current,rs1[i]);
8800           clear_const(&current,rt1[i]);
8801           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8802           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8803           {
8804             alloc_cc(&current,i);
8805             dirty_reg(&current,CCREG);
8806             alloc_reg(&current,i,rs1[i]);
8807             if(!(current.is32>>rs1[i]&1))
8808             {
8809               alloc_reg64(&current,i,rs1[i]);
8810             }
8811             if (rt1[i]==31) { // BLTZAL/BGEZAL
8812               alloc_reg(&current,i,31);
8813               dirty_reg(&current,31);
8814               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8815               //#ifdef REG_PREFETCH
8816               //alloc_reg(&current,i,PTEMP);
8817               //#endif
8818               //current.is32|=1LL<<rt1[i];
8819             }
8820             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8821               // The delay slot overwrites the branch condition.
8822               // Allocate the branch condition registers instead.
8823               // Note that such a sequence of instructions could
8824               // be considered a bug since the branch can not be
8825               // re-executed if an exception occurs.
8826               current.isconst=0;
8827               current.wasconst=0;
8828               regs[i].wasconst=0;
8829               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8830               if(!((current.is32>>rs1[i])&1))
8831               {
8832                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8833               }
8834             }
8835             else delayslot_alloc(&current,i+1);
8836           }
8837           else
8838           // Don't alloc the delay slot yet because we might not execute it
8839           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8840           {
8841             current.isconst=0;
8842             current.wasconst=0;
8843             regs[i].wasconst=0;
8844             alloc_cc(&current,i);
8845             dirty_reg(&current,CCREG);
8846             alloc_reg(&current,i,rs1[i]);
8847             if(!(current.is32>>rs1[i]&1))
8848             {
8849               alloc_reg64(&current,i,rs1[i]);
8850             }
8851           }
8852           ds=1;
8853           //current.isconst=0;
8854           break;
8855         case FJUMP:
8856           current.isconst=0;
8857           current.wasconst=0;
8858           regs[i].wasconst=0;
8859           if(likely[i]==0) // BC1F/BC1T
8860           {
8861             // TODO: Theoretically we can run out of registers here on x86.
8862             // The delay slot can allocate up to six, and we need to check
8863             // CSREG before executing the delay slot.  Possibly we can drop
8864             // the cycle count and then reload it after checking that the
8865             // FPU is in a usable state, or don't do out-of-order execution.
8866             alloc_cc(&current,i);
8867             dirty_reg(&current,CCREG);
8868             alloc_reg(&current,i,FSREG);
8869             alloc_reg(&current,i,CSREG);
8870             if(itype[i+1]==FCOMP) {
8871               // The delay slot overwrites the branch condition.
8872               // Allocate the branch condition registers instead.
8873               // Note that such a sequence of instructions could
8874               // be considered a bug since the branch can not be
8875               // re-executed if an exception occurs.
8876               alloc_cc(&current,i);
8877               dirty_reg(&current,CCREG);
8878               alloc_reg(&current,i,CSREG);
8879               alloc_reg(&current,i,FSREG);
8880             }
8881             else {
8882               delayslot_alloc(&current,i+1);
8883               alloc_reg(&current,i+1,CSREG);
8884             }
8885           }
8886           else
8887           // Don't alloc the delay slot yet because we might not execute it
8888           if(likely[i]) // BC1FL/BC1TL
8889           {
8890             alloc_cc(&current,i);
8891             dirty_reg(&current,CCREG);
8892             alloc_reg(&current,i,CSREG);
8893             alloc_reg(&current,i,FSREG);
8894           }
8895           ds=1;
8896           current.isconst=0;
8897           break;
8898         case IMM16:
8899           imm16_alloc(&current,i);
8900           break;
8901         case LOAD:
8902         case LOADLR:
8903           load_alloc(&current,i);
8904           break;
8905         case STORE:
8906         case STORELR:
8907           store_alloc(&current,i);
8908           break;
8909         case ALU:
8910           alu_alloc(&current,i);
8911           break;
8912         case SHIFT:
8913           shift_alloc(&current,i);
8914           break;
8915         case MULTDIV:
8916           multdiv_alloc(&current,i);
8917           break;
8918         case SHIFTIMM:
8919           shiftimm_alloc(&current,i);
8920           break;
8921         case MOV:
8922           mov_alloc(&current,i);
8923           break;
8924         case COP0:
8925           cop0_alloc(&current,i);
8926           break;
8927         case COP1:
8928         case COP2:
8929           cop1_alloc(&current,i);
8930           break;
8931         case C1LS:
8932           c1ls_alloc(&current,i);
8933           break;
8934         case C2LS:
8935           c2ls_alloc(&current,i);
8936           break;
8937         case C2OP:
8938           c2op_alloc(&current,i);
8939           break;
8940         case FCONV:
8941           fconv_alloc(&current,i);
8942           break;
8943         case FLOAT:
8944           float_alloc(&current,i);
8945           break;
8946         case FCOMP:
8947           fcomp_alloc(&current,i);
8948           break;
8949         case SYSCALL:
8950         case HLECALL:
8951           syscall_alloc(&current,i);
8952           break;
8953         case SPAN:
8954           pagespan_alloc(&current,i);
8955           break;
8956       }
8957
8958       // Drop the upper half of registers that have become 32-bit
8959       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8960       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8961         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8962         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8963         current.uu|=1;
8964       } else {
8965         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8966         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8967         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8968         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8969         current.uu|=1;
8970       }
8971
8972       // Create entry (branch target) regmap
8973       for(hr=0;hr<HOST_REGS;hr++)
8974       {
8975         int r,or,er;
8976         r=current.regmap[hr];
8977         if(r>=0) {
8978           if(r!=regmap_pre[i][hr]) {
8979             // TODO: delay slot (?)
8980             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8981             if(or<0||(r&63)>=TEMPREG){
8982               regs[i].regmap_entry[hr]=-1;
8983             }
8984             else
8985             {
8986               // Just move it to a different register
8987               regs[i].regmap_entry[hr]=r;
8988               // If it was dirty before, it's still dirty
8989               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8990             }
8991           }
8992           else
8993           {
8994             // Unneeded
8995             if(r==0){
8996               regs[i].regmap_entry[hr]=0;
8997             }
8998             else
8999             if(r<64){
9000               if((current.u>>r)&1) {
9001                 regs[i].regmap_entry[hr]=-1;
9002                 //regs[i].regmap[hr]=-1;
9003                 current.regmap[hr]=-1;
9004               }else
9005                 regs[i].regmap_entry[hr]=r;
9006             }
9007             else {
9008               if((current.uu>>(r&63))&1) {
9009                 regs[i].regmap_entry[hr]=-1;
9010                 //regs[i].regmap[hr]=-1;
9011                 current.regmap[hr]=-1;
9012               }else
9013                 regs[i].regmap_entry[hr]=r;
9014             }
9015           }
9016         } else {
9017           // Branches expect CCREG to be allocated at the target
9018           if(regmap_pre[i][hr]==CCREG)
9019             regs[i].regmap_entry[hr]=CCREG;
9020           else
9021             regs[i].regmap_entry[hr]=-1;
9022         }
9023       }
9024       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9025     }
9026     /* Branch post-alloc */
9027     if(i>0)
9028     {
9029       current.was32=current.is32;
9030       current.wasdirty=current.dirty;
9031       switch(itype[i-1]) {
9032         case UJUMP:
9033           memcpy(&branch_regs[i-1],&current,sizeof(current));
9034           branch_regs[i-1].isconst=0;
9035           branch_regs[i-1].wasconst=0;
9036           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9037           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9038           alloc_cc(&branch_regs[i-1],i-1);
9039           dirty_reg(&branch_regs[i-1],CCREG);
9040           if(rt1[i-1]==31) { // JAL
9041             alloc_reg(&branch_regs[i-1],i-1,31);
9042             dirty_reg(&branch_regs[i-1],31);
9043             branch_regs[i-1].is32|=1LL<<31;
9044           }
9045           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9046           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9047           break;
9048         case RJUMP:
9049           memcpy(&branch_regs[i-1],&current,sizeof(current));
9050           branch_regs[i-1].isconst=0;
9051           branch_regs[i-1].wasconst=0;
9052           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9053           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9054           alloc_cc(&branch_regs[i-1],i-1);
9055           dirty_reg(&branch_regs[i-1],CCREG);
9056           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9057           if(rt1[i-1]!=0) { // JALR
9058             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9059             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9060             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9061           }
9062           #ifdef USE_MINI_HT
9063           if(rs1[i-1]==31) { // JALR
9064             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9065             #ifndef HOST_IMM_ADDR32
9066             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9067             #endif
9068           }
9069           #endif
9070           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9071           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9072           break;
9073         case CJUMP:
9074           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9075           {
9076             alloc_cc(&current,i-1);
9077             dirty_reg(&current,CCREG);
9078             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9079                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9080               // The delay slot overwrote one of our conditions
9081               // Delay slot goes after the test (in order)
9082               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9083               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9084               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9085               current.u|=1;
9086               current.uu|=1;
9087               delayslot_alloc(&current,i);
9088               current.isconst=0;
9089             }
9090             else
9091             {
9092               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9093               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9094               // Alloc the branch condition registers
9095               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9096               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9097               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9098               {
9099                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9100                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9101               }
9102             }
9103             memcpy(&branch_regs[i-1],&current,sizeof(current));
9104             branch_regs[i-1].isconst=0;
9105             branch_regs[i-1].wasconst=0;
9106             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9107             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9108           }
9109           else
9110           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9111           {
9112             alloc_cc(&current,i-1);
9113             dirty_reg(&current,CCREG);
9114             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9115               // The delay slot overwrote the branch condition
9116               // Delay slot goes after the test (in order)
9117               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9118               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9119               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9120               current.u|=1;
9121               current.uu|=1;
9122               delayslot_alloc(&current,i);
9123               current.isconst=0;
9124             }
9125             else
9126             {
9127               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9128               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9129               // Alloc the branch condition register
9130               alloc_reg(&current,i-1,rs1[i-1]);
9131               if(!(current.is32>>rs1[i-1]&1))
9132               {
9133                 alloc_reg64(&current,i-1,rs1[i-1]);
9134               }
9135             }
9136             memcpy(&branch_regs[i-1],&current,sizeof(current));
9137             branch_regs[i-1].isconst=0;
9138             branch_regs[i-1].wasconst=0;
9139             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9140             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9141           }
9142           else
9143           // Alloc the delay slot in case the branch is taken
9144           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9145           {
9146             memcpy(&branch_regs[i-1],&current,sizeof(current));
9147             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9148             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9149             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9150             alloc_cc(&branch_regs[i-1],i);
9151             dirty_reg(&branch_regs[i-1],CCREG);
9152             delayslot_alloc(&branch_regs[i-1],i);
9153             branch_regs[i-1].isconst=0;
9154             alloc_reg(&current,i,CCREG); // Not taken path
9155             dirty_reg(&current,CCREG);
9156             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9157           }
9158           else
9159           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9160           {
9161             memcpy(&branch_regs[i-1],&current,sizeof(current));
9162             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9163             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9164             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9165             alloc_cc(&branch_regs[i-1],i);
9166             dirty_reg(&branch_regs[i-1],CCREG);
9167             delayslot_alloc(&branch_regs[i-1],i);
9168             branch_regs[i-1].isconst=0;
9169             alloc_reg(&current,i,CCREG); // Not taken path
9170             dirty_reg(&current,CCREG);
9171             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9172           }
9173           break;
9174         case SJUMP:
9175           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9176           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9177           {
9178             alloc_cc(&current,i-1);
9179             dirty_reg(&current,CCREG);
9180             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9181               // The delay slot overwrote the branch condition
9182               // Delay slot goes after the test (in order)
9183               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9184               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9185               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9186               current.u|=1;
9187               current.uu|=1;
9188               delayslot_alloc(&current,i);
9189               current.isconst=0;
9190             }
9191             else
9192             {
9193               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9194               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9195               // Alloc the branch condition register
9196               alloc_reg(&current,i-1,rs1[i-1]);
9197               if(!(current.is32>>rs1[i-1]&1))
9198               {
9199                 alloc_reg64(&current,i-1,rs1[i-1]);
9200               }
9201             }
9202             memcpy(&branch_regs[i-1],&current,sizeof(current));
9203             branch_regs[i-1].isconst=0;
9204             branch_regs[i-1].wasconst=0;
9205             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9206             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9207           }
9208           else
9209           // Alloc the delay slot in case the branch is taken
9210           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9211           {
9212             memcpy(&branch_regs[i-1],&current,sizeof(current));
9213             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9214             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9215             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9216             alloc_cc(&branch_regs[i-1],i);
9217             dirty_reg(&branch_regs[i-1],CCREG);
9218             delayslot_alloc(&branch_regs[i-1],i);
9219             branch_regs[i-1].isconst=0;
9220             alloc_reg(&current,i,CCREG); // Not taken path
9221             dirty_reg(&current,CCREG);
9222             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9223           }
9224           // FIXME: BLTZAL/BGEZAL
9225           if(opcode2[i-1]&0x10) { // BxxZAL
9226             alloc_reg(&branch_regs[i-1],i-1,31);
9227             dirty_reg(&branch_regs[i-1],31);
9228             branch_regs[i-1].is32|=1LL<<31;
9229           }
9230           break;
9231         case FJUMP:
9232           if(likely[i-1]==0) // BC1F/BC1T
9233           {
9234             alloc_cc(&current,i-1);
9235             dirty_reg(&current,CCREG);
9236             if(itype[i]==FCOMP) {
9237               // The delay slot overwrote the branch condition
9238               // Delay slot goes after the test (in order)
9239               delayslot_alloc(&current,i);
9240               current.isconst=0;
9241             }
9242             else
9243             {
9244               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9245               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9246               // Alloc the branch condition register
9247               alloc_reg(&current,i-1,FSREG);
9248             }
9249             memcpy(&branch_regs[i-1],&current,sizeof(current));
9250             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9251           }
9252           else // BC1FL/BC1TL
9253           {
9254             // Alloc the delay slot in case the branch is taken
9255             memcpy(&branch_regs[i-1],&current,sizeof(current));
9256             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9257             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9258             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9259             alloc_cc(&branch_regs[i-1],i);
9260             dirty_reg(&branch_regs[i-1],CCREG);
9261             delayslot_alloc(&branch_regs[i-1],i);
9262             branch_regs[i-1].isconst=0;
9263             alloc_reg(&current,i,CCREG); // Not taken path
9264             dirty_reg(&current,CCREG);
9265             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9266           }
9267           break;
9268       }
9269
9270       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9271       {
9272         if(rt1[i-1]==31) // JAL/JALR
9273         {
9274           // Subroutine call will return here, don't alloc any registers
9275           current.is32=1;
9276           current.dirty=0;
9277           clear_all_regs(current.regmap);
9278           alloc_reg(&current,i,CCREG);
9279           dirty_reg(&current,CCREG);
9280         }
9281         else if(i+1<slen)
9282         {
9283           // Internal branch will jump here, match registers to caller
9284           current.is32=0x3FFFFFFFFLL;
9285           current.dirty=0;
9286           clear_all_regs(current.regmap);
9287           alloc_reg(&current,i,CCREG);
9288           dirty_reg(&current,CCREG);
9289           for(j=i-1;j>=0;j--)
9290           {
9291             if(ba[j]==start+i*4+4) {
9292               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9293               current.is32=branch_regs[j].is32;
9294               current.dirty=branch_regs[j].dirty;
9295               break;
9296             }
9297           }
9298           while(j>=0) {
9299             if(ba[j]==start+i*4+4) {
9300               for(hr=0;hr<HOST_REGS;hr++) {
9301                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9302                   current.regmap[hr]=-1;
9303                 }
9304                 current.is32&=branch_regs[j].is32;
9305                 current.dirty&=branch_regs[j].dirty;
9306               }
9307             }
9308             j--;
9309           }
9310         }
9311       }
9312     }
9313
9314     // Count cycles in between branches
9315     ccadj[i]=cc;
9316     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9317     {
9318       cc=0;
9319     }
9320     else
9321     {
9322       cc++;
9323     }
9324
9325     flush_dirty_uppers(&current);
9326     if(!is_ds[i]) {
9327       regs[i].is32=current.is32;
9328       regs[i].dirty=current.dirty;
9329       regs[i].isconst=current.isconst;
9330       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9331     }
9332     for(hr=0;hr<HOST_REGS;hr++) {
9333       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9334         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9335           regs[i].wasconst&=~(1<<hr);
9336         }
9337       }
9338     }
9339     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9340   }
9341
9342   /* Pass 4 - Cull unused host registers */
9343
9344   uint64_t nr=0;
9345
9346   for (i=slen-1;i>=0;i--)
9347   {
9348     int hr;
9349     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9350     {
9351       if(ba[i]<start || ba[i]>=(start+slen*4))
9352       {
9353         // Branch out of this block, don't need anything
9354         nr=0;
9355       }
9356       else
9357       {
9358         // Internal branch
9359         // Need whatever matches the target
9360         nr=0;
9361         int t=(ba[i]-start)>>2;
9362         for(hr=0;hr<HOST_REGS;hr++)
9363         {
9364           if(regs[i].regmap_entry[hr]>=0) {
9365             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9366           }
9367         }
9368       }
9369       // Conditional branch may need registers for following instructions
9370       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9371       {
9372         if(i<slen-2) {
9373           nr|=needed_reg[i+2];
9374           for(hr=0;hr<HOST_REGS;hr++)
9375           {
9376             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9377             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9378           }
9379         }
9380       }
9381       // Don't need stuff which is overwritten
9382       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9383       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9384       // Merge in delay slot
9385       for(hr=0;hr<HOST_REGS;hr++)
9386       {
9387         if(!likely[i]) {
9388           // These are overwritten unless the branch is "likely"
9389           // and the delay slot is nullified if not taken
9390           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9391           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9392         }
9393         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9394         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9395         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9396         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9397         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9398         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9399         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9400         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9401         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9402           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9403           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9404         }
9405         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9406           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9407           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9408         }
9409         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9410           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9411           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9412         }
9413       }
9414     }
9415     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
9416     {
9417       // SYSCALL instruction (software interrupt)
9418       nr=0;
9419     }
9420     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9421     {
9422       // ERET instruction (return from interrupt)
9423       nr=0;
9424     }
9425     else // Non-branch
9426     {
9427       if(i<slen-1) {
9428         for(hr=0;hr<HOST_REGS;hr++) {
9429           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9430           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9431           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9432           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9433         }
9434       }
9435     }
9436     for(hr=0;hr<HOST_REGS;hr++)
9437     {
9438       // Overwritten registers are not needed
9439       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9440       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9441       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9442       // Source registers are needed
9443       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9444       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9445       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9446       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9447       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9448       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9449       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9450       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9451       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9452         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9453         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9454       }
9455       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9456         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9457         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9458       }
9459       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9460         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9461         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9462       }
9463       // Don't store a register immediately after writing it,
9464       // may prevent dual-issue.
9465       // But do so if this is a branch target, otherwise we
9466       // might have to load the register before the branch.
9467       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9468         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9469            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9470           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9471           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9472         }
9473         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9474            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9475           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9476           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9477         }
9478       }
9479     }
9480     // Cycle count is needed at branches.  Assume it is needed at the target too.
9481     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9482       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9483       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9484     }
9485     // Save it
9486     needed_reg[i]=nr;
9487
9488     // Deallocate unneeded registers
9489     for(hr=0;hr<HOST_REGS;hr++)
9490     {
9491       if(!((nr>>hr)&1)) {
9492         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9493         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9494            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9495            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9496         {
9497           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9498           {
9499             if(likely[i]) {
9500               regs[i].regmap[hr]=-1;
9501               regs[i].isconst&=~(1<<hr);
9502               if(i<slen-2) regmap_pre[i+2][hr]=-1;
9503             }
9504           }
9505         }
9506         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9507         {
9508           int d1=0,d2=0,map=0,temp=0;
9509           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9510           {
9511             d1=dep1[i+1];
9512             d2=dep2[i+1];
9513           }
9514           if(using_tlb) {
9515             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9516                itype[i+1]==STORE || itype[i+1]==STORELR ||
9517                itype[i+1]==C1LS || itype[i+1]==C2LS)
9518             map=TLREG;
9519           } else
9520           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9521              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9522             map=INVCP;
9523           }
9524           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9525              itype[i+1]==C1LS || itype[i+1]==C2LS)
9526             temp=FTEMP;
9527           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9528              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9529              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9530              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9531              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9532              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9533              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9534              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9535              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9536              regs[i].regmap[hr]!=map )
9537           {
9538             regs[i].regmap[hr]=-1;
9539             regs[i].isconst&=~(1<<hr);
9540             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9541                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9542                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9543                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9544                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9545                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9546                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9547                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9548                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9549                branch_regs[i].regmap[hr]!=map)
9550             {
9551               branch_regs[i].regmap[hr]=-1;
9552               branch_regs[i].regmap_entry[hr]=-1;
9553               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9554               {
9555                 if(!likely[i]&&i<slen-2) {
9556                   regmap_pre[i+2][hr]=-1;
9557                 }
9558               }
9559             }
9560           }
9561         }
9562         else
9563         {
9564           // Non-branch
9565           if(i>0)
9566           {
9567             int d1=0,d2=0,map=-1,temp=-1;
9568             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9569             {
9570               d1=dep1[i];
9571               d2=dep2[i];
9572             }
9573             if(using_tlb) {
9574               if(itype[i]==LOAD || itype[i]==LOADLR ||
9575                  itype[i]==STORE || itype[i]==STORELR ||
9576                  itype[i]==C1LS || itype[i]==C2LS)
9577               map=TLREG;
9578             } else if(itype[i]==STORE || itype[i]==STORELR ||
9579                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9580               map=INVCP;
9581             }
9582             if(itype[i]==LOADLR || itype[i]==STORELR ||
9583                itype[i]==C1LS || itype[i]==C2LS)
9584               temp=FTEMP;
9585             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9586                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9587                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9588                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9589                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9590                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9591             {
9592               if(i<slen-1&&!is_ds[i]) {
9593                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9594                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9595                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9596                 {
9597                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9598                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9599                 }
9600                 regmap_pre[i+1][hr]=-1;
9601                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9602               }
9603               regs[i].regmap[hr]=-1;
9604               regs[i].isconst&=~(1<<hr);
9605             }
9606           }
9607         }
9608       }
9609     }
9610   }
9611
9612   /* Pass 5 - Pre-allocate registers */
9613
9614   // If a register is allocated during a loop, try to allocate it for the
9615   // entire loop, if possible.  This avoids loading/storing registers
9616   // inside of the loop.
9617
9618   signed char f_regmap[HOST_REGS];
9619   clear_all_regs(f_regmap);
9620   for(i=0;i<slen-1;i++)
9621   {
9622     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9623     {
9624       if(ba[i]>=start && ba[i]<(start+i*4))
9625       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9626       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9627       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9628       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9629       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9630       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9631       {
9632         int t=(ba[i]-start)>>2;
9633         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9634         if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9635         for(hr=0;hr<HOST_REGS;hr++)
9636         {
9637           if(regs[i].regmap[hr]>64) {
9638             if(!((regs[i].dirty>>hr)&1))
9639               f_regmap[hr]=regs[i].regmap[hr];
9640             else f_regmap[hr]=-1;
9641           }
9642           else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9643           if(branch_regs[i].regmap[hr]>64) {
9644             if(!((branch_regs[i].dirty>>hr)&1))
9645               f_regmap[hr]=branch_regs[i].regmap[hr];
9646             else f_regmap[hr]=-1;
9647           }
9648           else if(branch_regs[i].regmap[hr]>=0) f_regmap[hr]=branch_regs[i].regmap[hr];
9649           if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9650           ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9651           ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9652           ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9653           {
9654             // Test both in case the delay slot is ooo,
9655             // could be done better...
9656             if(count_free_regs(branch_regs[i].regmap)<2
9657              ||count_free_regs(regs[i].regmap)<2)
9658               f_regmap[hr]=branch_regs[i].regmap[hr];
9659           }
9660           // Avoid dirty->clean transition
9661           // #ifdef DESTRUCTIVE_WRITEBACK here?
9662           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9663           if(f_regmap[hr]>0) {
9664             if(regs[t].regmap_entry[hr]<0) {
9665               int r=f_regmap[hr];
9666               for(j=t;j<=i;j++)
9667               {
9668                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9669                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9670                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9671                 if(r>63) {
9672                   // NB This can exclude the case where the upper-half
9673                   // register is lower numbered than the lower-half
9674                   // register.  Not sure if it's worth fixing...
9675                   if(get_reg(regs[j].regmap,r&63)<0) break;
9676                   if(regs[j].is32&(1LL<<(r&63))) break;
9677                 }
9678                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9679                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9680                   int k;
9681                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9682                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9683                     if(r>63) {
9684                       if(get_reg(regs[i].regmap,r&63)<0) break;
9685                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9686                     }
9687                     k=i;
9688                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9689                       if(itype[k-1]==STORE||itype[k-1]==STORELR
9690                       ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9691                       ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9692                       ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9693                         if(count_free_regs(regs[k-1].regmap)<2) {
9694                           //printf("no free regs for store %x\n",start+(k-1)*4);
9695                           break;
9696                         }
9697                       }
9698                       else
9699                       if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9700                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9701                         //printf("no-match due to different register\n");
9702                         break;
9703                       }
9704                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9705                         //printf("no-match due to branch\n");
9706                         break;
9707                       }
9708                       // call/ret fast path assumes no registers allocated
9709                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9710                         break;
9711                       }
9712                       if(r>63) {
9713                         // NB This can exclude the case where the upper-half
9714                         // register is lower numbered than the lower-half
9715                         // register.  Not sure if it's worth fixing...
9716                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9717                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9718                       }
9719                       k--;
9720                     }
9721                     if(i<slen-1) {
9722                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9723                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9724                         //printf("bad match after branch\n");
9725                         break;
9726                       }
9727                     }
9728                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9729                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
9730                       while(k<i) {
9731                         regs[k].regmap_entry[hr]=f_regmap[hr];
9732                         regs[k].regmap[hr]=f_regmap[hr];
9733                         regmap_pre[k+1][hr]=f_regmap[hr];
9734                         regs[k].wasdirty&=~(1<<hr);
9735                         regs[k].dirty&=~(1<<hr);
9736                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9737                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9738                         regs[k].wasconst&=~(1<<hr);
9739                         regs[k].isconst&=~(1<<hr);
9740                         k++;
9741                       }
9742                     }
9743                     else {
9744                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9745                       break;
9746                     }
9747                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9748                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9749                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
9750                       regs[i].regmap_entry[hr]=f_regmap[hr];
9751                       regs[i].regmap[hr]=f_regmap[hr];
9752                       regs[i].wasdirty&=~(1<<hr);
9753                       regs[i].dirty&=~(1<<hr);
9754                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9755                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9756                       regs[i].wasconst&=~(1<<hr);
9757                       regs[i].isconst&=~(1<<hr);
9758                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9759                       branch_regs[i].wasdirty&=~(1<<hr);
9760                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9761                       branch_regs[i].regmap[hr]=f_regmap[hr];
9762                       branch_regs[i].dirty&=~(1<<hr);
9763                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9764                       branch_regs[i].wasconst&=~(1<<hr);
9765                       branch_regs[i].isconst&=~(1<<hr);
9766                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9767                         regmap_pre[i+2][hr]=f_regmap[hr];
9768                         regs[i+2].wasdirty&=~(1<<hr);
9769                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9770                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9771                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9772                       }
9773                     }
9774                   }
9775                   for(k=t;k<j;k++) {
9776                     regs[k].regmap_entry[hr]=f_regmap[hr];
9777                     regs[k].regmap[hr]=f_regmap[hr];
9778                     regmap_pre[k+1][hr]=f_regmap[hr];
9779                     regs[k+1].wasdirty&=~(1<<hr);
9780                     regs[k].dirty&=~(1<<hr);
9781                     regs[k].wasconst&=~(1<<hr);
9782                     regs[k].isconst&=~(1<<hr);
9783                   }
9784                   if(regs[j].regmap[hr]==f_regmap[hr])
9785                     regs[j].regmap_entry[hr]=f_regmap[hr];
9786                   break;
9787                 }
9788                 if(j==i) break;
9789                 if(regs[j].regmap[hr]>=0)
9790                   break;
9791                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9792                   //printf("no-match due to different register\n");
9793                   break;
9794                 }
9795                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9796                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9797                   break;
9798                 }
9799                 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9800                 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9801                 ||itype[j]==FCOMP||itype[j]==FCONV
9802                 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9803                   if(count_free_regs(regs[j].regmap)<2) {
9804                     //printf("No free regs for store %x\n",start+j*4);
9805                     break;
9806                   }
9807                 }
9808                 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9809                 if(f_regmap[hr]>=64) {
9810                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9811                     break;
9812                   }
9813                   else
9814                   {
9815                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9816                       break;
9817                     }
9818                   }
9819                 }
9820               }
9821             }
9822           }
9823         }
9824       }
9825     }else{
9826       int count=0;
9827       for(hr=0;hr<HOST_REGS;hr++)
9828       {
9829         if(hr!=EXCLUDE_REG) {
9830           if(regs[i].regmap[hr]>64) {
9831             if(!((regs[i].dirty>>hr)&1))
9832               f_regmap[hr]=regs[i].regmap[hr];
9833           }
9834           else if(regs[i].regmap[hr]>=0) f_regmap[hr]=regs[i].regmap[hr];
9835           else if(regs[i].regmap[hr]<0) count++;
9836         }
9837       }
9838       // Try to restore cycle count at branch targets
9839       if(bt[i]) {
9840         for(j=i;j<slen-1;j++) {
9841           if(regs[j].regmap[HOST_CCREG]!=-1) break;
9842           if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9843           ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9844           ||itype[j]==FCOMP||itype[j]==FCONV
9845           ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9846             if(count_free_regs(regs[j].regmap)<2) {
9847               //printf("no free regs for store %x\n",start+j*4);
9848               break;
9849             }
9850           }
9851           else
9852           if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9853         }
9854         if(regs[j].regmap[HOST_CCREG]==CCREG) {
9855           int k=i;
9856           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9857           while(k<j) {
9858             regs[k].regmap_entry[HOST_CCREG]=CCREG;
9859             regs[k].regmap[HOST_CCREG]=CCREG;
9860             regmap_pre[k+1][HOST_CCREG]=CCREG;
9861             regs[k+1].wasdirty|=1<<HOST_CCREG;
9862             regs[k].dirty|=1<<HOST_CCREG;
9863             regs[k].wasconst&=~(1<<HOST_CCREG);
9864             regs[k].isconst&=~(1<<HOST_CCREG);
9865             k++;
9866           }
9867           regs[j].regmap_entry[HOST_CCREG]=CCREG;
9868         }
9869         // Work backwards from the branch target
9870         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9871         {
9872           //printf("Extend backwards\n");
9873           int k;
9874           k=i;
9875           while(regs[k-1].regmap[HOST_CCREG]==-1) {
9876             if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
9877             ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
9878             ||itype[k-1]==FCONV||itype[k-1]==FCOMP
9879             ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9880               if(count_free_regs(regs[k-1].regmap)<2) {
9881                 //printf("no free regs for store %x\n",start+(k-1)*4);
9882                 break;
9883               }
9884             }
9885             else
9886             if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9887             k--;
9888           }
9889           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9890             //printf("Extend CC, %x ->\n",start+k*4);
9891             while(k<=i) {
9892               regs[k].regmap_entry[HOST_CCREG]=CCREG;
9893               regs[k].regmap[HOST_CCREG]=CCREG;
9894               regmap_pre[k+1][HOST_CCREG]=CCREG;
9895               regs[k+1].wasdirty|=1<<HOST_CCREG;
9896               regs[k].dirty|=1<<HOST_CCREG;
9897               regs[k].wasconst&=~(1<<HOST_CCREG);
9898               regs[k].isconst&=~(1<<HOST_CCREG);
9899               k++;
9900             }
9901           }
9902           else {
9903             //printf("Fail Extend CC, %x ->\n",start+k*4);
9904           }
9905         }
9906       }
9907       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9908          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9909          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9910          itype[i]!=FCONV&&itype[i]!=FCOMP&&
9911          itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
9912       {
9913         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9914       }
9915     }
9916   }
9917
9918   // This allocates registers (if possible) one instruction prior
9919   // to use, which can avoid a load-use penalty on certain CPUs.
9920   for(i=0;i<slen-1;i++)
9921   {
9922     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9923     {
9924       if(!bt[i+1])
9925       {
9926         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9927            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
9928         {
9929           if(rs1[i+1]) {
9930             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9931             {
9932               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9933               {
9934                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9935                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9936                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9937                 regs[i].isconst&=~(1<<hr);
9938                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9939                 constmap[i][hr]=constmap[i+1][hr];
9940                 regs[i+1].wasdirty&=~(1<<hr);
9941                 regs[i].dirty&=~(1<<hr);
9942               }
9943             }
9944           }
9945           if(rs2[i+1]) {
9946             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9947             {
9948               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9949               {
9950                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9951                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9952                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9953                 regs[i].isconst&=~(1<<hr);
9954                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9955                 constmap[i][hr]=constmap[i+1][hr];
9956                 regs[i+1].wasdirty&=~(1<<hr);
9957                 regs[i].dirty&=~(1<<hr);
9958               }
9959             }
9960           }
9961           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9962             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9963             {
9964               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9965               {
9966                 regs[i].regmap[hr]=rs1[i+1];
9967                 regmap_pre[i+1][hr]=rs1[i+1];
9968                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9969                 regs[i].isconst&=~(1<<hr);
9970                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9971                 constmap[i][hr]=constmap[i+1][hr];
9972                 regs[i+1].wasdirty&=~(1<<hr);
9973                 regs[i].dirty&=~(1<<hr);
9974               }
9975             }
9976           }
9977           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9978             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9979             {
9980               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
9981               {
9982                 regs[i].regmap[hr]=rs1[i+1];
9983                 regmap_pre[i+1][hr]=rs1[i+1];
9984                 regs[i+1].regmap_entry[hr]=rs1[i+1];
9985                 regs[i].isconst&=~(1<<hr);
9986                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9987                 constmap[i][hr]=constmap[i+1][hr];
9988                 regs[i+1].wasdirty&=~(1<<hr);
9989                 regs[i].dirty&=~(1<<hr);
9990               }
9991             }
9992           }
9993           #ifndef HOST_IMM_ADDR32
9994           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
9995             hr=get_reg(regs[i+1].regmap,TLREG);
9996             if(hr>=0) {
9997               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
9998               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
9999                 int nr;
10000                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10001                 {
10002                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10003                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10004                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10005                   regs[i].isconst&=~(1<<hr);
10006                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10007                   constmap[i][hr]=constmap[i+1][hr];
10008                   regs[i+1].wasdirty&=~(1<<hr);
10009                   regs[i].dirty&=~(1<<hr);
10010                 }
10011                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10012                 {
10013                   // move it to another register
10014                   regs[i+1].regmap[hr]=-1;
10015                   regmap_pre[i+2][hr]=-1;
10016                   regs[i+1].regmap[nr]=TLREG;
10017                   regmap_pre[i+2][nr]=TLREG;
10018                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10019                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10020                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10021                   regs[i].isconst&=~(1<<nr);
10022                   regs[i+1].isconst&=~(1<<nr);
10023                   regs[i].dirty&=~(1<<nr);
10024                   regs[i+1].wasdirty&=~(1<<nr);
10025                   regs[i+1].dirty&=~(1<<nr);
10026                   regs[i+2].wasdirty&=~(1<<nr);
10027                 }
10028               }
10029             }
10030           }
10031           #endif
10032           if(itype[i+1]==STORE||itype[i+1]==STORELR
10033              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10034             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10035               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10036               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10037               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10038               assert(hr>=0);
10039               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10040               {
10041                 regs[i].regmap[hr]=rs1[i+1];
10042                 regmap_pre[i+1][hr]=rs1[i+1];
10043                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10044                 regs[i].isconst&=~(1<<hr);
10045                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10046                 constmap[i][hr]=constmap[i+1][hr];
10047                 regs[i+1].wasdirty&=~(1<<hr);
10048                 regs[i].dirty&=~(1<<hr);
10049               }
10050             }
10051           }
10052           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10053             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10054               int nr;
10055               hr=get_reg(regs[i+1].regmap,FTEMP);
10056               assert(hr>=0);
10057               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10058               {
10059                 regs[i].regmap[hr]=rs1[i+1];
10060                 regmap_pre[i+1][hr]=rs1[i+1];
10061                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10062                 regs[i].isconst&=~(1<<hr);
10063                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10064                 constmap[i][hr]=constmap[i+1][hr];
10065                 regs[i+1].wasdirty&=~(1<<hr);
10066                 regs[i].dirty&=~(1<<hr);
10067               }
10068               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10069               {
10070                 // move it to another register
10071                 regs[i+1].regmap[hr]=-1;
10072                 regmap_pre[i+2][hr]=-1;
10073                 regs[i+1].regmap[nr]=FTEMP;
10074                 regmap_pre[i+2][nr]=FTEMP;
10075                 regs[i].regmap[nr]=rs1[i+1];
10076                 regmap_pre[i+1][nr]=rs1[i+1];
10077                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10078                 regs[i].isconst&=~(1<<nr);
10079                 regs[i+1].isconst&=~(1<<nr);
10080                 regs[i].dirty&=~(1<<nr);
10081                 regs[i+1].wasdirty&=~(1<<nr);
10082                 regs[i+1].dirty&=~(1<<nr);
10083                 regs[i+2].wasdirty&=~(1<<nr);
10084               }
10085             }
10086           }
10087           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10088             if(itype[i+1]==LOAD)
10089               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10090             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10091               hr=get_reg(regs[i+1].regmap,FTEMP);
10092             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10093               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10094               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10095             }
10096             if(hr>=0&&regs[i].regmap[hr]<0) {
10097               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10098               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10099                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10100                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10101                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10102                 regs[i].isconst&=~(1<<hr);
10103                 regs[i+1].wasdirty&=~(1<<hr);
10104                 regs[i].dirty&=~(1<<hr);
10105               }
10106             }
10107           }
10108         }
10109       }
10110     }
10111   }
10112
10113   /* Pass 6 - Optimize clean/dirty state */
10114   clean_registers(0,slen-1,1);
10115
10116   /* Pass 7 - Identify 32-bit registers */
10117
10118   provisional_r32();
10119
10120   u_int r32=0;
10121
10122   for (i=slen-1;i>=0;i--)
10123   {
10124     int hr;
10125     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10126     {
10127       if(ba[i]<start || ba[i]>=(start+slen*4))
10128       {
10129         // Branch out of this block, don't need anything
10130         r32=0;
10131       }
10132       else
10133       {
10134         // Internal branch
10135         // Need whatever matches the target
10136         // (and doesn't get overwritten by the delay slot instruction)
10137         r32=0;
10138         int t=(ba[i]-start)>>2;
10139         if(ba[i]>start+i*4) {
10140           // Forward branch
10141           if(!(requires_32bit[t]&~regs[i].was32))
10142             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10143         }else{
10144           // Backward branch
10145           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10146           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10147           if(!(pr32[t]&~regs[i].was32))
10148             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10149         }
10150       }
10151       // Conditional branch may need registers for following instructions
10152       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10153       {
10154         if(i<slen-2) {
10155           r32|=requires_32bit[i+2];
10156           r32&=regs[i].was32;
10157           // Mark this address as a branch target since it may be called
10158           // upon return from interrupt
10159           bt[i+2]=1;
10160         }
10161       }
10162       // Merge in delay slot
10163       if(!likely[i]) {
10164         // These are overwritten unless the branch is "likely"
10165         // and the delay slot is nullified if not taken
10166         r32&=~(1LL<<rt1[i+1]);
10167         r32&=~(1LL<<rt2[i+1]);
10168       }
10169       // Assume these are needed (delay slot)
10170       if(us1[i+1]>0)
10171       {
10172         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10173       }
10174       if(us2[i+1]>0)
10175       {
10176         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10177       }
10178       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10179       {
10180         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10181       }
10182       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10183       {
10184         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10185       }
10186     }
10187     else if(itype[i]==SYSCALL||itype[i]==HLECALL)
10188     {
10189       // SYSCALL instruction (software interrupt)
10190       r32=0;
10191     }
10192     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10193     {
10194       // ERET instruction (return from interrupt)
10195       r32=0;
10196     }
10197     // Check 32 bits
10198     r32&=~(1LL<<rt1[i]);
10199     r32&=~(1LL<<rt2[i]);
10200     if(us1[i]>0)
10201     {
10202       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10203     }
10204     if(us2[i]>0)
10205     {
10206       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10207     }
10208     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10209     {
10210       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10211     }
10212     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10213     {
10214       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10215     }
10216     requires_32bit[i]=r32;
10217
10218     // Dirty registers which are 32-bit, require 32-bit input
10219     // as they will be written as 32-bit values
10220     for(hr=0;hr<HOST_REGS;hr++)
10221     {
10222       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10223         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10224           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10225           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10226         }
10227       }
10228     }
10229     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10230   }
10231
10232   if(itype[slen-1]==SPAN) {
10233     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10234   }
10235
10236   /* Debug/disassembly */
10237   if((void*)assem_debug==(void*)printf)
10238   for(i=0;i<slen;i++)
10239   {
10240     printf("U:");
10241     int r;
10242     for(r=1;r<=CCREG;r++) {
10243       if((unneeded_reg[i]>>r)&1) {
10244         if(r==HIREG) printf(" HI");
10245         else if(r==LOREG) printf(" LO");
10246         else printf(" r%d",r);
10247       }
10248     }
10249 #ifndef FORCE32
10250     printf(" UU:");
10251     for(r=1;r<=CCREG;r++) {
10252       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10253         if(r==HIREG) printf(" HI");
10254         else if(r==LOREG) printf(" LO");
10255         else printf(" r%d",r);
10256       }
10257     }
10258     printf(" 32:");
10259     for(r=0;r<=CCREG;r++) {
10260       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10261       if((regs[i].was32>>r)&1) {
10262         if(r==CCREG) printf(" CC");
10263         else if(r==HIREG) printf(" HI");
10264         else if(r==LOREG) printf(" LO");
10265         else printf(" r%d",r);
10266       }
10267     }
10268 #endif
10269     printf("\n");
10270     #if defined(__i386__) || defined(__x86_64__)
10271     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10272     #endif
10273     #ifdef __arm__
10274     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10275     #endif
10276     printf("needs: ");
10277     if(needed_reg[i]&1) printf("eax ");
10278     if((needed_reg[i]>>1)&1) printf("ecx ");
10279     if((needed_reg[i]>>2)&1) printf("edx ");
10280     if((needed_reg[i]>>3)&1) printf("ebx ");
10281     if((needed_reg[i]>>5)&1) printf("ebp ");
10282     if((needed_reg[i]>>6)&1) printf("esi ");
10283     if((needed_reg[i]>>7)&1) printf("edi ");
10284     printf("r:");
10285     for(r=0;r<=CCREG;r++) {
10286       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10287       if((requires_32bit[i]>>r)&1) {
10288         if(r==CCREG) printf(" CC");
10289         else if(r==HIREG) printf(" HI");
10290         else if(r==LOREG) printf(" LO");
10291         else printf(" r%d",r);
10292       }
10293     }
10294     printf("\n");
10295     /*printf("pr:");
10296     for(r=0;r<=CCREG;r++) {
10297       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10298       if((pr32[i]>>r)&1) {
10299         if(r==CCREG) printf(" CC");
10300         else if(r==HIREG) printf(" HI");
10301         else if(r==LOREG) printf(" LO");
10302         else printf(" r%d",r);
10303       }
10304     }
10305     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10306     printf("\n");*/
10307     #if defined(__i386__) || defined(__x86_64__)
10308     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10309     printf("dirty: ");
10310     if(regs[i].wasdirty&1) printf("eax ");
10311     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10312     if((regs[i].wasdirty>>2)&1) printf("edx ");
10313     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10314     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10315     if((regs[i].wasdirty>>6)&1) printf("esi ");
10316     if((regs[i].wasdirty>>7)&1) printf("edi ");
10317     #endif
10318     #ifdef __arm__
10319     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10320     printf("dirty: ");
10321     if(regs[i].wasdirty&1) printf("r0 ");
10322     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10323     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10324     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10325     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10326     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10327     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10328     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10329     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10330     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10331     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10332     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10333     #endif
10334     printf("\n");
10335     disassemble_inst(i);
10336     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10337     #if defined(__i386__) || defined(__x86_64__)
10338     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10339     if(regs[i].dirty&1) printf("eax ");
10340     if((regs[i].dirty>>1)&1) printf("ecx ");
10341     if((regs[i].dirty>>2)&1) printf("edx ");
10342     if((regs[i].dirty>>3)&1) printf("ebx ");
10343     if((regs[i].dirty>>5)&1) printf("ebp ");
10344     if((regs[i].dirty>>6)&1) printf("esi ");
10345     if((regs[i].dirty>>7)&1) printf("edi ");
10346     #endif
10347     #ifdef __arm__
10348     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10349     if(regs[i].dirty&1) printf("r0 ");
10350     if((regs[i].dirty>>1)&1) printf("r1 ");
10351     if((regs[i].dirty>>2)&1) printf("r2 ");
10352     if((regs[i].dirty>>3)&1) printf("r3 ");
10353     if((regs[i].dirty>>4)&1) printf("r4 ");
10354     if((regs[i].dirty>>5)&1) printf("r5 ");
10355     if((regs[i].dirty>>6)&1) printf("r6 ");
10356     if((regs[i].dirty>>7)&1) printf("r7 ");
10357     if((regs[i].dirty>>8)&1) printf("r8 ");
10358     if((regs[i].dirty>>9)&1) printf("r9 ");
10359     if((regs[i].dirty>>10)&1) printf("r10 ");
10360     if((regs[i].dirty>>12)&1) printf("r12 ");
10361     #endif
10362     printf("\n");
10363     if(regs[i].isconst) {
10364       printf("constants: ");
10365       #if defined(__i386__) || defined(__x86_64__)
10366       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10367       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10368       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10369       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10370       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10371       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10372       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10373       #endif
10374       #ifdef __arm__
10375       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10376       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10377       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10378       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10379       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10380       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10381       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10382       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10383       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10384       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10385       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10386       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10387       #endif
10388       printf("\n");
10389     }
10390 #ifndef FORCE32
10391     printf(" 32:");
10392     for(r=0;r<=CCREG;r++) {
10393       if((regs[i].is32>>r)&1) {
10394         if(r==CCREG) printf(" CC");
10395         else if(r==HIREG) printf(" HI");
10396         else if(r==LOREG) printf(" LO");
10397         else printf(" r%d",r);
10398       }
10399     }
10400     printf("\n");
10401 #endif
10402     /*printf(" p32:");
10403     for(r=0;r<=CCREG;r++) {
10404       if((p32[i]>>r)&1) {
10405         if(r==CCREG) printf(" CC");
10406         else if(r==HIREG) printf(" HI");
10407         else if(r==LOREG) printf(" LO");
10408         else printf(" r%d",r);
10409       }
10410     }
10411     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10412     else printf("\n");*/
10413     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10414       #if defined(__i386__) || defined(__x86_64__)
10415       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10416       if(branch_regs[i].dirty&1) printf("eax ");
10417       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10418       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10419       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10420       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10421       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10422       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10423       #endif
10424       #ifdef __arm__
10425       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10426       if(branch_regs[i].dirty&1) printf("r0 ");
10427       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10428       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10429       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10430       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10431       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10432       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10433       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10434       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10435       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10436       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10437       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10438       #endif
10439 #ifndef FORCE32
10440       printf(" 32:");
10441       for(r=0;r<=CCREG;r++) {
10442         if((branch_regs[i].is32>>r)&1) {
10443           if(r==CCREG) printf(" CC");
10444           else if(r==HIREG) printf(" HI");
10445           else if(r==LOREG) printf(" LO");
10446           else printf(" r%d",r);
10447         }
10448       }
10449       printf("\n");
10450 #endif
10451     }
10452   }
10453
10454   /* Pass 8 - Assembly */
10455   linkcount=0;stubcount=0;
10456   ds=0;is_delayslot=0;
10457   cop1_usable=0;
10458   uint64_t is32_pre=0;
10459   u_int dirty_pre=0;
10460   u_int beginning=(u_int)out;
10461   if((u_int)addr&1) {
10462     ds=1;
10463     pagespan_ds();
10464   }
10465   for(i=0;i<slen;i++)
10466   {
10467     //if(ds) printf("ds: ");
10468     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10469     if(ds) {
10470       ds=0; // Skip delay slot
10471       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10472       instr_addr[i]=0;
10473     } else {
10474       #ifndef DESTRUCTIVE_WRITEBACK
10475       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10476       {
10477         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10478               unneeded_reg[i],unneeded_reg_upper[i]);
10479         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10480               unneeded_reg[i],unneeded_reg_upper[i]);
10481       }
10482       is32_pre=regs[i].is32;
10483       dirty_pre=regs[i].dirty;
10484       #endif
10485       // write back
10486       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10487       {
10488         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10489                       unneeded_reg[i],unneeded_reg_upper[i]);
10490         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10491       }
10492       // branch target entry point
10493       instr_addr[i]=(u_int)out;
10494       assem_debug("<->\n");
10495       // load regs
10496       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10497         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10498       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10499       address_generation(i,&regs[i],regs[i].regmap_entry);
10500       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10501       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10502       {
10503         // Load the delay slot registers if necessary
10504         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10505           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10506         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10507           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10508         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10509           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10510       }
10511       else if(i+1<slen)
10512       {
10513         // Preload registers for following instruction
10514         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10515           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10516             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10517         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10518           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10519             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10520       }
10521       // TODO: if(is_ooo(i)) address_generation(i+1);
10522       if(itype[i]==CJUMP||itype[i]==FJUMP)
10523         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10524       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10525         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10526       if(bt[i]) cop1_usable=0;
10527       // assemble
10528       switch(itype[i]) {
10529         case ALU:
10530           alu_assemble(i,&regs[i]);break;
10531         case IMM16:
10532           imm16_assemble(i,&regs[i]);break;
10533         case SHIFT:
10534           shift_assemble(i,&regs[i]);break;
10535         case SHIFTIMM:
10536           shiftimm_assemble(i,&regs[i]);break;
10537         case LOAD:
10538           load_assemble(i,&regs[i]);break;
10539         case LOADLR:
10540           loadlr_assemble(i,&regs[i]);break;
10541         case STORE:
10542           store_assemble(i,&regs[i]);break;
10543         case STORELR:
10544           storelr_assemble(i,&regs[i]);break;
10545         case COP0:
10546           cop0_assemble(i,&regs[i]);break;
10547         case COP1:
10548           cop1_assemble(i,&regs[i]);break;
10549         case C1LS:
10550           c1ls_assemble(i,&regs[i]);break;
10551         case COP2:
10552           cop2_assemble(i,&regs[i]);break;
10553         case C2LS:
10554           c2ls_assemble(i,&regs[i]);break;
10555         case C2OP:
10556           c2op_assemble(i,&regs[i]);break;
10557         case FCONV:
10558           fconv_assemble(i,&regs[i]);break;
10559         case FLOAT:
10560           float_assemble(i,&regs[i]);break;
10561         case FCOMP:
10562           fcomp_assemble(i,&regs[i]);break;
10563         case MULTDIV:
10564           multdiv_assemble(i,&regs[i]);break;
10565         case MOV:
10566           mov_assemble(i,&regs[i]);break;
10567         case SYSCALL:
10568           syscall_assemble(i,&regs[i]);break;
10569         case HLECALL:
10570           hlecall_assemble(i,&regs[i]);break;
10571         case UJUMP:
10572           ujump_assemble(i,&regs[i]);ds=1;break;
10573         case RJUMP:
10574           rjump_assemble(i,&regs[i]);ds=1;break;
10575         case CJUMP:
10576           cjump_assemble(i,&regs[i]);ds=1;break;
10577         case SJUMP:
10578           sjump_assemble(i,&regs[i]);ds=1;break;
10579         case FJUMP:
10580           fjump_assemble(i,&regs[i]);ds=1;break;
10581         case SPAN:
10582           pagespan_assemble(i,&regs[i]);break;
10583       }
10584       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10585         literal_pool(1024);
10586       else
10587         literal_pool_jumpover(256);
10588     }
10589   }
10590   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10591   // If the block did not end with an unconditional branch,
10592   // add a jump to the next instruction.
10593   if(i>1) {
10594     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10595       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10596       assert(i==slen);
10597       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10598         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10599         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10600           emit_loadreg(CCREG,HOST_CCREG);
10601         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10602       }
10603       else if(!likely[i-2])
10604       {
10605         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10606         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10607       }
10608       else
10609       {
10610         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10611         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10612       }
10613       add_to_linker((int)out,start+i*4,0);
10614       emit_jmp(0);
10615     }
10616   }
10617   else
10618   {
10619     assert(i>0);
10620     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10621     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10622     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10623       emit_loadreg(CCREG,HOST_CCREG);
10624     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10625     add_to_linker((int)out,start+i*4,0);
10626     emit_jmp(0);
10627   }
10628
10629   // TODO: delay slot stubs?
10630   // Stubs
10631   for(i=0;i<stubcount;i++)
10632   {
10633     switch(stubs[i][0])
10634     {
10635       case LOADB_STUB:
10636       case LOADH_STUB:
10637       case LOADW_STUB:
10638       case LOADD_STUB:
10639       case LOADBU_STUB:
10640       case LOADHU_STUB:
10641         do_readstub(i);break;
10642       case STOREB_STUB:
10643       case STOREH_STUB:
10644       case STOREW_STUB:
10645       case STORED_STUB:
10646         do_writestub(i);break;
10647       case CC_STUB:
10648         do_ccstub(i);break;
10649       case INVCODE_STUB:
10650         do_invstub(i);break;
10651       case FP_STUB:
10652         do_cop1stub(i);break;
10653       case STORELR_STUB:
10654         do_unalignedwritestub(i);break;
10655     }
10656   }
10657
10658   /* Pass 9 - Linker */
10659   for(i=0;i<linkcount;i++)
10660   {
10661     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10662     literal_pool(64);
10663     if(!link_addr[i][2])
10664     {
10665       void *stub=out;
10666       void *addr=check_addr(link_addr[i][1]);
10667       emit_extjump(link_addr[i][0],link_addr[i][1]);
10668       if(addr) {
10669         set_jump_target(link_addr[i][0],(int)addr);
10670         add_link(link_addr[i][1],stub);
10671       }
10672       else set_jump_target(link_addr[i][0],(int)stub);
10673     }
10674     else
10675     {
10676       // Internal branch
10677       int target=(link_addr[i][1]-start)>>2;
10678       assert(target>=0&&target<slen);
10679       assert(instr_addr[target]);
10680       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10681       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10682       //#else
10683       set_jump_target(link_addr[i][0],instr_addr[target]);
10684       //#endif
10685     }
10686   }
10687   // External Branch Targets (jump_in)
10688   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10689   for(i=0;i<slen;i++)
10690   {
10691     if(bt[i]||i==0)
10692     {
10693       if(instr_addr[i]) // TODO - delay slots (=null)
10694       {
10695         u_int vaddr=start+i*4;
10696         u_int page=get_page(vaddr);
10697         u_int vpage=get_vpage(vaddr);
10698         literal_pool(256);
10699         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10700         if(!requires_32bit[i])
10701         {
10702           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10703           assem_debug("jump_in: %x\n",start+i*4);
10704           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10705           int entry_point=do_dirty_stub(i);
10706           ll_add(jump_in+page,vaddr,(void *)entry_point);
10707           // If there was an existing entry in the hash table,
10708           // replace it with the new address.
10709           // Don't add new entries.  We'll insert the
10710           // ones that actually get used in check_addr().
10711           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10712           if(ht_bin[0]==vaddr) {
10713             ht_bin[1]=entry_point;
10714           }
10715           if(ht_bin[2]==vaddr) {
10716             ht_bin[3]=entry_point;
10717           }
10718         }
10719         else
10720         {
10721           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10722           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10723           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10724           //int entry_point=(int)out;
10725           ////assem_debug("entry_point: %x\n",entry_point);
10726           //load_regs_entry(i);
10727           //if(entry_point==(int)out)
10728           //  entry_point=instr_addr[i];
10729           //else
10730           //  emit_jmp(instr_addr[i]);
10731           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10732           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10733           int entry_point=do_dirty_stub(i);
10734           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10735         }
10736       }
10737     }
10738   }
10739   // Write out the literal pool if necessary
10740   literal_pool(0);
10741   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10742   // Align code
10743   if(((u_int)out)&7) emit_addnop(13);
10744   #endif
10745   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10746   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10747   memcpy(copy,source,slen*4);
10748   copy+=slen*4;
10749
10750   #ifdef __arm__
10751   __clear_cache((void *)beginning,out);
10752   #endif
10753
10754   // If we're within 256K of the end of the buffer,
10755   // start over from the beginning. (Is 256K enough?)
10756   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10757
10758   // Trap writes to any of the pages we compiled
10759   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10760     invalid_code[i]=0;
10761 #ifndef DISABLE_TLB
10762     memory_map[i]|=0x40000000;
10763     if((signed int)start>=(signed int)0xC0000000) {
10764       assert(using_tlb);
10765       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10766       invalid_code[j]=0;
10767       memory_map[j]|=0x40000000;
10768       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10769     }
10770 #endif
10771   }
10772
10773   /* Pass 10 - Free memory by expiring oldest blocks */
10774
10775   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10776   while(expirep!=end)
10777   {
10778     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10779     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10780     inv_debug("EXP: Phase %d\n",expirep);
10781     switch((expirep>>11)&3)
10782     {
10783       case 0:
10784         // Clear jump_in and jump_dirty
10785         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10786         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10787         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10788         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10789         break;
10790       case 1:
10791         // Clear pointers
10792         ll_kill_pointers(jump_out[expirep&2047],base,shift);
10793         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10794         break;
10795       case 2:
10796         // Clear hash table
10797         for(i=0;i<32;i++) {
10798           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10799           if((ht_bin[3]>>shift)==(base>>shift) ||
10800              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10801             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10802             ht_bin[2]=ht_bin[3]=-1;
10803           }
10804           if((ht_bin[1]>>shift)==(base>>shift) ||
10805              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10806             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10807             ht_bin[0]=ht_bin[2];
10808             ht_bin[1]=ht_bin[3];
10809             ht_bin[2]=ht_bin[3]=-1;
10810           }
10811         }
10812         break;
10813       case 3:
10814         // Clear jump_out
10815         #ifdef __arm__
10816         if((expirep&2047)==0)
10817           __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
10818         #endif
10819         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10820         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10821         break;
10822     }
10823     expirep=(expirep+1)&65535;
10824   }
10825   return 0;
10826 }
10827
10828 // vim:shiftwidth=2:expandtab