libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  84   static uint64_t gte_rt[MAXBLOCK];
  85   static uint64_t gte_unneeded[MAXBLOCK];
  86   static int gte_reads_flags; // gte flag read encountered
  87   int imm[MAXBLOCK];
  88   u_int ba[MAXBLOCK];
  89   char likely[MAXBLOCK];
  90   char is_ds[MAXBLOCK];
  91   char ooo[MAXBLOCK];
  92   uint64_t unneeded_reg[MAXBLOCK];
  93   uint64_t unneeded_reg_upper[MAXBLOCK];
  94   uint64_t branch_unneeded_reg[MAXBLOCK];
  95   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  96   uint64_t p32[MAXBLOCK];
  97   uint64_t pr32[MAXBLOCK];
  98   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  99   signed char regmap[MAXBLOCK][HOST_REGS];
 100   signed char regmap_entry[MAXBLOCK][HOST_REGS];
 101   uint64_t constmap[MAXBLOCK][HOST_REGS];
 102   struct regstat regs[MAXBLOCK];
 103   struct regstat branch_regs[MAXBLOCK];
 104   signed char minimum_free_regs[MAXBLOCK];
 105   u_int needed_reg[MAXBLOCK];
 106   uint64_t requires_32bit[MAXBLOCK];
 107   u_int wont_dirty[MAXBLOCK];
 108   u_int will_dirty[MAXBLOCK];
 109   int ccadj[MAXBLOCK];
 110   int slen;
 111   u_int instr_addr[MAXBLOCK];
 112   u_int link_addr[MAXBLOCK][3];
 113   int linkcount;
 114   u_int stubs[MAXBLOCK*3][8];
 115   int stubcount;
 116   u_int literals[1024][2];
 117   int literalcount;
 118   int is_delayslot;
 119   int cop1_usable;
 120   u_char *out;
 121   struct ll_entry *jump_in[4096];
 122   struct ll_entry *jump_out[4096];
 123   struct ll_entry *jump_dirty[4096];
 124   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 125   char shadow[1048576]  __attribute__((aligned(16)));
 126   void *copy;
 127   int expirep;
 128 #ifndef PCSX
 129   u_int using_tlb;
 130 #else
 131   static const u_int using_tlb=0;
 132 #endif
 133   static u_int sp_in_mirror;
 134   u_int stop_after_jal;
 135   extern u_char restore_candidate[512];
 136   extern int cycle_count;
 137
 138   /* registers that may be allocated */
 139   /* 1-31 gpr */
 140 #define HIREG 32 // hi
 141 #define LOREG 33 // lo
 142 #define FSREG 34 // FPU status (FCSR)
 143 #define CSREG 35 // Coprocessor status
 144 #define CCREG 36 // Cycle count
 145 #define INVCP 37 // Pointer to invalid_code
 146 #define MMREG 38 // Pointer to memory_map
 147 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 148 #define TEMPREG 40
 149 #define FTEMP 40 // FPU temporary register
 150 #define PTEMP 41 // Prefetch temporary register
 151 #define TLREG 42 // TLB mapping offset
 152 #define RHASH 43 // Return address hash
 153 #define RHTBL 44 // Return address hash table address
 154 #define RTEMP 45 // JR/JALR address register
 155 #define MAXREG 45
 156 #define AGEN1 46 // Address generation temporary register
 157 #define AGEN2 47 // Address generation temporary register
 158 #define MGEN1 48 // Maptable address generation temporary register
 159 #define MGEN2 49 // Maptable address generation temporary register
 160 #define BTREG 50 // Branch target temporary register
 161
 162   /* instruction types */
 163 #define NOP 0     // No operation
 164 #define LOAD 1    // Load
 165 #define STORE 2   // Store
 166 #define LOADLR 3  // Unaligned load
 167 #define STORELR 4 // Unaligned store
 168 #define MOV 5     // Move
 169 #define ALU 6     // Arithmetic/logic
 170 #define MULTDIV 7 // Multiply/divide
 171 #define SHIFT 8   // Shift by register
 172 #define SHIFTIMM 9// Shift by immediate
 173 #define IMM16 10  // 16-bit immediate
 174 #define RJUMP 11  // Unconditional jump to register
 175 #define UJUMP 12  // Unconditional jump
 176 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 177 #define SJUMP 14  // Conditional branch (regimm format)
 178 #define COP0 15   // Coprocessor 0
 179 #define COP1 16   // Coprocessor 1
 180 #define C1LS 17   // Coprocessor 1 load/store
 181 #define FJUMP 18  // Conditional branch (floating point)
 182 #define FLOAT 19  // Floating point unit
 183 #define FCONV 20  // Convert integer to float
 184 #define FCOMP 21  // Floating point compare (sets FSREG)
 185 #define SYSCALL 22// SYSCALL
 186 #define OTHER 23  // Other
 187 #define SPAN 24   // Branch/delay slot spans 2 pages
 188 #define NI 25     // Not implemented
 189 #define HLECALL 26// PCSX fake opcodes for HLE
 190 #define COP2 27   // Coprocessor 2 move
 191 #define C2LS 28   // Coprocessor 2 load/store
 192 #define C2OP 29   // Coprocessor 2 operation
 193 #define INTCALL 30// Call interpreter to handle rare corner cases
 194
 195   /* stubs */
 196 #define CC_STUB 1
 197 #define FP_STUB 2
 198 #define LOADB_STUB 3
 199 #define LOADH_STUB 4
 200 #define LOADW_STUB 5
 201 #define LOADD_STUB 6
 202 #define LOADBU_STUB 7
 203 #define LOADHU_STUB 8
 204 #define STOREB_STUB 9
 205 #define STOREH_STUB 10
 206 #define STOREW_STUB 11
 207 #define STORED_STUB 12
 208 #define STORELR_STUB 13
 209 #define INVCODE_STUB 14
 210
 211   /* branch codes */
 212 #define TAKEN 1
 213 #define NOTTAKEN 2
 214 #define NULLDS 3
 215
 216 // asm linkage
 217 int new_recompile_block(int addr);
 218 void *get_addr_ht(u_int vaddr);
 219 void invalidate_block(u_int block);
 220 void invalidate_addr(u_int addr);
 221 void remove_hash(int vaddr);
 222 void jump_vaddr();
 223 void dyna_linker();
 224 void dyna_linker_ds();
 225 void verify_code();
 226 void verify_code_vm();
 227 void verify_code_ds();
 228 void cc_interrupt();
 229 void fp_exception();
 230 void fp_exception_ds();
 231 void jump_syscall();
 232 void jump_syscall_hle();
 233 void jump_eret();
 234 void jump_hlecall();
 235 void jump_intcall();
 236 void new_dyna_leave();
 237
 238 // TLB
 239 void TLBWI_new();
 240 void TLBWR_new();
 241 void read_nomem_new();
 242 void read_nomemb_new();
 243 void read_nomemh_new();
 244 void read_nomemd_new();
 245 void write_nomem_new();
 246 void write_nomemb_new();
 247 void write_nomemh_new();
 248 void write_nomemd_new();
 249 void write_rdram_new();
 250 void write_rdramb_new();
 251 void write_rdramh_new();
 252 void write_rdramd_new();
 253 extern u_int memory_map[1048576];
 254
 255 // Needed by assembler
 256 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 257 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 258 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 259 void load_all_regs(signed char i_regmap[]);
 260 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 261 void load_regs_entry(int t);
 262 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 263
 264 int tracedebug=0;
 265
 266 //#define DEBUG_CYCLE_COUNT 1
 267
 268 void nullf() {}
 269 //#define assem_debug printf
 270 //#define inv_debug printf
 271 #define assem_debug nullf
 272 #define inv_debug nullf
 273
 274 static void tlb_hacks()
 275 {
 276 #ifndef DISABLE_TLB
 277   // Goldeneye hack
 278   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 279   {
 280     u_int addr;
 281     int n;
 282     switch (ROM_HEADER->Country_code&0xFF)
 283     {
 284       case 0x45: // U
 285         addr=0x34b30;
 286         break;
 287       case 0x4A: // J
 288         addr=0x34b70;
 289         break;
 290       case 0x50: // E
 291         addr=0x329f0;
 292         break;
 293       default:
 294         // Unknown country code
 295         addr=0;
 296         break;
 297     }
 298     u_int rom_addr=(u_int)rom;
 299     #ifdef ROM_COPY
 300     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 301     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 302     if((void *)rom>(void *)0xffffffff) {
 303       munmap(ROM_COPY, 67108864);
 304       if(mmap(ROM_COPY, 12582912,
 305               PROT_READ | PROT_WRITE,
 306               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 307               -1, 0) <= 0) {printf("mmap() failed\n");}
 308       memcpy(ROM_COPY,rom,12582912);
 309       rom_addr=(u_int)ROM_COPY;
 310     }
 311     #endif
 312     if(addr) {
 313       for(n=0x7F000;n<0x80000;n++) {
 314         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 315       }
 316     }
 317   }
 318 #endif
 319 }
 320
 321 static u_int get_page(u_int vaddr)
 322 {
 323 #ifndef PCSX
 324   u_int page=(vaddr^0x80000000)>>12;
 325 #else
 326   u_int page=vaddr&~0xe0000000;
 327   if (page < 0x1000000)
 328     page &= ~0x0e00000; // RAM mirrors
 329   page>>=12;
 330 #endif
 331 #ifndef DISABLE_TLB
 332   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 333 #endif
 334   if(page>2048) page=2048+(page&2047);
 335   return page;
 336 }
 337
 338 static u_int get_vpage(u_int vaddr)
 339 {
 340   u_int vpage=(vaddr^0x80000000)>>12;
 341 #ifndef DISABLE_TLB
 342   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 343 #endif
 344   if(vpage>2048) vpage=2048+(vpage&2047);
 345   return vpage;
 346 }
 347
 348 // Get address from virtual address
 349 // This is called from the recompiled JR/JALR instructions
 350 void *get_addr(u_int vaddr)
 351 {
 352   u_int page=get_page(vaddr);
 353   u_int vpage=get_vpage(vaddr);
 354   struct ll_entry *head;
 355   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 356   head=jump_in[page];
 357   while(head!=NULL) {
 358     if(head->vaddr==vaddr&&head->reg32==0) {
 359   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 360       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 361       ht_bin[3]=ht_bin[1];
 362       ht_bin[2]=ht_bin[0];
 363       ht_bin[1]=(int)head->addr;
 364       ht_bin[0]=vaddr;
 365       return head->addr;
 366     }
 367     head=head->next;
 368   }
 369   head=jump_dirty[vpage];
 370   while(head!=NULL) {
 371     if(head->vaddr==vaddr&&head->reg32==0) {
 372       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 373       // Don't restore blocks which are about to expire from the cache
 374       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 375       if(verify_dirty(head->addr)) {
 376         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 377         invalid_code[vaddr>>12]=0;
 378         inv_code_start=inv_code_end=~0;
 379         memory_map[vaddr>>12]|=0x40000000;
 380         if(vpage<2048) {
 381 #ifndef DISABLE_TLB
 382           if(tlb_LUT_r[vaddr>>12]) {
 383             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 384             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 385           }
 386 #endif
 387           restore_candidate[vpage>>3]|=1<<(vpage&7);
 388         }
 389         else restore_candidate[page>>3]|=1<<(page&7);
 390         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 391         if(ht_bin[0]==vaddr) {
 392           ht_bin[1]=(int)head->addr; // Replace existing entry
 393         }
 394         else
 395         {
 396           ht_bin[3]=ht_bin[1];
 397           ht_bin[2]=ht_bin[0];
 398           ht_bin[1]=(int)head->addr;
 399           ht_bin[0]=vaddr;
 400         }
 401         return head->addr;
 402       }
 403     }
 404     head=head->next;
 405   }
 406   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 407   int r=new_recompile_block(vaddr);
 408   if(r==0) return get_addr(vaddr);
 409   // Execute in unmapped page, generate pagefault execption
 410   Status|=2;
 411   Cause=(vaddr<<31)|0x8;
 412   EPC=(vaddr&1)?vaddr-5:vaddr;
 413   BadVAddr=(vaddr&~1);
 414   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 415   EntryHi=BadVAddr&0xFFFFE000;
 416   return get_addr_ht(0x80000000);
 417 }
 418 // Look up address in hash table first
 419 void *get_addr_ht(u_int vaddr)
 420 {
 421   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 422   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 423   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 424   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 425   return get_addr(vaddr);
 426 }
 427
 428 void *get_addr_32(u_int vaddr,u_int flags)
 429 {
 430 #ifdef FORCE32
 431   return get_addr(vaddr);
 432 #else
 433   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 434   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 435   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 436   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 437   u_int page=get_page(vaddr);
 438   u_int vpage=get_vpage(vaddr);
 439   struct ll_entry *head;
 440   head=jump_in[page];
 441   while(head!=NULL) {
 442     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 443       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 444       if(head->reg32==0) {
 445         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 446         if(ht_bin[0]==-1) {
 447           ht_bin[1]=(int)head->addr;
 448           ht_bin[0]=vaddr;
 449         }else if(ht_bin[2]==-1) {
 450           ht_bin[3]=(int)head->addr;
 451           ht_bin[2]=vaddr;
 452         }
 453         //ht_bin[3]=ht_bin[1];
 454         //ht_bin[2]=ht_bin[0];
 455         //ht_bin[1]=(int)head->addr;
 456         //ht_bin[0]=vaddr;
 457       }
 458       return head->addr;
 459     }
 460     head=head->next;
 461   }
 462   head=jump_dirty[vpage];
 463   while(head!=NULL) {
 464     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 465       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 466       // Don't restore blocks which are about to expire from the cache
 467       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 468       if(verify_dirty(head->addr)) {
 469         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 470         invalid_code[vaddr>>12]=0;
 471         inv_code_start=inv_code_end=~0;
 472         memory_map[vaddr>>12]|=0x40000000;
 473         if(vpage<2048) {
 474 #ifndef DISABLE_TLB
 475           if(tlb_LUT_r[vaddr>>12]) {
 476             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 477             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 478           }
 479 #endif
 480           restore_candidate[vpage>>3]|=1<<(vpage&7);
 481         }
 482         else restore_candidate[page>>3]|=1<<(page&7);
 483         if(head->reg32==0) {
 484           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 485           if(ht_bin[0]==-1) {
 486             ht_bin[1]=(int)head->addr;
 487             ht_bin[0]=vaddr;
 488           }else if(ht_bin[2]==-1) {
 489             ht_bin[3]=(int)head->addr;
 490             ht_bin[2]=vaddr;
 491           }
 492           //ht_bin[3]=ht_bin[1];
 493           //ht_bin[2]=ht_bin[0];
 494           //ht_bin[1]=(int)head->addr;
 495           //ht_bin[0]=vaddr;
 496         }
 497         return head->addr;
 498       }
 499     }
 500     head=head->next;
 501   }
 502   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 503   int r=new_recompile_block(vaddr);
 504   if(r==0) return get_addr(vaddr);
 505   // Execute in unmapped page, generate pagefault execption
 506   Status|=2;
 507   Cause=(vaddr<<31)|0x8;
 508   EPC=(vaddr&1)?vaddr-5:vaddr;
 509   BadVAddr=(vaddr&~1);
 510   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 511   EntryHi=BadVAddr&0xFFFFE000;
 512   return get_addr_ht(0x80000000);
 513 #endif
 514 }
 515
 516 void clear_all_regs(signed char regmap[])
 517 {
 518   int hr;
 519   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 520 }
 521
 522 signed char get_reg(signed char regmap[],int r)
 523 {
 524   int hr;
 525   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 526   return -1;
 527 }
 528
 529 // Find a register that is available for two consecutive cycles
 530 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 531 {
 532   int hr;
 533   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 534   return -1;
 535 }
 536
 537 int count_free_regs(signed char regmap[])
 538 {
 539   int count=0;
 540   int hr;
 541   for(hr=0;hr<HOST_REGS;hr++)
 542   {
 543     if(hr!=EXCLUDE_REG) {
 544       if(regmap[hr]<0) count++;
 545     }
 546   }
 547   return count;
 548 }
 549
 550 void dirty_reg(struct regstat *cur,signed char reg)
 551 {
 552   int hr;
 553   if(!reg) return;
 554   for (hr=0;hr<HOST_REGS;hr++) {
 555     if((cur->regmap[hr]&63)==reg) {
 556       cur->dirty|=1<<hr;
 557     }
 558   }
 559 }
 560
 561 // If we dirty the lower half of a 64 bit register which is now being
 562 // sign-extended, we need to dump the upper half.
 563 // Note: Do this only after completion of the instruction, because
 564 // some instructions may need to read the full 64-bit value even if
 565 // overwriting it (eg SLTI, DSRA32).
 566 static void flush_dirty_uppers(struct regstat *cur)
 567 {
 568   int hr,reg;
 569   for (hr=0;hr<HOST_REGS;hr++) {
 570     if((cur->dirty>>hr)&1) {
 571       reg=cur->regmap[hr];
 572       if(reg>=64)
 573         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 574     }
 575   }
 576 }
 577
 578 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 579 {
 580   int hr;
 581   if(!reg) return;
 582   for (hr=0;hr<HOST_REGS;hr++) {
 583     if(cur->regmap[hr]==reg) {
 584       cur->isconst|=1<<hr;
 585       cur->constmap[hr]=value;
 586     }
 587     else if((cur->regmap[hr]^64)==reg) {
 588       cur->isconst|=1<<hr;
 589       cur->constmap[hr]=value>>32;
 590     }
 591   }
 592 }
 593
 594 void clear_const(struct regstat *cur,signed char reg)
 595 {
 596   int hr;
 597   if(!reg) return;
 598   for (hr=0;hr<HOST_REGS;hr++) {
 599     if((cur->regmap[hr]&63)==reg) {
 600       cur->isconst&=~(1<<hr);
 601     }
 602   }
 603 }
 604
 605 int is_const(struct regstat *cur,signed char reg)
 606 {
 607   int hr;
 608   if(reg<0) return 0;
 609   if(!reg) return 1;
 610   for (hr=0;hr<HOST_REGS;hr++) {
 611     if((cur->regmap[hr]&63)==reg) {
 612       return (cur->isconst>>hr)&1;
 613     }
 614   }
 615   return 0;
 616 }
 617 uint64_t get_const(struct regstat *cur,signed char reg)
 618 {
 619   int hr;
 620   if(!reg) return 0;
 621   for (hr=0;hr<HOST_REGS;hr++) {
 622     if(cur->regmap[hr]==reg) {
 623       return cur->constmap[hr];
 624     }
 625   }
 626   printf("Unknown constant in r%d\n",reg);
 627   exit(1);
 628 }
 629
 630 // Least soon needed registers
 631 // Look at the next ten instructions and see which registers
 632 // will be used.  Try not to reallocate these.
 633 void lsn(u_char hsn[], int i, int *preferred_reg)
 634 {
 635   int j;
 636   int b=-1;
 637   for(j=0;j<9;j++)
 638   {
 639     if(i+j>=slen) {
 640       j=slen-i-1;
 641       break;
 642     }
 643     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 644     {
 645       // Don't go past an unconditonal jump
 646       j++;
 647       break;
 648     }
 649   }
 650   for(;j>=0;j--)
 651   {
 652     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 653     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 654     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 655     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 656     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 657       // Stores can allocate zero
 658       hsn[rs1[i+j]]=j;
 659       hsn[rs2[i+j]]=j;
 660     }
 661     // On some architectures stores need invc_ptr
 662     #if defined(HOST_IMM8)
 663     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 664       hsn[INVCP]=j;
 665     }
 666     #endif
 667     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 668     {
 669       hsn[CCREG]=j;
 670       b=j;
 671     }
 672   }
 673   if(b>=0)
 674   {
 675     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 676     {
 677       // Follow first branch
 678       int t=(ba[i+b]-start)>>2;
 679       j=7-b;if(t+j>=slen) j=slen-t-1;
 680       for(;j>=0;j--)
 681       {
 682         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 683         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 684         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 685         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 686       }
 687     }
 688     // TODO: preferred register based on backward branch
 689   }
 690   // Delay slot should preferably not overwrite branch conditions or cycle count
 691   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 692     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 693     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 694     hsn[CCREG]=1;
 695     // ...or hash tables
 696     hsn[RHASH]=1;
 697     hsn[RHTBL]=1;
 698   }
 699   // Coprocessor load/store needs FTEMP, even if not declared
 700   if(itype[i]==C1LS||itype[i]==C2LS) {
 701     hsn[FTEMP]=0;
 702   }
 703   // Load L/R also uses FTEMP as a temporary register
 704   if(itype[i]==LOADLR) {
 705     hsn[FTEMP]=0;
 706   }
 707   // Also SWL/SWR/SDL/SDR
 708   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 709     hsn[FTEMP]=0;
 710   }
 711   // Don't remove the TLB registers either
 712   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 713     hsn[TLREG]=0;
 714   }
 715   // Don't remove the miniht registers
 716   if(itype[i]==UJUMP||itype[i]==RJUMP)
 717   {
 718     hsn[RHASH]=0;
 719     hsn[RHTBL]=0;
 720   }
 721 }
 722
 723 // We only want to allocate registers if we're going to use them again soon
 724 int needed_again(int r, int i)
 725 {
 726   int j;
 727   int b=-1;
 728   int rn=10;
 729
 730   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 731   {
 732     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 733       return 0; // Don't need any registers if exiting the block
 734   }
 735   for(j=0;j<9;j++)
 736   {
 737     if(i+j>=slen) {
 738       j=slen-i-1;
 739       break;
 740     }
 741     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 742     {
 743       // Don't go past an unconditonal jump
 744       j++;
 745       break;
 746     }
 747     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 748     {
 749       break;
 750     }
 751   }
 752   for(;j>=1;j--)
 753   {
 754     if(rs1[i+j]==r) rn=j;
 755     if(rs2[i+j]==r) rn=j;
 756     if((unneeded_reg[i+j]>>r)&1) rn=10;
 757     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 758     {
 759       b=j;
 760     }
 761   }
 762   /*
 763   if(b>=0)
 764   {
 765     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 766     {
 767       // Follow first branch
 768       int o=rn;
 769       int t=(ba[i+b]-start)>>2;
 770       j=7-b;if(t+j>=slen) j=slen-t-1;
 771       for(;j>=0;j--)
 772       {
 773         if(!((unneeded_reg[t+j]>>r)&1)) {
 774           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 775           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 776         }
 777         else rn=o;
 778       }
 779     }
 780   }*/
 781   if(rn<10) return 1;
 782   return 0;
 783 }
 784
 785 // Try to match register allocations at the end of a loop with those
 786 // at the beginning
 787 int loop_reg(int i, int r, int hr)
 788 {
 789   int j,k;
 790   for(j=0;j<9;j++)
 791   {
 792     if(i+j>=slen) {
 793       j=slen-i-1;
 794       break;
 795     }
 796     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 797     {
 798       // Don't go past an unconditonal jump
 799       j++;
 800       break;
 801     }
 802   }
 803   k=0;
 804   if(i>0){
 805     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 806       k--;
 807   }
 808   for(;k<j;k++)
 809   {
 810     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 811     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 812     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 813     {
 814       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 815       {
 816         int t=(ba[i+k]-start)>>2;
 817         int reg=get_reg(regs[t].regmap_entry,r);
 818         if(reg>=0) return reg;
 819         //reg=get_reg(regs[t+1].regmap_entry,r);
 820         //if(reg>=0) return reg;
 821       }
 822     }
 823   }
 824   return hr;
 825 }
 826
 827
 828 // Allocate every register, preserving source/target regs
 829 void alloc_all(struct regstat *cur,int i)
 830 {
 831   int hr;
 832
 833   for(hr=0;hr<HOST_REGS;hr++) {
 834     if(hr!=EXCLUDE_REG) {
 835       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 836          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 837       {
 838         cur->regmap[hr]=-1;
 839         cur->dirty&=~(1<<hr);
 840       }
 841       // Don't need zeros
 842       if((cur->regmap[hr]&63)==0)
 843       {
 844         cur->regmap[hr]=-1;
 845         cur->dirty&=~(1<<hr);
 846       }
 847     }
 848   }
 849 }
 850
 851
 852 void div64(int64_t dividend,int64_t divisor)
 853 {
 854   lo=dividend/divisor;
 855   hi=dividend%divisor;
 856   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 857   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 858 }
 859 void divu64(uint64_t dividend,uint64_t divisor)
 860 {
 861   lo=dividend/divisor;
 862   hi=dividend%divisor;
 863   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 864   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 865 }
 866
 867 void mult64(uint64_t m1,uint64_t m2)
 868 {
 869    unsigned long long int op1, op2, op3, op4;
 870    unsigned long long int result1, result2, result3, result4;
 871    unsigned long long int temp1, temp2, temp3, temp4;
 872    int sign = 0;
 873
 874    if (m1 < 0)
 875      {
 876     op2 = -m1;
 877     sign = 1 - sign;
 878      }
 879    else op2 = m1;
 880    if (m2 < 0)
 881      {
 882     op4 = -m2;
 883     sign = 1 - sign;
 884      }
 885    else op4 = m2;
 886
 887    op1 = op2 & 0xFFFFFFFF;
 888    op2 = (op2 >> 32) & 0xFFFFFFFF;
 889    op3 = op4 & 0xFFFFFFFF;
 890    op4 = (op4 >> 32) & 0xFFFFFFFF;
 891
 892    temp1 = op1 * op3;
 893    temp2 = (temp1 >> 32) + op1 * op4;
 894    temp3 = op2 * op3;
 895    temp4 = (temp3 >> 32) + op2 * op4;
 896
 897    result1 = temp1 & 0xFFFFFFFF;
 898    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 899    result3 = (result2 >> 32) + temp4;
 900    result4 = (result3 >> 32);
 901
 902    lo = result1 | (result2 << 32);
 903    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 904    if (sign)
 905      {
 906     hi = ~hi;
 907     if (!lo) hi++;
 908     else lo = ~lo + 1;
 909      }
 910 }
 911
 912 void multu64(uint64_t m1,uint64_t m2)
 913 {
 914    unsigned long long int op1, op2, op3, op4;
 915    unsigned long long int result1, result2, result3, result4;
 916    unsigned long long int temp1, temp2, temp3, temp4;
 917
 918    op1 = m1 & 0xFFFFFFFF;
 919    op2 = (m1 >> 32) & 0xFFFFFFFF;
 920    op3 = m2 & 0xFFFFFFFF;
 921    op4 = (m2 >> 32) & 0xFFFFFFFF;
 922
 923    temp1 = op1 * op3;
 924    temp2 = (temp1 >> 32) + op1 * op4;
 925    temp3 = op2 * op3;
 926    temp4 = (temp3 >> 32) + op2 * op4;
 927
 928    result1 = temp1 & 0xFFFFFFFF;
 929    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 930    result3 = (result2 >> 32) + temp4;
 931    result4 = (result3 >> 32);
 932
 933    lo = result1 | (result2 << 32);
 934    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 935
 936   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 937   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 938 }
 939
 940 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 941 {
 942   if(bits) {
 943     original<<=64-bits;
 944     original>>=64-bits;
 945     loaded<<=bits;
 946     original|=loaded;
 947   }
 948   else original=loaded;
 949   return original;
 950 }
 951 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 952 {
 953   if(bits^56) {
 954     original>>=64-(bits^56);
 955     original<<=64-(bits^56);
 956     loaded>>=bits^56;
 957     original|=loaded;
 958   }
 959   else original=loaded;
 960   return original;
 961 }
 962
 963 #ifdef __i386__
 964 #include "assem_x86.c"
 965 #endif
 966 #ifdef __x86_64__
 967 #include "assem_x64.c"
 968 #endif
 969 #ifdef __arm__
 970 #include "assem_arm.c"
 971 #endif
 972
 973 // Add virtual address mapping to linked list
 974 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 975 {
 976   struct ll_entry *new_entry;
 977   new_entry=malloc(sizeof(struct ll_entry));
 978   assert(new_entry!=NULL);
 979   new_entry->vaddr=vaddr;
 980   new_entry->reg32=0;
 981   new_entry->addr=addr;
 982   new_entry->next=*head;
 983   *head=new_entry;
 984 }
 985
 986 // Add virtual address mapping for 32-bit compiled block
 987 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 988 {
 989   ll_add(head,vaddr,addr);
 990 #ifndef FORCE32
 991   (*head)->reg32=reg32;
 992 #endif
 993 }
 994
 995 // Check if an address is already compiled
 996 // but don't return addresses which are about to expire from the cache
 997 void *check_addr(u_int vaddr)
 998 {
 999   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1000   if(ht_bin[0]==vaddr) {
1001     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1003   }
1004   if(ht_bin[2]==vaddr) {
1005     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1006       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1007   }
1008   u_int page=get_page(vaddr);
1009   struct ll_entry *head;
1010   head=jump_in[page];
1011   while(head!=NULL) {
1012     if(head->vaddr==vaddr&&head->reg32==0) {
1013       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1014         // Update existing entry with current address
1015         if(ht_bin[0]==vaddr) {
1016           ht_bin[1]=(int)head->addr;
1017           return head->addr;
1018         }
1019         if(ht_bin[2]==vaddr) {
1020           ht_bin[3]=(int)head->addr;
1021           return head->addr;
1022         }
1023         // Insert into hash table with low priority.
1024         // Don't evict existing entries, as they are probably
1025         // addresses that are being accessed frequently.
1026         if(ht_bin[0]==-1) {
1027           ht_bin[1]=(int)head->addr;
1028           ht_bin[0]=vaddr;
1029         }else if(ht_bin[2]==-1) {
1030           ht_bin[3]=(int)head->addr;
1031           ht_bin[2]=vaddr;
1032         }
1033         return head->addr;
1034       }
1035     }
1036     head=head->next;
1037   }
1038   return 0;
1039 }
1040
1041 void remove_hash(int vaddr)
1042 {
1043   //printf("remove hash: %x\n",vaddr);
1044   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1045   if(ht_bin[2]==vaddr) {
1046     ht_bin[2]=ht_bin[3]=-1;
1047   }
1048   if(ht_bin[0]==vaddr) {
1049     ht_bin[0]=ht_bin[2];
1050     ht_bin[1]=ht_bin[3];
1051     ht_bin[2]=ht_bin[3]=-1;
1052   }
1053 }
1054
1055 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1056 {
1057   struct ll_entry *next;
1058   while(*head) {
1059     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1060        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1061     {
1062       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1063       remove_hash((*head)->vaddr);
1064       next=(*head)->next;
1065       free(*head);
1066       *head=next;
1067     }
1068     else
1069     {
1070       head=&((*head)->next);
1071     }
1072   }
1073 }
1074
1075 // Remove all entries from linked list
1076 void ll_clear(struct ll_entry **head)
1077 {
1078   struct ll_entry *cur;
1079   struct ll_entry *next;
1080   if(cur=*head) {
1081     *head=0;
1082     while(cur) {
1083       next=cur->next;
1084       free(cur);
1085       cur=next;
1086     }
1087   }
1088 }
1089
1090 // Dereference the pointers and remove if it matches
1091 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1092 {
1093   while(head) {
1094     int ptr=get_pointer(head->addr);
1095     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1096     if(((ptr>>shift)==(addr>>shift)) ||
1097        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1098     {
1099       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1100       u_int host_addr=(u_int)kill_pointer(head->addr);
1101       #ifdef __arm__
1102         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1103       #endif
1104     }
1105     head=head->next;
1106   }
1107 }
1108
1109 // This is called when we write to a compiled block (see do_invstub)
1110 void invalidate_page(u_int page)
1111 {
1112   struct ll_entry *head;
1113   struct ll_entry *next;
1114   head=jump_in[page];
1115   jump_in[page]=0;
1116   while(head!=NULL) {
1117     inv_debug("INVALIDATE: %x\n",head->vaddr);
1118     remove_hash(head->vaddr);
1119     next=head->next;
1120     free(head);
1121     head=next;
1122   }
1123   head=jump_out[page];
1124   jump_out[page]=0;
1125   while(head!=NULL) {
1126     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1127     u_int host_addr=(u_int)kill_pointer(head->addr);
1128     #ifdef __arm__
1129       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1130     #endif
1131     next=head->next;
1132     free(head);
1133     head=next;
1134   }
1135 }
1136
1137 static void invalidate_block_range(u_int block, u_int first, u_int last)
1138 {
1139   u_int page=get_page(block<<12);
1140   //printf("first=%d last=%d\n",first,last);
1141   invalidate_page(page);
1142   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1143   assert(last<page+5);
1144   // Invalidate the adjacent pages if a block crosses a 4K boundary
1145   while(first<page) {
1146     invalidate_page(first);
1147     first++;
1148   }
1149   for(first=page+1;first<last;first++) {
1150     invalidate_page(first);
1151   }
1152   #ifdef __arm__
1153     do_clear_cache();
1154   #endif
1155
1156   // Don't trap writes
1157   invalid_code[block]=1;
1158 #ifndef DISABLE_TLB
1159   // If there is a valid TLB entry for this page, remove write protect
1160   if(tlb_LUT_w[block]) {
1161     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1162     // CHECK: Is this right?
1163     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1164     u_int real_block=tlb_LUT_w[block]>>12;
1165     invalid_code[real_block]=1;
1166     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1167   }
1168   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1169 #endif
1170
1171   #ifdef USE_MINI_HT
1172   memset(mini_ht,-1,sizeof(mini_ht));
1173   #endif
1174 }
1175
1176 void invalidate_block(u_int block)
1177 {
1178   u_int page=get_page(block<<12);
1179   u_int vpage=get_vpage(block<<12);
1180   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1181   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1182   u_int first,last;
1183   first=last=page;
1184   struct ll_entry *head;
1185   head=jump_dirty[vpage];
1186   //printf("page=%d vpage=%d\n",page,vpage);
1187   while(head!=NULL) {
1188     u_int start,end;
1189     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1190       get_bounds((int)head->addr,&start,&end);
1191       //printf("start: %x end: %x\n",start,end);
1192       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1193         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1194           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1195           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1196         }
1197       }
1198 #ifndef DISABLE_TLB
1199       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1200         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1201           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1202           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1203         }
1204       }
1205 #endif
1206     }
1207     head=head->next;
1208   }
1209   invalidate_block_range(block,first,last);
1210 }
1211
1212 void invalidate_addr(u_int addr)
1213 {
1214 #ifdef PCSX
1215   //static int rhits;
1216   // this check is done by the caller
1217   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1218   u_int page=get_page(addr);
1219   if(page<2048) { // RAM
1220     struct ll_entry *head;
1221     u_int addr_min=~0, addr_max=0;
1222     int mask=RAM_SIZE-1;
1223     int pg1;
1224     inv_code_start=addr&~0xfff;
1225     inv_code_end=addr|0xfff;
1226     pg1=page;
1227     if (pg1>0) {
1228       // must check previous page too because of spans..
1229       pg1--;
1230       inv_code_start-=0x1000;
1231     }
1232     for(;pg1<=page;pg1++) {
1233       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1234         u_int start,end;
1235         get_bounds((int)head->addr,&start,&end);
1236         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1237           if(start<addr_min) addr_min=start;
1238           if(end>addr_max) addr_max=end;
1239         }
1240         else if(addr<start) {
1241           if(start<inv_code_end)
1242             inv_code_end=start-1;
1243         }
1244         else {
1245           if(end>inv_code_start)
1246             inv_code_start=end;
1247         }
1248       }
1249     }
1250     if (addr_min!=~0) {
1251       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1252       inv_code_start=inv_code_end=~0;
1253       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1254       return;
1255     }
1256     else {
1257       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1258     }
1259     //rhits=0;
1260     if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1261       return;
1262   }
1263 #endif
1264   invalidate_block(addr>>12);
1265 }
1266
1267 // This is called when loading a save state.
1268 // Anything could have changed, so invalidate everything.
1269 void invalidate_all_pages()
1270 {
1271   u_int page,n;
1272   for(page=0;page<4096;page++)
1273     invalidate_page(page);
1274   for(page=0;page<1048576;page++)
1275     if(!invalid_code[page]) {
1276       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1277       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1278     }
1279   #ifdef __arm__
1280   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1281   #endif
1282   #ifdef USE_MINI_HT
1283   memset(mini_ht,-1,sizeof(mini_ht));
1284   #endif
1285   #ifndef DISABLE_TLB
1286   // TLB
1287   for(page=0;page<0x100000;page++) {
1288     if(tlb_LUT_r[page]) {
1289       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1290       if(!tlb_LUT_w[page]||!invalid_code[page])
1291         memory_map[page]|=0x40000000; // Write protect
1292     }
1293     else memory_map[page]=-1;
1294     if(page==0x80000) page=0xC0000;
1295   }
1296   tlb_hacks();
1297   #endif
1298 }
1299
1300 // Add an entry to jump_out after making a link
1301 void add_link(u_int vaddr,void *src)
1302 {
1303   u_int page=get_page(vaddr);
1304   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1305   int *ptr=(int *)(src+4);
1306   assert((*ptr&0x0fff0000)==0x059f0000);
1307   ll_add(jump_out+page,vaddr,src);
1308   //int ptr=get_pointer(src);
1309   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1310 }
1311
1312 // If a code block was found to be unmodified (bit was set in
1313 // restore_candidate) and it remains unmodified (bit is clear
1314 // in invalid_code) then move the entries for that 4K page from
1315 // the dirty list to the clean list.
1316 void clean_blocks(u_int page)
1317 {
1318   struct ll_entry *head;
1319   inv_debug("INV: clean_blocks page=%d\n",page);
1320   head=jump_dirty[page];
1321   while(head!=NULL) {
1322     if(!invalid_code[head->vaddr>>12]) {
1323       // Don't restore blocks which are about to expire from the cache
1324       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1325         u_int start,end;
1326         if(verify_dirty((int)head->addr)) {
1327           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1328           u_int i;
1329           u_int inv=0;
1330           get_bounds((int)head->addr,&start,&end);
1331           if(start-(u_int)rdram<RAM_SIZE) {
1332             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1333               inv|=invalid_code[i];
1334             }
1335           }
1336           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1337             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1338             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1339             if(addr<start||addr>=end) inv=1;
1340           }
1341           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1342             inv=1;
1343           }
1344           if(!inv) {
1345             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1346             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1347               u_int ppage=page;
1348 #ifndef DISABLE_TLB
1349               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1350 #endif
1351               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1352               //printf("page=%x, addr=%x\n",page,head->vaddr);
1353               //assert(head->vaddr>>12==(page|0x80000));
1354               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1355               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1356               if(!head->reg32) {
1357                 if(ht_bin[0]==head->vaddr) {
1358                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1359                 }
1360                 if(ht_bin[2]==head->vaddr) {
1361                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1362                 }
1363               }
1364             }
1365           }
1366         }
1367       }
1368     }
1369     head=head->next;
1370   }
1371 }
1372
1373
1374 void mov_alloc(struct regstat *current,int i)
1375 {
1376   // Note: Don't need to actually alloc the source registers
1377   if((~current->is32>>rs1[i])&1) {
1378     //alloc_reg64(current,i,rs1[i]);
1379     alloc_reg64(current,i,rt1[i]);
1380     current->is32&=~(1LL<<rt1[i]);
1381   } else {
1382     //alloc_reg(current,i,rs1[i]);
1383     alloc_reg(current,i,rt1[i]);
1384     current->is32|=(1LL<<rt1[i]);
1385   }
1386   clear_const(current,rs1[i]);
1387   clear_const(current,rt1[i]);
1388   dirty_reg(current,rt1[i]);
1389 }
1390
1391 void shiftimm_alloc(struct regstat *current,int i)
1392 {
1393   clear_const(current,rs1[i]);
1394   clear_const(current,rt1[i]);
1395   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1396   {
1397     if(rt1[i]) {
1398       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1399       else lt1[i]=rs1[i];
1400       alloc_reg(current,i,rt1[i]);
1401       current->is32|=1LL<<rt1[i];
1402       dirty_reg(current,rt1[i]);
1403     }
1404   }
1405   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1406   {
1407     if(rt1[i]) {
1408       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1409       alloc_reg64(current,i,rt1[i]);
1410       current->is32&=~(1LL<<rt1[i]);
1411       dirty_reg(current,rt1[i]);
1412     }
1413   }
1414   if(opcode2[i]==0x3c) // DSLL32
1415   {
1416     if(rt1[i]) {
1417       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1418       alloc_reg64(current,i,rt1[i]);
1419       current->is32&=~(1LL<<rt1[i]);
1420       dirty_reg(current,rt1[i]);
1421     }
1422   }
1423   if(opcode2[i]==0x3e) // DSRL32
1424   {
1425     if(rt1[i]) {
1426       alloc_reg64(current,i,rs1[i]);
1427       if(imm[i]==32) {
1428         alloc_reg64(current,i,rt1[i]);
1429         current->is32&=~(1LL<<rt1[i]);
1430       } else {
1431         alloc_reg(current,i,rt1[i]);
1432         current->is32|=1LL<<rt1[i];
1433       }
1434       dirty_reg(current,rt1[i]);
1435     }
1436   }
1437   if(opcode2[i]==0x3f) // DSRA32
1438   {
1439     if(rt1[i]) {
1440       alloc_reg64(current,i,rs1[i]);
1441       alloc_reg(current,i,rt1[i]);
1442       current->is32|=1LL<<rt1[i];
1443       dirty_reg(current,rt1[i]);
1444     }
1445   }
1446 }
1447
1448 void shift_alloc(struct regstat *current,int i)
1449 {
1450   if(rt1[i]) {
1451     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1452     {
1453       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1454       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1455       alloc_reg(current,i,rt1[i]);
1456       if(rt1[i]==rs2[i]) {
1457         alloc_reg_temp(current,i,-1);
1458         minimum_free_regs[i]=1;
1459       }
1460       current->is32|=1LL<<rt1[i];
1461     } else { // DSLLV/DSRLV/DSRAV
1462       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1463       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1464       alloc_reg64(current,i,rt1[i]);
1465       current->is32&=~(1LL<<rt1[i]);
1466       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1467       {
1468         alloc_reg_temp(current,i,-1);
1469         minimum_free_regs[i]=1;
1470       }
1471     }
1472     clear_const(current,rs1[i]);
1473     clear_const(current,rs2[i]);
1474     clear_const(current,rt1[i]);
1475     dirty_reg(current,rt1[i]);
1476   }
1477 }
1478
1479 void alu_alloc(struct regstat *current,int i)
1480 {
1481   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1482     if(rt1[i]) {
1483       if(rs1[i]&&rs2[i]) {
1484         alloc_reg(current,i,rs1[i]);
1485         alloc_reg(current,i,rs2[i]);
1486       }
1487       else {
1488         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1489         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1490       }
1491       alloc_reg(current,i,rt1[i]);
1492     }
1493     current->is32|=1LL<<rt1[i];
1494   }
1495   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1496     if(rt1[i]) {
1497       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1498       {
1499         alloc_reg64(current,i,rs1[i]);
1500         alloc_reg64(current,i,rs2[i]);
1501         alloc_reg(current,i,rt1[i]);
1502       } else {
1503         alloc_reg(current,i,rs1[i]);
1504         alloc_reg(current,i,rs2[i]);
1505         alloc_reg(current,i,rt1[i]);
1506       }
1507     }
1508     current->is32|=1LL<<rt1[i];
1509   }
1510   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1511     if(rt1[i]) {
1512       if(rs1[i]&&rs2[i]) {
1513         alloc_reg(current,i,rs1[i]);
1514         alloc_reg(current,i,rs2[i]);
1515       }
1516       else
1517       {
1518         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1520       }
1521       alloc_reg(current,i,rt1[i]);
1522       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1523       {
1524         if(!((current->uu>>rt1[i])&1)) {
1525           alloc_reg64(current,i,rt1[i]);
1526         }
1527         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1528           if(rs1[i]&&rs2[i]) {
1529             alloc_reg64(current,i,rs1[i]);
1530             alloc_reg64(current,i,rs2[i]);
1531           }
1532           else
1533           {
1534             // Is is really worth it to keep 64-bit values in registers?
1535             #ifdef NATIVE_64BIT
1536             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1537             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1538             #endif
1539           }
1540         }
1541         current->is32&=~(1LL<<rt1[i]);
1542       } else {
1543         current->is32|=1LL<<rt1[i];
1544       }
1545     }
1546   }
1547   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1548     if(rt1[i]) {
1549       if(rs1[i]&&rs2[i]) {
1550         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551           alloc_reg64(current,i,rs1[i]);
1552           alloc_reg64(current,i,rs2[i]);
1553           alloc_reg64(current,i,rt1[i]);
1554         } else {
1555           alloc_reg(current,i,rs1[i]);
1556           alloc_reg(current,i,rs2[i]);
1557           alloc_reg(current,i,rt1[i]);
1558         }
1559       }
1560       else {
1561         alloc_reg(current,i,rt1[i]);
1562         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1563           // DADD used as move, or zeroing
1564           // If we have a 64-bit source, then make the target 64 bits too
1565           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1566             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1567             alloc_reg64(current,i,rt1[i]);
1568           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1569             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1570             alloc_reg64(current,i,rt1[i]);
1571           }
1572           if(opcode2[i]>=0x2e&&rs2[i]) {
1573             // DSUB used as negation - 64-bit result
1574             // If we have a 32-bit register, extend it to 64 bits
1575             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1576             alloc_reg64(current,i,rt1[i]);
1577           }
1578         }
1579       }
1580       if(rs1[i]&&rs2[i]) {
1581         current->is32&=~(1LL<<rt1[i]);
1582       } else if(rs1[i]) {
1583         current->is32&=~(1LL<<rt1[i]);
1584         if((current->is32>>rs1[i])&1)
1585           current->is32|=1LL<<rt1[i];
1586       } else if(rs2[i]) {
1587         current->is32&=~(1LL<<rt1[i]);
1588         if((current->is32>>rs2[i])&1)
1589           current->is32|=1LL<<rt1[i];
1590       } else {
1591         current->is32|=1LL<<rt1[i];
1592       }
1593     }
1594   }
1595   clear_const(current,rs1[i]);
1596   clear_const(current,rs2[i]);
1597   clear_const(current,rt1[i]);
1598   dirty_reg(current,rt1[i]);
1599 }
1600
1601 void imm16_alloc(struct regstat *current,int i)
1602 {
1603   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1604   else lt1[i]=rs1[i];
1605   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1606   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1607     current->is32&=~(1LL<<rt1[i]);
1608     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1609       // TODO: Could preserve the 32-bit flag if the immediate is zero
1610       alloc_reg64(current,i,rt1[i]);
1611       alloc_reg64(current,i,rs1[i]);
1612     }
1613     clear_const(current,rs1[i]);
1614     clear_const(current,rt1[i]);
1615   }
1616   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1617     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1618     current->is32|=1LL<<rt1[i];
1619     clear_const(current,rs1[i]);
1620     clear_const(current,rt1[i]);
1621   }
1622   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1623     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1624       if(rs1[i]!=rt1[i]) {
1625         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1626         alloc_reg64(current,i,rt1[i]);
1627         current->is32&=~(1LL<<rt1[i]);
1628       }
1629     }
1630     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1631     if(is_const(current,rs1[i])) {
1632       int v=get_const(current,rs1[i]);
1633       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1634       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1635       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1636     }
1637     else clear_const(current,rt1[i]);
1638   }
1639   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1640     if(is_const(current,rs1[i])) {
1641       int v=get_const(current,rs1[i]);
1642       set_const(current,rt1[i],v+imm[i]);
1643     }
1644     else clear_const(current,rt1[i]);
1645     current->is32|=1LL<<rt1[i];
1646   }
1647   else {
1648     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1649     current->is32|=1LL<<rt1[i];
1650   }
1651   dirty_reg(current,rt1[i]);
1652 }
1653
1654 void load_alloc(struct regstat *current,int i)
1655 {
1656   clear_const(current,rt1[i]);
1657   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1658   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1659   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1660   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1661     alloc_reg(current,i,rt1[i]);
1662     assert(get_reg(current->regmap,rt1[i])>=0);
1663     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1664     {
1665       current->is32&=~(1LL<<rt1[i]);
1666       alloc_reg64(current,i,rt1[i]);
1667     }
1668     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1669     {
1670       current->is32&=~(1LL<<rt1[i]);
1671       alloc_reg64(current,i,rt1[i]);
1672       alloc_all(current,i);
1673       alloc_reg64(current,i,FTEMP);
1674       minimum_free_regs[i]=HOST_REGS;
1675     }
1676     else current->is32|=1LL<<rt1[i];
1677     dirty_reg(current,rt1[i]);
1678     // If using TLB, need a register for pointer to the mapping table
1679     if(using_tlb) alloc_reg(current,i,TLREG);
1680     // LWL/LWR need a temporary register for the old value
1681     if(opcode[i]==0x22||opcode[i]==0x26)
1682     {
1683       alloc_reg(current,i,FTEMP);
1684       alloc_reg_temp(current,i,-1);
1685       minimum_free_regs[i]=1;
1686     }
1687   }
1688   else
1689   {
1690     // Load to r0 or unneeded register (dummy load)
1691     // but we still need a register to calculate the address
1692     if(opcode[i]==0x22||opcode[i]==0x26)
1693     {
1694       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1695     }
1696     // If using TLB, need a register for pointer to the mapping table
1697     if(using_tlb) alloc_reg(current,i,TLREG);
1698     alloc_reg_temp(current,i,-1);
1699     minimum_free_regs[i]=1;
1700     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1701     {
1702       alloc_all(current,i);
1703       alloc_reg64(current,i,FTEMP);
1704       minimum_free_regs[i]=HOST_REGS;
1705     }
1706   }
1707 }
1708
1709 void store_alloc(struct regstat *current,int i)
1710 {
1711   clear_const(current,rs2[i]);
1712   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1713   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1714   alloc_reg(current,i,rs2[i]);
1715   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1716     alloc_reg64(current,i,rs2[i]);
1717     if(rs2[i]) alloc_reg(current,i,FTEMP);
1718   }
1719   // If using TLB, need a register for pointer to the mapping table
1720   if(using_tlb) alloc_reg(current,i,TLREG);
1721   #if defined(HOST_IMM8)
1722   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1723   else alloc_reg(current,i,INVCP);
1724   #endif
1725   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1726     alloc_reg(current,i,FTEMP);
1727   }
1728   // We need a temporary register for address generation
1729   alloc_reg_temp(current,i,-1);
1730   minimum_free_regs[i]=1;
1731 }
1732
1733 void c1ls_alloc(struct regstat *current,int i)
1734 {
1735   //clear_const(current,rs1[i]); // FIXME
1736   clear_const(current,rt1[i]);
1737   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738   alloc_reg(current,i,CSREG); // Status
1739   alloc_reg(current,i,FTEMP);
1740   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1741     alloc_reg64(current,i,FTEMP);
1742   }
1743   // If using TLB, need a register for pointer to the mapping table
1744   if(using_tlb) alloc_reg(current,i,TLREG);
1745   #if defined(HOST_IMM8)
1746   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1748     alloc_reg(current,i,INVCP);
1749   #endif
1750   // We need a temporary register for address generation
1751   alloc_reg_temp(current,i,-1);
1752 }
1753
1754 void c2ls_alloc(struct regstat *current,int i)
1755 {
1756   clear_const(current,rt1[i]);
1757   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1758   alloc_reg(current,i,FTEMP);
1759   // If using TLB, need a register for pointer to the mapping table
1760   if(using_tlb) alloc_reg(current,i,TLREG);
1761   #if defined(HOST_IMM8)
1762   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1763   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1764     alloc_reg(current,i,INVCP);
1765   #endif
1766   // We need a temporary register for address generation
1767   alloc_reg_temp(current,i,-1);
1768   minimum_free_regs[i]=1;
1769 }
1770
1771 #ifndef multdiv_alloc
1772 void multdiv_alloc(struct regstat *current,int i)
1773 {
1774   //  case 0x18: MULT
1775   //  case 0x19: MULTU
1776   //  case 0x1A: DIV
1777   //  case 0x1B: DIVU
1778   //  case 0x1C: DMULT
1779   //  case 0x1D: DMULTU
1780   //  case 0x1E: DDIV
1781   //  case 0x1F: DDIVU
1782   clear_const(current,rs1[i]);
1783   clear_const(current,rs2[i]);
1784   if(rs1[i]&&rs2[i])
1785   {
1786     if((opcode2[i]&4)==0) // 32-bit
1787     {
1788       current->u&=~(1LL<<HIREG);
1789       current->u&=~(1LL<<LOREG);
1790       alloc_reg(current,i,HIREG);
1791       alloc_reg(current,i,LOREG);
1792       alloc_reg(current,i,rs1[i]);
1793       alloc_reg(current,i,rs2[i]);
1794       current->is32|=1LL<<HIREG;
1795       current->is32|=1LL<<LOREG;
1796       dirty_reg(current,HIREG);
1797       dirty_reg(current,LOREG);
1798     }
1799     else // 64-bit
1800     {
1801       current->u&=~(1LL<<HIREG);
1802       current->u&=~(1LL<<LOREG);
1803       current->uu&=~(1LL<<HIREG);
1804       current->uu&=~(1LL<<LOREG);
1805       alloc_reg64(current,i,HIREG);
1806       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1807       alloc_reg64(current,i,rs1[i]);
1808       alloc_reg64(current,i,rs2[i]);
1809       alloc_all(current,i);
1810       current->is32&=~(1LL<<HIREG);
1811       current->is32&=~(1LL<<LOREG);
1812       dirty_reg(current,HIREG);
1813       dirty_reg(current,LOREG);
1814       minimum_free_regs[i]=HOST_REGS;
1815     }
1816   }
1817   else
1818   {
1819     // Multiply by zero is zero.
1820     // MIPS does not have a divide by zero exception.
1821     // The result is undefined, we return zero.
1822     alloc_reg(current,i,HIREG);
1823     alloc_reg(current,i,LOREG);
1824     current->is32|=1LL<<HIREG;
1825     current->is32|=1LL<<LOREG;
1826     dirty_reg(current,HIREG);
1827     dirty_reg(current,LOREG);
1828   }
1829 }
1830 #endif
1831
1832 void cop0_alloc(struct regstat *current,int i)
1833 {
1834   if(opcode2[i]==0) // MFC0
1835   {
1836     if(rt1[i]) {
1837       clear_const(current,rt1[i]);
1838       alloc_all(current,i);
1839       alloc_reg(current,i,rt1[i]);
1840       current->is32|=1LL<<rt1[i];
1841       dirty_reg(current,rt1[i]);
1842     }
1843   }
1844   else if(opcode2[i]==4) // MTC0
1845   {
1846     if(rs1[i]){
1847       clear_const(current,rs1[i]);
1848       alloc_reg(current,i,rs1[i]);
1849       alloc_all(current,i);
1850     }
1851     else {
1852       alloc_all(current,i); // FIXME: Keep r0
1853       current->u&=~1LL;
1854       alloc_reg(current,i,0);
1855     }
1856   }
1857   else
1858   {
1859     // TLBR/TLBWI/TLBWR/TLBP/ERET
1860     assert(opcode2[i]==0x10);
1861     alloc_all(current,i);
1862   }
1863   minimum_free_regs[i]=HOST_REGS;
1864 }
1865
1866 void cop1_alloc(struct regstat *current,int i)
1867 {
1868   alloc_reg(current,i,CSREG); // Load status
1869   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1870   {
1871     if(rt1[i]){
1872       clear_const(current,rt1[i]);
1873       if(opcode2[i]==1) {
1874         alloc_reg64(current,i,rt1[i]); // DMFC1
1875         current->is32&=~(1LL<<rt1[i]);
1876       }else{
1877         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1878         current->is32|=1LL<<rt1[i];
1879       }
1880       dirty_reg(current,rt1[i]);
1881     }
1882     alloc_reg_temp(current,i,-1);
1883   }
1884   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1885   {
1886     if(rs1[i]){
1887       clear_const(current,rs1[i]);
1888       if(opcode2[i]==5)
1889         alloc_reg64(current,i,rs1[i]); // DMTC1
1890       else
1891         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1892       alloc_reg_temp(current,i,-1);
1893     }
1894     else {
1895       current->u&=~1LL;
1896       alloc_reg(current,i,0);
1897       alloc_reg_temp(current,i,-1);
1898     }
1899   }
1900   minimum_free_regs[i]=1;
1901 }
1902 void fconv_alloc(struct regstat *current,int i)
1903 {
1904   alloc_reg(current,i,CSREG); // Load status
1905   alloc_reg_temp(current,i,-1);
1906   minimum_free_regs[i]=1;
1907 }
1908 void float_alloc(struct regstat *current,int i)
1909 {
1910   alloc_reg(current,i,CSREG); // Load status
1911   alloc_reg_temp(current,i,-1);
1912   minimum_free_regs[i]=1;
1913 }
1914 void c2op_alloc(struct regstat *current,int i)
1915 {
1916   alloc_reg_temp(current,i,-1);
1917 }
1918 void fcomp_alloc(struct regstat *current,int i)
1919 {
1920   alloc_reg(current,i,CSREG); // Load status
1921   alloc_reg(current,i,FSREG); // Load flags
1922   dirty_reg(current,FSREG); // Flag will be modified
1923   alloc_reg_temp(current,i,-1);
1924   minimum_free_regs[i]=1;
1925 }
1926
1927 void syscall_alloc(struct regstat *current,int i)
1928 {
1929   alloc_cc(current,i);
1930   dirty_reg(current,CCREG);
1931   alloc_all(current,i);
1932   minimum_free_regs[i]=HOST_REGS;
1933   current->isconst=0;
1934 }
1935
1936 void delayslot_alloc(struct regstat *current,int i)
1937 {
1938   switch(itype[i]) {
1939     case UJUMP:
1940     case CJUMP:
1941     case SJUMP:
1942     case RJUMP:
1943     case FJUMP:
1944     case SYSCALL:
1945     case HLECALL:
1946     case SPAN:
1947       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1948       printf("Disabled speculative precompilation\n");
1949       stop_after_jal=1;
1950       break;
1951     case IMM16:
1952       imm16_alloc(current,i);
1953       break;
1954     case LOAD:
1955     case LOADLR:
1956       load_alloc(current,i);
1957       break;
1958     case STORE:
1959     case STORELR:
1960       store_alloc(current,i);
1961       break;
1962     case ALU:
1963       alu_alloc(current,i);
1964       break;
1965     case SHIFT:
1966       shift_alloc(current,i);
1967       break;
1968     case MULTDIV:
1969       multdiv_alloc(current,i);
1970       break;
1971     case SHIFTIMM:
1972       shiftimm_alloc(current,i);
1973       break;
1974     case MOV:
1975       mov_alloc(current,i);
1976       break;
1977     case COP0:
1978       cop0_alloc(current,i);
1979       break;
1980     case COP1:
1981     case COP2:
1982       cop1_alloc(current,i);
1983       break;
1984     case C1LS:
1985       c1ls_alloc(current,i);
1986       break;
1987     case C2LS:
1988       c2ls_alloc(current,i);
1989       break;
1990     case FCONV:
1991       fconv_alloc(current,i);
1992       break;
1993     case FLOAT:
1994       float_alloc(current,i);
1995       break;
1996     case FCOMP:
1997       fcomp_alloc(current,i);
1998       break;
1999     case C2OP:
2000       c2op_alloc(current,i);
2001       break;
2002   }
2003 }
2004
2005 // Special case where a branch and delay slot span two pages in virtual memory
2006 static void pagespan_alloc(struct regstat *current,int i)
2007 {
2008   current->isconst=0;
2009   current->wasconst=0;
2010   regs[i].wasconst=0;
2011   minimum_free_regs[i]=HOST_REGS;
2012   alloc_all(current,i);
2013   alloc_cc(current,i);
2014   dirty_reg(current,CCREG);
2015   if(opcode[i]==3) // JAL
2016   {
2017     alloc_reg(current,i,31);
2018     dirty_reg(current,31);
2019   }
2020   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2021   {
2022     alloc_reg(current,i,rs1[i]);
2023     if (rt1[i]!=0) {
2024       alloc_reg(current,i,rt1[i]);
2025       dirty_reg(current,rt1[i]);
2026     }
2027   }
2028   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2029   {
2030     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2031     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2032     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2033     {
2034       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2035       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2036     }
2037   }
2038   else
2039   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2040   {
2041     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2042     if(!((current->is32>>rs1[i])&1))
2043     {
2044       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2045     }
2046   }
2047   else
2048   if(opcode[i]==0x11) // BC1
2049   {
2050     alloc_reg(current,i,FSREG);
2051     alloc_reg(current,i,CSREG);
2052   }
2053   //else ...
2054 }
2055
2056 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2057 {
2058   stubs[stubcount][0]=type;
2059   stubs[stubcount][1]=addr;
2060   stubs[stubcount][2]=retaddr;
2061   stubs[stubcount][3]=a;
2062   stubs[stubcount][4]=b;
2063   stubs[stubcount][5]=c;
2064   stubs[stubcount][6]=d;
2065   stubs[stubcount][7]=e;
2066   stubcount++;
2067 }
2068
2069 // Write out a single register
2070 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2071 {
2072   int hr;
2073   for(hr=0;hr<HOST_REGS;hr++) {
2074     if(hr!=EXCLUDE_REG) {
2075       if((regmap[hr]&63)==r) {
2076         if((dirty>>hr)&1) {
2077           if(regmap[hr]<64) {
2078             emit_storereg(r,hr);
2079 #ifndef FORCE32
2080             if((is32>>regmap[hr])&1) {
2081               emit_sarimm(hr,31,hr);
2082               emit_storereg(r|64,hr);
2083             }
2084 #endif
2085           }else{
2086             emit_storereg(r|64,hr);
2087           }
2088         }
2089       }
2090     }
2091   }
2092 }
2093
2094 int mchecksum()
2095 {
2096   //if(!tracedebug) return 0;
2097   int i;
2098   int sum=0;
2099   for(i=0;i<2097152;i++) {
2100     unsigned int temp=sum;
2101     sum<<=1;
2102     sum|=(~temp)>>31;
2103     sum^=((u_int *)rdram)[i];
2104   }
2105   return sum;
2106 }
2107 int rchecksum()
2108 {
2109   int i;
2110   int sum=0;
2111   for(i=0;i<64;i++)
2112     sum^=((u_int *)reg)[i];
2113   return sum;
2114 }
2115 void rlist()
2116 {
2117   int i;
2118   printf("TRACE: ");
2119   for(i=0;i<32;i++)
2120     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2121   printf("\n");
2122 #ifndef DISABLE_COP1
2123   printf("TRACE: ");
2124   for(i=0;i<32;i++)
2125     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2126   printf("\n");
2127 #endif
2128 }
2129
2130 void enabletrace()
2131 {
2132   tracedebug=1;
2133 }
2134
2135 void memdebug(int i)
2136 {
2137   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2138   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2139   //rlist();
2140   //if(tracedebug) {
2141   //if(Count>=-2084597794) {
2142   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2143   //if(0) {
2144     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2145     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2146     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2147     rlist();
2148     #ifdef __i386__
2149     printf("TRACE: %x\n",(&i)[-1]);
2150     #endif
2151     #ifdef __arm__
2152     int j;
2153     printf("TRACE: %x \n",(&j)[10]);
2154     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2155     #endif
2156     //fflush(stdout);
2157   }
2158   //printf("TRACE: %x\n",(&i)[-1]);
2159 }
2160
2161 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2162 {
2163   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2164 }
2165
2166 void alu_assemble(int i,struct regstat *i_regs)
2167 {
2168   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2169     if(rt1[i]) {
2170       signed char s1,s2,t;
2171       t=get_reg(i_regs->regmap,rt1[i]);
2172       if(t>=0) {
2173         s1=get_reg(i_regs->regmap,rs1[i]);
2174         s2=get_reg(i_regs->regmap,rs2[i]);
2175         if(rs1[i]&&rs2[i]) {
2176           assert(s1>=0);
2177           assert(s2>=0);
2178           if(opcode2[i]&2) emit_sub(s1,s2,t);
2179           else emit_add(s1,s2,t);
2180         }
2181         else if(rs1[i]) {
2182           if(s1>=0) emit_mov(s1,t);
2183           else emit_loadreg(rs1[i],t);
2184         }
2185         else if(rs2[i]) {
2186           if(s2>=0) {
2187             if(opcode2[i]&2) emit_neg(s2,t);
2188             else emit_mov(s2,t);
2189           }
2190           else {
2191             emit_loadreg(rs2[i],t);
2192             if(opcode2[i]&2) emit_neg(t,t);
2193           }
2194         }
2195         else emit_zeroreg(t);
2196       }
2197     }
2198   }
2199   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2200     if(rt1[i]) {
2201       signed char s1l,s2l,s1h,s2h,tl,th;
2202       tl=get_reg(i_regs->regmap,rt1[i]);
2203       th=get_reg(i_regs->regmap,rt1[i]|64);
2204       if(tl>=0) {
2205         s1l=get_reg(i_regs->regmap,rs1[i]);
2206         s2l=get_reg(i_regs->regmap,rs2[i]);
2207         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2208         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2209         if(rs1[i]&&rs2[i]) {
2210           assert(s1l>=0);
2211           assert(s2l>=0);
2212           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2213           else emit_adds(s1l,s2l,tl);
2214           if(th>=0) {
2215             #ifdef INVERTED_CARRY
2216             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2217             #else
2218             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2219             #endif
2220             else emit_add(s1h,s2h,th);
2221           }
2222         }
2223         else if(rs1[i]) {
2224           if(s1l>=0) emit_mov(s1l,tl);
2225           else emit_loadreg(rs1[i],tl);
2226           if(th>=0) {
2227             if(s1h>=0) emit_mov(s1h,th);
2228             else emit_loadreg(rs1[i]|64,th);
2229           }
2230         }
2231         else if(rs2[i]) {
2232           if(s2l>=0) {
2233             if(opcode2[i]&2) emit_negs(s2l,tl);
2234             else emit_mov(s2l,tl);
2235           }
2236           else {
2237             emit_loadreg(rs2[i],tl);
2238             if(opcode2[i]&2) emit_negs(tl,tl);
2239           }
2240           if(th>=0) {
2241             #ifdef INVERTED_CARRY
2242             if(s2h>=0) emit_mov(s2h,th);
2243             else emit_loadreg(rs2[i]|64,th);
2244             if(opcode2[i]&2) {
2245               emit_adcimm(-1,th); // x86 has inverted carry flag
2246               emit_not(th,th);
2247             }
2248             #else
2249             if(opcode2[i]&2) {
2250               if(s2h>=0) emit_rscimm(s2h,0,th);
2251               else {
2252                 emit_loadreg(rs2[i]|64,th);
2253                 emit_rscimm(th,0,th);
2254               }
2255             }else{
2256               if(s2h>=0) emit_mov(s2h,th);
2257               else emit_loadreg(rs2[i]|64,th);
2258             }
2259             #endif
2260           }
2261         }
2262         else {
2263           emit_zeroreg(tl);
2264           if(th>=0) emit_zeroreg(th);
2265         }
2266       }
2267     }
2268   }
2269   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2270     if(rt1[i]) {
2271       signed char s1l,s1h,s2l,s2h,t;
2272       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2273       {
2274         t=get_reg(i_regs->regmap,rt1[i]);
2275         //assert(t>=0);
2276         if(t>=0) {
2277           s1l=get_reg(i_regs->regmap,rs1[i]);
2278           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2279           s2l=get_reg(i_regs->regmap,rs2[i]);
2280           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2281           if(rs2[i]==0) // rx<r0
2282           {
2283             assert(s1h>=0);
2284             if(opcode2[i]==0x2a) // SLT
2285               emit_shrimm(s1h,31,t);
2286             else // SLTU (unsigned can not be less than zero)
2287               emit_zeroreg(t);
2288           }
2289           else if(rs1[i]==0) // r0<rx
2290           {
2291             assert(s2h>=0);
2292             if(opcode2[i]==0x2a) // SLT
2293               emit_set_gz64_32(s2h,s2l,t);
2294             else // SLTU (set if not zero)
2295               emit_set_nz64_32(s2h,s2l,t);
2296           }
2297           else {
2298             assert(s1l>=0);assert(s1h>=0);
2299             assert(s2l>=0);assert(s2h>=0);
2300             if(opcode2[i]==0x2a) // SLT
2301               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2302             else // SLTU
2303               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2304           }
2305         }
2306       } else {
2307         t=get_reg(i_regs->regmap,rt1[i]);
2308         //assert(t>=0);
2309         if(t>=0) {
2310           s1l=get_reg(i_regs->regmap,rs1[i]);
2311           s2l=get_reg(i_regs->regmap,rs2[i]);
2312           if(rs2[i]==0) // rx<r0
2313           {
2314             assert(s1l>=0);
2315             if(opcode2[i]==0x2a) // SLT
2316               emit_shrimm(s1l,31,t);
2317             else // SLTU (unsigned can not be less than zero)
2318               emit_zeroreg(t);
2319           }
2320           else if(rs1[i]==0) // r0<rx
2321           {
2322             assert(s2l>=0);
2323             if(opcode2[i]==0x2a) // SLT
2324               emit_set_gz32(s2l,t);
2325             else // SLTU (set if not zero)
2326               emit_set_nz32(s2l,t);
2327           }
2328           else{
2329             assert(s1l>=0);assert(s2l>=0);
2330             if(opcode2[i]==0x2a) // SLT
2331               emit_set_if_less32(s1l,s2l,t);
2332             else // SLTU
2333               emit_set_if_carry32(s1l,s2l,t);
2334           }
2335         }
2336       }
2337     }
2338   }
2339   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2340     if(rt1[i]) {
2341       signed char s1l,s1h,s2l,s2h,th,tl;
2342       tl=get_reg(i_regs->regmap,rt1[i]);
2343       th=get_reg(i_regs->regmap,rt1[i]|64);
2344       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2345       {
2346         assert(tl>=0);
2347         if(tl>=0) {
2348           s1l=get_reg(i_regs->regmap,rs1[i]);
2349           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2350           s2l=get_reg(i_regs->regmap,rs2[i]);
2351           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2352           if(rs1[i]&&rs2[i]) {
2353             assert(s1l>=0);assert(s1h>=0);
2354             assert(s2l>=0);assert(s2h>=0);
2355             if(opcode2[i]==0x24) { // AND
2356               emit_and(s1l,s2l,tl);
2357               emit_and(s1h,s2h,th);
2358             } else
2359             if(opcode2[i]==0x25) { // OR
2360               emit_or(s1l,s2l,tl);
2361               emit_or(s1h,s2h,th);
2362             } else
2363             if(opcode2[i]==0x26) { // XOR
2364               emit_xor(s1l,s2l,tl);
2365               emit_xor(s1h,s2h,th);
2366             } else
2367             if(opcode2[i]==0x27) { // NOR
2368               emit_or(s1l,s2l,tl);
2369               emit_or(s1h,s2h,th);
2370               emit_not(tl,tl);
2371               emit_not(th,th);
2372             }
2373           }
2374           else
2375           {
2376             if(opcode2[i]==0x24) { // AND
2377               emit_zeroreg(tl);
2378               emit_zeroreg(th);
2379             } else
2380             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2381               if(rs1[i]){
2382                 if(s1l>=0) emit_mov(s1l,tl);
2383                 else emit_loadreg(rs1[i],tl);
2384                 if(s1h>=0) emit_mov(s1h,th);
2385                 else emit_loadreg(rs1[i]|64,th);
2386               }
2387               else
2388               if(rs2[i]){
2389                 if(s2l>=0) emit_mov(s2l,tl);
2390                 else emit_loadreg(rs2[i],tl);
2391                 if(s2h>=0) emit_mov(s2h,th);
2392                 else emit_loadreg(rs2[i]|64,th);
2393               }
2394               else{
2395                 emit_zeroreg(tl);
2396                 emit_zeroreg(th);
2397               }
2398             } else
2399             if(opcode2[i]==0x27) { // NOR
2400               if(rs1[i]){
2401                 if(s1l>=0) emit_not(s1l,tl);
2402                 else{
2403                   emit_loadreg(rs1[i],tl);
2404                   emit_not(tl,tl);
2405                 }
2406                 if(s1h>=0) emit_not(s1h,th);
2407                 else{
2408                   emit_loadreg(rs1[i]|64,th);
2409                   emit_not(th,th);
2410                 }
2411               }
2412               else
2413               if(rs2[i]){
2414                 if(s2l>=0) emit_not(s2l,tl);
2415                 else{
2416                   emit_loadreg(rs2[i],tl);
2417                   emit_not(tl,tl);
2418                 }
2419                 if(s2h>=0) emit_not(s2h,th);
2420                 else{
2421                   emit_loadreg(rs2[i]|64,th);
2422                   emit_not(th,th);
2423                 }
2424               }
2425               else {
2426                 emit_movimm(-1,tl);
2427                 emit_movimm(-1,th);
2428               }
2429             }
2430           }
2431         }
2432       }
2433       else
2434       {
2435         // 32 bit
2436         if(tl>=0) {
2437           s1l=get_reg(i_regs->regmap,rs1[i]);
2438           s2l=get_reg(i_regs->regmap,rs2[i]);
2439           if(rs1[i]&&rs2[i]) {
2440             assert(s1l>=0);
2441             assert(s2l>=0);
2442             if(opcode2[i]==0x24) { // AND
2443               emit_and(s1l,s2l,tl);
2444             } else
2445             if(opcode2[i]==0x25) { // OR
2446               emit_or(s1l,s2l,tl);
2447             } else
2448             if(opcode2[i]==0x26) { // XOR
2449               emit_xor(s1l,s2l,tl);
2450             } else
2451             if(opcode2[i]==0x27) { // NOR
2452               emit_or(s1l,s2l,tl);
2453               emit_not(tl,tl);
2454             }
2455           }
2456           else
2457           {
2458             if(opcode2[i]==0x24) { // AND
2459               emit_zeroreg(tl);
2460             } else
2461             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2462               if(rs1[i]){
2463                 if(s1l>=0) emit_mov(s1l,tl);
2464                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2465               }
2466               else
2467               if(rs2[i]){
2468                 if(s2l>=0) emit_mov(s2l,tl);
2469                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2470               }
2471               else emit_zeroreg(tl);
2472             } else
2473             if(opcode2[i]==0x27) { // NOR
2474               if(rs1[i]){
2475                 if(s1l>=0) emit_not(s1l,tl);
2476                 else {
2477                   emit_loadreg(rs1[i],tl);
2478                   emit_not(tl,tl);
2479                 }
2480               }
2481               else
2482               if(rs2[i]){
2483                 if(s2l>=0) emit_not(s2l,tl);
2484                 else {
2485                   emit_loadreg(rs2[i],tl);
2486                   emit_not(tl,tl);
2487                 }
2488               }
2489               else emit_movimm(-1,tl);
2490             }
2491           }
2492         }
2493       }
2494     }
2495   }
2496 }
2497
2498 void imm16_assemble(int i,struct regstat *i_regs)
2499 {
2500   if (opcode[i]==0x0f) { // LUI
2501     if(rt1[i]) {
2502       signed char t;
2503       t=get_reg(i_regs->regmap,rt1[i]);
2504       //assert(t>=0);
2505       if(t>=0) {
2506         if(!((i_regs->isconst>>t)&1))
2507           emit_movimm(imm[i]<<16,t);
2508       }
2509     }
2510   }
2511   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2512     if(rt1[i]) {
2513       signed char s,t;
2514       t=get_reg(i_regs->regmap,rt1[i]);
2515       s=get_reg(i_regs->regmap,rs1[i]);
2516       if(rs1[i]) {
2517         //assert(t>=0);
2518         //assert(s>=0);
2519         if(t>=0) {
2520           if(!((i_regs->isconst>>t)&1)) {
2521             if(s<0) {
2522               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523               emit_addimm(t,imm[i],t);
2524             }else{
2525               if(!((i_regs->wasconst>>s)&1))
2526                 emit_addimm(s,imm[i],t);
2527               else
2528                 emit_movimm(constmap[i][s]+imm[i],t);
2529             }
2530           }
2531         }
2532       } else {
2533         if(t>=0) {
2534           if(!((i_regs->isconst>>t)&1))
2535             emit_movimm(imm[i],t);
2536         }
2537       }
2538     }
2539   }
2540   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2541     if(rt1[i]) {
2542       signed char sh,sl,th,tl;
2543       th=get_reg(i_regs->regmap,rt1[i]|64);
2544       tl=get_reg(i_regs->regmap,rt1[i]);
2545       sh=get_reg(i_regs->regmap,rs1[i]|64);
2546       sl=get_reg(i_regs->regmap,rs1[i]);
2547       if(tl>=0) {
2548         if(rs1[i]) {
2549           assert(sh>=0);
2550           assert(sl>=0);
2551           if(th>=0) {
2552             emit_addimm64_32(sh,sl,imm[i],th,tl);
2553           }
2554           else {
2555             emit_addimm(sl,imm[i],tl);
2556           }
2557         } else {
2558           emit_movimm(imm[i],tl);
2559           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2560         }
2561       }
2562     }
2563   }
2564   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2565     if(rt1[i]) {
2566       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2567       signed char sh,sl,t;
2568       t=get_reg(i_regs->regmap,rt1[i]);
2569       sh=get_reg(i_regs->regmap,rs1[i]|64);
2570       sl=get_reg(i_regs->regmap,rs1[i]);
2571       //assert(t>=0);
2572       if(t>=0) {
2573         if(rs1[i]>0) {
2574           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2575           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2576             if(opcode[i]==0x0a) { // SLTI
2577               if(sl<0) {
2578                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2579                 emit_slti32(t,imm[i],t);
2580               }else{
2581                 emit_slti32(sl,imm[i],t);
2582               }
2583             }
2584             else { // SLTIU
2585               if(sl<0) {
2586                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2587                 emit_sltiu32(t,imm[i],t);
2588               }else{
2589                 emit_sltiu32(sl,imm[i],t);
2590               }
2591             }
2592           }else{ // 64-bit
2593             assert(sl>=0);
2594             if(opcode[i]==0x0a) // SLTI
2595               emit_slti64_32(sh,sl,imm[i],t);
2596             else // SLTIU
2597               emit_sltiu64_32(sh,sl,imm[i],t);
2598           }
2599         }else{
2600           // SLTI(U) with r0 is just stupid,
2601           // nonetheless examples can be found
2602           if(opcode[i]==0x0a) // SLTI
2603             if(0<imm[i]) emit_movimm(1,t);
2604             else emit_zeroreg(t);
2605           else // SLTIU
2606           {
2607             if(imm[i]) emit_movimm(1,t);
2608             else emit_zeroreg(t);
2609           }
2610         }
2611       }
2612     }
2613   }
2614   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2615     if(rt1[i]) {
2616       signed char sh,sl,th,tl;
2617       th=get_reg(i_regs->regmap,rt1[i]|64);
2618       tl=get_reg(i_regs->regmap,rt1[i]);
2619       sh=get_reg(i_regs->regmap,rs1[i]|64);
2620       sl=get_reg(i_regs->regmap,rs1[i]);
2621       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2622         if(opcode[i]==0x0c) //ANDI
2623         {
2624           if(rs1[i]) {
2625             if(sl<0) {
2626               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2627               emit_andimm(tl,imm[i],tl);
2628             }else{
2629               if(!((i_regs->wasconst>>sl)&1))
2630                 emit_andimm(sl,imm[i],tl);
2631               else
2632                 emit_movimm(constmap[i][sl]&imm[i],tl);
2633             }
2634           }
2635           else
2636             emit_zeroreg(tl);
2637           if(th>=0) emit_zeroreg(th);
2638         }
2639         else
2640         {
2641           if(rs1[i]) {
2642             if(sl<0) {
2643               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2644             }
2645             if(th>=0) {
2646               if(sh<0) {
2647                 emit_loadreg(rs1[i]|64,th);
2648               }else{
2649                 emit_mov(sh,th);
2650               }
2651             }
2652             if(opcode[i]==0x0d) //ORI
2653             if(sl<0) {
2654               emit_orimm(tl,imm[i],tl);
2655             }else{
2656               if(!((i_regs->wasconst>>sl)&1))
2657                 emit_orimm(sl,imm[i],tl);
2658               else
2659                 emit_movimm(constmap[i][sl]|imm[i],tl);
2660             }
2661             if(opcode[i]==0x0e) //XORI
2662             if(sl<0) {
2663               emit_xorimm(tl,imm[i],tl);
2664             }else{
2665               if(!((i_regs->wasconst>>sl)&1))
2666                 emit_xorimm(sl,imm[i],tl);
2667               else
2668                 emit_movimm(constmap[i][sl]^imm[i],tl);
2669             }
2670           }
2671           else {
2672             emit_movimm(imm[i],tl);
2673             if(th>=0) emit_zeroreg(th);
2674           }
2675         }
2676       }
2677     }
2678   }
2679 }
2680
2681 void shiftimm_assemble(int i,struct regstat *i_regs)
2682 {
2683   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2684   {
2685     if(rt1[i]) {
2686       signed char s,t;
2687       t=get_reg(i_regs->regmap,rt1[i]);
2688       s=get_reg(i_regs->regmap,rs1[i]);
2689       //assert(t>=0);
2690       if(t>=0){
2691         if(rs1[i]==0)
2692         {
2693           emit_zeroreg(t);
2694         }
2695         else
2696         {
2697           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2698           if(imm[i]) {
2699             if(opcode2[i]==0) // SLL
2700             {
2701               emit_shlimm(s<0?t:s,imm[i],t);
2702             }
2703             if(opcode2[i]==2) // SRL
2704             {
2705               emit_shrimm(s<0?t:s,imm[i],t);
2706             }
2707             if(opcode2[i]==3) // SRA
2708             {
2709               emit_sarimm(s<0?t:s,imm[i],t);
2710             }
2711           }else{
2712             // Shift by zero
2713             if(s>=0 && s!=t) emit_mov(s,t);
2714           }
2715         }
2716       }
2717       //emit_storereg(rt1[i],t); //DEBUG
2718     }
2719   }
2720   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2721   {
2722     if(rt1[i]) {
2723       signed char sh,sl,th,tl;
2724       th=get_reg(i_regs->regmap,rt1[i]|64);
2725       tl=get_reg(i_regs->regmap,rt1[i]);
2726       sh=get_reg(i_regs->regmap,rs1[i]|64);
2727       sl=get_reg(i_regs->regmap,rs1[i]);
2728       if(tl>=0) {
2729         if(rs1[i]==0)
2730         {
2731           emit_zeroreg(tl);
2732           if(th>=0) emit_zeroreg(th);
2733         }
2734         else
2735         {
2736           assert(sl>=0);
2737           assert(sh>=0);
2738           if(imm[i]) {
2739             if(opcode2[i]==0x38) // DSLL
2740             {
2741               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2742               emit_shlimm(sl,imm[i],tl);
2743             }
2744             if(opcode2[i]==0x3a) // DSRL
2745             {
2746               emit_shrdimm(sl,sh,imm[i],tl);
2747               if(th>=0) emit_shrimm(sh,imm[i],th);
2748             }
2749             if(opcode2[i]==0x3b) // DSRA
2750             {
2751               emit_shrdimm(sl,sh,imm[i],tl);
2752               if(th>=0) emit_sarimm(sh,imm[i],th);
2753             }
2754           }else{
2755             // Shift by zero
2756             if(sl!=tl) emit_mov(sl,tl);
2757             if(th>=0&&sh!=th) emit_mov(sh,th);
2758           }
2759         }
2760       }
2761     }
2762   }
2763   if(opcode2[i]==0x3c) // DSLL32
2764   {
2765     if(rt1[i]) {
2766       signed char sl,tl,th;
2767       tl=get_reg(i_regs->regmap,rt1[i]);
2768       th=get_reg(i_regs->regmap,rt1[i]|64);
2769       sl=get_reg(i_regs->regmap,rs1[i]);
2770       if(th>=0||tl>=0){
2771         assert(tl>=0);
2772         assert(th>=0);
2773         assert(sl>=0);
2774         emit_mov(sl,th);
2775         emit_zeroreg(tl);
2776         if(imm[i]>32)
2777         {
2778           emit_shlimm(th,imm[i]&31,th);
2779         }
2780       }
2781     }
2782   }
2783   if(opcode2[i]==0x3e) // DSRL32
2784   {
2785     if(rt1[i]) {
2786       signed char sh,tl,th;
2787       tl=get_reg(i_regs->regmap,rt1[i]);
2788       th=get_reg(i_regs->regmap,rt1[i]|64);
2789       sh=get_reg(i_regs->regmap,rs1[i]|64);
2790       if(tl>=0){
2791         assert(sh>=0);
2792         emit_mov(sh,tl);
2793         if(th>=0) emit_zeroreg(th);
2794         if(imm[i]>32)
2795         {
2796           emit_shrimm(tl,imm[i]&31,tl);
2797         }
2798       }
2799     }
2800   }
2801   if(opcode2[i]==0x3f) // DSRA32
2802   {
2803     if(rt1[i]) {
2804       signed char sh,tl;
2805       tl=get_reg(i_regs->regmap,rt1[i]);
2806       sh=get_reg(i_regs->regmap,rs1[i]|64);
2807       if(tl>=0){
2808         assert(sh>=0);
2809         emit_mov(sh,tl);
2810         if(imm[i]>32)
2811         {
2812           emit_sarimm(tl,imm[i]&31,tl);
2813         }
2814       }
2815     }
2816   }
2817 }
2818
2819 #ifndef shift_assemble
2820 void shift_assemble(int i,struct regstat *i_regs)
2821 {
2822   printf("Need shift_assemble for this architecture.\n");
2823   exit(1);
2824 }
2825 #endif
2826
2827 void load_assemble(int i,struct regstat *i_regs)
2828 {
2829   int s,th,tl,addr,map=-1;
2830   int offset;
2831   int jaddr=0;
2832   int memtarget=0,c=0;
2833   int fastload_reg_override=0;
2834   u_int hr,reglist=0;
2835   th=get_reg(i_regs->regmap,rt1[i]|64);
2836   tl=get_reg(i_regs->regmap,rt1[i]);
2837   s=get_reg(i_regs->regmap,rs1[i]);
2838   offset=imm[i];
2839   for(hr=0;hr<HOST_REGS;hr++) {
2840     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2841   }
2842   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2843   if(s>=0) {
2844     c=(i_regs->wasconst>>s)&1;
2845     if (c) {
2846       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2847       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2848     }
2849   }
2850   //printf("load_assemble: c=%d\n",c);
2851   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2852   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2853 #ifdef PCSX
2854   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2855     ||rt1[i]==0) {
2856       // could be FIFO, must perform the read
2857       // ||dummy read
2858       assem_debug("(forced read)\n");
2859       tl=get_reg(i_regs->regmap,-1);
2860       assert(tl>=0);
2861   }
2862 #endif
2863   if(offset||s<0||c) addr=tl;
2864   else addr=s;
2865   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2866  if(tl>=0) {
2867   //printf("load_assemble: c=%d\n",c);
2868   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2869   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2870   reglist&=~(1<<tl);
2871   if(th>=0) reglist&=~(1<<th);
2872   if(!using_tlb) {
2873     if(!c) {
2874       #ifdef RAM_OFFSET
2875       map=get_reg(i_regs->regmap,ROREG);
2876       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2877       #endif
2878 //#define R29_HACK 1
2879       #ifdef R29_HACK
2880       // Strmnnrmn's speed hack
2881       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2882       #endif
2883       {
2884         #ifdef PCSX
2885         if(sp_in_mirror&&rs1[i]==29) {
2886           emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2887           emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2888           fastload_reg_override=HOST_TEMPREG;
2889         }
2890         else
2891         #endif
2892         emit_cmpimm(addr,RAM_SIZE);
2893         jaddr=(int)out;
2894         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2895         // Hint to branch predictor that the branch is unlikely to be taken
2896         if(rs1[i]>=28)
2897           emit_jno_unlikely(0);
2898         else
2899         #endif
2900         emit_jno(0);
2901       }
2902     }
2903   }else{ // using tlb
2904     int x=0;
2905     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2906     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2907     map=get_reg(i_regs->regmap,TLREG);
2908     assert(map>=0);
2909     reglist&=~(1<<map);
2910     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2911     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2912   }
2913   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2914   if (opcode[i]==0x20) { // LB
2915     if(!c||memtarget) {
2916       if(!dummy) {
2917         #ifdef HOST_IMM_ADDR32
2918         if(c)
2919           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2920         else
2921         #endif
2922         {
2923           //emit_xorimm(addr,3,tl);
2924           //gen_tlb_addr_r(tl,map);
2925           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2926           int x=0,a=tl;
2927 #ifdef BIG_ENDIAN_MIPS
2928           if(!c) emit_xorimm(addr,3,tl);
2929           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2930 #else
2931           if(!c) a=addr;
2932 #endif
2933           if(fastload_reg_override) a=fastload_reg_override;
2934
2935           emit_movsbl_indexed_tlb(x,a,map,tl);
2936         }
2937       }
2938       if(jaddr)
2939         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2940     }
2941     else
2942       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2943   }
2944   if (opcode[i]==0x21) { // LH
2945     if(!c||memtarget) {
2946       if(!dummy) {
2947         #ifdef HOST_IMM_ADDR32
2948         if(c)
2949           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2950         else
2951         #endif
2952         {
2953           int x=0,a=tl;
2954 #ifdef BIG_ENDIAN_MIPS
2955           if(!c) emit_xorimm(addr,2,tl);
2956           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2957 #else
2958           if(!c) a=addr;
2959 #endif
2960           if(fastload_reg_override) a=fastload_reg_override;
2961           //#ifdef
2962           //emit_movswl_indexed_tlb(x,tl,map,tl);
2963           //else
2964           if(map>=0) {
2965             gen_tlb_addr_r(a,map);
2966             emit_movswl_indexed(x,a,tl);
2967           }else{
2968             #ifdef RAM_OFFSET
2969             emit_movswl_indexed(x,a,tl);
2970             #else
2971             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2972             #endif
2973           }
2974         }
2975       }
2976       if(jaddr)
2977         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2978     }
2979     else
2980       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2981   }
2982   if (opcode[i]==0x23) { // LW
2983     if(!c||memtarget) {
2984       if(!dummy) {
2985         int a=addr;
2986         if(fastload_reg_override) a=fastload_reg_override;
2987         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2988         #ifdef HOST_IMM_ADDR32
2989         if(c)
2990           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2991         else
2992         #endif
2993         emit_readword_indexed_tlb(0,a,map,tl);
2994       }
2995       if(jaddr)
2996         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2997     }
2998     else
2999       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3000   }
3001   if (opcode[i]==0x24) { // LBU
3002     if(!c||memtarget) {
3003       if(!dummy) {
3004         #ifdef HOST_IMM_ADDR32
3005         if(c)
3006           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3007         else
3008         #endif
3009         {
3010           //emit_xorimm(addr,3,tl);
3011           //gen_tlb_addr_r(tl,map);
3012           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3013           int x=0,a=tl;
3014 #ifdef BIG_ENDIAN_MIPS
3015           if(!c) emit_xorimm(addr,3,tl);
3016           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3017 #else
3018           if(!c) a=addr;
3019 #endif
3020           if(fastload_reg_override) a=fastload_reg_override;
3021
3022           emit_movzbl_indexed_tlb(x,a,map,tl);
3023         }
3024       }
3025       if(jaddr)
3026         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3027     }
3028     else
3029       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3030   }
3031   if (opcode[i]==0x25) { // LHU
3032     if(!c||memtarget) {
3033       if(!dummy) {
3034         #ifdef HOST_IMM_ADDR32
3035         if(c)
3036           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3037         else
3038         #endif
3039         {
3040           int x=0,a=tl;
3041 #ifdef BIG_ENDIAN_MIPS
3042           if(!c) emit_xorimm(addr,2,tl);
3043           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3044 #else
3045           if(!c) a=addr;
3046 #endif
3047           if(fastload_reg_override) a=fastload_reg_override;
3048           //#ifdef
3049           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3050           //#else
3051           if(map>=0) {
3052             gen_tlb_addr_r(a,map);
3053             emit_movzwl_indexed(x,a,tl);
3054           }else{
3055             #ifdef RAM_OFFSET
3056             emit_movzwl_indexed(x,a,tl);
3057             #else
3058             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3059             #endif
3060           }
3061         }
3062       }
3063       if(jaddr)
3064         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3065     }
3066     else
3067       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3068   }
3069   if (opcode[i]==0x27) { // LWU
3070     assert(th>=0);
3071     if(!c||memtarget) {
3072       if(!dummy) {
3073         int a=addr;
3074         if(fastload_reg_override) a=fastload_reg_override;
3075         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3076         #ifdef HOST_IMM_ADDR32
3077         if(c)
3078           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3079         else
3080         #endif
3081         emit_readword_indexed_tlb(0,a,map,tl);
3082       }
3083       if(jaddr)
3084         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3085     }
3086     else {
3087       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3088     }
3089     emit_zeroreg(th);
3090   }
3091   if (opcode[i]==0x37) { // LD
3092     if(!c||memtarget) {
3093       if(!dummy) {
3094         int a=addr;
3095         if(fastload_reg_override) a=fastload_reg_override;
3096         //gen_tlb_addr_r(tl,map);
3097         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3098         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3099         #ifdef HOST_IMM_ADDR32
3100         if(c)
3101           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3102         else
3103         #endif
3104         emit_readdword_indexed_tlb(0,a,map,th,tl);
3105       }
3106       if(jaddr)
3107         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3108     }
3109     else
3110       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3111   }
3112  }
3113   //emit_storereg(rt1[i],tl); // DEBUG
3114   //if(opcode[i]==0x23)
3115   //if(opcode[i]==0x24)
3116   //if(opcode[i]==0x23||opcode[i]==0x24)
3117   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3118   {
3119     //emit_pusha();
3120     save_regs(0x100f);
3121         emit_readword((int)&last_count,ECX);
3122         #ifdef __i386__
3123         if(get_reg(i_regs->regmap,CCREG)<0)
3124           emit_loadreg(CCREG,HOST_CCREG);
3125         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3126         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3127         emit_writeword(HOST_CCREG,(int)&Count);
3128         #endif
3129         #ifdef __arm__
3130         if(get_reg(i_regs->regmap,CCREG)<0)
3131           emit_loadreg(CCREG,0);
3132         else
3133           emit_mov(HOST_CCREG,0);
3134         emit_add(0,ECX,0);
3135         emit_addimm(0,2*ccadj[i],0);
3136         emit_writeword(0,(int)&Count);
3137         #endif
3138     emit_call((int)memdebug);
3139     //emit_popa();
3140     restore_regs(0x100f);
3141   }/**/
3142 }
3143
3144 #ifndef loadlr_assemble
3145 void loadlr_assemble(int i,struct regstat *i_regs)
3146 {
3147   printf("Need loadlr_assemble for this architecture.\n");
3148   exit(1);
3149 }
3150 #endif
3151
3152 void store_assemble(int i,struct regstat *i_regs)
3153 {
3154   int s,th,tl,map=-1;
3155   int addr,temp;
3156   int offset;
3157   int jaddr=0,jaddr2,type;
3158   int memtarget=0,c=0;
3159   int agr=AGEN1+(i&1);
3160   int faststore_reg_override=0;
3161   u_int hr,reglist=0;
3162   th=get_reg(i_regs->regmap,rs2[i]|64);
3163   tl=get_reg(i_regs->regmap,rs2[i]);
3164   s=get_reg(i_regs->regmap,rs1[i]);
3165   temp=get_reg(i_regs->regmap,agr);
3166   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3167   offset=imm[i];
3168   if(s>=0) {
3169     c=(i_regs->wasconst>>s)&1;
3170     if(c) {
3171       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3172       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3173     }
3174   }
3175   assert(tl>=0);
3176   assert(temp>=0);
3177   for(hr=0;hr<HOST_REGS;hr++) {
3178     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3179   }
3180   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3181   if(offset||s<0||c) addr=temp;
3182   else addr=s;
3183   if(!using_tlb) {
3184     if(!c) {
3185       #ifdef PCSX
3186       if(sp_in_mirror&&rs1[i]==29) {
3187         emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3188         emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3189         faststore_reg_override=HOST_TEMPREG;
3190       }
3191       else
3192       #endif
3193       #ifdef R29_HACK
3194       // Strmnnrmn's speed hack
3195       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3196       #endif
3197       emit_cmpimm(addr,RAM_SIZE);
3198       #ifdef DESTRUCTIVE_SHIFT
3199       if(s==addr) emit_mov(s,temp);
3200       #endif
3201       #ifdef R29_HACK
3202       memtarget=1;
3203       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3204       #endif
3205       {
3206         jaddr=(int)out;
3207         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3208         // Hint to branch predictor that the branch is unlikely to be taken
3209         if(rs1[i]>=28)
3210           emit_jno_unlikely(0);
3211         else
3212         #endif
3213         emit_jno(0);
3214       }
3215     }
3216   }else{ // using tlb
3217     int x=0;
3218     if (opcode[i]==0x28) x=3; // SB
3219     if (opcode[i]==0x29) x=2; // SH
3220     map=get_reg(i_regs->regmap,TLREG);
3221     assert(map>=0);
3222     reglist&=~(1<<map);
3223     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3224     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3225   }
3226
3227   if (opcode[i]==0x28) { // SB
3228     if(!c||memtarget) {
3229       int x=0,a=temp;
3230 #ifdef BIG_ENDIAN_MIPS
3231       if(!c) emit_xorimm(addr,3,temp);
3232       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3233 #else
3234       if(!c) a=addr;
3235 #endif
3236       if(faststore_reg_override) a=faststore_reg_override;
3237       //gen_tlb_addr_w(temp,map);
3238       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3239       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3240     }
3241     type=STOREB_STUB;
3242   }
3243   if (opcode[i]==0x29) { // SH
3244     if(!c||memtarget) {
3245       int x=0,a=temp;
3246 #ifdef BIG_ENDIAN_MIPS
3247       if(!c) emit_xorimm(addr,2,temp);
3248       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3249 #else
3250       if(!c) a=addr;
3251 #endif
3252       if(faststore_reg_override) a=faststore_reg_override;
3253       //#ifdef
3254       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3255       //#else
3256       if(map>=0) {
3257         gen_tlb_addr_w(a,map);
3258         emit_writehword_indexed(tl,x,a);
3259       }else
3260         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3261     }
3262     type=STOREH_STUB;
3263   }
3264   if (opcode[i]==0x2B) { // SW
3265     if(!c||memtarget) {
3266       int a=addr;
3267       if(faststore_reg_override) a=faststore_reg_override;
3268       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3269       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3270     }
3271     type=STOREW_STUB;
3272   }
3273   if (opcode[i]==0x3F) { // SD
3274     if(!c||memtarget) {
3275       int a=addr;
3276       if(faststore_reg_override) a=faststore_reg_override;
3277       if(rs2[i]) {
3278         assert(th>=0);
3279         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3280         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3281         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3282       }else{
3283         // Store zero
3284         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3285         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3286         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3287       }
3288     }
3289     type=STORED_STUB;
3290   }
3291 #ifdef PCSX
3292   if(jaddr) {
3293     // PCSX store handlers don't check invcode again
3294     reglist|=1<<addr;
3295     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3296     jaddr=0;
3297   }
3298 #endif
3299   if(!using_tlb) {
3300     if(!c||memtarget) {
3301       #ifdef DESTRUCTIVE_SHIFT
3302       // The x86 shift operation is 'destructive'; it overwrites the
3303       // source register, so we need to make a copy first and use that.
3304       addr=temp;
3305       #endif
3306       #if defined(HOST_IMM8)
3307       int ir=get_reg(i_regs->regmap,INVCP);
3308       assert(ir>=0);
3309       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3310       #else
3311       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3312       #endif
3313       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3314       emit_callne(invalidate_addr_reg[addr]);
3315       #else
3316       jaddr2=(int)out;
3317       emit_jne(0);
3318       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3319       #endif
3320     }
3321   }
3322   if(jaddr) {
3323     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3324   } else if(c&&!memtarget) {
3325     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3326   }
3327   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3328   //if(opcode[i]==0x2B || opcode[i]==0x28)
3329   //if(opcode[i]==0x2B || opcode[i]==0x29)
3330   //if(opcode[i]==0x2B)
3331   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3332   {
3333     #ifdef __i386__
3334     emit_pusha();
3335     #endif
3336     #ifdef __arm__
3337     save_regs(0x100f);
3338     #endif
3339         emit_readword((int)&last_count,ECX);
3340         #ifdef __i386__
3341         if(get_reg(i_regs->regmap,CCREG)<0)
3342           emit_loadreg(CCREG,HOST_CCREG);
3343         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3344         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3345         emit_writeword(HOST_CCREG,(int)&Count);
3346         #endif
3347         #ifdef __arm__
3348         if(get_reg(i_regs->regmap,CCREG)<0)
3349           emit_loadreg(CCREG,0);
3350         else
3351           emit_mov(HOST_CCREG,0);
3352         emit_add(0,ECX,0);
3353         emit_addimm(0,2*ccadj[i],0);
3354         emit_writeword(0,(int)&Count);
3355         #endif
3356     emit_call((int)memdebug);
3357     #ifdef __i386__
3358     emit_popa();
3359     #endif
3360     #ifdef __arm__
3361     restore_regs(0x100f);
3362     #endif
3363   }/**/
3364 }
3365
3366 void storelr_assemble(int i,struct regstat *i_regs)
3367 {
3368   int s,th,tl;
3369   int temp;
3370   int temp2;
3371   int offset;
3372   int jaddr=0,jaddr2;
3373   int case1,case2,case3;
3374   int done0,done1,done2;
3375   int memtarget=0,c=0;
3376   int agr=AGEN1+(i&1);
3377   u_int hr,reglist=0;
3378   th=get_reg(i_regs->regmap,rs2[i]|64);
3379   tl=get_reg(i_regs->regmap,rs2[i]);
3380   s=get_reg(i_regs->regmap,rs1[i]);
3381   temp=get_reg(i_regs->regmap,agr);
3382   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3383   offset=imm[i];
3384   if(s>=0) {
3385     c=(i_regs->isconst>>s)&1;
3386     if(c) {
3387       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3388       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3389     }
3390   }
3391   assert(tl>=0);
3392   for(hr=0;hr<HOST_REGS;hr++) {
3393     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3394   }
3395   assert(temp>=0);
3396   if(!using_tlb) {
3397     if(!c) {
3398       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3399       if(!offset&&s!=temp) emit_mov(s,temp);
3400       jaddr=(int)out;
3401       emit_jno(0);
3402     }
3403     else
3404     {
3405       if(!memtarget||!rs1[i]) {
3406         jaddr=(int)out;
3407         emit_jmp(0);
3408       }
3409     }
3410     #ifdef RAM_OFFSET
3411     int map=get_reg(i_regs->regmap,ROREG);
3412     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3413     gen_tlb_addr_w(temp,map);
3414     #else
3415     if((u_int)rdram!=0x80000000)
3416       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3417     #endif
3418   }else{ // using tlb
3419     int map=get_reg(i_regs->regmap,TLREG);
3420     assert(map>=0);
3421     reglist&=~(1<<map);
3422     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3423     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3424     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3425     if(!jaddr&&!memtarget) {
3426       jaddr=(int)out;
3427       emit_jmp(0);
3428     }
3429     gen_tlb_addr_w(temp,map);
3430   }
3431
3432   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3433     temp2=get_reg(i_regs->regmap,FTEMP);
3434     if(!rs2[i]) temp2=th=tl;
3435   }
3436
3437 #ifndef BIG_ENDIAN_MIPS
3438     emit_xorimm(temp,3,temp);
3439 #endif
3440   emit_testimm(temp,2);
3441   case2=(int)out;
3442   emit_jne(0);
3443   emit_testimm(temp,1);
3444   case1=(int)out;
3445   emit_jne(0);
3446   // 0
3447   if (opcode[i]==0x2A) { // SWL
3448     emit_writeword_indexed(tl,0,temp);
3449   }
3450   if (opcode[i]==0x2E) { // SWR
3451     emit_writebyte_indexed(tl,3,temp);
3452   }
3453   if (opcode[i]==0x2C) { // SDL
3454     emit_writeword_indexed(th,0,temp);
3455     if(rs2[i]) emit_mov(tl,temp2);
3456   }
3457   if (opcode[i]==0x2D) { // SDR
3458     emit_writebyte_indexed(tl,3,temp);
3459     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3460   }
3461   done0=(int)out;
3462   emit_jmp(0);
3463   // 1
3464   set_jump_target(case1,(int)out);
3465   if (opcode[i]==0x2A) { // SWL
3466     // Write 3 msb into three least significant bytes
3467     if(rs2[i]) emit_rorimm(tl,8,tl);
3468     emit_writehword_indexed(tl,-1,temp);
3469     if(rs2[i]) emit_rorimm(tl,16,tl);
3470     emit_writebyte_indexed(tl,1,temp);
3471     if(rs2[i]) emit_rorimm(tl,8,tl);
3472   }
3473   if (opcode[i]==0x2E) { // SWR
3474     // Write two lsb into two most significant bytes
3475     emit_writehword_indexed(tl,1,temp);
3476   }
3477   if (opcode[i]==0x2C) { // SDL
3478     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3479     // Write 3 msb into three least significant bytes
3480     if(rs2[i]) emit_rorimm(th,8,th);
3481     emit_writehword_indexed(th,-1,temp);
3482     if(rs2[i]) emit_rorimm(th,16,th);
3483     emit_writebyte_indexed(th,1,temp);
3484     if(rs2[i]) emit_rorimm(th,8,th);
3485   }
3486   if (opcode[i]==0x2D) { // SDR
3487     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3488     // Write two lsb into two most significant bytes
3489     emit_writehword_indexed(tl,1,temp);
3490   }
3491   done1=(int)out;
3492   emit_jmp(0);
3493   // 2
3494   set_jump_target(case2,(int)out);
3495   emit_testimm(temp,1);
3496   case3=(int)out;
3497   emit_jne(0);
3498   if (opcode[i]==0x2A) { // SWL
3499     // Write two msb into two least significant bytes
3500     if(rs2[i]) emit_rorimm(tl,16,tl);
3501     emit_writehword_indexed(tl,-2,temp);
3502     if(rs2[i]) emit_rorimm(tl,16,tl);
3503   }
3504   if (opcode[i]==0x2E) { // SWR
3505     // Write 3 lsb into three most significant bytes
3506     emit_writebyte_indexed(tl,-1,temp);
3507     if(rs2[i]) emit_rorimm(tl,8,tl);
3508     emit_writehword_indexed(tl,0,temp);
3509     if(rs2[i]) emit_rorimm(tl,24,tl);
3510   }
3511   if (opcode[i]==0x2C) { // SDL
3512     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3513     // Write two msb into two least significant bytes
3514     if(rs2[i]) emit_rorimm(th,16,th);
3515     emit_writehword_indexed(th,-2,temp);
3516     if(rs2[i]) emit_rorimm(th,16,th);
3517   }
3518   if (opcode[i]==0x2D) { // SDR
3519     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3520     // Write 3 lsb into three most significant bytes
3521     emit_writebyte_indexed(tl,-1,temp);
3522     if(rs2[i]) emit_rorimm(tl,8,tl);
3523     emit_writehword_indexed(tl,0,temp);
3524     if(rs2[i]) emit_rorimm(tl,24,tl);
3525   }
3526   done2=(int)out;
3527   emit_jmp(0);
3528   // 3
3529   set_jump_target(case3,(int)out);
3530   if (opcode[i]==0x2A) { // SWL
3531     // Write msb into least significant byte
3532     if(rs2[i]) emit_rorimm(tl,24,tl);
3533     emit_writebyte_indexed(tl,-3,temp);
3534     if(rs2[i]) emit_rorimm(tl,8,tl);
3535   }
3536   if (opcode[i]==0x2E) { // SWR
3537     // Write entire word
3538     emit_writeword_indexed(tl,-3,temp);
3539   }
3540   if (opcode[i]==0x2C) { // SDL
3541     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3542     // Write msb into least significant byte
3543     if(rs2[i]) emit_rorimm(th,24,th);
3544     emit_writebyte_indexed(th,-3,temp);
3545     if(rs2[i]) emit_rorimm(th,8,th);
3546   }
3547   if (opcode[i]==0x2D) { // SDR
3548     if(rs2[i]) emit_mov(th,temp2);
3549     // Write entire word
3550     emit_writeword_indexed(tl,-3,temp);
3551   }
3552   set_jump_target(done0,(int)out);
3553   set_jump_target(done1,(int)out);
3554   set_jump_target(done2,(int)out);
3555   if (opcode[i]==0x2C) { // SDL
3556     emit_testimm(temp,4);
3557     done0=(int)out;
3558     emit_jne(0);
3559     emit_andimm(temp,~3,temp);
3560     emit_writeword_indexed(temp2,4,temp);
3561     set_jump_target(done0,(int)out);
3562   }
3563   if (opcode[i]==0x2D) { // SDR
3564     emit_testimm(temp,4);
3565     done0=(int)out;
3566     emit_jeq(0);
3567     emit_andimm(temp,~3,temp);
3568     emit_writeword_indexed(temp2,-4,temp);
3569     set_jump_target(done0,(int)out);
3570   }
3571   if(!c||!memtarget)
3572     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3573   if(!using_tlb) {
3574     #ifdef RAM_OFFSET
3575     int map=get_reg(i_regs->regmap,ROREG);
3576     if(map<0) map=HOST_TEMPREG;
3577     gen_orig_addr_w(temp,map);
3578     #else
3579     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3580     #endif
3581     #if defined(HOST_IMM8)
3582     int ir=get_reg(i_regs->regmap,INVCP);
3583     assert(ir>=0);
3584     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3585     #else
3586     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3587     #endif
3588     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3589     emit_callne(invalidate_addr_reg[temp]);
3590     #else
3591     jaddr2=(int)out;
3592     emit_jne(0);
3593     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3594     #endif
3595   }
3596   /*
3597     emit_pusha();
3598     //save_regs(0x100f);
3599         emit_readword((int)&last_count,ECX);
3600         if(get_reg(i_regs->regmap,CCREG)<0)
3601           emit_loadreg(CCREG,HOST_CCREG);
3602         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3603         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3604         emit_writeword(HOST_CCREG,(int)&Count);
3605     emit_call((int)memdebug);
3606     emit_popa();
3607     //restore_regs(0x100f);
3608   /**/
3609 }
3610
3611 void c1ls_assemble(int i,struct regstat *i_regs)
3612 {
3613 #ifndef DISABLE_COP1
3614   int s,th,tl;
3615   int temp,ar;
3616   int map=-1;
3617   int offset;
3618   int c=0;
3619   int jaddr,jaddr2=0,jaddr3,type;
3620   int agr=AGEN1+(i&1);
3621   u_int hr,reglist=0;
3622   th=get_reg(i_regs->regmap,FTEMP|64);
3623   tl=get_reg(i_regs->regmap,FTEMP);
3624   s=get_reg(i_regs->regmap,rs1[i]);
3625   temp=get_reg(i_regs->regmap,agr);
3626   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3627   offset=imm[i];
3628   assert(tl>=0);
3629   assert(rs1[i]>0);
3630   assert(temp>=0);
3631   for(hr=0;hr<HOST_REGS;hr++) {
3632     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3633   }
3634   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3635   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3636   {
3637     // Loads use a temporary register which we need to save
3638     reglist|=1<<temp;
3639   }
3640   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3641     ar=temp;
3642   else // LWC1/LDC1
3643     ar=tl;
3644   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3645   //else c=(i_regs->wasconst>>s)&1;
3646   if(s>=0) c=(i_regs->wasconst>>s)&1;
3647   // Check cop1 unusable
3648   if(!cop1_usable) {
3649     signed char rs=get_reg(i_regs->regmap,CSREG);
3650     assert(rs>=0);
3651     emit_testimm(rs,0x20000000);
3652     jaddr=(int)out;
3653     emit_jeq(0);
3654     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3655     cop1_usable=1;
3656   }
3657   if (opcode[i]==0x39) { // SWC1 (get float address)
3658     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3659   }
3660   if (opcode[i]==0x3D) { // SDC1 (get double address)
3661     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3662   }
3663   // Generate address + offset
3664   if(!using_tlb) {
3665     if(!c)
3666       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3667   }
3668   else
3669   {
3670     map=get_reg(i_regs->regmap,TLREG);
3671     assert(map>=0);
3672     reglist&=~(1<<map);
3673     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3674       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3675     }
3676     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3677       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3678     }
3679   }
3680   if (opcode[i]==0x39) { // SWC1 (read float)
3681     emit_readword_indexed(0,tl,tl);
3682   }
3683   if (opcode[i]==0x3D) { // SDC1 (read double)
3684     emit_readword_indexed(4,tl,th);
3685     emit_readword_indexed(0,tl,tl);
3686   }
3687   if (opcode[i]==0x31) { // LWC1 (get target address)
3688     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3689   }
3690   if (opcode[i]==0x35) { // LDC1 (get target address)
3691     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3692   }
3693   if(!using_tlb) {
3694     if(!c) {
3695       jaddr2=(int)out;
3696       emit_jno(0);
3697     }
3698     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3699       jaddr2=(int)out;
3700       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3701     }
3702     #ifdef DESTRUCTIVE_SHIFT
3703     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3704       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3705     }
3706     #endif
3707   }else{
3708     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3709       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3710     }
3711     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3712       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3713     }
3714   }
3715   if (opcode[i]==0x31) { // LWC1
3716     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3717     //gen_tlb_addr_r(ar,map);
3718     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3719     #ifdef HOST_IMM_ADDR32
3720     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3721     else
3722     #endif
3723     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3724     type=LOADW_STUB;
3725   }
3726   if (opcode[i]==0x35) { // LDC1
3727     assert(th>=0);
3728     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3729     //gen_tlb_addr_r(ar,map);
3730     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3731     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3732     #ifdef HOST_IMM_ADDR32
3733     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3734     else
3735     #endif
3736     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3737     type=LOADD_STUB;
3738   }
3739   if (opcode[i]==0x39) { // SWC1
3740     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3741     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3742     type=STOREW_STUB;
3743   }
3744   if (opcode[i]==0x3D) { // SDC1
3745     assert(th>=0);
3746     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3747     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3748     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3749     type=STORED_STUB;
3750   }
3751   if(!using_tlb) {
3752     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3753       #ifndef DESTRUCTIVE_SHIFT
3754       temp=offset||c||s<0?ar:s;
3755       #endif
3756       #if defined(HOST_IMM8)
3757       int ir=get_reg(i_regs->regmap,INVCP);
3758       assert(ir>=0);
3759       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3760       #else
3761       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3762       #endif
3763       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3764       emit_callne(invalidate_addr_reg[temp]);
3765       #else
3766       jaddr3=(int)out;
3767       emit_jne(0);
3768       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3769       #endif
3770     }
3771   }
3772   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3773   if (opcode[i]==0x31) { // LWC1 (write float)
3774     emit_writeword_indexed(tl,0,temp);
3775   }
3776   if (opcode[i]==0x35) { // LDC1 (write double)
3777     emit_writeword_indexed(th,4,temp);
3778     emit_writeword_indexed(tl,0,temp);
3779   }
3780   //if(opcode[i]==0x39)
3781   /*if(opcode[i]==0x39||opcode[i]==0x31)
3782   {
3783     emit_pusha();
3784         emit_readword((int)&last_count,ECX);
3785         if(get_reg(i_regs->regmap,CCREG)<0)
3786           emit_loadreg(CCREG,HOST_CCREG);
3787         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3788         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3789         emit_writeword(HOST_CCREG,(int)&Count);
3790     emit_call((int)memdebug);
3791     emit_popa();
3792   }/**/
3793 #else
3794   cop1_unusable(i, i_regs);
3795 #endif
3796 }
3797
3798 void c2ls_assemble(int i,struct regstat *i_regs)
3799 {
3800   int s,tl;
3801   int ar;
3802   int offset;
3803   int memtarget=0,c=0;
3804   int jaddr2=0,jaddr3,type;
3805   int agr=AGEN1+(i&1);
3806   u_int hr,reglist=0;
3807   u_int copr=(source[i]>>16)&0x1f;
3808   s=get_reg(i_regs->regmap,rs1[i]);
3809   tl=get_reg(i_regs->regmap,FTEMP);
3810   offset=imm[i];
3811   assert(rs1[i]>0);
3812   assert(tl>=0);
3813   assert(!using_tlb);
3814
3815   for(hr=0;hr<HOST_REGS;hr++) {
3816     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3817   }
3818   if(i_regs->regmap[HOST_CCREG]==CCREG)
3819     reglist&=~(1<<HOST_CCREG);
3820
3821   // get the address
3822   if (opcode[i]==0x3a) { // SWC2
3823     ar=get_reg(i_regs->regmap,agr);
3824     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3825     reglist|=1<<ar;
3826   } else { // LWC2
3827     ar=tl;
3828   }
3829   if(s>=0) c=(i_regs->wasconst>>s)&1;
3830   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3831   if (!offset&&!c&&s>=0) ar=s;
3832   assert(ar>=0);
3833
3834   if (opcode[i]==0x3a) { // SWC2
3835     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3836     type=STOREW_STUB;
3837   }
3838   else
3839     type=LOADW_STUB;
3840
3841   if(c&&!memtarget) {
3842     jaddr2=(int)out;
3843     emit_jmp(0); // inline_readstub/inline_writestub?
3844   }
3845   else {
3846     if(!c) {
3847       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3848       jaddr2=(int)out;
3849       emit_jno(0);
3850     }
3851     if (opcode[i]==0x32) { // LWC2
3852       #ifdef HOST_IMM_ADDR32
3853       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3854       else
3855       #endif
3856       emit_readword_indexed(0,ar,tl);
3857     }
3858     if (opcode[i]==0x3a) { // SWC2
3859       #ifdef DESTRUCTIVE_SHIFT
3860       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3861       #endif
3862       emit_writeword_indexed(tl,0,ar);
3863     }
3864   }
3865   if(jaddr2)
3866     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3867   if (opcode[i]==0x3a) { // SWC2
3868 #if defined(HOST_IMM8)
3869     int ir=get_reg(i_regs->regmap,INVCP);
3870     assert(ir>=0);
3871     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3872 #else
3873     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3874 #endif
3875     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3876     emit_callne(invalidate_addr_reg[ar]);
3877     #else
3878     jaddr3=(int)out;
3879     emit_jne(0);
3880     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3881     #endif
3882   }
3883   if (opcode[i]==0x32) { // LWC2
3884     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3885   }
3886 }
3887
3888 #ifndef multdiv_assemble
3889 void multdiv_assemble(int i,struct regstat *i_regs)
3890 {
3891   printf("Need multdiv_assemble for this architecture.\n");
3892   exit(1);
3893 }
3894 #endif
3895
3896 void mov_assemble(int i,struct regstat *i_regs)
3897 {
3898   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3899   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3900   if(rt1[i]) {
3901     signed char sh,sl,th,tl;
3902     th=get_reg(i_regs->regmap,rt1[i]|64);
3903     tl=get_reg(i_regs->regmap,rt1[i]);
3904     //assert(tl>=0);
3905     if(tl>=0) {
3906       sh=get_reg(i_regs->regmap,rs1[i]|64);
3907       sl=get_reg(i_regs->regmap,rs1[i]);
3908       if(sl>=0) emit_mov(sl,tl);
3909       else emit_loadreg(rs1[i],tl);
3910       if(th>=0) {
3911         if(sh>=0) emit_mov(sh,th);
3912         else emit_loadreg(rs1[i]|64,th);
3913       }
3914     }
3915   }
3916 }
3917
3918 #ifndef fconv_assemble
3919 void fconv_assemble(int i,struct regstat *i_regs)
3920 {
3921   printf("Need fconv_assemble for this architecture.\n");
3922   exit(1);
3923 }
3924 #endif
3925
3926 #if 0
3927 void float_assemble(int i,struct regstat *i_regs)
3928 {
3929   printf("Need float_assemble for this architecture.\n");
3930   exit(1);
3931 }
3932 #endif
3933
3934 void syscall_assemble(int i,struct regstat *i_regs)
3935 {
3936   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3937   assert(ccreg==HOST_CCREG);
3938   assert(!is_delayslot);
3939   emit_movimm(start+i*4,EAX); // Get PC
3940   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3941   emit_jmp((int)jump_syscall_hle); // XXX
3942 }
3943
3944 void hlecall_assemble(int i,struct regstat *i_regs)
3945 {
3946   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3947   assert(ccreg==HOST_CCREG);
3948   assert(!is_delayslot);
3949   emit_movimm(start+i*4+4,0); // Get PC
3950   emit_movimm((int)psxHLEt[source[i]&7],1);
3951   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3952   emit_jmp((int)jump_hlecall);
3953 }
3954
3955 void intcall_assemble(int i,struct regstat *i_regs)
3956 {
3957   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3958   assert(ccreg==HOST_CCREG);
3959   assert(!is_delayslot);
3960   emit_movimm(start+i*4,0); // Get PC
3961   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3962   emit_jmp((int)jump_intcall);
3963 }
3964
3965 void ds_assemble(int i,struct regstat *i_regs)
3966 {
3967   is_delayslot=1;