1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
83 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
84 static uint64_t gte_rt[MAXBLOCK];
85 static uint64_t gte_unneeded[MAXBLOCK];
86 static int gte_reads_flags; // gte flag read encountered
89 char likely[MAXBLOCK];
92 uint64_t unneeded_reg[MAXBLOCK];
93 uint64_t unneeded_reg_upper[MAXBLOCK];
94 uint64_t branch_unneeded_reg[MAXBLOCK];
95 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
96 uint64_t p32[MAXBLOCK];
97 uint64_t pr32[MAXBLOCK];
98 signed char regmap_pre[MAXBLOCK][HOST_REGS];
99 signed char regmap[MAXBLOCK][HOST_REGS];
100 signed char regmap_entry[MAXBLOCK][HOST_REGS];
101 uint64_t constmap[MAXBLOCK][HOST_REGS];
102 struct regstat regs[MAXBLOCK];
103 struct regstat branch_regs[MAXBLOCK];
104 signed char minimum_free_regs[MAXBLOCK];
105 u_int needed_reg[MAXBLOCK];
106 uint64_t requires_32bit[MAXBLOCK];
107 u_int wont_dirty[MAXBLOCK];
108 u_int will_dirty[MAXBLOCK];
111 u_int instr_addr[MAXBLOCK];
112 u_int link_addr[MAXBLOCK][3];
114 u_int stubs[MAXBLOCK*3][8];
116 u_int literals[1024][2];
121 struct ll_entry *jump_in[4096];
122 struct ll_entry *jump_out[4096];
123 struct ll_entry *jump_dirty[4096];
124 u_int hash_table[65536][4] __attribute__((aligned(16)));
125 char shadow[1048576] __attribute__((aligned(16)));
131 static const u_int using_tlb=0;
133 static u_int sp_in_mirror;
134 u_int stop_after_jal;
135 extern u_char restore_candidate[512];
136 extern int cycle_count;
138 /* registers that may be allocated */
140 #define HIREG 32 // hi
141 #define LOREG 33 // lo
142 #define FSREG 34 // FPU status (FCSR)
143 #define CSREG 35 // Coprocessor status
144 #define CCREG 36 // Cycle count
145 #define INVCP 37 // Pointer to invalid_code
146 #define MMREG 38 // Pointer to memory_map
147 #define ROREG 39 // ram offset (if rdram!=0x80000000)
149 #define FTEMP 40 // FPU temporary register
150 #define PTEMP 41 // Prefetch temporary register
151 #define TLREG 42 // TLB mapping offset
152 #define RHASH 43 // Return address hash
153 #define RHTBL 44 // Return address hash table address
154 #define RTEMP 45 // JR/JALR address register
156 #define AGEN1 46 // Address generation temporary register
157 #define AGEN2 47 // Address generation temporary register
158 #define MGEN1 48 // Maptable address generation temporary register
159 #define MGEN2 49 // Maptable address generation temporary register
160 #define BTREG 50 // Branch target temporary register
162 /* instruction types */
163 #define NOP 0 // No operation
164 #define LOAD 1 // Load
165 #define STORE 2 // Store
166 #define LOADLR 3 // Unaligned load
167 #define STORELR 4 // Unaligned store
168 #define MOV 5 // Move
169 #define ALU 6 // Arithmetic/logic
170 #define MULTDIV 7 // Multiply/divide
171 #define SHIFT 8 // Shift by register
172 #define SHIFTIMM 9// Shift by immediate
173 #define IMM16 10 // 16-bit immediate
174 #define RJUMP 11 // Unconditional jump to register
175 #define UJUMP 12 // Unconditional jump
176 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
177 #define SJUMP 14 // Conditional branch (regimm format)
178 #define COP0 15 // Coprocessor 0
179 #define COP1 16 // Coprocessor 1
180 #define C1LS 17 // Coprocessor 1 load/store
181 #define FJUMP 18 // Conditional branch (floating point)
182 #define FLOAT 19 // Floating point unit
183 #define FCONV 20 // Convert integer to float
184 #define FCOMP 21 // Floating point compare (sets FSREG)
185 #define SYSCALL 22// SYSCALL
186 #define OTHER 23 // Other
187 #define SPAN 24 // Branch/delay slot spans 2 pages
188 #define NI 25 // Not implemented
189 #define HLECALL 26// PCSX fake opcodes for HLE
190 #define COP2 27 // Coprocessor 2 move
191 #define C2LS 28 // Coprocessor 2 load/store
192 #define C2OP 29 // Coprocessor 2 operation
193 #define INTCALL 30// Call interpreter to handle rare corner cases
202 #define LOADBU_STUB 7
203 #define LOADHU_STUB 8
204 #define STOREB_STUB 9
205 #define STOREH_STUB 10
206 #define STOREW_STUB 11
207 #define STORED_STUB 12
208 #define STORELR_STUB 13
209 #define INVCODE_STUB 14
217 int new_recompile_block(int addr);
218 void *get_addr_ht(u_int vaddr);
219 void invalidate_block(u_int block);
220 void invalidate_addr(u_int addr);
221 void remove_hash(int vaddr);
224 void dyna_linker_ds();
226 void verify_code_vm();
227 void verify_code_ds();
230 void fp_exception_ds();
232 void jump_syscall_hle();
236 void new_dyna_leave();
241 void read_nomem_new();
242 void read_nomemb_new();
243 void read_nomemh_new();
244 void read_nomemd_new();
245 void write_nomem_new();
246 void write_nomemb_new();
247 void write_nomemh_new();
248 void write_nomemd_new();
249 void write_rdram_new();
250 void write_rdramb_new();
251 void write_rdramh_new();
252 void write_rdramd_new();
253 extern u_int memory_map[1048576];
255 // Needed by assembler
256 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
257 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
258 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
259 void load_all_regs(signed char i_regmap[]);
260 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
261 void load_regs_entry(int t);
262 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
266 //#define DEBUG_CYCLE_COUNT 1
269 //#define assem_debug printf
270 //#define inv_debug printf
271 #define assem_debug nullf
272 #define inv_debug nullf
274 static void tlb_hacks()
278 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
282 switch (ROM_HEADER->Country_code&0xFF)
294 // Unknown country code
298 u_int rom_addr=(u_int)rom;
300 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
301 // in the lower 4G of memory to use this hack. Copy it if necessary.
302 if((void *)rom>(void *)0xffffffff) {
303 munmap(ROM_COPY, 67108864);
304 if(mmap(ROM_COPY, 12582912,
305 PROT_READ | PROT_WRITE,
306 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
307 -1, 0) <= 0) {printf("mmap() failed\n");}
308 memcpy(ROM_COPY,rom,12582912);
309 rom_addr=(u_int)ROM_COPY;
313 for(n=0x7F000;n<0x80000;n++) {
314 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
321 static u_int get_page(u_int vaddr)
324 u_int page=(vaddr^0x80000000)>>12;
326 u_int page=vaddr&~0xe0000000;
327 if (page < 0x1000000)
328 page &= ~0x0e00000; // RAM mirrors
332 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
334 if(page>2048) page=2048+(page&2047);
338 static u_int get_vpage(u_int vaddr)
340 u_int vpage=(vaddr^0x80000000)>>12;
342 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
344 if(vpage>2048) vpage=2048+(vpage&2047);
348 // Get address from virtual address
349 // This is called from the recompiled JR/JALR instructions
350 void *get_addr(u_int vaddr)
352 u_int page=get_page(vaddr);
353 u_int vpage=get_vpage(vaddr);
354 struct ll_entry *head;
355 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
358 if(head->vaddr==vaddr&&head->reg32==0) {
359 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
360 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 ht_bin[1]=(int)head->addr;
369 head=jump_dirty[vpage];
371 if(head->vaddr==vaddr&&head->reg32==0) {
372 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
373 // Don't restore blocks which are about to expire from the cache
374 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
375 if(verify_dirty(head->addr)) {
376 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
377 invalid_code[vaddr>>12]=0;
378 inv_code_start=inv_code_end=~0;
379 memory_map[vaddr>>12]|=0x40000000;
382 if(tlb_LUT_r[vaddr>>12]) {
383 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
384 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
387 restore_candidate[vpage>>3]|=1<<(vpage&7);
389 else restore_candidate[page>>3]|=1<<(page&7);
390 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
391 if(ht_bin[0]==vaddr) {
392 ht_bin[1]=(int)head->addr; // Replace existing entry
398 ht_bin[1]=(int)head->addr;
406 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
407 int r=new_recompile_block(vaddr);
408 if(r==0) return get_addr(vaddr);
409 // Execute in unmapped page, generate pagefault execption
411 Cause=(vaddr<<31)|0x8;
412 EPC=(vaddr&1)?vaddr-5:vaddr;
414 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
415 EntryHi=BadVAddr&0xFFFFE000;
416 return get_addr_ht(0x80000000);
418 // Look up address in hash table first
419 void *get_addr_ht(u_int vaddr)
421 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
425 return get_addr(vaddr);
428 void *get_addr_32(u_int vaddr,u_int flags)
431 return get_addr(vaddr);
433 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
434 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
435 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
436 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
437 u_int page=get_page(vaddr);
438 u_int vpage=get_vpage(vaddr);
439 struct ll_entry *head;
442 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
443 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
447 ht_bin[1]=(int)head->addr;
449 }else if(ht_bin[2]==-1) {
450 ht_bin[3]=(int)head->addr;
453 //ht_bin[3]=ht_bin[1];
454 //ht_bin[2]=ht_bin[0];
455 //ht_bin[1]=(int)head->addr;
462 head=jump_dirty[vpage];
464 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
465 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
466 // Don't restore blocks which are about to expire from the cache
467 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
468 if(verify_dirty(head->addr)) {
469 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
470 invalid_code[vaddr>>12]=0;
471 inv_code_start=inv_code_end=~0;
472 memory_map[vaddr>>12]|=0x40000000;
475 if(tlb_LUT_r[vaddr>>12]) {
476 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
477 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
480 restore_candidate[vpage>>3]|=1<<(vpage&7);
482 else restore_candidate[page>>3]|=1<<(page&7);
484 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
486 ht_bin[1]=(int)head->addr;
488 }else if(ht_bin[2]==-1) {
489 ht_bin[3]=(int)head->addr;
492 //ht_bin[3]=ht_bin[1];
493 //ht_bin[2]=ht_bin[0];
494 //ht_bin[1]=(int)head->addr;
502 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
503 int r=new_recompile_block(vaddr);
504 if(r==0) return get_addr(vaddr);
505 // Execute in unmapped page, generate pagefault execption
507 Cause=(vaddr<<31)|0x8;
508 EPC=(vaddr&1)?vaddr-5:vaddr;
510 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
511 EntryHi=BadVAddr&0xFFFFE000;
512 return get_addr_ht(0x80000000);
516 void clear_all_regs(signed char regmap[])
519 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
522 signed char get_reg(signed char regmap[],int r)
525 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
529 // Find a register that is available for two consecutive cycles
530 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
533 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
537 int count_free_regs(signed char regmap[])
541 for(hr=0;hr<HOST_REGS;hr++)
543 if(hr!=EXCLUDE_REG) {
544 if(regmap[hr]<0) count++;
550 void dirty_reg(struct regstat *cur,signed char reg)
554 for (hr=0;hr<HOST_REGS;hr++) {
555 if((cur->regmap[hr]&63)==reg) {
561 // If we dirty the lower half of a 64 bit register which is now being
562 // sign-extended, we need to dump the upper half.
563 // Note: Do this only after completion of the instruction, because
564 // some instructions may need to read the full 64-bit value even if
565 // overwriting it (eg SLTI, DSRA32).
566 static void flush_dirty_uppers(struct regstat *cur)
569 for (hr=0;hr<HOST_REGS;hr++) {
570 if((cur->dirty>>hr)&1) {
573 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
578 void set_const(struct regstat *cur,signed char reg,uint64_t value)
582 for (hr=0;hr<HOST_REGS;hr++) {
583 if(cur->regmap[hr]==reg) {
585 cur->constmap[hr]=value;
587 else if((cur->regmap[hr]^64)==reg) {
589 cur->constmap[hr]=value>>32;
594 void clear_const(struct regstat *cur,signed char reg)
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if((cur->regmap[hr]&63)==reg) {
600 cur->isconst&=~(1<<hr);
605 int is_const(struct regstat *cur,signed char reg)
610 for (hr=0;hr<HOST_REGS;hr++) {
611 if((cur->regmap[hr]&63)==reg) {
612 return (cur->isconst>>hr)&1;
617 uint64_t get_const(struct regstat *cur,signed char reg)
621 for (hr=0;hr<HOST_REGS;hr++) {
622 if(cur->regmap[hr]==reg) {
623 return cur->constmap[hr];
626 printf("Unknown constant in r%d\n",reg);
630 // Least soon needed registers
631 // Look at the next ten instructions and see which registers
632 // will be used. Try not to reallocate these.
633 void lsn(u_char hsn[], int i, int *preferred_reg)
643 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
645 // Don't go past an unconditonal jump
652 if(rs1[i+j]) hsn[rs1[i+j]]=j;
653 if(rs2[i+j]) hsn[rs2[i+j]]=j;
654 if(rt1[i+j]) hsn[rt1[i+j]]=j;
655 if(rt2[i+j]) hsn[rt2[i+j]]=j;
656 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
657 // Stores can allocate zero
661 // On some architectures stores need invc_ptr
662 #if defined(HOST_IMM8)
663 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
667 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
675 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
677 // Follow first branch
678 int t=(ba[i+b]-start)>>2;
679 j=7-b;if(t+j>=slen) j=slen-t-1;
682 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
683 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
684 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
685 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
688 // TODO: preferred register based on backward branch
690 // Delay slot should preferably not overwrite branch conditions or cycle count
691 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
692 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
693 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
699 // Coprocessor load/store needs FTEMP, even if not declared
700 if(itype[i]==C1LS||itype[i]==C2LS) {
703 // Load L/R also uses FTEMP as a temporary register
704 if(itype[i]==LOADLR) {
707 // Also SWL/SWR/SDL/SDR
708 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
711 // Don't remove the TLB registers either
712 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
715 // Don't remove the miniht registers
716 if(itype[i]==UJUMP||itype[i]==RJUMP)
723 // We only want to allocate registers if we're going to use them again soon
724 int needed_again(int r, int i)
730 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
732 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
733 return 0; // Don't need any registers if exiting the block
741 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
743 // Don't go past an unconditonal jump
747 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
754 if(rs1[i+j]==r) rn=j;
755 if(rs2[i+j]==r) rn=j;
756 if((unneeded_reg[i+j]>>r)&1) rn=10;
757 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
765 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
767 // Follow first branch
769 int t=(ba[i+b]-start)>>2;
770 j=7-b;if(t+j>=slen) j=slen-t-1;
773 if(!((unneeded_reg[t+j]>>r)&1)) {
774 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
775 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
785 // Try to match register allocations at the end of a loop with those
787 int loop_reg(int i, int r, int hr)
796 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
798 // Don't go past an unconditonal jump
805 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
810 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
811 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
812 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
814 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
816 int t=(ba[i+k]-start)>>2;
817 int reg=get_reg(regs[t].regmap_entry,r);
818 if(reg>=0) return reg;
819 //reg=get_reg(regs[t+1].regmap_entry,r);
820 //if(reg>=0) return reg;
828 // Allocate every register, preserving source/target regs
829 void alloc_all(struct regstat *cur,int i)
833 for(hr=0;hr<HOST_REGS;hr++) {
834 if(hr!=EXCLUDE_REG) {
835 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
836 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
839 cur->dirty&=~(1<<hr);
842 if((cur->regmap[hr]&63)==0)
845 cur->dirty&=~(1<<hr);
852 void div64(int64_t dividend,int64_t divisor)
856 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
857 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859 void divu64(uint64_t dividend,uint64_t divisor)
863 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
864 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
867 void mult64(uint64_t m1,uint64_t m2)
869 unsigned long long int op1, op2, op3, op4;
870 unsigned long long int result1, result2, result3, result4;
871 unsigned long long int temp1, temp2, temp3, temp4;
887 op1 = op2 & 0xFFFFFFFF;
888 op2 = (op2 >> 32) & 0xFFFFFFFF;
889 op3 = op4 & 0xFFFFFFFF;
890 op4 = (op4 >> 32) & 0xFFFFFFFF;
893 temp2 = (temp1 >> 32) + op1 * op4;
895 temp4 = (temp3 >> 32) + op2 * op4;
897 result1 = temp1 & 0xFFFFFFFF;
898 result2 = temp2 + (temp3 & 0xFFFFFFFF);
899 result3 = (result2 >> 32) + temp4;
900 result4 = (result3 >> 32);
902 lo = result1 | (result2 << 32);
903 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
912 void multu64(uint64_t m1,uint64_t m2)
914 unsigned long long int op1, op2, op3, op4;
915 unsigned long long int result1, result2, result3, result4;
916 unsigned long long int temp1, temp2, temp3, temp4;
918 op1 = m1 & 0xFFFFFFFF;
919 op2 = (m1 >> 32) & 0xFFFFFFFF;
920 op3 = m2 & 0xFFFFFFFF;
921 op4 = (m2 >> 32) & 0xFFFFFFFF;
924 temp2 = (temp1 >> 32) + op1 * op4;
926 temp4 = (temp3 >> 32) + op2 * op4;
928 result1 = temp1 & 0xFFFFFFFF;
929 result2 = temp2 + (temp3 & 0xFFFFFFFF);
930 result3 = (result2 >> 32) + temp4;
931 result4 = (result3 >> 32);
933 lo = result1 | (result2 << 32);
934 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
936 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
937 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
940 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
948 else original=loaded;
951 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
954 original>>=64-(bits^56);
955 original<<=64-(bits^56);
959 else original=loaded;
964 #include "assem_x86.c"
967 #include "assem_x64.c"
970 #include "assem_arm.c"
973 // Add virtual address mapping to linked list
974 void ll_add(struct ll_entry **head,int vaddr,void *addr)
976 struct ll_entry *new_entry;
977 new_entry=malloc(sizeof(struct ll_entry));
978 assert(new_entry!=NULL);
979 new_entry->vaddr=vaddr;
981 new_entry->addr=addr;
982 new_entry->next=*head;
986 // Add virtual address mapping for 32-bit compiled block
987 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
989 ll_add(head,vaddr,addr);
991 (*head)->reg32=reg32;
995 // Check if an address is already compiled
996 // but don't return addresses which are about to expire from the cache
997 void *check_addr(u_int vaddr)
999 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1000 if(ht_bin[0]==vaddr) {
1001 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1002 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1004 if(ht_bin[2]==vaddr) {
1005 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1006 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1008 u_int page=get_page(vaddr);
1009 struct ll_entry *head;
1012 if(head->vaddr==vaddr&&head->reg32==0) {
1013 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1014 // Update existing entry with current address
1015 if(ht_bin[0]==vaddr) {
1016 ht_bin[1]=(int)head->addr;
1019 if(ht_bin[2]==vaddr) {
1020 ht_bin[3]=(int)head->addr;
1023 // Insert into hash table with low priority.
1024 // Don't evict existing entries, as they are probably
1025 // addresses that are being accessed frequently.
1027 ht_bin[1]=(int)head->addr;
1029 }else if(ht_bin[2]==-1) {
1030 ht_bin[3]=(int)head->addr;
1041 void remove_hash(int vaddr)
1043 //printf("remove hash: %x\n",vaddr);
1044 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1045 if(ht_bin[2]==vaddr) {
1046 ht_bin[2]=ht_bin[3]=-1;
1048 if(ht_bin[0]==vaddr) {
1049 ht_bin[0]=ht_bin[2];
1050 ht_bin[1]=ht_bin[3];
1051 ht_bin[2]=ht_bin[3]=-1;
1055 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1057 struct ll_entry *next;
1059 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1060 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1062 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1063 remove_hash((*head)->vaddr);
1070 head=&((*head)->next);
1075 // Remove all entries from linked list
1076 void ll_clear(struct ll_entry **head)
1078 struct ll_entry *cur;
1079 struct ll_entry *next;
1090 // Dereference the pointers and remove if it matches
1091 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1094 int ptr=get_pointer(head->addr);
1095 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1096 if(((ptr>>shift)==(addr>>shift)) ||
1097 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1099 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1100 u_int host_addr=(u_int)kill_pointer(head->addr);
1102 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1109 // This is called when we write to a compiled block (see do_invstub)
1110 void invalidate_page(u_int page)
1112 struct ll_entry *head;
1113 struct ll_entry *next;
1117 inv_debug("INVALIDATE: %x\n",head->vaddr);
1118 remove_hash(head->vaddr);
1123 head=jump_out[page];
1126 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1127 u_int host_addr=(u_int)kill_pointer(head->addr);
1129 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1137 static void invalidate_block_range(u_int block, u_int first, u_int last)
1139 u_int page=get_page(block<<12);
1140 //printf("first=%d last=%d\n",first,last);
1141 invalidate_page(page);
1142 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1143 assert(last<page+5);
1144 // Invalidate the adjacent pages if a block crosses a 4K boundary
1146 invalidate_page(first);
1149 for(first=page+1;first<last;first++) {
1150 invalidate_page(first);
1156 // Don't trap writes
1157 invalid_code[block]=1;
1159 // If there is a valid TLB entry for this page, remove write protect
1160 if(tlb_LUT_w[block]) {
1161 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1162 // CHECK: Is this right?
1163 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1164 u_int real_block=tlb_LUT_w[block]>>12;
1165 invalid_code[real_block]=1;
1166 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1168 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1172 memset(mini_ht,-1,sizeof(mini_ht));
1176 void invalidate_block(u_int block)
1178 u_int page=get_page(block<<12);
1179 u_int vpage=get_vpage(block<<12);
1180 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1181 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1184 struct ll_entry *head;
1185 head=jump_dirty[vpage];
1186 //printf("page=%d vpage=%d\n",page,vpage);
1189 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1190 get_bounds((int)head->addr,&start,&end);
1191 //printf("start: %x end: %x\n",start,end);
1192 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1193 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1194 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1195 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1199 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1200 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1201 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1202 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1209 invalidate_block_range(block,first,last);
1212 void invalidate_addr(u_int addr)
1216 // this check is done by the caller
1217 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1218 u_int page=get_page(addr);
1219 if(page<2048) { // RAM
1220 struct ll_entry *head;
1221 u_int addr_min=~0, addr_max=0;
1222 int mask=RAM_SIZE-1;
1224 inv_code_start=addr&~0xfff;
1225 inv_code_end=addr|0xfff;
1228 // must check previous page too because of spans..
1230 inv_code_start-=0x1000;
1232 for(;pg1<=page;pg1++) {
1233 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1235 get_bounds((int)head->addr,&start,&end);
1236 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1237 if(start<addr_min) addr_min=start;
1238 if(end>addr_max) addr_max=end;
1240 else if(addr<start) {
1241 if(start<inv_code_end)
1242 inv_code_end=start-1;
1245 if(end>inv_code_start)
1251 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1252 inv_code_start=inv_code_end=~0;
1253 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1257 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1260 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1264 invalidate_block(addr>>12);
1267 // This is called when loading a save state.
1268 // Anything could have changed, so invalidate everything.
1269 void invalidate_all_pages()
1272 for(page=0;page<4096;page++)
1273 invalidate_page(page);
1274 for(page=0;page<1048576;page++)
1275 if(!invalid_code[page]) {
1276 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1277 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1280 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1283 memset(mini_ht,-1,sizeof(mini_ht));
1287 for(page=0;page<0x100000;page++) {
1288 if(tlb_LUT_r[page]) {
1289 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1290 if(!tlb_LUT_w[page]||!invalid_code[page])
1291 memory_map[page]|=0x40000000; // Write protect
1293 else memory_map[page]=-1;
1294 if(page==0x80000) page=0xC0000;
1300 // Add an entry to jump_out after making a link
1301 void add_link(u_int vaddr,void *src)
1303 u_int page=get_page(vaddr);
1304 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1305 int *ptr=(int *)(src+4);
1306 assert((*ptr&0x0fff0000)==0x059f0000);
1307 ll_add(jump_out+page,vaddr,src);
1308 //int ptr=get_pointer(src);
1309 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1312 // If a code block was found to be unmodified (bit was set in
1313 // restore_candidate) and it remains unmodified (bit is clear
1314 // in invalid_code) then move the entries for that 4K page from
1315 // the dirty list to the clean list.
1316 void clean_blocks(u_int page)
1318 struct ll_entry *head;
1319 inv_debug("INV: clean_blocks page=%d\n",page);
1320 head=jump_dirty[page];
1322 if(!invalid_code[head->vaddr>>12]) {
1323 // Don't restore blocks which are about to expire from the cache
1324 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1326 if(verify_dirty((int)head->addr)) {
1327 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1330 get_bounds((int)head->addr,&start,&end);
1331 if(start-(u_int)rdram<RAM_SIZE) {
1332 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1333 inv|=invalid_code[i];
1336 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1337 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1338 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1339 if(addr<start||addr>=end) inv=1;
1341 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1345 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1346 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1349 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1351 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1352 //printf("page=%x, addr=%x\n",page,head->vaddr);
1353 //assert(head->vaddr>>12==(page|0x80000));
1354 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1355 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1357 if(ht_bin[0]==head->vaddr) {
1358 ht_bin[1]=(int)clean_addr; // Replace existing entry
1360 if(ht_bin[2]==head->vaddr) {
1361 ht_bin[3]=(int)clean_addr; // Replace existing entry
1374 void mov_alloc(struct regstat *current,int i)
1376 // Note: Don't need to actually alloc the source registers
1377 if((~current->is32>>rs1[i])&1) {
1378 //alloc_reg64(current,i,rs1[i]);
1379 alloc_reg64(current,i,rt1[i]);
1380 current->is32&=~(1LL<<rt1[i]);
1382 //alloc_reg(current,i,rs1[i]);
1383 alloc_reg(current,i,rt1[i]);
1384 current->is32|=(1LL<<rt1[i]);
1386 clear_const(current,rs1[i]);
1387 clear_const(current,rt1[i]);
1388 dirty_reg(current,rt1[i]);
1391 void shiftimm_alloc(struct regstat *current,int i)
1393 clear_const(current,rs1[i]);
1394 clear_const(current,rt1[i]);
1395 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1398 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1400 alloc_reg(current,i,rt1[i]);
1401 current->is32|=1LL<<rt1[i];
1402 dirty_reg(current,rt1[i]);
1405 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1408 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1409 alloc_reg64(current,i,rt1[i]);
1410 current->is32&=~(1LL<<rt1[i]);
1411 dirty_reg(current,rt1[i]);
1414 if(opcode2[i]==0x3c) // DSLL32
1417 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1418 alloc_reg64(current,i,rt1[i]);
1419 current->is32&=~(1LL<<rt1[i]);
1420 dirty_reg(current,rt1[i]);
1423 if(opcode2[i]==0x3e) // DSRL32
1426 alloc_reg64(current,i,rs1[i]);
1428 alloc_reg64(current,i,rt1[i]);
1429 current->is32&=~(1LL<<rt1[i]);
1431 alloc_reg(current,i,rt1[i]);
1432 current->is32|=1LL<<rt1[i];
1434 dirty_reg(current,rt1[i]);
1437 if(opcode2[i]==0x3f) // DSRA32
1440 alloc_reg64(current,i,rs1[i]);
1441 alloc_reg(current,i,rt1[i]);
1442 current->is32|=1LL<<rt1[i];
1443 dirty_reg(current,rt1[i]);
1448 void shift_alloc(struct regstat *current,int i)
1451 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1453 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1455 alloc_reg(current,i,rt1[i]);
1456 if(rt1[i]==rs2[i]) {
1457 alloc_reg_temp(current,i,-1);
1458 minimum_free_regs[i]=1;
1460 current->is32|=1LL<<rt1[i];
1461 } else { // DSLLV/DSRLV/DSRAV
1462 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1463 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1464 alloc_reg64(current,i,rt1[i]);
1465 current->is32&=~(1LL<<rt1[i]);
1466 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1468 alloc_reg_temp(current,i,-1);
1469 minimum_free_regs[i]=1;
1472 clear_const(current,rs1[i]);
1473 clear_const(current,rs2[i]);
1474 clear_const(current,rt1[i]);
1475 dirty_reg(current,rt1[i]);
1479 void alu_alloc(struct regstat *current,int i)
1481 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1483 if(rs1[i]&&rs2[i]) {
1484 alloc_reg(current,i,rs1[i]);
1485 alloc_reg(current,i,rs2[i]);
1488 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1489 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1491 alloc_reg(current,i,rt1[i]);
1493 current->is32|=1LL<<rt1[i];
1495 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1497 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1499 alloc_reg64(current,i,rs1[i]);
1500 alloc_reg64(current,i,rs2[i]);
1501 alloc_reg(current,i,rt1[i]);
1503 alloc_reg(current,i,rs1[i]);
1504 alloc_reg(current,i,rs2[i]);
1505 alloc_reg(current,i,rt1[i]);
1508 current->is32|=1LL<<rt1[i];
1510 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1512 if(rs1[i]&&rs2[i]) {
1513 alloc_reg(current,i,rs1[i]);
1514 alloc_reg(current,i,rs2[i]);
1518 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1521 alloc_reg(current,i,rt1[i]);
1522 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1524 if(!((current->uu>>rt1[i])&1)) {
1525 alloc_reg64(current,i,rt1[i]);
1527 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1528 if(rs1[i]&&rs2[i]) {
1529 alloc_reg64(current,i,rs1[i]);
1530 alloc_reg64(current,i,rs2[i]);
1534 // Is is really worth it to keep 64-bit values in registers?
1536 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1537 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1541 current->is32&=~(1LL<<rt1[i]);
1543 current->is32|=1LL<<rt1[i];
1547 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1549 if(rs1[i]&&rs2[i]) {
1550 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1551 alloc_reg64(current,i,rs1[i]);
1552 alloc_reg64(current,i,rs2[i]);
1553 alloc_reg64(current,i,rt1[i]);
1555 alloc_reg(current,i,rs1[i]);
1556 alloc_reg(current,i,rs2[i]);
1557 alloc_reg(current,i,rt1[i]);
1561 alloc_reg(current,i,rt1[i]);
1562 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1563 // DADD used as move, or zeroing
1564 // If we have a 64-bit source, then make the target 64 bits too
1565 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1566 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1567 alloc_reg64(current,i,rt1[i]);
1568 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1569 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1570 alloc_reg64(current,i,rt1[i]);
1572 if(opcode2[i]>=0x2e&&rs2[i]) {
1573 // DSUB used as negation - 64-bit result
1574 // If we have a 32-bit register, extend it to 64 bits
1575 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1576 alloc_reg64(current,i,rt1[i]);
1580 if(rs1[i]&&rs2[i]) {
1581 current->is32&=~(1LL<<rt1[i]);
1583 current->is32&=~(1LL<<rt1[i]);
1584 if((current->is32>>rs1[i])&1)
1585 current->is32|=1LL<<rt1[i];
1587 current->is32&=~(1LL<<rt1[i]);
1588 if((current->is32>>rs2[i])&1)
1589 current->is32|=1LL<<rt1[i];
1591 current->is32|=1LL<<rt1[i];
1595 clear_const(current,rs1[i]);
1596 clear_const(current,rs2[i]);
1597 clear_const(current,rt1[i]);
1598 dirty_reg(current,rt1[i]);
1601 void imm16_alloc(struct regstat *current,int i)
1603 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1605 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1606 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1607 current->is32&=~(1LL<<rt1[i]);
1608 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1609 // TODO: Could preserve the 32-bit flag if the immediate is zero
1610 alloc_reg64(current,i,rt1[i]);
1611 alloc_reg64(current,i,rs1[i]);
1613 clear_const(current,rs1[i]);
1614 clear_const(current,rt1[i]);
1616 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1617 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1618 current->is32|=1LL<<rt1[i];
1619 clear_const(current,rs1[i]);
1620 clear_const(current,rt1[i]);
1622 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1623 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1624 if(rs1[i]!=rt1[i]) {
1625 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1626 alloc_reg64(current,i,rt1[i]);
1627 current->is32&=~(1LL<<rt1[i]);
1630 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1631 if(is_const(current,rs1[i])) {
1632 int v=get_const(current,rs1[i]);
1633 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1634 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1635 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1637 else clear_const(current,rt1[i]);
1639 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1640 if(is_const(current,rs1[i])) {
1641 int v=get_const(current,rs1[i]);
1642 set_const(current,rt1[i],v+imm[i]);
1644 else clear_const(current,rt1[i]);
1645 current->is32|=1LL<<rt1[i];
1648 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1649 current->is32|=1LL<<rt1[i];
1651 dirty_reg(current,rt1[i]);
1654 void load_alloc(struct regstat *current,int i)
1656 clear_const(current,rt1[i]);
1657 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1658 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1659 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1660 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1661 alloc_reg(current,i,rt1[i]);
1662 assert(get_reg(current->regmap,rt1[i])>=0);
1663 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1665 current->is32&=~(1LL<<rt1[i]);
1666 alloc_reg64(current,i,rt1[i]);
1668 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1670 current->is32&=~(1LL<<rt1[i]);
1671 alloc_reg64(current,i,rt1[i]);
1672 alloc_all(current,i);
1673 alloc_reg64(current,i,FTEMP);
1674 minimum_free_regs[i]=HOST_REGS;
1676 else current->is32|=1LL<<rt1[i];
1677 dirty_reg(current,rt1[i]);
1678 // If using TLB, need a register for pointer to the mapping table
1679 if(using_tlb) alloc_reg(current,i,TLREG);
1680 // LWL/LWR need a temporary register for the old value
1681 if(opcode[i]==0x22||opcode[i]==0x26)
1683 alloc_reg(current,i,FTEMP);
1684 alloc_reg_temp(current,i,-1);
1685 minimum_free_regs[i]=1;
1690 // Load to r0 or unneeded register (dummy load)
1691 // but we still need a register to calculate the address
1692 if(opcode[i]==0x22||opcode[i]==0x26)
1694 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1696 // If using TLB, need a register for pointer to the mapping table
1697 if(using_tlb) alloc_reg(current,i,TLREG);
1698 alloc_reg_temp(current,i,-1);
1699 minimum_free_regs[i]=1;
1700 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1702 alloc_all(current,i);
1703 alloc_reg64(current,i,FTEMP);
1704 minimum_free_regs[i]=HOST_REGS;
1709 void store_alloc(struct regstat *current,int i)
1711 clear_const(current,rs2[i]);
1712 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1713 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1714 alloc_reg(current,i,rs2[i]);
1715 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1716 alloc_reg64(current,i,rs2[i]);
1717 if(rs2[i]) alloc_reg(current,i,FTEMP);
1719 // If using TLB, need a register for pointer to the mapping table
1720 if(using_tlb) alloc_reg(current,i,TLREG);
1721 #if defined(HOST_IMM8)
1722 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1723 else alloc_reg(current,i,INVCP);
1725 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1726 alloc_reg(current,i,FTEMP);
1728 // We need a temporary register for address generation
1729 alloc_reg_temp(current,i,-1);
1730 minimum_free_regs[i]=1;
1733 void c1ls_alloc(struct regstat *current,int i)
1735 //clear_const(current,rs1[i]); // FIXME
1736 clear_const(current,rt1[i]);
1737 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738 alloc_reg(current,i,CSREG); // Status
1739 alloc_reg(current,i,FTEMP);
1740 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1741 alloc_reg64(current,i,FTEMP);
1743 // If using TLB, need a register for pointer to the mapping table
1744 if(using_tlb) alloc_reg(current,i,TLREG);
1745 #if defined(HOST_IMM8)
1746 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1748 alloc_reg(current,i,INVCP);
1750 // We need a temporary register for address generation
1751 alloc_reg_temp(current,i,-1);
1754 void c2ls_alloc(struct regstat *current,int i)
1756 clear_const(current,rt1[i]);
1757 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1758 alloc_reg(current,i,FTEMP);
1759 // If using TLB, need a register for pointer to the mapping table
1760 if(using_tlb) alloc_reg(current,i,TLREG);
1761 #if defined(HOST_IMM8)
1762 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1763 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1764 alloc_reg(current,i,INVCP);
1766 // We need a temporary register for address generation
1767 alloc_reg_temp(current,i,-1);
1768 minimum_free_regs[i]=1;
1771 #ifndef multdiv_alloc
1772 void multdiv_alloc(struct regstat *current,int i)
1779 // case 0x1D: DMULTU
1782 clear_const(current,rs1[i]);
1783 clear_const(current,rs2[i]);
1786 if((opcode2[i]&4)==0) // 32-bit
1788 current->u&=~(1LL<<HIREG);
1789 current->u&=~(1LL<<LOREG);
1790 alloc_reg(current,i,HIREG);
1791 alloc_reg(current,i,LOREG);
1792 alloc_reg(current,i,rs1[i]);
1793 alloc_reg(current,i,rs2[i]);
1794 current->is32|=1LL<<HIREG;
1795 current->is32|=1LL<<LOREG;
1796 dirty_reg(current,HIREG);
1797 dirty_reg(current,LOREG);
1801 current->u&=~(1LL<<HIREG);
1802 current->u&=~(1LL<<LOREG);
1803 current->uu&=~(1LL<<HIREG);
1804 current->uu&=~(1LL<<LOREG);
1805 alloc_reg64(current,i,HIREG);
1806 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1807 alloc_reg64(current,i,rs1[i]);
1808 alloc_reg64(current,i,rs2[i]);
1809 alloc_all(current,i);
1810 current->is32&=~(1LL<<HIREG);
1811 current->is32&=~(1LL<<LOREG);
1812 dirty_reg(current,HIREG);
1813 dirty_reg(current,LOREG);
1814 minimum_free_regs[i]=HOST_REGS;
1819 // Multiply by zero is zero.
1820 // MIPS does not have a divide by zero exception.
1821 // The result is undefined, we return zero.
1822 alloc_reg(current,i,HIREG);
1823 alloc_reg(current,i,LOREG);
1824 current->is32|=1LL<<HIREG;
1825 current->is32|=1LL<<LOREG;
1826 dirty_reg(current,HIREG);
1827 dirty_reg(current,LOREG);
1832 void cop0_alloc(struct regstat *current,int i)
1834 if(opcode2[i]==0) // MFC0
1837 clear_const(current,rt1[i]);
1838 alloc_all(current,i);
1839 alloc_reg(current,i,rt1[i]);
1840 current->is32|=1LL<<rt1[i];
1841 dirty_reg(current,rt1[i]);
1844 else if(opcode2[i]==4) // MTC0
1847 clear_const(current,rs1[i]);
1848 alloc_reg(current,i,rs1[i]);
1849 alloc_all(current,i);
1852 alloc_all(current,i); // FIXME: Keep r0
1854 alloc_reg(current,i,0);
1859 // TLBR/TLBWI/TLBWR/TLBP/ERET
1860 assert(opcode2[i]==0x10);
1861 alloc_all(current,i);
1863 minimum_free_regs[i]=HOST_REGS;
1866 void cop1_alloc(struct regstat *current,int i)
1868 alloc_reg(current,i,CSREG); // Load status
1869 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1872 clear_const(current,rt1[i]);
1874 alloc_reg64(current,i,rt1[i]); // DMFC1
1875 current->is32&=~(1LL<<rt1[i]);
1877 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1878 current->is32|=1LL<<rt1[i];
1880 dirty_reg(current,rt1[i]);
1882 alloc_reg_temp(current,i,-1);
1884 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1887 clear_const(current,rs1[i]);
1889 alloc_reg64(current,i,rs1[i]); // DMTC1
1891 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1892 alloc_reg_temp(current,i,-1);
1896 alloc_reg(current,i,0);
1897 alloc_reg_temp(current,i,-1);
1900 minimum_free_regs[i]=1;
1902 void fconv_alloc(struct regstat *current,int i)
1904 alloc_reg(current,i,CSREG); // Load status
1905 alloc_reg_temp(current,i,-1);
1906 minimum_free_regs[i]=1;
1908 void float_alloc(struct regstat *current,int i)
1910 alloc_reg(current,i,CSREG); // Load status
1911 alloc_reg_temp(current,i,-1);
1912 minimum_free_regs[i]=1;
1914 void c2op_alloc(struct regstat *current,int i)
1916 alloc_reg_temp(current,i,-1);
1918 void fcomp_alloc(struct regstat *current,int i)
1920 alloc_reg(current,i,CSREG); // Load status
1921 alloc_reg(current,i,FSREG); // Load flags
1922 dirty_reg(current,FSREG); // Flag will be modified
1923 alloc_reg_temp(current,i,-1);
1924 minimum_free_regs[i]=1;
1927 void syscall_alloc(struct regstat *current,int i)
1929 alloc_cc(current,i);
1930 dirty_reg(current,CCREG);
1931 alloc_all(current,i);
1932 minimum_free_regs[i]=HOST_REGS;
1936 void delayslot_alloc(struct regstat *current,int i)
1947 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1948 printf("Disabled speculative precompilation\n");
1952 imm16_alloc(current,i);
1956 load_alloc(current,i);
1960 store_alloc(current,i);
1963 alu_alloc(current,i);
1966 shift_alloc(current,i);
1969 multdiv_alloc(current,i);
1972 shiftimm_alloc(current,i);
1975 mov_alloc(current,i);
1978 cop0_alloc(current,i);
1982 cop1_alloc(current,i);
1985 c1ls_alloc(current,i);
1988 c2ls_alloc(current,i);
1991 fconv_alloc(current,i);
1994 float_alloc(current,i);
1997 fcomp_alloc(current,i);
2000 c2op_alloc(current,i);
2005 // Special case where a branch and delay slot span two pages in virtual memory
2006 static void pagespan_alloc(struct regstat *current,int i)
2009 current->wasconst=0;
2011 minimum_free_regs[i]=HOST_REGS;
2012 alloc_all(current,i);
2013 alloc_cc(current,i);
2014 dirty_reg(current,CCREG);
2015 if(opcode[i]==3) // JAL
2017 alloc_reg(current,i,31);
2018 dirty_reg(current,31);
2020 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2022 alloc_reg(current,i,rs1[i]);
2024 alloc_reg(current,i,rt1[i]);
2025 dirty_reg(current,rt1[i]);
2028 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2030 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2031 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2032 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2034 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2035 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2039 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2041 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2042 if(!((current->is32>>rs1[i])&1))
2044 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2048 if(opcode[i]==0x11) // BC1
2050 alloc_reg(current,i,FSREG);
2051 alloc_reg(current,i,CSREG);
2056 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2058 stubs[stubcount][0]=type;
2059 stubs[stubcount][1]=addr;
2060 stubs[stubcount][2]=retaddr;
2061 stubs[stubcount][3]=a;
2062 stubs[stubcount][4]=b;
2063 stubs[stubcount][5]=c;
2064 stubs[stubcount][6]=d;
2065 stubs[stubcount][7]=e;
2069 // Write out a single register
2070 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2073 for(hr=0;hr<HOST_REGS;hr++) {
2074 if(hr!=EXCLUDE_REG) {
2075 if((regmap[hr]&63)==r) {
2078 emit_storereg(r,hr);
2080 if((is32>>regmap[hr])&1) {
2081 emit_sarimm(hr,31,hr);
2082 emit_storereg(r|64,hr);
2086 emit_storereg(r|64,hr);
2096 //if(!tracedebug) return 0;
2099 for(i=0;i<2097152;i++) {
2100 unsigned int temp=sum;
2103 sum^=((u_int *)rdram)[i];
2112 sum^=((u_int *)reg)[i];
2120 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2122 #ifndef DISABLE_COP1
2125 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2135 void memdebug(int i)
2137 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2138 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2141 //if(Count>=-2084597794) {
2142 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2144 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2145 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2146 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2149 printf("TRACE: %x\n",(&i)[-1]);
2153 printf("TRACE: %x \n",(&j)[10]);
2154 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2158 //printf("TRACE: %x\n",(&i)[-1]);
2161 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2163 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2166 void alu_assemble(int i,struct regstat *i_regs)
2168 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2170 signed char s1,s2,t;
2171 t=get_reg(i_regs->regmap,rt1[i]);
2173 s1=get_reg(i_regs->regmap,rs1[i]);
2174 s2=get_reg(i_regs->regmap,rs2[i]);
2175 if(rs1[i]&&rs2[i]) {
2178 if(opcode2[i]&2) emit_sub(s1,s2,t);
2179 else emit_add(s1,s2,t);
2182 if(s1>=0) emit_mov(s1,t);
2183 else emit_loadreg(rs1[i],t);
2187 if(opcode2[i]&2) emit_neg(s2,t);
2188 else emit_mov(s2,t);
2191 emit_loadreg(rs2[i],t);
2192 if(opcode2[i]&2) emit_neg(t,t);
2195 else emit_zeroreg(t);
2199 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2201 signed char s1l,s2l,s1h,s2h,tl,th;
2202 tl=get_reg(i_regs->regmap,rt1[i]);
2203 th=get_reg(i_regs->regmap,rt1[i]|64);
2205 s1l=get_reg(i_regs->regmap,rs1[i]);
2206 s2l=get_reg(i_regs->regmap,rs2[i]);
2207 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2208 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2209 if(rs1[i]&&rs2[i]) {
2212 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2213 else emit_adds(s1l,s2l,tl);
2215 #ifdef INVERTED_CARRY
2216 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2218 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2220 else emit_add(s1h,s2h,th);
2224 if(s1l>=0) emit_mov(s1l,tl);
2225 else emit_loadreg(rs1[i],tl);
2227 if(s1h>=0) emit_mov(s1h,th);
2228 else emit_loadreg(rs1[i]|64,th);
2233 if(opcode2[i]&2) emit_negs(s2l,tl);
2234 else emit_mov(s2l,tl);
2237 emit_loadreg(rs2[i],tl);
2238 if(opcode2[i]&2) emit_negs(tl,tl);
2241 #ifdef INVERTED_CARRY
2242 if(s2h>=0) emit_mov(s2h,th);
2243 else emit_loadreg(rs2[i]|64,th);
2245 emit_adcimm(-1,th); // x86 has inverted carry flag
2250 if(s2h>=0) emit_rscimm(s2h,0,th);
2252 emit_loadreg(rs2[i]|64,th);
2253 emit_rscimm(th,0,th);
2256 if(s2h>=0) emit_mov(s2h,th);
2257 else emit_loadreg(rs2[i]|64,th);
2264 if(th>=0) emit_zeroreg(th);
2269 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2271 signed char s1l,s1h,s2l,s2h,t;
2272 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2274 t=get_reg(i_regs->regmap,rt1[i]);
2277 s1l=get_reg(i_regs->regmap,rs1[i]);
2278 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2279 s2l=get_reg(i_regs->regmap,rs2[i]);
2280 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2281 if(rs2[i]==0) // rx<r0
2284 if(opcode2[i]==0x2a) // SLT
2285 emit_shrimm(s1h,31,t);
2286 else // SLTU (unsigned can not be less than zero)
2289 else if(rs1[i]==0) // r0<rx
2292 if(opcode2[i]==0x2a) // SLT
2293 emit_set_gz64_32(s2h,s2l,t);
2294 else // SLTU (set if not zero)
2295 emit_set_nz64_32(s2h,s2l,t);
2298 assert(s1l>=0);assert(s1h>=0);
2299 assert(s2l>=0);assert(s2h>=0);
2300 if(opcode2[i]==0x2a) // SLT
2301 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2303 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2307 t=get_reg(i_regs->regmap,rt1[i]);
2310 s1l=get_reg(i_regs->regmap,rs1[i]);
2311 s2l=get_reg(i_regs->regmap,rs2[i]);
2312 if(rs2[i]==0) // rx<r0
2315 if(opcode2[i]==0x2a) // SLT
2316 emit_shrimm(s1l,31,t);
2317 else // SLTU (unsigned can not be less than zero)
2320 else if(rs1[i]==0) // r0<rx
2323 if(opcode2[i]==0x2a) // SLT
2324 emit_set_gz32(s2l,t);
2325 else // SLTU (set if not zero)
2326 emit_set_nz32(s2l,t);
2329 assert(s1l>=0);assert(s2l>=0);
2330 if(opcode2[i]==0x2a) // SLT
2331 emit_set_if_less32(s1l,s2l,t);
2333 emit_set_if_carry32(s1l,s2l,t);
2339 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2341 signed char s1l,s1h,s2l,s2h,th,tl;
2342 tl=get_reg(i_regs->regmap,rt1[i]);
2343 th=get_reg(i_regs->regmap,rt1[i]|64);
2344 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2348 s1l=get_reg(i_regs->regmap,rs1[i]);
2349 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2350 s2l=get_reg(i_regs->regmap,rs2[i]);
2351 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2352 if(rs1[i]&&rs2[i]) {
2353 assert(s1l>=0);assert(s1h>=0);
2354 assert(s2l>=0);assert(s2h>=0);
2355 if(opcode2[i]==0x24) { // AND
2356 emit_and(s1l,s2l,tl);
2357 emit_and(s1h,s2h,th);
2359 if(opcode2[i]==0x25) { // OR
2360 emit_or(s1l,s2l,tl);
2361 emit_or(s1h,s2h,th);
2363 if(opcode2[i]==0x26) { // XOR
2364 emit_xor(s1l,s2l,tl);
2365 emit_xor(s1h,s2h,th);
2367 if(opcode2[i]==0x27) { // NOR
2368 emit_or(s1l,s2l,tl);
2369 emit_or(s1h,s2h,th);
2376 if(opcode2[i]==0x24) { // AND
2380 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2382 if(s1l>=0) emit_mov(s1l,tl);
2383 else emit_loadreg(rs1[i],tl);
2384 if(s1h>=0) emit_mov(s1h,th);
2385 else emit_loadreg(rs1[i]|64,th);
2389 if(s2l>=0) emit_mov(s2l,tl);
2390 else emit_loadreg(rs2[i],tl);
2391 if(s2h>=0) emit_mov(s2h,th);
2392 else emit_loadreg(rs2[i]|64,th);
2399 if(opcode2[i]==0x27) { // NOR
2401 if(s1l>=0) emit_not(s1l,tl);
2403 emit_loadreg(rs1[i],tl);
2406 if(s1h>=0) emit_not(s1h,th);
2408 emit_loadreg(rs1[i]|64,th);
2414 if(s2l>=0) emit_not(s2l,tl);
2416 emit_loadreg(rs2[i],tl);
2419 if(s2h>=0) emit_not(s2h,th);
2421 emit_loadreg(rs2[i]|64,th);
2437 s1l=get_reg(i_regs->regmap,rs1[i]);
2438 s2l=get_reg(i_regs->regmap,rs2[i]);
2439 if(rs1[i]&&rs2[i]) {
2442 if(opcode2[i]==0x24) { // AND
2443 emit_and(s1l,s2l,tl);
2445 if(opcode2[i]==0x25) { // OR
2446 emit_or(s1l,s2l,tl);
2448 if(opcode2[i]==0x26) { // XOR
2449 emit_xor(s1l,s2l,tl);
2451 if(opcode2[i]==0x27) { // NOR
2452 emit_or(s1l,s2l,tl);
2458 if(opcode2[i]==0x24) { // AND
2461 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2463 if(s1l>=0) emit_mov(s1l,tl);
2464 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2468 if(s2l>=0) emit_mov(s2l,tl);
2469 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2471 else emit_zeroreg(tl);
2473 if(opcode2[i]==0x27) { // NOR
2475 if(s1l>=0) emit_not(s1l,tl);
2477 emit_loadreg(rs1[i],tl);
2483 if(s2l>=0) emit_not(s2l,tl);
2485 emit_loadreg(rs2[i],tl);
2489 else emit_movimm(-1,tl);
2498 void imm16_assemble(int i,struct regstat *i_regs)
2500 if (opcode[i]==0x0f) { // LUI
2503 t=get_reg(i_regs->regmap,rt1[i]);
2506 if(!((i_regs->isconst>>t)&1))
2507 emit_movimm(imm[i]<<16,t);
2511 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2514 t=get_reg(i_regs->regmap,rt1[i]);
2515 s=get_reg(i_regs->regmap,rs1[i]);
2520 if(!((i_regs->isconst>>t)&1)) {
2522 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523 emit_addimm(t,imm[i],t);
2525 if(!((i_regs->wasconst>>s)&1))
2526 emit_addimm(s,imm[i],t);
2528 emit_movimm(constmap[i][s]+imm[i],t);
2534 if(!((i_regs->isconst>>t)&1))
2535 emit_movimm(imm[i],t);
2540 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2542 signed char sh,sl,th,tl;
2543 th=get_reg(i_regs->regmap,rt1[i]|64);
2544 tl=get_reg(i_regs->regmap,rt1[i]);
2545 sh=get_reg(i_regs->regmap,rs1[i]|64);
2546 sl=get_reg(i_regs->regmap,rs1[i]);
2552 emit_addimm64_32(sh,sl,imm[i],th,tl);
2555 emit_addimm(sl,imm[i],tl);
2558 emit_movimm(imm[i],tl);
2559 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2564 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2566 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2567 signed char sh,sl,t;
2568 t=get_reg(i_regs->regmap,rt1[i]);
2569 sh=get_reg(i_regs->regmap,rs1[i]|64);
2570 sl=get_reg(i_regs->regmap,rs1[i]);
2574 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2575 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2576 if(opcode[i]==0x0a) { // SLTI
2578 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2579 emit_slti32(t,imm[i],t);
2581 emit_slti32(sl,imm[i],t);
2586 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2587 emit_sltiu32(t,imm[i],t);
2589 emit_sltiu32(sl,imm[i],t);
2594 if(opcode[i]==0x0a) // SLTI
2595 emit_slti64_32(sh,sl,imm[i],t);
2597 emit_sltiu64_32(sh,sl,imm[i],t);
2600 // SLTI(U) with r0 is just stupid,
2601 // nonetheless examples can be found
2602 if(opcode[i]==0x0a) // SLTI
2603 if(0<imm[i]) emit_movimm(1,t);
2604 else emit_zeroreg(t);
2607 if(imm[i]) emit_movimm(1,t);
2608 else emit_zeroreg(t);
2614 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2616 signed char sh,sl,th,tl;
2617 th=get_reg(i_regs->regmap,rt1[i]|64);
2618 tl=get_reg(i_regs->regmap,rt1[i]);
2619 sh=get_reg(i_regs->regmap,rs1[i]|64);
2620 sl=get_reg(i_regs->regmap,rs1[i]);
2621 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2622 if(opcode[i]==0x0c) //ANDI
2626 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2627 emit_andimm(tl,imm[i],tl);
2629 if(!((i_regs->wasconst>>sl)&1))
2630 emit_andimm(sl,imm[i],tl);
2632 emit_movimm(constmap[i][sl]&imm[i],tl);
2637 if(th>=0) emit_zeroreg(th);
2643 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2647 emit_loadreg(rs1[i]|64,th);
2652 if(opcode[i]==0x0d) //ORI
2654 emit_orimm(tl,imm[i],tl);
2656 if(!((i_regs->wasconst>>sl)&1))
2657 emit_orimm(sl,imm[i],tl);
2659 emit_movimm(constmap[i][sl]|imm[i],tl);
2661 if(opcode[i]==0x0e) //XORI
2663 emit_xorimm(tl,imm[i],tl);
2665 if(!((i_regs->wasconst>>sl)&1))
2666 emit_xorimm(sl,imm[i],tl);
2668 emit_movimm(constmap[i][sl]^imm[i],tl);
2672 emit_movimm(imm[i],tl);
2673 if(th>=0) emit_zeroreg(th);
2681 void shiftimm_assemble(int i,struct regstat *i_regs)
2683 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2687 t=get_reg(i_regs->regmap,rt1[i]);
2688 s=get_reg(i_regs->regmap,rs1[i]);
2697 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2699 if(opcode2[i]==0) // SLL
2701 emit_shlimm(s<0?t:s,imm[i],t);
2703 if(opcode2[i]==2) // SRL
2705 emit_shrimm(s<0?t:s,imm[i],t);
2707 if(opcode2[i]==3) // SRA
2709 emit_sarimm(s<0?t:s,imm[i],t);
2713 if(s>=0 && s!=t) emit_mov(s,t);
2717 //emit_storereg(rt1[i],t); //DEBUG
2720 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2723 signed char sh,sl,th,tl;
2724 th=get_reg(i_regs->regmap,rt1[i]|64);
2725 tl=get_reg(i_regs->regmap,rt1[i]);
2726 sh=get_reg(i_regs->regmap,rs1[i]|64);
2727 sl=get_reg(i_regs->regmap,rs1[i]);
2732 if(th>=0) emit_zeroreg(th);
2739 if(opcode2[i]==0x38) // DSLL
2741 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2742 emit_shlimm(sl,imm[i],tl);
2744 if(opcode2[i]==0x3a) // DSRL
2746 emit_shrdimm(sl,sh,imm[i],tl);
2747 if(th>=0) emit_shrimm(sh,imm[i],th);
2749 if(opcode2[i]==0x3b) // DSRA
2751 emit_shrdimm(sl,sh,imm[i],tl);
2752 if(th>=0) emit_sarimm(sh,imm[i],th);
2756 if(sl!=tl) emit_mov(sl,tl);
2757 if(th>=0&&sh!=th) emit_mov(sh,th);
2763 if(opcode2[i]==0x3c) // DSLL32
2766 signed char sl,tl,th;
2767 tl=get_reg(i_regs->regmap,rt1[i]);
2768 th=get_reg(i_regs->regmap,rt1[i]|64);
2769 sl=get_reg(i_regs->regmap,rs1[i]);
2778 emit_shlimm(th,imm[i]&31,th);
2783 if(opcode2[i]==0x3e) // DSRL32
2786 signed char sh,tl,th;
2787 tl=get_reg(i_regs->regmap,rt1[i]);
2788 th=get_reg(i_regs->regmap,rt1[i]|64);
2789 sh=get_reg(i_regs->regmap,rs1[i]|64);
2793 if(th>=0) emit_zeroreg(th);
2796 emit_shrimm(tl,imm[i]&31,tl);
2801 if(opcode2[i]==0x3f) // DSRA32
2805 tl=get_reg(i_regs->regmap,rt1[i]);
2806 sh=get_reg(i_regs->regmap,rs1[i]|64);
2812 emit_sarimm(tl,imm[i]&31,tl);
2819 #ifndef shift_assemble
2820 void shift_assemble(int i,struct regstat *i_regs)
2822 printf("Need shift_assemble for this architecture.\n");
2827 void load_assemble(int i,struct regstat *i_regs)
2829 int s,th,tl,addr,map=-1;
2832 int memtarget=0,c=0;
2833 int fastload_reg_override=0;
2835 th=get_reg(i_regs->regmap,rt1[i]|64);
2836 tl=get_reg(i_regs->regmap,rt1[i]);
2837 s=get_reg(i_regs->regmap,rs1[i]);
2839 for(hr=0;hr<HOST_REGS;hr++) {
2840 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2842 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2844 c=(i_regs->wasconst>>s)&1;
2846 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2847 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2850 //printf("load_assemble: c=%d\n",c);
2851 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2852 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2854 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2856 // could be FIFO, must perform the read
2858 assem_debug("(forced read)\n");
2859 tl=get_reg(i_regs->regmap,-1);
2863 if(offset||s<0||c) addr=tl;
2865 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2867 //printf("load_assemble: c=%d\n",c);
2868 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2869 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2871 if(th>=0) reglist&=~(1<<th);
2875 map=get_reg(i_regs->regmap,ROREG);
2876 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2878 //#define R29_HACK 1
2880 // Strmnnrmn's speed hack
2881 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2885 if(sp_in_mirror&&rs1[i]==29) {
2886 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2887 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2888 fastload_reg_override=HOST_TEMPREG;
2892 emit_cmpimm(addr,RAM_SIZE);
2894 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2895 // Hint to branch predictor that the branch is unlikely to be taken
2897 emit_jno_unlikely(0);
2905 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2906 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2907 map=get_reg(i_regs->regmap,TLREG);
2910 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2911 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2913 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2914 if (opcode[i]==0x20) { // LB
2917 #ifdef HOST_IMM_ADDR32
2919 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2923 //emit_xorimm(addr,3,tl);
2924 //gen_tlb_addr_r(tl,map);
2925 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2927 #ifdef BIG_ENDIAN_MIPS
2928 if(!c) emit_xorimm(addr,3,tl);
2929 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2933 if(fastload_reg_override) a=fastload_reg_override;
2935 emit_movsbl_indexed_tlb(x,a,map,tl);
2939 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2942 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2944 if (opcode[i]==0x21) { // LH
2947 #ifdef HOST_IMM_ADDR32
2949 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2954 #ifdef BIG_ENDIAN_MIPS
2955 if(!c) emit_xorimm(addr,2,tl);
2956 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2960 if(fastload_reg_override) a=fastload_reg_override;
2962 //emit_movswl_indexed_tlb(x,tl,map,tl);
2965 gen_tlb_addr_r(a,map);
2966 emit_movswl_indexed(x,a,tl);
2969 emit_movswl_indexed(x,a,tl);
2971 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2977 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2980 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2982 if (opcode[i]==0x23) { // LW
2986 if(fastload_reg_override) a=fastload_reg_override;
2987 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2988 #ifdef HOST_IMM_ADDR32
2990 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2993 emit_readword_indexed_tlb(0,a,map,tl);
2996 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2999 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3001 if (opcode[i]==0x24) { // LBU
3004 #ifdef HOST_IMM_ADDR32
3006 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3010 //emit_xorimm(addr,3,tl);
3011 //gen_tlb_addr_r(tl,map);
3012 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3014 #ifdef BIG_ENDIAN_MIPS
3015 if(!c) emit_xorimm(addr,3,tl);
3016 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3020 if(fastload_reg_override) a=fastload_reg_override;
3022 emit_movzbl_indexed_tlb(x,a,map,tl);
3026 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3029 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3031 if (opcode[i]==0x25) { // LHU
3034 #ifdef HOST_IMM_ADDR32
3036 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3041 #ifdef BIG_ENDIAN_MIPS
3042 if(!c) emit_xorimm(addr,2,tl);
3043 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3047 if(fastload_reg_override) a=fastload_reg_override;
3049 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3052 gen_tlb_addr_r(a,map);
3053 emit_movzwl_indexed(x,a,tl);
3056 emit_movzwl_indexed(x,a,tl);
3058 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3064 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3067 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3069 if (opcode[i]==0x27) { // LWU
3074 if(fastload_reg_override) a=fastload_reg_override;
3075 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3076 #ifdef HOST_IMM_ADDR32
3078 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3081 emit_readword_indexed_tlb(0,a,map,tl);
3084 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3087 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3091 if (opcode[i]==0x37) { // LD
3095 if(fastload_reg_override) a=fastload_reg_override;
3096 //gen_tlb_addr_r(tl,map);
3097 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3098 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3099 #ifdef HOST_IMM_ADDR32
3101 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3104 emit_readdword_indexed_tlb(0,a,map,th,tl);
3107 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3110 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3113 //emit_storereg(rt1[i],tl); // DEBUG
3114 //if(opcode[i]==0x23)
3115 //if(opcode[i]==0x24)
3116 //if(opcode[i]==0x23||opcode[i]==0x24)
3117 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3121 emit_readword((int)&last_count,ECX);
3123 if(get_reg(i_regs->regmap,CCREG)<0)
3124 emit_loadreg(CCREG,HOST_CCREG);
3125 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3126 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3127 emit_writeword(HOST_CCREG,(int)&Count);
3130 if(get_reg(i_regs->regmap,CCREG)<0)
3131 emit_loadreg(CCREG,0);
3133 emit_mov(HOST_CCREG,0);
3135 emit_addimm(0,2*ccadj[i],0);
3136 emit_writeword(0,(int)&Count);
3138 emit_call((int)memdebug);
3140 restore_regs(0x100f);
3144 #ifndef loadlr_assemble
3145 void loadlr_assemble(int i,struct regstat *i_regs)
3147 printf("Need loadlr_assemble for this architecture.\n");
3152 void store_assemble(int i,struct regstat *i_regs)
3157 int jaddr=0,jaddr2,type;
3158 int memtarget=0,c=0;
3159 int agr=AGEN1+(i&1);
3160 int faststore_reg_override=0;
3162 th=get_reg(i_regs->regmap,rs2[i]|64);
3163 tl=get_reg(i_regs->regmap,rs2[i]);
3164 s=get_reg(i_regs->regmap,rs1[i]);
3165 temp=get_reg(i_regs->regmap,agr);
3166 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3169 c=(i_regs->wasconst>>s)&1;
3171 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3172 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3177 for(hr=0;hr<HOST_REGS;hr++) {
3178 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3180 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3181 if(offset||s<0||c) addr=temp;
3186 if(sp_in_mirror&&rs1[i]==29) {
3187 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3188 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3189 faststore_reg_override=HOST_TEMPREG;
3194 // Strmnnrmn's speed hack
3195 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3197 emit_cmpimm(addr,RAM_SIZE);
3198 #ifdef DESTRUCTIVE_SHIFT
3199 if(s==addr) emit_mov(s,temp);
3203 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3207 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3208 // Hint to branch predictor that the branch is unlikely to be taken
3210 emit_jno_unlikely(0);
3218 if (opcode[i]==0x28) x=3; // SB
3219 if (opcode[i]==0x29) x=2; // SH
3220 map=get_reg(i_regs->regmap,TLREG);
3223 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3224 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3227 if (opcode[i]==0x28) { // SB
3230 #ifdef BIG_ENDIAN_MIPS
3231 if(!c) emit_xorimm(addr,3,temp);
3232 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3236 if(faststore_reg_override) a=faststore_reg_override;
3237 //gen_tlb_addr_w(temp,map);
3238 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3239 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3243 if (opcode[i]==0x29) { // SH
3246 #ifdef BIG_ENDIAN_MIPS
3247 if(!c) emit_xorimm(addr,2,temp);
3248 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3252 if(faststore_reg_override) a=faststore_reg_override;
3254 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3257 gen_tlb_addr_w(a,map);
3258 emit_writehword_indexed(tl,x,a);
3260 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3264 if (opcode[i]==0x2B) { // SW
3267 if(faststore_reg_override) a=faststore_reg_override;
3268 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3269 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3273 if (opcode[i]==0x3F) { // SD
3276 if(faststore_reg_override) a=faststore_reg_override;
3279 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3280 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3281 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3284 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3285 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3286 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3293 // PCSX store handlers don't check invcode again
3295 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3301 #ifdef DESTRUCTIVE_SHIFT
3302 // The x86 shift operation is 'destructive'; it overwrites the
3303 // source register, so we need to make a copy first and use that.
3306 #if defined(HOST_IMM8)
3307 int ir=get_reg(i_regs->regmap,INVCP);
3309 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3311 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3313 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3314 emit_callne(invalidate_addr_reg[addr]);
3318 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3323 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3324 } else if(c&&!memtarget) {
3325 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3327 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3328 //if(opcode[i]==0x2B || opcode[i]==0x28)
3329 //if(opcode[i]==0x2B || opcode[i]==0x29)
3330 //if(opcode[i]==0x2B)
3331 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3339 emit_readword((int)&last_count,ECX);
3341 if(get_reg(i_regs->regmap,CCREG)<0)
3342 emit_loadreg(CCREG,HOST_CCREG);
3343 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3344 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3345 emit_writeword(HOST_CCREG,(int)&Count);
3348 if(get_reg(i_regs->regmap,CCREG)<0)
3349 emit_loadreg(CCREG,0);
3351 emit_mov(HOST_CCREG,0);
3353 emit_addimm(0,2*ccadj[i],0);
3354 emit_writeword(0,(int)&Count);
3356 emit_call((int)memdebug);
3361 restore_regs(0x100f);
3366 void storelr_assemble(int i,struct regstat *i_regs)
3373 int case1,case2,case3;
3374 int done0,done1,done2;
3375 int memtarget=0,c=0;
3376 int agr=AGEN1+(i&1);
3378 th=get_reg(i_regs->regmap,rs2[i]|64);
3379 tl=get_reg(i_regs->regmap,rs2[i]);
3380 s=get_reg(i_regs->regmap,rs1[i]);
3381 temp=get_reg(i_regs->regmap,agr);
3382 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3385 c=(i_regs->isconst>>s)&1;
3387 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3388 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3392 for(hr=0;hr<HOST_REGS;hr++) {
3393 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3398 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3399 if(!offset&&s!=temp) emit_mov(s,temp);
3405 if(!memtarget||!rs1[i]) {
3411 int map=get_reg(i_regs->regmap,ROREG);
3412 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3413 gen_tlb_addr_w(temp,map);
3415 if((u_int)rdram!=0x80000000)
3416 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3419 int map=get_reg(i_regs->regmap,TLREG);
3422 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3423 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3424 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3425 if(!jaddr&&!memtarget) {
3429 gen_tlb_addr_w(temp,map);
3432 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3433 temp2=get_reg(i_regs->regmap,FTEMP);
3434 if(!rs2[i]) temp2=th=tl;
3437 #ifndef BIG_ENDIAN_MIPS
3438 emit_xorimm(temp,3,temp);
3440 emit_testimm(temp,2);
3443 emit_testimm(temp,1);
3447 if (opcode[i]==0x2A) { // SWL
3448 emit_writeword_indexed(tl,0,temp);
3450 if (opcode[i]==0x2E) { // SWR
3451 emit_writebyte_indexed(tl,3,temp);
3453 if (opcode[i]==0x2C) { // SDL
3454 emit_writeword_indexed(th,0,temp);
3455 if(rs2[i]) emit_mov(tl,temp2);
3457 if (opcode[i]==0x2D) { // SDR
3458 emit_writebyte_indexed(tl,3,temp);
3459 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3464 set_jump_target(case1,(int)out);
3465 if (opcode[i]==0x2A) { // SWL
3466 // Write 3 msb into three least significant bytes
3467 if(rs2[i]) emit_rorimm(tl,8,tl);
3468 emit_writehword_indexed(tl,-1,temp);
3469 if(rs2[i]) emit_rorimm(tl,16,tl);
3470 emit_writebyte_indexed(tl,1,temp);
3471 if(rs2[i]) emit_rorimm(tl,8,tl);
3473 if (opcode[i]==0x2E) { // SWR
3474 // Write two lsb into two most significant bytes
3475 emit_writehword_indexed(tl,1,temp);
3477 if (opcode[i]==0x2C) { // SDL
3478 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3479 // Write 3 msb into three least significant bytes
3480 if(rs2[i]) emit_rorimm(th,8,th);
3481 emit_writehword_indexed(th,-1,temp);
3482 if(rs2[i]) emit_rorimm(th,16,th);
3483 emit_writebyte_indexed(th,1,temp);
3484 if(rs2[i]) emit_rorimm(th,8,th);
3486 if (opcode[i]==0x2D) { // SDR
3487 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3488 // Write two lsb into two most significant bytes
3489 emit_writehword_indexed(tl,1,temp);
3494 set_jump_target(case2,(int)out);
3495 emit_testimm(temp,1);
3498 if (opcode[i]==0x2A) { // SWL
3499 // Write two msb into two least significant bytes
3500 if(rs2[i]) emit_rorimm(tl,16,tl);
3501 emit_writehword_indexed(tl,-2,temp);
3502 if(rs2[i]) emit_rorimm(tl,16,tl);
3504 if (opcode[i]==0x2E) { // SWR
3505 // Write 3 lsb into three most significant bytes
3506 emit_writebyte_indexed(tl,-1,temp);
3507 if(rs2[i]) emit_rorimm(tl,8,tl);
3508 emit_writehword_indexed(tl,0,temp);
3509 if(rs2[i]) emit_rorimm(tl,24,tl);
3511 if (opcode[i]==0x2C) { // SDL
3512 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3513 // Write two msb into two least significant bytes
3514 if(rs2[i]) emit_rorimm(th,16,th);
3515 emit_writehword_indexed(th,-2,temp);
3516 if(rs2[i]) emit_rorimm(th,16,th);
3518 if (opcode[i]==0x2D) { // SDR
3519 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3520 // Write 3 lsb into three most significant bytes
3521 emit_writebyte_indexed(tl,-1,temp);
3522 if(rs2[i]) emit_rorimm(tl,8,tl);
3523 emit_writehword_indexed(tl,0,temp);
3524 if(rs2[i]) emit_rorimm(tl,24,tl);
3529 set_jump_target(case3,(int)out);
3530 if (opcode[i]==0x2A) { // SWL
3531 // Write msb into least significant byte
3532 if(rs2[i]) emit_rorimm(tl,24,tl);
3533 emit_writebyte_indexed(tl,-3,temp);
3534 if(rs2[i]) emit_rorimm(tl,8,tl);
3536 if (opcode[i]==0x2E) { // SWR
3537 // Write entire word
3538 emit_writeword_indexed(tl,-3,temp);
3540 if (opcode[i]==0x2C) { // SDL
3541 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3542 // Write msb into least significant byte
3543 if(rs2[i]) emit_rorimm(th,24,th);
3544 emit_writebyte_indexed(th,-3,temp);
3545 if(rs2[i]) emit_rorimm(th,8,th);
3547 if (opcode[i]==0x2D) { // SDR
3548 if(rs2[i]) emit_mov(th,temp2);
3549 // Write entire word
3550 emit_writeword_indexed(tl,-3,temp);
3552 set_jump_target(done0,(int)out);
3553 set_jump_target(done1,(int)out);
3554 set_jump_target(done2,(int)out);
3555 if (opcode[i]==0x2C) { // SDL
3556 emit_testimm(temp,4);
3559 emit_andimm(temp,~3,temp);
3560 emit_writeword_indexed(temp2,4,temp);
3561 set_jump_target(done0,(int)out);
3563 if (opcode[i]==0x2D) { // SDR
3564 emit_testimm(temp,4);
3567 emit_andimm(temp,~3,temp);
3568 emit_writeword_indexed(temp2,-4,temp);
3569 set_jump_target(done0,(int)out);
3572 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3575 int map=get_reg(i_regs->regmap,ROREG);
3576 if(map<0) map=HOST_TEMPREG;
3577 gen_orig_addr_w(temp,map);
3579 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3581 #if defined(HOST_IMM8)
3582 int ir=get_reg(i_regs->regmap,INVCP);
3584 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3586 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3588 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3589 emit_callne(invalidate_addr_reg[temp]);
3593 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3598 //save_regs(0x100f);
3599 emit_readword((int)&last_count,ECX);
3600 if(get_reg(i_regs->regmap,CCREG)<0)
3601 emit_loadreg(CCREG,HOST_CCREG);
3602 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3603 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3604 emit_writeword(HOST_CCREG,(int)&Count);
3605 emit_call((int)memdebug);
3607 //restore_regs(0x100f);
3611 void c1ls_assemble(int i,struct regstat *i_regs)
3613 #ifndef DISABLE_COP1
3619 int jaddr,jaddr2=0,jaddr3,type;
3620 int agr=AGEN1+(i&1);
3622 th=get_reg(i_regs->regmap,FTEMP|64);
3623 tl=get_reg(i_regs->regmap,FTEMP);
3624 s=get_reg(i_regs->regmap,rs1[i]);
3625 temp=get_reg(i_regs->regmap,agr);
3626 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3631 for(hr=0;hr<HOST_REGS;hr++) {
3632 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3634 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3635 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3637 // Loads use a temporary register which we need to save
3640 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3644 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3645 //else c=(i_regs->wasconst>>s)&1;
3646 if(s>=0) c=(i_regs->wasconst>>s)&1;
3647 // Check cop1 unusable
3649 signed char rs=get_reg(i_regs->regmap,CSREG);
3651 emit_testimm(rs,0x20000000);
3654 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3657 if (opcode[i]==0x39) { // SWC1 (get float address)
3658 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3660 if (opcode[i]==0x3D) { // SDC1 (get double address)
3661 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3663 // Generate address + offset
3666 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3670 map=get_reg(i_regs->regmap,TLREG);
3673 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3674 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3676 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3677 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3680 if (opcode[i]==0x39) { // SWC1 (read float)
3681 emit_readword_indexed(0,tl,tl);
3683 if (opcode[i]==0x3D) { // SDC1 (read double)
3684 emit_readword_indexed(4,tl,th);
3685 emit_readword_indexed(0,tl,tl);
3687 if (opcode[i]==0x31) { // LWC1 (get target address)
3688 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3690 if (opcode[i]==0x35) { // LDC1 (get target address)
3691 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3698 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3700 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3702 #ifdef DESTRUCTIVE_SHIFT
3703 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3704 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3708 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3709 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3711 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3712 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3715 if (opcode[i]==0x31) { // LWC1
3716 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3717 //gen_tlb_addr_r(ar,map);
3718 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3719 #ifdef HOST_IMM_ADDR32
3720 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3723 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3726 if (opcode[i]==0x35) { // LDC1
3728 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3729 //gen_tlb_addr_r(ar,map);
3730 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3731 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3732 #ifdef HOST_IMM_ADDR32
3733 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3736 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3739 if (opcode[i]==0x39) { // SWC1
3740 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3741 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3744 if (opcode[i]==0x3D) { // SDC1
3746 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3747 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3748 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3752 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3753 #ifndef DESTRUCTIVE_SHIFT
3754 temp=offset||c||s<0?ar:s;
3756 #if defined(HOST_IMM8)
3757 int ir=get_reg(i_regs->regmap,INVCP);
3759 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3761 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3763 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3764 emit_callne(invalidate_addr_reg[temp]);
3768 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3772 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3773 if (opcode[i]==0x31) { // LWC1 (write float)
3774 emit_writeword_indexed(tl,0,temp);
3776 if (opcode[i]==0x35) { // LDC1 (write double)
3777 emit_writeword_indexed(th,4,temp);
3778 emit_writeword_indexed(tl,0,temp);
3780 //if(opcode[i]==0x39)
3781 /*if(opcode[i]==0x39||opcode[i]==0x31)
3784 emit_readword((int)&last_count,ECX);
3785 if(get_reg(i_regs->regmap,CCREG)<0)
3786 emit_loadreg(CCREG,HOST_CCREG);
3787 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3788 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3789 emit_writeword(HOST_CCREG,(int)&Count);
3790 emit_call((int)memdebug);
3794 cop1_unusable(i, i_regs);
3798 void c2ls_assemble(int i,struct regstat *i_regs)
3803 int memtarget=0,c=0;
3804 int jaddr2=0,jaddr3,type;
3805 int agr=AGEN1+(i&1);
3807 u_int copr=(source[i]>>16)&0x1f;
3808 s=get_reg(i_regs->regmap,rs1[i]);
3809 tl=get_reg(i_regs->regmap,FTEMP);
3815 for(hr=0;hr<HOST_REGS;hr++) {
3816 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3818 if(i_regs->regmap[HOST_CCREG]==CCREG)
3819 reglist&=~(1<<HOST_CCREG);
3822 if (opcode[i]==0x3a) { // SWC2
3823 ar=get_reg(i_regs->regmap,agr);
3824 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3829 if(s>=0) c=(i_regs->wasconst>>s)&1;
3830 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3831 if (!offset&&!c&&s>=0) ar=s;
3834 if (opcode[i]==0x3a) { // SWC2
3835 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3843 emit_jmp(0); // inline_readstub/inline_writestub?
3847 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3851 if (opcode[i]==0x32) { // LWC2
3852 #ifdef HOST_IMM_ADDR32
3853 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3856 emit_readword_indexed(0,ar,tl);
3858 if (opcode[i]==0x3a) { // SWC2
3859 #ifdef DESTRUCTIVE_SHIFT
3860 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3862 emit_writeword_indexed(tl,0,ar);
3866 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3867 if (opcode[i]==0x3a) { // SWC2
3868 #if defined(HOST_IMM8)
3869 int ir=get_reg(i_regs->regmap,INVCP);
3871 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3873 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3875 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3876 emit_callne(invalidate_addr_reg[ar]);
3880 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3883 if (opcode[i]==0x32) { // LWC2
3884 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3888 #ifndef multdiv_assemble
3889 void multdiv_assemble(int i,struct regstat *i_regs)
3891 printf("Need multdiv_assemble for this architecture.\n");
3896 void mov_assemble(int i,struct regstat *i_regs)
3898 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3899 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3901 signed char sh,sl,th,tl;
3902 th=get_reg(i_regs->regmap,rt1[i]|64);
3903 tl=get_reg(i_regs->regmap,rt1[i]);
3906 sh=get_reg(i_regs->regmap,rs1[i]|64);
3907 sl=get_reg(i_regs->regmap,rs1[i]);
3908 if(sl>=0) emit_mov(sl,tl);
3909 else emit_loadreg(rs1[i],tl);
3911 if(sh>=0) emit_mov(sh,th);
3912 else emit_loadreg(rs1[i]|64,th);
3918 #ifndef fconv_assemble
3919 void fconv_assemble(int i,struct regstat *i_regs)
3921 printf("Need fconv_assemble for this architecture.\n");
3927 void float_assemble(int i,struct regstat *i_regs)
3929 printf("Need float_assemble for this architecture.\n");
3934 void syscall_assemble(int i,struct regstat *i_regs)
3936 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3937 assert(ccreg==HOST_CCREG);
3938 assert(!is_delayslot);
3939 emit_movimm(start+i*4,EAX); // Get PC
3940 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3941 emit_jmp((int)jump_syscall_hle); // XXX
3944 void hlecall_assemble(int i,struct regstat *i_regs)
3946 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3947 assert(ccreg==HOST_CCREG);
3948 assert(!is_delayslot);
3949 emit_movimm(start+i*4+4,0); // Get PC
3950 emit_movimm((int)psxHLEt[source[i]&7],1);
3951 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3952 emit_jmp((int)jump_hlecall);
3955 void intcall_assemble(int i,struct regstat *i_regs)
3957 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3958 assert(ccreg==HOST_CCREG);
3959 assert(!is_delayslot);
3960 emit_movimm(start+i*4,0); // Get PC
3961 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3962 emit_jmp((int)jump_intcall);
3965 void ds_assemble(int i,struct regstat *i_regs)