1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
46 #define CLOCK_DIVIDER 2
50 signed char regmap_entry[HOST_REGS];
51 signed char regmap[HOST_REGS];
60 uint64_t constmap[HOST_REGS];
68 struct ll_entry *next;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
91 static int gte_reads_flags; // gte flag read encountered
94 char likely[MAXBLOCK];
97 uint64_t unneeded_reg[MAXBLOCK];
98 uint64_t unneeded_reg_upper[MAXBLOCK];
99 uint64_t branch_unneeded_reg[MAXBLOCK];
100 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
101 uint64_t p32[MAXBLOCK];
102 uint64_t pr32[MAXBLOCK];
103 signed char regmap_pre[MAXBLOCK][HOST_REGS];
104 signed char regmap[MAXBLOCK][HOST_REGS];
105 signed char regmap_entry[MAXBLOCK][HOST_REGS];
106 uint64_t constmap[MAXBLOCK][HOST_REGS];
107 struct regstat regs[MAXBLOCK];
108 struct regstat branch_regs[MAXBLOCK];
109 signed char minimum_free_regs[MAXBLOCK];
110 u_int needed_reg[MAXBLOCK];
111 uint64_t requires_32bit[MAXBLOCK];
112 u_int wont_dirty[MAXBLOCK];
113 u_int will_dirty[MAXBLOCK];
116 u_int instr_addr[MAXBLOCK];
117 u_int link_addr[MAXBLOCK][3];
119 u_int stubs[MAXBLOCK*3][8];
121 u_int literals[1024][2];
126 struct ll_entry *jump_in[4096];
127 struct ll_entry *jump_out[4096];
128 struct ll_entry *jump_dirty[4096];
129 u_int hash_table[65536][4] __attribute__((aligned(16)));
130 char shadow[1048576] __attribute__((aligned(16)));
136 static const u_int using_tlb=0;
138 static u_int sp_in_mirror;
139 int new_dynarec_did_compile;
140 u_int stop_after_jal;
141 extern u_char restore_candidate[512];
142 extern int cycle_count;
144 /* registers that may be allocated */
146 #define HIREG 32 // hi
147 #define LOREG 33 // lo
148 #define FSREG 34 // FPU status (FCSR)
149 #define CSREG 35 // Coprocessor status
150 #define CCREG 36 // Cycle count
151 #define INVCP 37 // Pointer to invalid_code
152 #define MMREG 38 // Pointer to memory_map
153 #define ROREG 39 // ram offset (if rdram!=0x80000000)
155 #define FTEMP 40 // FPU temporary register
156 #define PTEMP 41 // Prefetch temporary register
157 #define TLREG 42 // TLB mapping offset
158 #define RHASH 43 // Return address hash
159 #define RHTBL 44 // Return address hash table address
160 #define RTEMP 45 // JR/JALR address register
162 #define AGEN1 46 // Address generation temporary register
163 #define AGEN2 47 // Address generation temporary register
164 #define MGEN1 48 // Maptable address generation temporary register
165 #define MGEN2 49 // Maptable address generation temporary register
166 #define BTREG 50 // Branch target temporary register
168 /* instruction types */
169 #define NOP 0 // No operation
170 #define LOAD 1 // Load
171 #define STORE 2 // Store
172 #define LOADLR 3 // Unaligned load
173 #define STORELR 4 // Unaligned store
174 #define MOV 5 // Move
175 #define ALU 6 // Arithmetic/logic
176 #define MULTDIV 7 // Multiply/divide
177 #define SHIFT 8 // Shift by register
178 #define SHIFTIMM 9// Shift by immediate
179 #define IMM16 10 // 16-bit immediate
180 #define RJUMP 11 // Unconditional jump to register
181 #define UJUMP 12 // Unconditional jump
182 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
183 #define SJUMP 14 // Conditional branch (regimm format)
184 #define COP0 15 // Coprocessor 0
185 #define COP1 16 // Coprocessor 1
186 #define C1LS 17 // Coprocessor 1 load/store
187 #define FJUMP 18 // Conditional branch (floating point)
188 #define FLOAT 19 // Floating point unit
189 #define FCONV 20 // Convert integer to float
190 #define FCOMP 21 // Floating point compare (sets FSREG)
191 #define SYSCALL 22// SYSCALL
192 #define OTHER 23 // Other
193 #define SPAN 24 // Branch/delay slot spans 2 pages
194 #define NI 25 // Not implemented
195 #define HLECALL 26// PCSX fake opcodes for HLE
196 #define COP2 27 // Coprocessor 2 move
197 #define C2LS 28 // Coprocessor 2 load/store
198 #define C2OP 29 // Coprocessor 2 operation
199 #define INTCALL 30// Call interpreter to handle rare corner cases
208 #define LOADBU_STUB 7
209 #define LOADHU_STUB 8
210 #define STOREB_STUB 9
211 #define STOREH_STUB 10
212 #define STOREW_STUB 11
213 #define STORED_STUB 12
214 #define STORELR_STUB 13
215 #define INVCODE_STUB 14
223 int new_recompile_block(int addr);
224 void *get_addr_ht(u_int vaddr);
225 void invalidate_block(u_int block);
226 void invalidate_addr(u_int addr);
227 void remove_hash(int vaddr);
230 void dyna_linker_ds();
232 void verify_code_vm();
233 void verify_code_ds();
236 void fp_exception_ds();
238 void jump_syscall_hle();
242 void new_dyna_leave();
247 void read_nomem_new();
248 void read_nomemb_new();
249 void read_nomemh_new();
250 void read_nomemd_new();
251 void write_nomem_new();
252 void write_nomemb_new();
253 void write_nomemh_new();
254 void write_nomemd_new();
255 void write_rdram_new();
256 void write_rdramb_new();
257 void write_rdramh_new();
258 void write_rdramd_new();
259 extern u_int memory_map[1048576];
261 // Needed by assembler
262 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
263 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
264 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
265 void load_all_regs(signed char i_regmap[]);
266 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
267 void load_regs_entry(int t);
268 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
272 //#define DEBUG_CYCLE_COUNT 1
274 static void tlb_hacks()
278 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
282 switch (ROM_HEADER->Country_code&0xFF)
294 // Unknown country code
298 u_int rom_addr=(u_int)rom;
300 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
301 // in the lower 4G of memory to use this hack. Copy it if necessary.
302 if((void *)rom>(void *)0xffffffff) {
303 munmap(ROM_COPY, 67108864);
304 if(mmap(ROM_COPY, 12582912,
305 PROT_READ | PROT_WRITE,
306 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
307 -1, 0) <= 0) {printf("mmap() failed\n");}
308 memcpy(ROM_COPY,rom,12582912);
309 rom_addr=(u_int)ROM_COPY;
313 for(n=0x7F000;n<0x80000;n++) {
314 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
321 static u_int get_page(u_int vaddr)
324 u_int page=(vaddr^0x80000000)>>12;
326 u_int page=vaddr&~0xe0000000;
327 if (page < 0x1000000)
328 page &= ~0x0e00000; // RAM mirrors
332 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
334 if(page>2048) page=2048+(page&2047);
338 static u_int get_vpage(u_int vaddr)
340 u_int vpage=(vaddr^0x80000000)>>12;
342 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
344 if(vpage>2048) vpage=2048+(vpage&2047);
348 // Get address from virtual address
349 // This is called from the recompiled JR/JALR instructions
350 void *get_addr(u_int vaddr)
352 u_int page=get_page(vaddr);
353 u_int vpage=get_vpage(vaddr);
354 struct ll_entry *head;
355 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
358 if(head->vaddr==vaddr&&head->reg32==0) {
359 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
360 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363 ht_bin[1]=(int)head->addr;
369 head=jump_dirty[vpage];
371 if(head->vaddr==vaddr&&head->reg32==0) {
372 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
373 // Don't restore blocks which are about to expire from the cache
374 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
375 if(verify_dirty(head->addr)) {
376 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
377 invalid_code[vaddr>>12]=0;
378 inv_code_start=inv_code_end=~0;
379 memory_map[vaddr>>12]|=0x40000000;
382 if(tlb_LUT_r[vaddr>>12]) {
383 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
384 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
387 restore_candidate[vpage>>3]|=1<<(vpage&7);
389 else restore_candidate[page>>3]|=1<<(page&7);
390 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
391 if(ht_bin[0]==vaddr) {
392 ht_bin[1]=(int)head->addr; // Replace existing entry
398 ht_bin[1]=(int)head->addr;
406 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
407 int r=new_recompile_block(vaddr);
408 if(r==0) return get_addr(vaddr);
409 // Execute in unmapped page, generate pagefault execption
411 Cause=(vaddr<<31)|0x8;
412 EPC=(vaddr&1)?vaddr-5:vaddr;
414 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
415 EntryHi=BadVAddr&0xFFFFE000;
416 return get_addr_ht(0x80000000);
418 // Look up address in hash table first
419 void *get_addr_ht(u_int vaddr)
421 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
422 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
423 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
424 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
425 return get_addr(vaddr);
428 void *get_addr_32(u_int vaddr,u_int flags)
431 return get_addr(vaddr);
433 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
434 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
435 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
436 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
437 u_int page=get_page(vaddr);
438 u_int vpage=get_vpage(vaddr);
439 struct ll_entry *head;
442 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
443 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
447 ht_bin[1]=(int)head->addr;
449 }else if(ht_bin[2]==-1) {
450 ht_bin[3]=(int)head->addr;
453 //ht_bin[3]=ht_bin[1];
454 //ht_bin[2]=ht_bin[0];
455 //ht_bin[1]=(int)head->addr;
462 head=jump_dirty[vpage];
464 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
465 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
466 // Don't restore blocks which are about to expire from the cache
467 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
468 if(verify_dirty(head->addr)) {
469 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
470 invalid_code[vaddr>>12]=0;
471 inv_code_start=inv_code_end=~0;
472 memory_map[vaddr>>12]|=0x40000000;
475 if(tlb_LUT_r[vaddr>>12]) {
476 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
477 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
480 restore_candidate[vpage>>3]|=1<<(vpage&7);
482 else restore_candidate[page>>3]|=1<<(page&7);
484 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
486 ht_bin[1]=(int)head->addr;
488 }else if(ht_bin[2]==-1) {
489 ht_bin[3]=(int)head->addr;
492 //ht_bin[3]=ht_bin[1];
493 //ht_bin[2]=ht_bin[0];
494 //ht_bin[1]=(int)head->addr;
502 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
503 int r=new_recompile_block(vaddr);
504 if(r==0) return get_addr(vaddr);
505 // Execute in unmapped page, generate pagefault execption
507 Cause=(vaddr<<31)|0x8;
508 EPC=(vaddr&1)?vaddr-5:vaddr;
510 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
511 EntryHi=BadVAddr&0xFFFFE000;
512 return get_addr_ht(0x80000000);
516 void clear_all_regs(signed char regmap[])
519 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
522 signed char get_reg(signed char regmap[],int r)
525 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
529 // Find a register that is available for two consecutive cycles
530 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
533 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
537 int count_free_regs(signed char regmap[])
541 for(hr=0;hr<HOST_REGS;hr++)
543 if(hr!=EXCLUDE_REG) {
544 if(regmap[hr]<0) count++;
550 void dirty_reg(struct regstat *cur,signed char reg)
554 for (hr=0;hr<HOST_REGS;hr++) {
555 if((cur->regmap[hr]&63)==reg) {
561 // If we dirty the lower half of a 64 bit register which is now being
562 // sign-extended, we need to dump the upper half.
563 // Note: Do this only after completion of the instruction, because
564 // some instructions may need to read the full 64-bit value even if
565 // overwriting it (eg SLTI, DSRA32).
566 static void flush_dirty_uppers(struct regstat *cur)
569 for (hr=0;hr<HOST_REGS;hr++) {
570 if((cur->dirty>>hr)&1) {
573 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
578 void set_const(struct regstat *cur,signed char reg,uint64_t value)
582 for (hr=0;hr<HOST_REGS;hr++) {
583 if(cur->regmap[hr]==reg) {
585 cur->constmap[hr]=value;
587 else if((cur->regmap[hr]^64)==reg) {
589 cur->constmap[hr]=value>>32;
594 void clear_const(struct regstat *cur,signed char reg)
598 for (hr=0;hr<HOST_REGS;hr++) {
599 if((cur->regmap[hr]&63)==reg) {
600 cur->isconst&=~(1<<hr);
605 int is_const(struct regstat *cur,signed char reg)
610 for (hr=0;hr<HOST_REGS;hr++) {
611 if((cur->regmap[hr]&63)==reg) {
612 return (cur->isconst>>hr)&1;
617 uint64_t get_const(struct regstat *cur,signed char reg)
621 for (hr=0;hr<HOST_REGS;hr++) {
622 if(cur->regmap[hr]==reg) {
623 return cur->constmap[hr];
626 printf("Unknown constant in r%d\n",reg);
630 // Least soon needed registers
631 // Look at the next ten instructions and see which registers
632 // will be used. Try not to reallocate these.
633 void lsn(u_char hsn[], int i, int *preferred_reg)
643 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
645 // Don't go past an unconditonal jump
652 if(rs1[i+j]) hsn[rs1[i+j]]=j;
653 if(rs2[i+j]) hsn[rs2[i+j]]=j;
654 if(rt1[i+j]) hsn[rt1[i+j]]=j;
655 if(rt2[i+j]) hsn[rt2[i+j]]=j;
656 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
657 // Stores can allocate zero
661 // On some architectures stores need invc_ptr
662 #if defined(HOST_IMM8)
663 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
667 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
675 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
677 // Follow first branch
678 int t=(ba[i+b]-start)>>2;
679 j=7-b;if(t+j>=slen) j=slen-t-1;
682 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
683 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
684 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
685 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
688 // TODO: preferred register based on backward branch
690 // Delay slot should preferably not overwrite branch conditions or cycle count
691 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
692 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
693 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
699 // Coprocessor load/store needs FTEMP, even if not declared
700 if(itype[i]==C1LS||itype[i]==C2LS) {
703 // Load L/R also uses FTEMP as a temporary register
704 if(itype[i]==LOADLR) {
707 // Also SWL/SWR/SDL/SDR
708 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
711 // Don't remove the TLB registers either
712 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
715 // Don't remove the miniht registers
716 if(itype[i]==UJUMP||itype[i]==RJUMP)
723 // We only want to allocate registers if we're going to use them again soon
724 int needed_again(int r, int i)
730 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
732 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
733 return 0; // Don't need any registers if exiting the block
741 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
743 // Don't go past an unconditonal jump
747 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
754 if(rs1[i+j]==r) rn=j;
755 if(rs2[i+j]==r) rn=j;
756 if((unneeded_reg[i+j]>>r)&1) rn=10;
757 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
765 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
767 // Follow first branch
769 int t=(ba[i+b]-start)>>2;
770 j=7-b;if(t+j>=slen) j=slen-t-1;
773 if(!((unneeded_reg[t+j]>>r)&1)) {
774 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
775 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
785 // Try to match register allocations at the end of a loop with those
787 int loop_reg(int i, int r, int hr)
796 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
798 // Don't go past an unconditonal jump
805 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
810 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
811 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
812 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
814 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
816 int t=(ba[i+k]-start)>>2;
817 int reg=get_reg(regs[t].regmap_entry,r);
818 if(reg>=0) return reg;
819 //reg=get_reg(regs[t+1].regmap_entry,r);
820 //if(reg>=0) return reg;
828 // Allocate every register, preserving source/target regs
829 void alloc_all(struct regstat *cur,int i)
833 for(hr=0;hr<HOST_REGS;hr++) {
834 if(hr!=EXCLUDE_REG) {
835 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
836 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
839 cur->dirty&=~(1<<hr);
842 if((cur->regmap[hr]&63)==0)
845 cur->dirty&=~(1<<hr);
852 void div64(int64_t dividend,int64_t divisor)
856 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
857 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859 void divu64(uint64_t dividend,uint64_t divisor)
863 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
864 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
867 void mult64(uint64_t m1,uint64_t m2)
869 unsigned long long int op1, op2, op3, op4;
870 unsigned long long int result1, result2, result3, result4;
871 unsigned long long int temp1, temp2, temp3, temp4;
887 op1 = op2 & 0xFFFFFFFF;
888 op2 = (op2 >> 32) & 0xFFFFFFFF;
889 op3 = op4 & 0xFFFFFFFF;
890 op4 = (op4 >> 32) & 0xFFFFFFFF;
893 temp2 = (temp1 >> 32) + op1 * op4;
895 temp4 = (temp3 >> 32) + op2 * op4;
897 result1 = temp1 & 0xFFFFFFFF;
898 result2 = temp2 + (temp3 & 0xFFFFFFFF);
899 result3 = (result2 >> 32) + temp4;
900 result4 = (result3 >> 32);
902 lo = result1 | (result2 << 32);
903 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
912 void multu64(uint64_t m1,uint64_t m2)
914 unsigned long long int op1, op2, op3, op4;
915 unsigned long long int result1, result2, result3, result4;
916 unsigned long long int temp1, temp2, temp3, temp4;
918 op1 = m1 & 0xFFFFFFFF;
919 op2 = (m1 >> 32) & 0xFFFFFFFF;
920 op3 = m2 & 0xFFFFFFFF;
921 op4 = (m2 >> 32) & 0xFFFFFFFF;
924 temp2 = (temp1 >> 32) + op1 * op4;
926 temp4 = (temp3 >> 32) + op2 * op4;
928 result1 = temp1 & 0xFFFFFFFF;
929 result2 = temp2 + (temp3 & 0xFFFFFFFF);
930 result3 = (result2 >> 32) + temp4;
931 result4 = (result3 >> 32);
933 lo = result1 | (result2 << 32);
934 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
936 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
937 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
940 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
948 else original=loaded;
951 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
954 original>>=64-(bits^56);
955 original<<=64-(bits^56);
959 else original=loaded;
965 #include "assem_x86.c"
968 #include "assem_x64.c"
971 #include "assem_arm.c"
974 // Add virtual address mapping to linked list
975 void ll_add(struct ll_entry **head,int vaddr,void *addr)
977 struct ll_entry *new_entry;
978 new_entry=malloc(sizeof(struct ll_entry));
979 assert(new_entry!=NULL);
980 new_entry->vaddr=vaddr;
982 new_entry->addr=addr;
983 new_entry->next=*head;
987 // Add virtual address mapping for 32-bit compiled block
988 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
990 ll_add(head,vaddr,addr);
992 (*head)->reg32=reg32;
996 // Check if an address is already compiled
997 // but don't return addresses which are about to expire from the cache
998 void *check_addr(u_int vaddr)
1000 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1001 if(ht_bin[0]==vaddr) {
1002 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1003 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1005 if(ht_bin[2]==vaddr) {
1006 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1007 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1009 u_int page=get_page(vaddr);
1010 struct ll_entry *head;
1013 if(head->vaddr==vaddr&&head->reg32==0) {
1014 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1015 // Update existing entry with current address
1016 if(ht_bin[0]==vaddr) {
1017 ht_bin[1]=(int)head->addr;
1020 if(ht_bin[2]==vaddr) {
1021 ht_bin[3]=(int)head->addr;
1024 // Insert into hash table with low priority.
1025 // Don't evict existing entries, as they are probably
1026 // addresses that are being accessed frequently.
1028 ht_bin[1]=(int)head->addr;
1030 }else if(ht_bin[2]==-1) {
1031 ht_bin[3]=(int)head->addr;
1042 void remove_hash(int vaddr)
1044 //printf("remove hash: %x\n",vaddr);
1045 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1046 if(ht_bin[2]==vaddr) {
1047 ht_bin[2]=ht_bin[3]=-1;
1049 if(ht_bin[0]==vaddr) {
1050 ht_bin[0]=ht_bin[2];
1051 ht_bin[1]=ht_bin[3];
1052 ht_bin[2]=ht_bin[3]=-1;
1056 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1058 struct ll_entry *next;
1060 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1061 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1063 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1064 remove_hash((*head)->vaddr);
1071 head=&((*head)->next);
1076 // Remove all entries from linked list
1077 void ll_clear(struct ll_entry **head)
1079 struct ll_entry *cur;
1080 struct ll_entry *next;
1091 // Dereference the pointers and remove if it matches
1092 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1095 int ptr=get_pointer(head->addr);
1096 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1097 if(((ptr>>shift)==(addr>>shift)) ||
1098 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1100 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1101 u_int host_addr=(u_int)kill_pointer(head->addr);
1103 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1110 // This is called when we write to a compiled block (see do_invstub)
1111 void invalidate_page(u_int page)
1113 struct ll_entry *head;
1114 struct ll_entry *next;
1118 inv_debug("INVALIDATE: %x\n",head->vaddr);
1119 remove_hash(head->vaddr);
1124 head=jump_out[page];
1127 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1128 u_int host_addr=(u_int)kill_pointer(head->addr);
1130 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1138 static void invalidate_block_range(u_int block, u_int first, u_int last)
1140 u_int page=get_page(block<<12);
1141 //printf("first=%d last=%d\n",first,last);
1142 invalidate_page(page);
1143 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1144 assert(last<page+5);
1145 // Invalidate the adjacent pages if a block crosses a 4K boundary
1147 invalidate_page(first);
1150 for(first=page+1;first<last;first++) {
1151 invalidate_page(first);
1157 // Don't trap writes
1158 invalid_code[block]=1;
1160 // If there is a valid TLB entry for this page, remove write protect
1161 if(tlb_LUT_w[block]) {
1162 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1163 // CHECK: Is this right?
1164 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1165 u_int real_block=tlb_LUT_w[block]>>12;
1166 invalid_code[real_block]=1;
1167 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1169 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1173 memset(mini_ht,-1,sizeof(mini_ht));
1177 void invalidate_block(u_int block)
1179 u_int page=get_page(block<<12);
1180 u_int vpage=get_vpage(block<<12);
1181 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1182 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1185 struct ll_entry *head;
1186 head=jump_dirty[vpage];
1187 //printf("page=%d vpage=%d\n",page,vpage);
1190 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1191 get_bounds((int)head->addr,&start,&end);
1192 //printf("start: %x end: %x\n",start,end);
1193 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1194 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1195 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1196 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1200 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1201 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1202 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1203 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1210 invalidate_block_range(block,first,last);
1213 void invalidate_addr(u_int addr)
1217 // this check is done by the caller
1218 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1219 u_int page=get_page(addr);
1220 if(page<2048) { // RAM
1221 struct ll_entry *head;
1222 u_int addr_min=~0, addr_max=0;
1223 int mask=RAM_SIZE-1;
1225 inv_code_start=addr&~0xfff;
1226 inv_code_end=addr|0xfff;
1229 // must check previous page too because of spans..
1231 inv_code_start-=0x1000;
1233 for(;pg1<=page;pg1++) {
1234 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1236 get_bounds((int)head->addr,&start,&end);
1237 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1238 if(start<addr_min) addr_min=start;
1239 if(end>addr_max) addr_max=end;
1241 else if(addr<start) {
1242 if(start<inv_code_end)
1243 inv_code_end=start-1;
1246 if(end>inv_code_start)
1252 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1253 inv_code_start=inv_code_end=~0;
1254 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1258 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1261 if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1265 invalidate_block(addr>>12);
1268 // This is called when loading a save state.
1269 // Anything could have changed, so invalidate everything.
1270 void invalidate_all_pages()
1273 for(page=0;page<4096;page++)
1274 invalidate_page(page);
1275 for(page=0;page<1048576;page++)
1276 if(!invalid_code[page]) {
1277 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1278 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1281 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1284 memset(mini_ht,-1,sizeof(mini_ht));
1288 for(page=0;page<0x100000;page++) {
1289 if(tlb_LUT_r[page]) {
1290 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1291 if(!tlb_LUT_w[page]||!invalid_code[page])
1292 memory_map[page]|=0x40000000; // Write protect
1294 else memory_map[page]=-1;
1295 if(page==0x80000) page=0xC0000;
1301 // Add an entry to jump_out after making a link
1302 void add_link(u_int vaddr,void *src)
1304 u_int page=get_page(vaddr);
1305 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1306 int *ptr=(int *)(src+4);
1307 assert((*ptr&0x0fff0000)==0x059f0000);
1308 ll_add(jump_out+page,vaddr,src);
1309 //int ptr=get_pointer(src);
1310 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1313 // If a code block was found to be unmodified (bit was set in
1314 // restore_candidate) and it remains unmodified (bit is clear
1315 // in invalid_code) then move the entries for that 4K page from
1316 // the dirty list to the clean list.
1317 void clean_blocks(u_int page)
1319 struct ll_entry *head;
1320 inv_debug("INV: clean_blocks page=%d\n",page);
1321 head=jump_dirty[page];
1323 if(!invalid_code[head->vaddr>>12]) {
1324 // Don't restore blocks which are about to expire from the cache
1325 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1327 if(verify_dirty((int)head->addr)) {
1328 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1331 get_bounds((int)head->addr,&start,&end);
1332 if(start-(u_int)rdram<RAM_SIZE) {
1333 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1334 inv|=invalid_code[i];
1337 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1338 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1339 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1340 if(addr<start||addr>=end) inv=1;
1342 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1346 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1347 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1350 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1352 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1353 //printf("page=%x, addr=%x\n",page,head->vaddr);
1354 //assert(head->vaddr>>12==(page|0x80000));
1355 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1356 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1358 if(ht_bin[0]==head->vaddr) {
1359 ht_bin[1]=(int)clean_addr; // Replace existing entry
1361 if(ht_bin[2]==head->vaddr) {
1362 ht_bin[3]=(int)clean_addr; // Replace existing entry
1375 void mov_alloc(struct regstat *current,int i)
1377 // Note: Don't need to actually alloc the source registers
1378 if((~current->is32>>rs1[i])&1) {
1379 //alloc_reg64(current,i,rs1[i]);
1380 alloc_reg64(current,i,rt1[i]);
1381 current->is32&=~(1LL<<rt1[i]);
1383 //alloc_reg(current,i,rs1[i]);
1384 alloc_reg(current,i,rt1[i]);
1385 current->is32|=(1LL<<rt1[i]);
1387 clear_const(current,rs1[i]);
1388 clear_const(current,rt1[i]);
1389 dirty_reg(current,rt1[i]);
1392 void shiftimm_alloc(struct regstat *current,int i)
1394 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1397 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1399 alloc_reg(current,i,rt1[i]);
1400 current->is32|=1LL<<rt1[i];
1401 dirty_reg(current,rt1[i]);
1402 if(is_const(current,rs1[i])) {
1403 int v=get_const(current,rs1[i]);
1404 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1405 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1406 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1408 else clear_const(current,rt1[i]);
1413 clear_const(current,rs1[i]);
1414 clear_const(current,rt1[i]);
1417 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1420 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1421 alloc_reg64(current,i,rt1[i]);
1422 current->is32&=~(1LL<<rt1[i]);
1423 dirty_reg(current,rt1[i]);
1426 if(opcode2[i]==0x3c) // DSLL32
1429 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1430 alloc_reg64(current,i,rt1[i]);
1431 current->is32&=~(1LL<<rt1[i]);
1432 dirty_reg(current,rt1[i]);
1435 if(opcode2[i]==0x3e) // DSRL32
1438 alloc_reg64(current,i,rs1[i]);
1440 alloc_reg64(current,i,rt1[i]);
1441 current->is32&=~(1LL<<rt1[i]);
1443 alloc_reg(current,i,rt1[i]);
1444 current->is32|=1LL<<rt1[i];
1446 dirty_reg(current,rt1[i]);
1449 if(opcode2[i]==0x3f) // DSRA32
1452 alloc_reg64(current,i,rs1[i]);
1453 alloc_reg(current,i,rt1[i]);
1454 current->is32|=1LL<<rt1[i];
1455 dirty_reg(current,rt1[i]);
1460 void shift_alloc(struct regstat *current,int i)
1463 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1465 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1466 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1467 alloc_reg(current,i,rt1[i]);
1468 if(rt1[i]==rs2[i]) {
1469 alloc_reg_temp(current,i,-1);
1470 minimum_free_regs[i]=1;
1472 current->is32|=1LL<<rt1[i];
1473 } else { // DSLLV/DSRLV/DSRAV
1474 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1475 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1476 alloc_reg64(current,i,rt1[i]);
1477 current->is32&=~(1LL<<rt1[i]);
1478 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1480 alloc_reg_temp(current,i,-1);
1481 minimum_free_regs[i]=1;
1484 clear_const(current,rs1[i]);
1485 clear_const(current,rs2[i]);
1486 clear_const(current,rt1[i]);
1487 dirty_reg(current,rt1[i]);
1491 void alu_alloc(struct regstat *current,int i)
1493 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1495 if(rs1[i]&&rs2[i]) {
1496 alloc_reg(current,i,rs1[i]);
1497 alloc_reg(current,i,rs2[i]);
1500 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1501 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1503 alloc_reg(current,i,rt1[i]);
1505 current->is32|=1LL<<rt1[i];
1507 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1509 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1511 alloc_reg64(current,i,rs1[i]);
1512 alloc_reg64(current,i,rs2[i]);
1513 alloc_reg(current,i,rt1[i]);
1515 alloc_reg(current,i,rs1[i]);
1516 alloc_reg(current,i,rs2[i]);
1517 alloc_reg(current,i,rt1[i]);
1520 current->is32|=1LL<<rt1[i];
1522 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1524 if(rs1[i]&&rs2[i]) {
1525 alloc_reg(current,i,rs1[i]);
1526 alloc_reg(current,i,rs2[i]);
1530 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1531 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1533 alloc_reg(current,i,rt1[i]);
1534 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1536 if(!((current->uu>>rt1[i])&1)) {
1537 alloc_reg64(current,i,rt1[i]);
1539 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1540 if(rs1[i]&&rs2[i]) {
1541 alloc_reg64(current,i,rs1[i]);
1542 alloc_reg64(current,i,rs2[i]);
1546 // Is is really worth it to keep 64-bit values in registers?
1548 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1549 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1553 current->is32&=~(1LL<<rt1[i]);
1555 current->is32|=1LL<<rt1[i];
1559 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1561 if(rs1[i]&&rs2[i]) {
1562 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1563 alloc_reg64(current,i,rs1[i]);
1564 alloc_reg64(current,i,rs2[i]);
1565 alloc_reg64(current,i,rt1[i]);
1567 alloc_reg(current,i,rs1[i]);
1568 alloc_reg(current,i,rs2[i]);
1569 alloc_reg(current,i,rt1[i]);
1573 alloc_reg(current,i,rt1[i]);
1574 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1575 // DADD used as move, or zeroing
1576 // If we have a 64-bit source, then make the target 64 bits too
1577 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1578 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1579 alloc_reg64(current,i,rt1[i]);
1580 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1581 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1582 alloc_reg64(current,i,rt1[i]);
1584 if(opcode2[i]>=0x2e&&rs2[i]) {
1585 // DSUB used as negation - 64-bit result
1586 // If we have a 32-bit register, extend it to 64 bits
1587 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1588 alloc_reg64(current,i,rt1[i]);
1592 if(rs1[i]&&rs2[i]) {
1593 current->is32&=~(1LL<<rt1[i]);
1595 current->is32&=~(1LL<<rt1[i]);
1596 if((current->is32>>rs1[i])&1)
1597 current->is32|=1LL<<rt1[i];
1599 current->is32&=~(1LL<<rt1[i]);
1600 if((current->is32>>rs2[i])&1)
1601 current->is32|=1LL<<rt1[i];
1603 current->is32|=1LL<<rt1[i];
1607 clear_const(current,rs1[i]);
1608 clear_const(current,rs2[i]);
1609 clear_const(current,rt1[i]);
1610 dirty_reg(current,rt1[i]);
1613 void imm16_alloc(struct regstat *current,int i)
1615 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1617 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1618 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1619 current->is32&=~(1LL<<rt1[i]);
1620 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1621 // TODO: Could preserve the 32-bit flag if the immediate is zero
1622 alloc_reg64(current,i,rt1[i]);
1623 alloc_reg64(current,i,rs1[i]);
1625 clear_const(current,rs1[i]);
1626 clear_const(current,rt1[i]);
1628 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1629 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1630 current->is32|=1LL<<rt1[i];
1631 clear_const(current,rs1[i]);
1632 clear_const(current,rt1[i]);
1634 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1635 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1636 if(rs1[i]!=rt1[i]) {
1637 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1638 alloc_reg64(current,i,rt1[i]);
1639 current->is32&=~(1LL<<rt1[i]);
1642 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1643 if(is_const(current,rs1[i])) {
1644 int v=get_const(current,rs1[i]);
1645 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1646 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1647 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1649 else clear_const(current,rt1[i]);
1651 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1652 if(is_const(current,rs1[i])) {
1653 int v=get_const(current,rs1[i]);
1654 set_const(current,rt1[i],v+imm[i]);
1656 else clear_const(current,rt1[i]);
1657 current->is32|=1LL<<rt1[i];
1660 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1661 current->is32|=1LL<<rt1[i];
1663 dirty_reg(current,rt1[i]);
1666 void load_alloc(struct regstat *current,int i)
1668 clear_const(current,rt1[i]);
1669 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1670 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1671 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1672 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1673 alloc_reg(current,i,rt1[i]);
1674 assert(get_reg(current->regmap,rt1[i])>=0);
1675 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1677 current->is32&=~(1LL<<rt1[i]);
1678 alloc_reg64(current,i,rt1[i]);
1680 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1682 current->is32&=~(1LL<<rt1[i]);
1683 alloc_reg64(current,i,rt1[i]);
1684 alloc_all(current,i);
1685 alloc_reg64(current,i,FTEMP);
1686 minimum_free_regs[i]=HOST_REGS;
1688 else current->is32|=1LL<<rt1[i];
1689 dirty_reg(current,rt1[i]);
1690 // If using TLB, need a register for pointer to the mapping table
1691 if(using_tlb) alloc_reg(current,i,TLREG);
1692 // LWL/LWR need a temporary register for the old value
1693 if(opcode[i]==0x22||opcode[i]==0x26)
1695 alloc_reg(current,i,FTEMP);
1696 alloc_reg_temp(current,i,-1);
1697 minimum_free_regs[i]=1;
1702 // Load to r0 or unneeded register (dummy load)
1703 // but we still need a register to calculate the address
1704 if(opcode[i]==0x22||opcode[i]==0x26)
1706 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1708 // If using TLB, need a register for pointer to the mapping table
1709 if(using_tlb) alloc_reg(current,i,TLREG);
1710 alloc_reg_temp(current,i,-1);
1711 minimum_free_regs[i]=1;
1712 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1714 alloc_all(current,i);
1715 alloc_reg64(current,i,FTEMP);
1716 minimum_free_regs[i]=HOST_REGS;
1721 void store_alloc(struct regstat *current,int i)
1723 clear_const(current,rs2[i]);
1724 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1725 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1726 alloc_reg(current,i,rs2[i]);
1727 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1728 alloc_reg64(current,i,rs2[i]);
1729 if(rs2[i]) alloc_reg(current,i,FTEMP);
1731 // If using TLB, need a register for pointer to the mapping table
1732 if(using_tlb) alloc_reg(current,i,TLREG);
1733 #if defined(HOST_IMM8)
1734 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1735 else alloc_reg(current,i,INVCP);
1737 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1738 alloc_reg(current,i,FTEMP);
1740 // We need a temporary register for address generation
1741 alloc_reg_temp(current,i,-1);
1742 minimum_free_regs[i]=1;
1745 void c1ls_alloc(struct regstat *current,int i)
1747 //clear_const(current,rs1[i]); // FIXME
1748 clear_const(current,rt1[i]);
1749 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1750 alloc_reg(current,i,CSREG); // Status
1751 alloc_reg(current,i,FTEMP);
1752 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1753 alloc_reg64(current,i,FTEMP);
1755 // If using TLB, need a register for pointer to the mapping table
1756 if(using_tlb) alloc_reg(current,i,TLREG);
1757 #if defined(HOST_IMM8)
1758 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1759 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1760 alloc_reg(current,i,INVCP);
1762 // We need a temporary register for address generation
1763 alloc_reg_temp(current,i,-1);
1766 void c2ls_alloc(struct regstat *current,int i)
1768 clear_const(current,rt1[i]);
1769 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1770 alloc_reg(current,i,FTEMP);
1771 // If using TLB, need a register for pointer to the mapping table
1772 if(using_tlb) alloc_reg(current,i,TLREG);
1773 #if defined(HOST_IMM8)
1774 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1775 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1776 alloc_reg(current,i,INVCP);
1778 // We need a temporary register for address generation
1779 alloc_reg_temp(current,i,-1);
1780 minimum_free_regs[i]=1;
1783 #ifndef multdiv_alloc
1784 void multdiv_alloc(struct regstat *current,int i)
1791 // case 0x1D: DMULTU
1794 clear_const(current,rs1[i]);
1795 clear_const(current,rs2[i]);
1798 if((opcode2[i]&4)==0) // 32-bit
1800 current->u&=~(1LL<<HIREG);
1801 current->u&=~(1LL<<LOREG);
1802 alloc_reg(current,i,HIREG);
1803 alloc_reg(current,i,LOREG);
1804 alloc_reg(current,i,rs1[i]);
1805 alloc_reg(current,i,rs2[i]);
1806 current->is32|=1LL<<HIREG;
1807 current->is32|=1LL<<LOREG;
1808 dirty_reg(current,HIREG);
1809 dirty_reg(current,LOREG);
1813 current->u&=~(1LL<<HIREG);
1814 current->u&=~(1LL<<LOREG);
1815 current->uu&=~(1LL<<HIREG);
1816 current->uu&=~(1LL<<LOREG);
1817 alloc_reg64(current,i,HIREG);
1818 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1819 alloc_reg64(current,i,rs1[i]);
1820 alloc_reg64(current,i,rs2[i]);
1821 alloc_all(current,i);
1822 current->is32&=~(1LL<<HIREG);
1823 current->is32&=~(1LL<<LOREG);
1824 dirty_reg(current,HIREG);
1825 dirty_reg(current,LOREG);
1826 minimum_free_regs[i]=HOST_REGS;
1831 // Multiply by zero is zero.
1832 // MIPS does not have a divide by zero exception.
1833 // The result is undefined, we return zero.
1834 alloc_reg(current,i,HIREG);
1835 alloc_reg(current,i,LOREG);
1836 current->is32|=1LL<<HIREG;
1837 current->is32|=1LL<<LOREG;
1838 dirty_reg(current,HIREG);
1839 dirty_reg(current,LOREG);
1844 void cop0_alloc(struct regstat *current,int i)
1846 if(opcode2[i]==0) // MFC0
1849 clear_const(current,rt1[i]);
1850 alloc_all(current,i);
1851 alloc_reg(current,i,rt1[i]);
1852 current->is32|=1LL<<rt1[i];
1853 dirty_reg(current,rt1[i]);
1856 else if(opcode2[i]==4) // MTC0
1859 clear_const(current,rs1[i]);
1860 alloc_reg(current,i,rs1[i]);
1861 alloc_all(current,i);
1864 alloc_all(current,i); // FIXME: Keep r0
1866 alloc_reg(current,i,0);
1871 // TLBR/TLBWI/TLBWR/TLBP/ERET
1872 assert(opcode2[i]==0x10);
1873 alloc_all(current,i);
1875 minimum_free_regs[i]=HOST_REGS;
1878 void cop1_alloc(struct regstat *current,int i)
1880 alloc_reg(current,i,CSREG); // Load status
1881 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1884 clear_const(current,rt1[i]);
1886 alloc_reg64(current,i,rt1[i]); // DMFC1
1887 current->is32&=~(1LL<<rt1[i]);
1889 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1890 current->is32|=1LL<<rt1[i];
1892 dirty_reg(current,rt1[i]);
1894 alloc_reg_temp(current,i,-1);
1896 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1899 clear_const(current,rs1[i]);
1901 alloc_reg64(current,i,rs1[i]); // DMTC1
1903 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1904 alloc_reg_temp(current,i,-1);
1908 alloc_reg(current,i,0);
1909 alloc_reg_temp(current,i,-1);
1912 minimum_free_regs[i]=1;
1914 void fconv_alloc(struct regstat *current,int i)
1916 alloc_reg(current,i,CSREG); // Load status
1917 alloc_reg_temp(current,i,-1);
1918 minimum_free_regs[i]=1;
1920 void float_alloc(struct regstat *current,int i)
1922 alloc_reg(current,i,CSREG); // Load status
1923 alloc_reg_temp(current,i,-1);
1924 minimum_free_regs[i]=1;
1926 void c2op_alloc(struct regstat *current,int i)
1928 alloc_reg_temp(current,i,-1);
1930 void fcomp_alloc(struct regstat *current,int i)
1932 alloc_reg(current,i,CSREG); // Load status
1933 alloc_reg(current,i,FSREG); // Load flags
1934 dirty_reg(current,FSREG); // Flag will be modified
1935 alloc_reg_temp(current,i,-1);
1936 minimum_free_regs[i]=1;
1939 void syscall_alloc(struct regstat *current,int i)
1941 alloc_cc(current,i);
1942 dirty_reg(current,CCREG);
1943 alloc_all(current,i);
1944 minimum_free_regs[i]=HOST_REGS;
1948 void delayslot_alloc(struct regstat *current,int i)
1959 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1960 printf("Disabled speculative precompilation\n");
1964 imm16_alloc(current,i);
1968 load_alloc(current,i);
1972 store_alloc(current,i);
1975 alu_alloc(current,i);
1978 shift_alloc(current,i);
1981 multdiv_alloc(current,i);
1984 shiftimm_alloc(current,i);
1987 mov_alloc(current,i);
1990 cop0_alloc(current,i);
1994 cop1_alloc(current,i);
1997 c1ls_alloc(current,i);
2000 c2ls_alloc(current,i);
2003 fconv_alloc(current,i);
2006 float_alloc(current,i);
2009 fcomp_alloc(current,i);
2012 c2op_alloc(current,i);
2017 // Special case where a branch and delay slot span two pages in virtual memory
2018 static void pagespan_alloc(struct regstat *current,int i)
2021 current->wasconst=0;
2023 minimum_free_regs[i]=HOST_REGS;
2024 alloc_all(current,i);
2025 alloc_cc(current,i);
2026 dirty_reg(current,CCREG);
2027 if(opcode[i]==3) // JAL
2029 alloc_reg(current,i,31);
2030 dirty_reg(current,31);
2032 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2034 alloc_reg(current,i,rs1[i]);
2036 alloc_reg(current,i,rt1[i]);
2037 dirty_reg(current,rt1[i]);
2040 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2042 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2043 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2044 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2046 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2047 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2051 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2053 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2054 if(!((current->is32>>rs1[i])&1))
2056 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2060 if(opcode[i]==0x11) // BC1
2062 alloc_reg(current,i,FSREG);
2063 alloc_reg(current,i,CSREG);
2068 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2070 stubs[stubcount][0]=type;
2071 stubs[stubcount][1]=addr;
2072 stubs[stubcount][2]=retaddr;
2073 stubs[stubcount][3]=a;
2074 stubs[stubcount][4]=b;
2075 stubs[stubcount][5]=c;
2076 stubs[stubcount][6]=d;
2077 stubs[stubcount][7]=e;
2081 // Write out a single register
2082 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2085 for(hr=0;hr<HOST_REGS;hr++) {
2086 if(hr!=EXCLUDE_REG) {
2087 if((regmap[hr]&63)==r) {
2090 emit_storereg(r,hr);
2092 if((is32>>regmap[hr])&1) {
2093 emit_sarimm(hr,31,hr);
2094 emit_storereg(r|64,hr);
2098 emit_storereg(r|64,hr);
2108 //if(!tracedebug) return 0;
2111 for(i=0;i<2097152;i++) {
2112 unsigned int temp=sum;
2115 sum^=((u_int *)rdram)[i];
2124 sum^=((u_int *)reg)[i];
2132 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2134 #ifndef DISABLE_COP1
2137 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2147 void memdebug(int i)
2149 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2150 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2153 //if(Count>=-2084597794) {
2154 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2156 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2157 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2158 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2161 printf("TRACE: %x\n",(&i)[-1]);
2165 printf("TRACE: %x \n",(&j)[10]);
2166 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2170 //printf("TRACE: %x\n",(&i)[-1]);
2173 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2175 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2178 void alu_assemble(int i,struct regstat *i_regs)
2180 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2182 signed char s1,s2,t;
2183 t=get_reg(i_regs->regmap,rt1[i]);
2185 s1=get_reg(i_regs->regmap,rs1[i]);
2186 s2=get_reg(i_regs->regmap,rs2[i]);
2187 if(rs1[i]&&rs2[i]) {
2190 if(opcode2[i]&2) emit_sub(s1,s2,t);
2191 else emit_add(s1,s2,t);
2194 if(s1>=0) emit_mov(s1,t);
2195 else emit_loadreg(rs1[i],t);
2199 if(opcode2[i]&2) emit_neg(s2,t);
2200 else emit_mov(s2,t);
2203 emit_loadreg(rs2[i],t);
2204 if(opcode2[i]&2) emit_neg(t,t);
2207 else emit_zeroreg(t);
2211 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2213 signed char s1l,s2l,s1h,s2h,tl,th;
2214 tl=get_reg(i_regs->regmap,rt1[i]);
2215 th=get_reg(i_regs->regmap,rt1[i]|64);
2217 s1l=get_reg(i_regs->regmap,rs1[i]);
2218 s2l=get_reg(i_regs->regmap,rs2[i]);
2219 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2220 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2221 if(rs1[i]&&rs2[i]) {
2224 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2225 else emit_adds(s1l,s2l,tl);
2227 #ifdef INVERTED_CARRY
2228 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2230 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2232 else emit_add(s1h,s2h,th);
2236 if(s1l>=0) emit_mov(s1l,tl);
2237 else emit_loadreg(rs1[i],tl);
2239 if(s1h>=0) emit_mov(s1h,th);
2240 else emit_loadreg(rs1[i]|64,th);
2245 if(opcode2[i]&2) emit_negs(s2l,tl);
2246 else emit_mov(s2l,tl);
2249 emit_loadreg(rs2[i],tl);
2250 if(opcode2[i]&2) emit_negs(tl,tl);
2253 #ifdef INVERTED_CARRY
2254 if(s2h>=0) emit_mov(s2h,th);
2255 else emit_loadreg(rs2[i]|64,th);
2257 emit_adcimm(-1,th); // x86 has inverted carry flag
2262 if(s2h>=0) emit_rscimm(s2h,0,th);
2264 emit_loadreg(rs2[i]|64,th);
2265 emit_rscimm(th,0,th);
2268 if(s2h>=0) emit_mov(s2h,th);
2269 else emit_loadreg(rs2[i]|64,th);
2276 if(th>=0) emit_zeroreg(th);
2281 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2283 signed char s1l,s1h,s2l,s2h,t;
2284 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2286 t=get_reg(i_regs->regmap,rt1[i]);
2289 s1l=get_reg(i_regs->regmap,rs1[i]);
2290 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2291 s2l=get_reg(i_regs->regmap,rs2[i]);
2292 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2293 if(rs2[i]==0) // rx<r0
2296 if(opcode2[i]==0x2a) // SLT
2297 emit_shrimm(s1h,31,t);
2298 else // SLTU (unsigned can not be less than zero)
2301 else if(rs1[i]==0) // r0<rx
2304 if(opcode2[i]==0x2a) // SLT
2305 emit_set_gz64_32(s2h,s2l,t);
2306 else // SLTU (set if not zero)
2307 emit_set_nz64_32(s2h,s2l,t);
2310 assert(s1l>=0);assert(s1h>=0);
2311 assert(s2l>=0);assert(s2h>=0);
2312 if(opcode2[i]==0x2a) // SLT
2313 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2315 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2319 t=get_reg(i_regs->regmap,rt1[i]);
2322 s1l=get_reg(i_regs->regmap,rs1[i]);
2323 s2l=get_reg(i_regs->regmap,rs2[i]);
2324 if(rs2[i]==0) // rx<r0
2327 if(opcode2[i]==0x2a) // SLT
2328 emit_shrimm(s1l,31,t);
2329 else // SLTU (unsigned can not be less than zero)
2332 else if(rs1[i]==0) // r0<rx
2335 if(opcode2[i]==0x2a) // SLT
2336 emit_set_gz32(s2l,t);
2337 else // SLTU (set if not zero)
2338 emit_set_nz32(s2l,t);
2341 assert(s1l>=0);assert(s2l>=0);
2342 if(opcode2[i]==0x2a) // SLT
2343 emit_set_if_less32(s1l,s2l,t);
2345 emit_set_if_carry32(s1l,s2l,t);
2351 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2353 signed char s1l,s1h,s2l,s2h,th,tl;
2354 tl=get_reg(i_regs->regmap,rt1[i]);
2355 th=get_reg(i_regs->regmap,rt1[i]|64);
2356 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2360 s1l=get_reg(i_regs->regmap,rs1[i]);
2361 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2362 s2l=get_reg(i_regs->regmap,rs2[i]);
2363 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2364 if(rs1[i]&&rs2[i]) {
2365 assert(s1l>=0);assert(s1h>=0);
2366 assert(s2l>=0);assert(s2h>=0);
2367 if(opcode2[i]==0x24) { // AND
2368 emit_and(s1l,s2l,tl);
2369 emit_and(s1h,s2h,th);
2371 if(opcode2[i]==0x25) { // OR
2372 emit_or(s1l,s2l,tl);
2373 emit_or(s1h,s2h,th);
2375 if(opcode2[i]==0x26) { // XOR
2376 emit_xor(s1l,s2l,tl);
2377 emit_xor(s1h,s2h,th);
2379 if(opcode2[i]==0x27) { // NOR
2380 emit_or(s1l,s2l,tl);
2381 emit_or(s1h,s2h,th);
2388 if(opcode2[i]==0x24) { // AND
2392 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2394 if(s1l>=0) emit_mov(s1l,tl);
2395 else emit_loadreg(rs1[i],tl);
2396 if(s1h>=0) emit_mov(s1h,th);
2397 else emit_loadreg(rs1[i]|64,th);
2401 if(s2l>=0) emit_mov(s2l,tl);
2402 else emit_loadreg(rs2[i],tl);
2403 if(s2h>=0) emit_mov(s2h,th);
2404 else emit_loadreg(rs2[i]|64,th);
2411 if(opcode2[i]==0x27) { // NOR
2413 if(s1l>=0) emit_not(s1l,tl);
2415 emit_loadreg(rs1[i],tl);
2418 if(s1h>=0) emit_not(s1h,th);
2420 emit_loadreg(rs1[i]|64,th);
2426 if(s2l>=0) emit_not(s2l,tl);
2428 emit_loadreg(rs2[i],tl);
2431 if(s2h>=0) emit_not(s2h,th);
2433 emit_loadreg(rs2[i]|64,th);
2449 s1l=get_reg(i_regs->regmap,rs1[i]);
2450 s2l=get_reg(i_regs->regmap,rs2[i]);
2451 if(rs1[i]&&rs2[i]) {
2454 if(opcode2[i]==0x24) { // AND
2455 emit_and(s1l,s2l,tl);
2457 if(opcode2[i]==0x25) { // OR
2458 emit_or(s1l,s2l,tl);
2460 if(opcode2[i]==0x26) { // XOR
2461 emit_xor(s1l,s2l,tl);
2463 if(opcode2[i]==0x27) { // NOR
2464 emit_or(s1l,s2l,tl);
2470 if(opcode2[i]==0x24) { // AND
2473 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2475 if(s1l>=0) emit_mov(s1l,tl);
2476 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2480 if(s2l>=0) emit_mov(s2l,tl);
2481 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2483 else emit_zeroreg(tl);
2485 if(opcode2[i]==0x27) { // NOR
2487 if(s1l>=0) emit_not(s1l,tl);
2489 emit_loadreg(rs1[i],tl);
2495 if(s2l>=0) emit_not(s2l,tl);
2497 emit_loadreg(rs2[i],tl);
2501 else emit_movimm(-1,tl);
2510 void imm16_assemble(int i,struct regstat *i_regs)
2512 if (opcode[i]==0x0f) { // LUI
2515 t=get_reg(i_regs->regmap,rt1[i]);
2518 if(!((i_regs->isconst>>t)&1))
2519 emit_movimm(imm[i]<<16,t);
2523 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2526 t=get_reg(i_regs->regmap,rt1[i]);
2527 s=get_reg(i_regs->regmap,rs1[i]);
2532 if(!((i_regs->isconst>>t)&1)) {
2534 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2535 emit_addimm(t,imm[i],t);
2537 if(!((i_regs->wasconst>>s)&1))
2538 emit_addimm(s,imm[i],t);
2540 emit_movimm(constmap[i][s]+imm[i],t);
2546 if(!((i_regs->isconst>>t)&1))
2547 emit_movimm(imm[i],t);
2552 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2554 signed char sh,sl,th,tl;
2555 th=get_reg(i_regs->regmap,rt1[i]|64);
2556 tl=get_reg(i_regs->regmap,rt1[i]);
2557 sh=get_reg(i_regs->regmap,rs1[i]|64);
2558 sl=get_reg(i_regs->regmap,rs1[i]);
2564 emit_addimm64_32(sh,sl,imm[i],th,tl);
2567 emit_addimm(sl,imm[i],tl);
2570 emit_movimm(imm[i],tl);
2571 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2576 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2578 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2579 signed char sh,sl,t;
2580 t=get_reg(i_regs->regmap,rt1[i]);
2581 sh=get_reg(i_regs->regmap,rs1[i]|64);
2582 sl=get_reg(i_regs->regmap,rs1[i]);
2586 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2587 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2588 if(opcode[i]==0x0a) { // SLTI
2590 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2591 emit_slti32(t,imm[i],t);
2593 emit_slti32(sl,imm[i],t);
2598 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2599 emit_sltiu32(t,imm[i],t);
2601 emit_sltiu32(sl,imm[i],t);
2606 if(opcode[i]==0x0a) // SLTI
2607 emit_slti64_32(sh,sl,imm[i],t);
2609 emit_sltiu64_32(sh,sl,imm[i],t);
2612 // SLTI(U) with r0 is just stupid,
2613 // nonetheless examples can be found
2614 if(opcode[i]==0x0a) // SLTI
2615 if(0<imm[i]) emit_movimm(1,t);
2616 else emit_zeroreg(t);
2619 if(imm[i]) emit_movimm(1,t);
2620 else emit_zeroreg(t);
2626 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2628 signed char sh,sl,th,tl;
2629 th=get_reg(i_regs->regmap,rt1[i]|64);
2630 tl=get_reg(i_regs->regmap,rt1[i]);
2631 sh=get_reg(i_regs->regmap,rs1[i]|64);
2632 sl=get_reg(i_regs->regmap,rs1[i]);
2633 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2634 if(opcode[i]==0x0c) //ANDI
2638 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2639 emit_andimm(tl,imm[i],tl);
2641 if(!((i_regs->wasconst>>sl)&1))
2642 emit_andimm(sl,imm[i],tl);
2644 emit_movimm(constmap[i][sl]&imm[i],tl);
2649 if(th>=0) emit_zeroreg(th);
2655 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2659 emit_loadreg(rs1[i]|64,th);
2664 if(opcode[i]==0x0d) //ORI
2666 emit_orimm(tl,imm[i],tl);
2668 if(!((i_regs->wasconst>>sl)&1))
2669 emit_orimm(sl,imm[i],tl);
2671 emit_movimm(constmap[i][sl]|imm[i],tl);
2673 if(opcode[i]==0x0e) //XORI
2675 emit_xorimm(tl,imm[i],tl);
2677 if(!((i_regs->wasconst>>sl)&1))
2678 emit_xorimm(sl,imm[i],tl);
2680 emit_movimm(constmap[i][sl]^imm[i],tl);
2684 emit_movimm(imm[i],tl);
2685 if(th>=0) emit_zeroreg(th);
2693 void shiftimm_assemble(int i,struct regstat *i_regs)
2695 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2699 t=get_reg(i_regs->regmap,rt1[i]);
2700 s=get_reg(i_regs->regmap,rs1[i]);
2702 if(t>=0&&!((i_regs->isconst>>t)&1)){
2709 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2711 if(opcode2[i]==0) // SLL
2713 emit_shlimm(s<0?t:s,imm[i],t);
2715 if(opcode2[i]==2) // SRL
2717 emit_shrimm(s<0?t:s,imm[i],t);
2719 if(opcode2[i]==3) // SRA
2721 emit_sarimm(s<0?t:s,imm[i],t);
2725 if(s>=0 && s!=t) emit_mov(s,t);
2729 //emit_storereg(rt1[i],t); //DEBUG
2732 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2735 signed char sh,sl,th,tl;
2736 th=get_reg(i_regs->regmap,rt1[i]|64);
2737 tl=get_reg(i_regs->regmap,rt1[i]);
2738 sh=get_reg(i_regs->regmap,rs1[i]|64);
2739 sl=get_reg(i_regs->regmap,rs1[i]);
2744 if(th>=0) emit_zeroreg(th);
2751 if(opcode2[i]==0x38) // DSLL
2753 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2754 emit_shlimm(sl,imm[i],tl);
2756 if(opcode2[i]==0x3a) // DSRL
2758 emit_shrdimm(sl,sh,imm[i],tl);
2759 if(th>=0) emit_shrimm(sh,imm[i],th);
2761 if(opcode2[i]==0x3b) // DSRA
2763 emit_shrdimm(sl,sh,imm[i],tl);
2764 if(th>=0) emit_sarimm(sh,imm[i],th);
2768 if(sl!=tl) emit_mov(sl,tl);
2769 if(th>=0&&sh!=th) emit_mov(sh,th);
2775 if(opcode2[i]==0x3c) // DSLL32
2778 signed char sl,tl,th;
2779 tl=get_reg(i_regs->regmap,rt1[i]);
2780 th=get_reg(i_regs->regmap,rt1[i]|64);
2781 sl=get_reg(i_regs->regmap,rs1[i]);
2790 emit_shlimm(th,imm[i]&31,th);
2795 if(opcode2[i]==0x3e) // DSRL32
2798 signed char sh,tl,th;
2799 tl=get_reg(i_regs->regmap,rt1[i]);
2800 th=get_reg(i_regs->regmap,rt1[i]|64);
2801 sh=get_reg(i_regs->regmap,rs1[i]|64);
2805 if(th>=0) emit_zeroreg(th);
2808 emit_shrimm(tl,imm[i]&31,tl);
2813 if(opcode2[i]==0x3f) // DSRA32
2817 tl=get_reg(i_regs->regmap,rt1[i]);
2818 sh=get_reg(i_regs->regmap,rs1[i]|64);
2824 emit_sarimm(tl,imm[i]&31,tl);
2831 #ifndef shift_assemble
2832 void shift_assemble(int i,struct regstat *i_regs)
2834 printf("Need shift_assemble for this architecture.\n");
2839 void load_assemble(int i,struct regstat *i_regs)
2841 int s,th,tl,addr,map=-1;
2844 int memtarget=0,c=0;
2845 int fastload_reg_override=0;
2847 th=get_reg(i_regs->regmap,rt1[i]|64);
2848 tl=get_reg(i_regs->regmap,rt1[i]);
2849 s=get_reg(i_regs->regmap,rs1[i]);
2851 for(hr=0;hr<HOST_REGS;hr++) {
2852 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2854 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2856 c=(i_regs->wasconst>>s)&1;
2858 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2859 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2862 //printf("load_assemble: c=%d\n",c);
2863 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2864 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2866 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2868 // could be FIFO, must perform the read
2870 assem_debug("(forced read)\n");
2871 tl=get_reg(i_regs->regmap,-1);
2875 if(offset||s<0||c) addr=tl;
2877 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2879 //printf("load_assemble: c=%d\n",c);
2880 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2881 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2883 if(th>=0) reglist&=~(1<<th);
2887 map=get_reg(i_regs->regmap,ROREG);
2888 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2890 //#define R29_HACK 1
2892 // Strmnnrmn's speed hack
2893 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2897 if(sp_in_mirror&&rs1[i]==29) {
2898 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2899 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2900 fastload_reg_override=HOST_TEMPREG;
2904 emit_cmpimm(addr,RAM_SIZE);
2906 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2907 // Hint to branch predictor that the branch is unlikely to be taken
2909 emit_jno_unlikely(0);
2917 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2918 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2919 map=get_reg(i_regs->regmap,TLREG);
2922 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2923 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2925 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2926 if (opcode[i]==0x20) { // LB
2929 #ifdef HOST_IMM_ADDR32
2931 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2935 //emit_xorimm(addr,3,tl);
2936 //gen_tlb_addr_r(tl,map);
2937 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2939 #ifdef BIG_ENDIAN_MIPS
2940 if(!c) emit_xorimm(addr,3,tl);
2941 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2945 if(fastload_reg_override) a=fastload_reg_override;
2947 emit_movsbl_indexed_tlb(x,a,map,tl);
2951 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2954 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2956 if (opcode[i]==0x21) { // LH
2959 #ifdef HOST_IMM_ADDR32
2961 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2966 #ifdef BIG_ENDIAN_MIPS
2967 if(!c) emit_xorimm(addr,2,tl);
2968 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2972 if(fastload_reg_override) a=fastload_reg_override;
2974 //emit_movswl_indexed_tlb(x,tl,map,tl);
2977 gen_tlb_addr_r(a,map);
2978 emit_movswl_indexed(x,a,tl);
2981 emit_movswl_indexed(x,a,tl);
2983 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2989 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2992 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2994 if (opcode[i]==0x23) { // LW
2998 if(fastload_reg_override) a=fastload_reg_override;
2999 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3000 #ifdef HOST_IMM_ADDR32
3002 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3005 emit_readword_indexed_tlb(0,a,map,tl);
3008 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3011 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3013 if (opcode[i]==0x24) { // LBU
3016 #ifdef HOST_IMM_ADDR32
3018 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3022 //emit_xorimm(addr,3,tl);
3023 //gen_tlb_addr_r(tl,map);
3024 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3026 #ifdef BIG_ENDIAN_MIPS
3027 if(!c) emit_xorimm(addr,3,tl);
3028 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3032 if(fastload_reg_override) a=fastload_reg_override;
3034 emit_movzbl_indexed_tlb(x,a,map,tl);
3038 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3041 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3043 if (opcode[i]==0x25) { // LHU
3046 #ifdef HOST_IMM_ADDR32
3048 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3053 #ifdef BIG_ENDIAN_MIPS
3054 if(!c) emit_xorimm(addr,2,tl);
3055 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3059 if(fastload_reg_override) a=fastload_reg_override;
3061 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3064 gen_tlb_addr_r(a,map);
3065 emit_movzwl_indexed(x,a,tl);
3068 emit_movzwl_indexed(x,a,tl);
3070 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3076 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3079 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3081 if (opcode[i]==0x27) { // LWU
3086 if(fastload_reg_override) a=fastload_reg_override;
3087 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3088 #ifdef HOST_IMM_ADDR32
3090 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3093 emit_readword_indexed_tlb(0,a,map,tl);
3096 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3099 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3103 if (opcode[i]==0x37) { // LD
3107 if(fastload_reg_override) a=fastload_reg_override;
3108 //gen_tlb_addr_r(tl,map);
3109 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3110 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3111 #ifdef HOST_IMM_ADDR32
3113 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3116 emit_readdword_indexed_tlb(0,a,map,th,tl);
3119 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3122 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3125 //emit_storereg(rt1[i],tl); // DEBUG
3126 //if(opcode[i]==0x23)
3127 //if(opcode[i]==0x24)
3128 //if(opcode[i]==0x23||opcode[i]==0x24)
3129 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3133 emit_readword((int)&last_count,ECX);
3135 if(get_reg(i_regs->regmap,CCREG)<0)
3136 emit_loadreg(CCREG,HOST_CCREG);
3137 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3138 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3139 emit_writeword(HOST_CCREG,(int)&Count);
3142 if(get_reg(i_regs->regmap,CCREG)<0)
3143 emit_loadreg(CCREG,0);
3145 emit_mov(HOST_CCREG,0);
3147 emit_addimm(0,2*ccadj[i],0);
3148 emit_writeword(0,(int)&Count);
3150 emit_call((int)memdebug);
3152 restore_regs(0x100f);
3156 #ifndef loadlr_assemble
3157 void loadlr_assemble(int i,struct regstat *i_regs)
3159 printf("Need loadlr_assemble for this architecture.\n");
3164 void store_assemble(int i,struct regstat *i_regs)
3169 int jaddr=0,jaddr2,type;
3170 int memtarget=0,c=0;
3171 int agr=AGEN1+(i&1);
3172 int faststore_reg_override=0;
3174 th=get_reg(i_regs->regmap,rs2[i]|64);
3175 tl=get_reg(i_regs->regmap,rs2[i]);
3176 s=get_reg(i_regs->regmap,rs1[i]);
3177 temp=get_reg(i_regs->regmap,agr);
3178 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3181 c=(i_regs->wasconst>>s)&1;
3183 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3184 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3189 for(hr=0;hr<HOST_REGS;hr++) {
3190 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3192 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3193 if(offset||s<0||c) addr=temp;
3198 if(sp_in_mirror&&rs1[i]==29) {
3199 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3200 emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3201 faststore_reg_override=HOST_TEMPREG;
3206 // Strmnnrmn's speed hack
3207 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3209 emit_cmpimm(addr,RAM_SIZE);
3210 #ifdef DESTRUCTIVE_SHIFT
3211 if(s==addr) emit_mov(s,temp);
3215 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3219 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3220 // Hint to branch predictor that the branch is unlikely to be taken
3222 emit_jno_unlikely(0);
3230 if (opcode[i]==0x28) x=3; // SB
3231 if (opcode[i]==0x29) x=2; // SH
3232 map=get_reg(i_regs->regmap,TLREG);
3235 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3236 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3239 if (opcode[i]==0x28) { // SB
3242 #ifdef BIG_ENDIAN_MIPS
3243 if(!c) emit_xorimm(addr,3,temp);
3244 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3248 if(faststore_reg_override) a=faststore_reg_override;
3249 //gen_tlb_addr_w(temp,map);
3250 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3251 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3255 if (opcode[i]==0x29) { // SH
3258 #ifdef BIG_ENDIAN_MIPS
3259 if(!c) emit_xorimm(addr,2,temp);
3260 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3264 if(faststore_reg_override) a=faststore_reg_override;
3266 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3269 gen_tlb_addr_w(a,map);
3270 emit_writehword_indexed(tl,x,a);
3272 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3276 if (opcode[i]==0x2B) { // SW
3279 if(faststore_reg_override) a=faststore_reg_override;
3280 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3281 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3285 if (opcode[i]==0x3F) { // SD
3288 if(faststore_reg_override) a=faststore_reg_override;
3291 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3292 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3293 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3296 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3297 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3298 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3305 // PCSX store handlers don't check invcode again
3307 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3313 #ifdef DESTRUCTIVE_SHIFT
3314 // The x86 shift operation is 'destructive'; it overwrites the
3315 // source register, so we need to make a copy first and use that.
3318 #if defined(HOST_IMM8)
3319 int ir=get_reg(i_regs->regmap,INVCP);
3321 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3323 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3325 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3326 emit_callne(invalidate_addr_reg[addr]);
3330 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3335 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3336 } else if(c&&!memtarget) {
3337 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3339 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3340 //if(opcode[i]==0x2B || opcode[i]==0x28)
3341 //if(opcode[i]==0x2B || opcode[i]==0x29)
3342 //if(opcode[i]==0x2B)
3343 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3351 emit_readword((int)&last_count,ECX);
3353 if(get_reg(i_regs->regmap,CCREG)<0)
3354 emit_loadreg(CCREG,HOST_CCREG);
3355 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3356 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3357 emit_writeword(HOST_CCREG,(int)&Count);
3360 if(get_reg(i_regs->regmap,CCREG)<0)
3361 emit_loadreg(CCREG,0);
3363 emit_mov(HOST_CCREG,0);
3365 emit_addimm(0,2*ccadj[i],0);
3366 emit_writeword(0,(int)&Count);
3368 emit_call((int)memdebug);
3373 restore_regs(0x100f);
3378 void storelr_assemble(int i,struct regstat *i_regs)