66603ea8857f33dfafeb15242cfd39b12d4aa7b0
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2  *   Mupen64plus - new_dynarec.c                                           *
3  *   Copyright (C) 2009-2011 Ari64                                         *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21 #include <stdlib.h>
22 #include <stdint.h> //include for uint64_t
23 #include <assert.h>
24
25 #include "emu_if.h" //emulator interface
26
27 #include <sys/mman.h>
28
29 #ifdef __i386__
30 #include "assem_x86.h"
31 #endif
32 #ifdef __x86_64__
33 #include "assem_x64.h"
34 #endif
35 #ifdef __arm__
36 #include "assem_arm.h"
37 #endif
38
39 #define MAXBLOCK 4096
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
42
43 struct regstat
44 {
45   signed char regmap_entry[HOST_REGS];
46   signed char regmap[HOST_REGS];
47   uint64_t was32;
48   uint64_t is32;
49   uint64_t wasdirty;
50   uint64_t dirty;
51   uint64_t u;
52   uint64_t uu;
53   u_int wasconst;
54   u_int isconst;
55   uint64_t constmap[HOST_REGS];
56 };
57
58 struct ll_entry
59 {
60   u_int vaddr;
61   u_int reg32;
62   void *addr;
63   struct ll_entry *next;
64 };
65
66   u_int start;
67   u_int *source;
68   u_int pagelimit;
69   char insn[MAXBLOCK][10];
70   u_char itype[MAXBLOCK];
71   u_char opcode[MAXBLOCK];
72   u_char opcode2[MAXBLOCK];
73   u_char bt[MAXBLOCK];
74   u_char rs1[MAXBLOCK];
75   u_char rs2[MAXBLOCK];
76   u_char rt1[MAXBLOCK];
77   u_char rt2[MAXBLOCK];
78   u_char us1[MAXBLOCK];
79   u_char us2[MAXBLOCK];
80   u_char dep1[MAXBLOCK];
81   u_char dep2[MAXBLOCK];
82   u_char lt1[MAXBLOCK];
83   int imm[MAXBLOCK];
84   u_int ba[MAXBLOCK];
85   char likely[MAXBLOCK];
86   char is_ds[MAXBLOCK];
87   char ooo[MAXBLOCK];
88   uint64_t unneeded_reg[MAXBLOCK];
89   uint64_t unneeded_reg_upper[MAXBLOCK];
90   uint64_t branch_unneeded_reg[MAXBLOCK];
91   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
92   uint64_t p32[MAXBLOCK];
93   uint64_t pr32[MAXBLOCK];
94   signed char regmap_pre[MAXBLOCK][HOST_REGS];
95   signed char regmap[MAXBLOCK][HOST_REGS];
96   signed char regmap_entry[MAXBLOCK][HOST_REGS];
97   uint64_t constmap[MAXBLOCK][HOST_REGS];
98   struct regstat regs[MAXBLOCK];
99   struct regstat branch_regs[MAXBLOCK];
100   signed char minimum_free_regs[MAXBLOCK];
101   u_int needed_reg[MAXBLOCK];
102   uint64_t requires_32bit[MAXBLOCK];
103   u_int wont_dirty[MAXBLOCK];
104   u_int will_dirty[MAXBLOCK];
105   int ccadj[MAXBLOCK];
106   int slen;
107   u_int instr_addr[MAXBLOCK];
108   u_int link_addr[MAXBLOCK][3];
109   int linkcount;
110   u_int stubs[MAXBLOCK*3][8];
111   int stubcount;
112   u_int literals[1024][2];
113   int literalcount;
114   int is_delayslot;
115   int cop1_usable;
116   u_char *out;
117   struct ll_entry *jump_in[4096];
118   struct ll_entry *jump_out[4096];
119   struct ll_entry *jump_dirty[4096];
120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
121   char shadow[1048576]  __attribute__((aligned(16)));
122   void *copy;
123   int expirep;
124 #ifndef PCSX
125   u_int using_tlb;
126 #else
127   static const u_int using_tlb=0;
128 #endif
129   static u_int sp_in_mirror;
130   u_int stop_after_jal;
131   extern u_char restore_candidate[512];
132   extern int cycle_count;
133
134   /* registers that may be allocated */
135   /* 1-31 gpr */
136 #define HIREG 32 // hi
137 #define LOREG 33 // lo
138 #define FSREG 34 // FPU status (FCSR)
139 #define CSREG 35 // Coprocessor status
140 #define CCREG 36 // Cycle count
141 #define INVCP 37 // Pointer to invalid_code
142 #define MMREG 38 // Pointer to memory_map
143 #define ROREG 39 // ram offset (if rdram!=0x80000000)
144 #define TEMPREG 40
145 #define FTEMP 40 // FPU temporary register
146 #define PTEMP 41 // Prefetch temporary register
147 #define TLREG 42 // TLB mapping offset
148 #define RHASH 43 // Return address hash
149 #define RHTBL 44 // Return address hash table address
150 #define RTEMP 45 // JR/JALR address register
151 #define MAXREG 45
152 #define AGEN1 46 // Address generation temporary register
153 #define AGEN2 47 // Address generation temporary register
154 #define MGEN1 48 // Maptable address generation temporary register
155 #define MGEN2 49 // Maptable address generation temporary register
156 #define BTREG 50 // Branch target temporary register
157
158   /* instruction types */
159 #define NOP 0     // No operation
160 #define LOAD 1    // Load
161 #define STORE 2   // Store
162 #define LOADLR 3  // Unaligned load
163 #define STORELR 4 // Unaligned store
164 #define MOV 5     // Move 
165 #define ALU 6     // Arithmetic/logic
166 #define MULTDIV 7 // Multiply/divide
167 #define SHIFT 8   // Shift by register
168 #define SHIFTIMM 9// Shift by immediate
169 #define IMM16 10  // 16-bit immediate
170 #define RJUMP 11  // Unconditional jump to register
171 #define UJUMP 12  // Unconditional jump
172 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
173 #define SJUMP 14  // Conditional branch (regimm format)
174 #define COP0 15   // Coprocessor 0
175 #define COP1 16   // Coprocessor 1
176 #define C1LS 17   // Coprocessor 1 load/store
177 #define FJUMP 18  // Conditional branch (floating point)
178 #define FLOAT 19  // Floating point unit
179 #define FCONV 20  // Convert integer to float
180 #define FCOMP 21  // Floating point compare (sets FSREG)
181 #define SYSCALL 22// SYSCALL
182 #define OTHER 23  // Other
183 #define SPAN 24   // Branch/delay slot spans 2 pages
184 #define NI 25     // Not implemented
185 #define HLECALL 26// PCSX fake opcodes for HLE
186 #define COP2 27   // Coprocessor 2 move
187 #define C2LS 28   // Coprocessor 2 load/store
188 #define C2OP 29   // Coprocessor 2 operation
189 #define INTCALL 30// Call interpreter to handle rare corner cases
190
191   /* stubs */
192 #define CC_STUB 1
193 #define FP_STUB 2
194 #define LOADB_STUB 3
195 #define LOADH_STUB 4
196 #define LOADW_STUB 5
197 #define LOADD_STUB 6
198 #define LOADBU_STUB 7
199 #define LOADHU_STUB 8
200 #define STOREB_STUB 9
201 #define STOREH_STUB 10
202 #define STOREW_STUB 11
203 #define STORED_STUB 12
204 #define STORELR_STUB 13
205 #define INVCODE_STUB 14
206
207   /* branch codes */
208 #define TAKEN 1
209 #define NOTTAKEN 2
210 #define NULLDS 3
211
212 // asm linkage
213 int new_recompile_block(int addr);
214 void *get_addr_ht(u_int vaddr);
215 void invalidate_block(u_int block);
216 void invalidate_addr(u_int addr);
217 void remove_hash(int vaddr);
218 void jump_vaddr();
219 void dyna_linker();
220 void dyna_linker_ds();
221 void verify_code();
222 void verify_code_vm();
223 void verify_code_ds();
224 void cc_interrupt();
225 void fp_exception();
226 void fp_exception_ds();
227 void jump_syscall();
228 void jump_syscall_hle();
229 void jump_eret();
230 void jump_hlecall();
231 void jump_intcall();
232 void new_dyna_leave();
233
234 // TLB
235 void TLBWI_new();
236 void TLBWR_new();
237 void read_nomem_new();
238 void read_nomemb_new();
239 void read_nomemh_new();
240 void read_nomemd_new();
241 void write_nomem_new();
242 void write_nomemb_new();
243 void write_nomemh_new();
244 void write_nomemd_new();
245 void write_rdram_new();
246 void write_rdramb_new();
247 void write_rdramh_new();
248 void write_rdramd_new();
249 extern u_int memory_map[1048576];
250
251 // Needed by assembler
252 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
253 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
254 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
255 void load_all_regs(signed char i_regmap[]);
256 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
257 void load_regs_entry(int t);
258 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
259
260 int tracedebug=0;
261
262 //#define DEBUG_CYCLE_COUNT 1
263
264 void nullf() {}
265 //#define assem_debug printf
266 //#define inv_debug printf
267 #define assem_debug nullf
268 #define inv_debug nullf
269
270 static void tlb_hacks()
271 {
272 #ifndef DISABLE_TLB
273   // Goldeneye hack
274   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
275   {
276     u_int addr;
277     int n;
278     switch (ROM_HEADER->Country_code&0xFF) 
279     {
280       case 0x45: // U
281         addr=0x34b30;
282         break;                   
283       case 0x4A: // J 
284         addr=0x34b70;    
285         break;    
286       case 0x50: // E 
287         addr=0x329f0;
288         break;                        
289       default: 
290         // Unknown country code
291         addr=0;
292         break;
293     }
294     u_int rom_addr=(u_int)rom;
295     #ifdef ROM_COPY
296     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
297     // in the lower 4G of memory to use this hack.  Copy it if necessary.
298     if((void *)rom>(void *)0xffffffff) {
299       munmap(ROM_COPY, 67108864);
300       if(mmap(ROM_COPY, 12582912,
301               PROT_READ | PROT_WRITE,
302               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
303               -1, 0) <= 0) {printf("mmap() failed\n");}
304       memcpy(ROM_COPY,rom,12582912);
305       rom_addr=(u_int)ROM_COPY;
306     }
307     #endif
308     if(addr) {
309       for(n=0x7F000;n<0x80000;n++) {
310         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
311       }
312     }
313   }
314 #endif
315 }
316
317 static u_int get_page(u_int vaddr)
318 {
319 #ifndef PCSX
320   u_int page=(vaddr^0x80000000)>>12;
321 #else
322   u_int page=vaddr&~0xe0000000;
323   if (page < 0x1000000)
324     page &= ~0x0e00000; // RAM mirrors
325   page>>=12;
326 #endif
327 #ifndef DISABLE_TLB
328   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
329 #endif
330   if(page>2048) page=2048+(page&2047);
331   return page;
332 }
333
334 static u_int get_vpage(u_int vaddr)
335 {
336   u_int vpage=(vaddr^0x80000000)>>12;
337 #ifndef DISABLE_TLB
338   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
339 #endif
340   if(vpage>2048) vpage=2048+(vpage&2047);
341   return vpage;
342 }
343
344 // Get address from virtual address
345 // This is called from the recompiled JR/JALR instructions
346 void *get_addr(u_int vaddr)
347 {
348   u_int page=get_page(vaddr);
349   u_int vpage=get_vpage(vaddr);
350   struct ll_entry *head;
351   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
352   head=jump_in[page];
353   while(head!=NULL) {
354     if(head->vaddr==vaddr&&head->reg32==0) {
355   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
356       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
357       ht_bin[3]=ht_bin[1];
358       ht_bin[2]=ht_bin[0];
359       ht_bin[1]=(int)head->addr;
360       ht_bin[0]=vaddr;
361       return head->addr;
362     }
363     head=head->next;
364   }
365   head=jump_dirty[vpage];
366   while(head!=NULL) {
367     if(head->vaddr==vaddr&&head->reg32==0) {
368       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
369       // Don't restore blocks which are about to expire from the cache
370       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
371       if(verify_dirty(head->addr)) {
372         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
373         invalid_code[vaddr>>12]=0;
374         memory_map[vaddr>>12]|=0x40000000;
375         if(vpage<2048) {
376 #ifndef DISABLE_TLB
377           if(tlb_LUT_r[vaddr>>12]) {
378             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
379             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
380           }
381 #endif
382           restore_candidate[vpage>>3]|=1<<(vpage&7);
383         }
384         else restore_candidate[page>>3]|=1<<(page&7);
385         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
386         if(ht_bin[0]==vaddr) {
387           ht_bin[1]=(int)head->addr; // Replace existing entry
388         }
389         else
390         {
391           ht_bin[3]=ht_bin[1];
392           ht_bin[2]=ht_bin[0];
393           ht_bin[1]=(int)head->addr;
394           ht_bin[0]=vaddr;
395         }
396         return head->addr;
397       }
398     }
399     head=head->next;
400   }
401   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
402   int r=new_recompile_block(vaddr);
403   if(r==0) return get_addr(vaddr);
404   // Execute in unmapped page, generate pagefault execption
405   Status|=2;
406   Cause=(vaddr<<31)|0x8;
407   EPC=(vaddr&1)?vaddr-5:vaddr;
408   BadVAddr=(vaddr&~1);
409   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
410   EntryHi=BadVAddr&0xFFFFE000;
411   return get_addr_ht(0x80000000);
412 }
413 // Look up address in hash table first
414 void *get_addr_ht(u_int vaddr)
415 {
416   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
417   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
418   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
419   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
420   return get_addr(vaddr);
421 }
422
423 void *get_addr_32(u_int vaddr,u_int flags)
424 {
425 #ifdef FORCE32
426   return get_addr(vaddr);
427 #else
428   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
429   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
430   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
431   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
432   u_int page=get_page(vaddr);
433   u_int vpage=get_vpage(vaddr);
434   struct ll_entry *head;
435   head=jump_in[page];
436   while(head!=NULL) {
437     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
438       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
439       if(head->reg32==0) {
440         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
441         if(ht_bin[0]==-1) {
442           ht_bin[1]=(int)head->addr;
443           ht_bin[0]=vaddr;
444         }else if(ht_bin[2]==-1) {
445           ht_bin[3]=(int)head->addr;
446           ht_bin[2]=vaddr;
447         }
448         //ht_bin[3]=ht_bin[1];
449         //ht_bin[2]=ht_bin[0];
450         //ht_bin[1]=(int)head->addr;
451         //ht_bin[0]=vaddr;
452       }
453       return head->addr;
454     }
455     head=head->next;
456   }
457   head=jump_dirty[vpage];
458   while(head!=NULL) {
459     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
460       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
461       // Don't restore blocks which are about to expire from the cache
462       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
463       if(verify_dirty(head->addr)) {
464         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
465         invalid_code[vaddr>>12]=0;
466         memory_map[vaddr>>12]|=0x40000000;
467         if(vpage<2048) {
468 #ifndef DISABLE_TLB
469           if(tlb_LUT_r[vaddr>>12]) {
470             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
471             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
472           }
473 #endif
474           restore_candidate[vpage>>3]|=1<<(vpage&7);
475         }
476         else restore_candidate[page>>3]|=1<<(page&7);
477         if(head->reg32==0) {
478           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
479           if(ht_bin[0]==-1) {
480             ht_bin[1]=(int)head->addr;
481             ht_bin[0]=vaddr;
482           }else if(ht_bin[2]==-1) {
483             ht_bin[3]=(int)head->addr;
484             ht_bin[2]=vaddr;
485           }
486           //ht_bin[3]=ht_bin[1];
487           //ht_bin[2]=ht_bin[0];
488           //ht_bin[1]=(int)head->addr;
489           //ht_bin[0]=vaddr;
490         }
491         return head->addr;
492       }
493     }
494     head=head->next;
495   }
496   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
497   int r=new_recompile_block(vaddr);
498   if(r==0) return get_addr(vaddr);
499   // Execute in unmapped page, generate pagefault execption
500   Status|=2;
501   Cause=(vaddr<<31)|0x8;
502   EPC=(vaddr&1)?vaddr-5:vaddr;
503   BadVAddr=(vaddr&~1);
504   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
505   EntryHi=BadVAddr&0xFFFFE000;
506   return get_addr_ht(0x80000000);
507 #endif
508 }
509
510 void clear_all_regs(signed char regmap[])
511 {
512   int hr;
513   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
514 }
515
516 signed char get_reg(signed char regmap[],int r)
517 {
518   int hr;
519   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
520   return -1;
521 }
522
523 // Find a register that is available for two consecutive cycles
524 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
525 {
526   int hr;
527   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
528   return -1;
529 }
530
531 int count_free_regs(signed char regmap[])
532 {
533   int count=0;
534   int hr;
535   for(hr=0;hr<HOST_REGS;hr++)
536   {
537     if(hr!=EXCLUDE_REG) {
538       if(regmap[hr]<0) count++;
539     }
540   }
541   return count;
542 }
543
544 void dirty_reg(struct regstat *cur,signed char reg)
545 {
546   int hr;
547   if(!reg) return;
548   for (hr=0;hr<HOST_REGS;hr++) {
549     if((cur->regmap[hr]&63)==reg) {
550       cur->dirty|=1<<hr;
551     }
552   }
553 }
554
555 // If we dirty the lower half of a 64 bit register which is now being
556 // sign-extended, we need to dump the upper half.
557 // Note: Do this only after completion of the instruction, because
558 // some instructions may need to read the full 64-bit value even if
559 // overwriting it (eg SLTI, DSRA32).
560 static void flush_dirty_uppers(struct regstat *cur)
561 {
562   int hr,reg;
563   for (hr=0;hr<HOST_REGS;hr++) {
564     if((cur->dirty>>hr)&1) {
565       reg=cur->regmap[hr];
566       if(reg>=64) 
567         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
568     }
569   }
570 }
571
572 void set_const(struct regstat *cur,signed char reg,uint64_t value)
573 {
574   int hr;
575   if(!reg) return;
576   for (hr=0;hr<HOST_REGS;hr++) {
577     if(cur->regmap[hr]==reg) {
578       cur->isconst|=1<<hr;
579       cur->constmap[hr]=value;
580     }
581     else if((cur->regmap[hr]^64)==reg) {
582       cur->isconst|=1<<hr;
583       cur->constmap[hr]=value>>32;
584     }
585   }
586 }
587
588 void clear_const(struct regstat *cur,signed char reg)
589 {
590   int hr;
591   if(!reg) return;
592   for (hr=0;hr<HOST_REGS;hr++) {
593     if((cur->regmap[hr]&63)==reg) {
594       cur->isconst&=~(1<<hr);
595     }
596   }
597 }
598
599 int is_const(struct regstat *cur,signed char reg)
600 {
601   int hr;
602   if(reg<0) return 0;
603   if(!reg) return 1;
604   for (hr=0;hr<HOST_REGS;hr++) {
605     if((cur->regmap[hr]&63)==reg) {
606       return (cur->isconst>>hr)&1;
607     }
608   }
609   return 0;
610 }
611 uint64_t get_const(struct regstat *cur,signed char reg)
612 {
613   int hr;
614   if(!reg) return 0;
615   for (hr=0;hr<HOST_REGS;hr++) {
616     if(cur->regmap[hr]==reg) {
617       return cur->constmap[hr];
618     }
619   }
620   printf("Unknown constant in r%d\n",reg);
621   exit(1);
622 }
623
624 // Least soon needed registers
625 // Look at the next ten instructions and see which registers
626 // will be used.  Try not to reallocate these.
627 void lsn(u_char hsn[], int i, int *preferred_reg)
628 {
629   int j;
630   int b=-1;
631   for(j=0;j<9;j++)
632   {
633     if(i+j>=slen) {
634       j=slen-i-1;
635       break;
636     }
637     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
638     {
639       // Don't go past an unconditonal jump
640       j++;
641       break;
642     }
643   }
644   for(;j>=0;j--)
645   {
646     if(rs1[i+j]) hsn[rs1[i+j]]=j;
647     if(rs2[i+j]) hsn[rs2[i+j]]=j;
648     if(rt1[i+j]) hsn[rt1[i+j]]=j;
649     if(rt2[i+j]) hsn[rt2[i+j]]=j;
650     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
651       // Stores can allocate zero
652       hsn[rs1[i+j]]=j;
653       hsn[rs2[i+j]]=j;
654     }
655     // On some architectures stores need invc_ptr
656     #if defined(HOST_IMM8)
657     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
658       hsn[INVCP]=j;
659     }
660     #endif
661     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
662     {
663       hsn[CCREG]=j;
664       b=j;
665     }
666   }
667   if(b>=0)
668   {
669     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
670     {
671       // Follow first branch
672       int t=(ba[i+b]-start)>>2;
673       j=7-b;if(t+j>=slen) j=slen-t-1;
674       for(;j>=0;j--)
675       {
676         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
677         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
678         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
679         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
680       }
681     }
682     // TODO: preferred register based on backward branch
683   }
684   // Delay slot should preferably not overwrite branch conditions or cycle count
685   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
686     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
687     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
688     hsn[CCREG]=1;
689     // ...or hash tables
690     hsn[RHASH]=1;
691     hsn[RHTBL]=1;
692   }
693   // Coprocessor load/store needs FTEMP, even if not declared
694   if(itype[i]==C1LS||itype[i]==C2LS) {
695     hsn[FTEMP]=0;
696   }
697   // Load L/R also uses FTEMP as a temporary register
698   if(itype[i]==LOADLR) {
699     hsn[FTEMP]=0;
700   }
701   // Also SWL/SWR/SDL/SDR
702   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
703     hsn[FTEMP]=0;
704   }
705   // Don't remove the TLB registers either
706   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
707     hsn[TLREG]=0;
708   }
709   // Don't remove the miniht registers
710   if(itype[i]==UJUMP||itype[i]==RJUMP)
711   {
712     hsn[RHASH]=0;
713     hsn[RHTBL]=0;
714   }
715 }
716
717 // We only want to allocate registers if we're going to use them again soon
718 int needed_again(int r, int i)
719 {
720   int j;
721   int b=-1;
722   int rn=10;
723   
724   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
725   {
726     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
727       return 0; // Don't need any registers if exiting the block
728   }
729   for(j=0;j<9;j++)
730   {
731     if(i+j>=slen) {
732       j=slen-i-1;
733       break;
734     }
735     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
736     {
737       // Don't go past an unconditonal jump
738       j++;
739       break;
740     }
741     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
742     {
743       break;
744     }
745   }
746   for(;j>=1;j--)
747   {
748     if(rs1[i+j]==r) rn=j;
749     if(rs2[i+j]==r) rn=j;
750     if((unneeded_reg[i+j]>>r)&1) rn=10;
751     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
752     {
753       b=j;
754     }
755   }
756   /*
757   if(b>=0)
758   {
759     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
760     {
761       // Follow first branch
762       int o=rn;
763       int t=(ba[i+b]-start)>>2;
764       j=7-b;if(t+j>=slen) j=slen-t-1;
765       for(;j>=0;j--)
766       {
767         if(!((unneeded_reg[t+j]>>r)&1)) {
768           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
769           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
770         }
771         else rn=o;
772       }
773     }
774   }*/
775   if(rn<10) return 1;
776   return 0;
777 }
778
779 // Try to match register allocations at the end of a loop with those
780 // at the beginning
781 int loop_reg(int i, int r, int hr)
782 {
783   int j,k;
784   for(j=0;j<9;j++)
785   {
786     if(i+j>=slen) {
787       j=slen-i-1;
788       break;
789     }
790     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
791     {
792       // Don't go past an unconditonal jump
793       j++;
794       break;
795     }
796   }
797   k=0;
798   if(i>0){
799     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
800       k--;
801   }
802   for(;k<j;k++)
803   {
804     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
805     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
806     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
807     {
808       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
809       {
810         int t=(ba[i+k]-start)>>2;
811         int reg=get_reg(regs[t].regmap_entry,r);
812         if(reg>=0) return reg;
813         //reg=get_reg(regs[t+1].regmap_entry,r);
814         //if(reg>=0) return reg;
815       }
816     }
817   }
818   return hr;
819 }
820
821
822 // Allocate every register, preserving source/target regs
823 void alloc_all(struct regstat *cur,int i)
824 {
825   int hr;
826   
827   for(hr=0;hr<HOST_REGS;hr++) {
828     if(hr!=EXCLUDE_REG) {
829       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
830          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
831       {
832         cur->regmap[hr]=-1;
833         cur->dirty&=~(1<<hr);
834       }
835       // Don't need zeros
836       if((cur->regmap[hr]&63)==0)
837       {
838         cur->regmap[hr]=-1;
839         cur->dirty&=~(1<<hr);
840       }
841     }
842   }
843 }
844
845
846 void div64(int64_t dividend,int64_t divisor)
847 {
848   lo=dividend/divisor;
849   hi=dividend%divisor;
850   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
851   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
852 }
853 void divu64(uint64_t dividend,uint64_t divisor)
854 {
855   lo=dividend/divisor;
856   hi=dividend%divisor;
857   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
858   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
859 }
860
861 void mult64(uint64_t m1,uint64_t m2)
862 {
863    unsigned long long int op1, op2, op3, op4;
864    unsigned long long int result1, result2, result3, result4;
865    unsigned long long int temp1, temp2, temp3, temp4;
866    int sign = 0;
867    
868    if (m1 < 0)
869      {
870     op2 = -m1;
871     sign = 1 - sign;
872      }
873    else op2 = m1;
874    if (m2 < 0)
875      {
876     op4 = -m2;
877     sign = 1 - sign;
878      }
879    else op4 = m2;
880    
881    op1 = op2 & 0xFFFFFFFF;
882    op2 = (op2 >> 32) & 0xFFFFFFFF;
883    op3 = op4 & 0xFFFFFFFF;
884    op4 = (op4 >> 32) & 0xFFFFFFFF;
885    
886    temp1 = op1 * op3;
887    temp2 = (temp1 >> 32) + op1 * op4;
888    temp3 = op2 * op3;
889    temp4 = (temp3 >> 32) + op2 * op4;
890    
891    result1 = temp1 & 0xFFFFFFFF;
892    result2 = temp2 + (temp3 & 0xFFFFFFFF);
893    result3 = (result2 >> 32) + temp4;
894    result4 = (result3 >> 32);
895    
896    lo = result1 | (result2 << 32);
897    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898    if (sign)
899      {
900     hi = ~hi;
901     if (!lo) hi++;
902     else lo = ~lo + 1;
903      }
904 }
905
906 void multu64(uint64_t m1,uint64_t m2)
907 {
908    unsigned long long int op1, op2, op3, op4;
909    unsigned long long int result1, result2, result3, result4;
910    unsigned long long int temp1, temp2, temp3, temp4;
911    
912    op1 = m1 & 0xFFFFFFFF;
913    op2 = (m1 >> 32) & 0xFFFFFFFF;
914    op3 = m2 & 0xFFFFFFFF;
915    op4 = (m2 >> 32) & 0xFFFFFFFF;
916    
917    temp1 = op1 * op3;
918    temp2 = (temp1 >> 32) + op1 * op4;
919    temp3 = op2 * op3;
920    temp4 = (temp3 >> 32) + op2 * op4;
921    
922    result1 = temp1 & 0xFFFFFFFF;
923    result2 = temp2 + (temp3 & 0xFFFFFFFF);
924    result3 = (result2 >> 32) + temp4;
925    result4 = (result3 >> 32);
926    
927    lo = result1 | (result2 << 32);
928    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
929    
930   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
931   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
932 }
933
934 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
935 {
936   if(bits) {
937     original<<=64-bits;
938     original>>=64-bits;
939     loaded<<=bits;
940     original|=loaded;
941   }
942   else original=loaded;
943   return original;
944 }
945 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
946 {
947   if(bits^56) {
948     original>>=64-(bits^56);
949     original<<=64-(bits^56);
950     loaded>>=bits^56;
951     original|=loaded;
952   }
953   else original=loaded;
954   return original;
955 }
956
957 #ifdef __i386__
958 #include "assem_x86.c"
959 #endif
960 #ifdef __x86_64__
961 #include "assem_x64.c"
962 #endif
963 #ifdef __arm__
964 #include "assem_arm.c"
965 #endif
966
967 // Add virtual address mapping to linked list
968 void ll_add(struct ll_entry **head,int vaddr,void *addr)
969 {
970   struct ll_entry *new_entry;
971   new_entry=malloc(sizeof(struct ll_entry));
972   assert(new_entry!=NULL);
973   new_entry->vaddr=vaddr;
974   new_entry->reg32=0;
975   new_entry->addr=addr;
976   new_entry->next=*head;
977   *head=new_entry;
978 }
979
980 // Add virtual address mapping for 32-bit compiled block
981 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
982 {
983   ll_add(head,vaddr,addr);
984 #ifndef FORCE32
985   (*head)->reg32=reg32;
986 #endif
987 }
988
989 // Check if an address is already compiled
990 // but don't return addresses which are about to expire from the cache
991 void *check_addr(u_int vaddr)
992 {
993   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
994   if(ht_bin[0]==vaddr) {
995     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
996       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
997   }
998   if(ht_bin[2]==vaddr) {
999     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1001   }
1002   u_int page=get_page(vaddr);
1003   struct ll_entry *head;
1004   head=jump_in[page];
1005   while(head!=NULL) {
1006     if(head->vaddr==vaddr&&head->reg32==0) {
1007       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1008         // Update existing entry with current address
1009         if(ht_bin[0]==vaddr) {
1010           ht_bin[1]=(int)head->addr;
1011           return head->addr;
1012         }
1013         if(ht_bin[2]==vaddr) {
1014           ht_bin[3]=(int)head->addr;
1015           return head->addr;
1016         }
1017         // Insert into hash table with low priority.
1018         // Don't evict existing entries, as they are probably
1019         // addresses that are being accessed frequently.
1020         if(ht_bin[0]==-1) {
1021           ht_bin[1]=(int)head->addr;
1022           ht_bin[0]=vaddr;
1023         }else if(ht_bin[2]==-1) {
1024           ht_bin[3]=(int)head->addr;
1025           ht_bin[2]=vaddr;
1026         }
1027         return head->addr;
1028       }
1029     }
1030     head=head->next;
1031   }
1032   return 0;
1033 }
1034
1035 void remove_hash(int vaddr)
1036 {
1037   //printf("remove hash: %x\n",vaddr);
1038   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1039   if(ht_bin[2]==vaddr) {
1040     ht_bin[2]=ht_bin[3]=-1;
1041   }
1042   if(ht_bin[0]==vaddr) {
1043     ht_bin[0]=ht_bin[2];
1044     ht_bin[1]=ht_bin[3];
1045     ht_bin[2]=ht_bin[3]=-1;
1046   }
1047 }
1048
1049 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1050 {
1051   struct ll_entry *next;
1052   while(*head) {
1053     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
1054        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1055     {
1056       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1057       remove_hash((*head)->vaddr);
1058       next=(*head)->next;
1059       free(*head);
1060       *head=next;
1061     }
1062     else
1063     {
1064       head=&((*head)->next);
1065     }
1066   }
1067 }
1068
1069 // Remove all entries from linked list
1070 void ll_clear(struct ll_entry **head)
1071 {
1072   struct ll_entry *cur;
1073   struct ll_entry *next;
1074   if(cur=*head) {
1075     *head=0;
1076     while(cur) {
1077       next=cur->next;
1078       free(cur);
1079       cur=next;
1080     }
1081   }
1082 }
1083
1084 // Dereference the pointers and remove if it matches
1085 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1086 {
1087   while(head) {
1088     int ptr=get_pointer(head->addr);
1089     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1090     if(((ptr>>shift)==(addr>>shift)) ||
1091        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1092     {
1093       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1094       u_int host_addr=(u_int)kill_pointer(head->addr);
1095       #ifdef __arm__
1096         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1097       #endif
1098     }
1099     head=head->next;
1100   }
1101 }
1102
1103 // This is called when we write to a compiled block (see do_invstub)
1104 void invalidate_page(u_int page)
1105 {
1106   struct ll_entry *head;
1107   struct ll_entry *next;
1108   head=jump_in[page];
1109   jump_in[page]=0;
1110   while(head!=NULL) {
1111     inv_debug("INVALIDATE: %x\n",head->vaddr);
1112     remove_hash(head->vaddr);
1113     next=head->next;
1114     free(head);
1115     head=next;
1116   }
1117   head=jump_out[page];
1118   jump_out[page]=0;
1119   while(head!=NULL) {
1120     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1121     u_int host_addr=(u_int)kill_pointer(head->addr);
1122     #ifdef __arm__
1123       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1124     #endif
1125     next=head->next;
1126     free(head);
1127     head=next;
1128   }
1129 }
1130 void invalidate_block(u_int block)
1131 {
1132   u_int page=get_page(block<<12);
1133   u_int vpage=get_vpage(block<<12);
1134   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1135   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1136   u_int first,last;
1137   first=last=page;
1138   struct ll_entry *head;
1139   head=jump_dirty[vpage];
1140   //printf("page=%d vpage=%d\n",page,vpage);
1141   while(head!=NULL) {
1142     u_int start,end;
1143     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1144       get_bounds((int)head->addr,&start,&end);
1145       //printf("start: %x end: %x\n",start,end);
1146       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1147         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1148           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1149           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1150         }
1151       }
1152 #ifndef DISABLE_TLB
1153       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1154         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1155           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1156           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1157         }
1158       }
1159 #endif
1160     }
1161     head=head->next;
1162   }
1163   //printf("first=%d last=%d\n",first,last);
1164   invalidate_page(page);
1165   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166   assert(last<page+5);
1167   // Invalidate the adjacent pages if a block crosses a 4K boundary
1168   while(first<page) {
1169     invalidate_page(first);
1170     first++;
1171   }
1172   for(first=page+1;first<last;first++) {
1173     invalidate_page(first);
1174   }
1175   #ifdef __arm__
1176     do_clear_cache();
1177   #endif
1178   
1179   // Don't trap writes
1180   invalid_code[block]=1;
1181 #ifdef PCSX
1182   invalid_code[((u_int)0x80000000>>12)|page]=1;
1183 #endif
1184 #ifndef DISABLE_TLB
1185   // If there is a valid TLB entry for this page, remove write protect
1186   if(tlb_LUT_w[block]) {
1187     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1188     // CHECK: Is this right?
1189     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1190     u_int real_block=tlb_LUT_w[block]>>12;
1191     invalid_code[real_block]=1;
1192     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1193   }
1194   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1195 #endif
1196
1197   #ifdef USE_MINI_HT
1198   memset(mini_ht,-1,sizeof(mini_ht));
1199   #endif
1200 }
1201 void invalidate_addr(u_int addr)
1202 {
1203   invalidate_block(addr>>12);
1204 }
1205 // This is called when loading a save state.
1206 // Anything could have changed, so invalidate everything.
1207 void invalidate_all_pages()
1208 {
1209   u_int page,n;
1210   for(page=0;page<4096;page++)
1211     invalidate_page(page);
1212   for(page=0;page<1048576;page++)
1213     if(!invalid_code[page]) {
1214       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1215       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1216     }
1217   #ifdef __arm__
1218   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1219   #endif
1220   #ifdef USE_MINI_HT
1221   memset(mini_ht,-1,sizeof(mini_ht));
1222   #endif
1223   #ifndef DISABLE_TLB
1224   // TLB
1225   for(page=0;page<0x100000;page++) {
1226     if(tlb_LUT_r[page]) {
1227       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1228       if(!tlb_LUT_w[page]||!invalid_code[page])
1229         memory_map[page]|=0x40000000; // Write protect
1230     }
1231     else memory_map[page]=-1;
1232     if(page==0x80000) page=0xC0000;
1233   }
1234   tlb_hacks();
1235   #endif
1236 }
1237
1238 // Add an entry to jump_out after making a link
1239 void add_link(u_int vaddr,void *src)
1240 {
1241   u_int page=get_page(vaddr);
1242   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1243   ll_add(jump_out+page,vaddr,src);
1244   //int ptr=get_pointer(src);
1245   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1246 }
1247
1248 // If a code block was found to be unmodified (bit was set in
1249 // restore_candidate) and it remains unmodified (bit is clear
1250 // in invalid_code) then move the entries for that 4K page from
1251 // the dirty list to the clean list.
1252 void clean_blocks(u_int page)
1253 {
1254   struct ll_entry *head;
1255   inv_debug("INV: clean_blocks page=%d\n",page);
1256   head=jump_dirty[page];
1257   while(head!=NULL) {
1258     if(!invalid_code[head->vaddr>>12]) {
1259       // Don't restore blocks which are about to expire from the cache
1260       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1261         u_int start,end;
1262         if(verify_dirty((int)head->addr)) {
1263           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1264           u_int i;
1265           u_int inv=0;
1266           get_bounds((int)head->addr,&start,&end);
1267           if(start-(u_int)rdram<RAM_SIZE) {
1268             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1269               inv|=invalid_code[i];
1270             }
1271           }
1272           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1273             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1274             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1275             if(addr<start||addr>=end) inv=1;
1276           }
1277           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1278             inv=1;
1279           }
1280           if(!inv) {
1281             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1282             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1283               u_int ppage=page;
1284 #ifndef DISABLE_TLB
1285               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1286 #endif
1287               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1288               //printf("page=%x, addr=%x\n",page,head->vaddr);
1289               //assert(head->vaddr>>12==(page|0x80000));
1290               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1291               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1292               if(!head->reg32) {
1293                 if(ht_bin[0]==head->vaddr) {
1294                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1295                 }
1296                 if(ht_bin[2]==head->vaddr) {
1297                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1298                 }
1299               }
1300             }
1301           }
1302         }
1303       }
1304     }
1305     head=head->next;
1306   }
1307 }
1308
1309
1310 void mov_alloc(struct regstat *current,int i)
1311 {
1312   // Note: Don't need to actually alloc the source registers
1313   if((~current->is32>>rs1[i])&1) {
1314     //alloc_reg64(current,i,rs1[i]);
1315     alloc_reg64(current,i,rt1[i]);
1316     current->is32&=~(1LL<<rt1[i]);
1317   } else {
1318     //alloc_reg(current,i,rs1[i]);
1319     alloc_reg(current,i,rt1[i]);
1320     current->is32|=(1LL<<rt1[i]);
1321   }
1322   clear_const(current,rs1[i]);
1323   clear_const(current,rt1[i]);
1324   dirty_reg(current,rt1[i]);
1325 }
1326
1327 void shiftimm_alloc(struct regstat *current,int i)
1328 {
1329   clear_const(current,rs1[i]);
1330   clear_const(current,rt1[i]);
1331   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1332   {
1333     if(rt1[i]) {
1334       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1335       else lt1[i]=rs1[i];
1336       alloc_reg(current,i,rt1[i]);
1337       current->is32|=1LL<<rt1[i];
1338       dirty_reg(current,rt1[i]);
1339     }
1340   }
1341   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1342   {
1343     if(rt1[i]) {
1344       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1345       alloc_reg64(current,i,rt1[i]);
1346       current->is32&=~(1LL<<rt1[i]);
1347       dirty_reg(current,rt1[i]);
1348     }
1349   }
1350   if(opcode2[i]==0x3c) // DSLL32
1351   {
1352     if(rt1[i]) {
1353       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1354       alloc_reg64(current,i,rt1[i]);
1355       current->is32&=~(1LL<<rt1[i]);
1356       dirty_reg(current,rt1[i]);
1357     }
1358   }
1359   if(opcode2[i]==0x3e) // DSRL32
1360   {
1361     if(rt1[i]) {
1362       alloc_reg64(current,i,rs1[i]);
1363       if(imm[i]==32) {
1364         alloc_reg64(current,i,rt1[i]);
1365         current->is32&=~(1LL<<rt1[i]);
1366       } else {
1367         alloc_reg(current,i,rt1[i]);
1368         current->is32|=1LL<<rt1[i];
1369       }
1370       dirty_reg(current,rt1[i]);
1371     }
1372   }
1373   if(opcode2[i]==0x3f) // DSRA32
1374   {
1375     if(rt1[i]) {
1376       alloc_reg64(current,i,rs1[i]);
1377       alloc_reg(current,i,rt1[i]);
1378       current->is32|=1LL<<rt1[i];
1379       dirty_reg(current,rt1[i]);
1380     }
1381   }
1382 }
1383
1384 void shift_alloc(struct regstat *current,int i)
1385 {
1386   if(rt1[i]) {
1387     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1388     {
1389       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1390       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1391       alloc_reg(current,i,rt1[i]);
1392       if(rt1[i]==rs2[i]) {
1393         alloc_reg_temp(current,i,-1);
1394         minimum_free_regs[i]=1;
1395       }
1396       current->is32|=1LL<<rt1[i];
1397     } else { // DSLLV/DSRLV/DSRAV
1398       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400       alloc_reg64(current,i,rt1[i]);
1401       current->is32&=~(1LL<<rt1[i]);
1402       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1403       {
1404         alloc_reg_temp(current,i,-1);
1405         minimum_free_regs[i]=1;
1406       }
1407     }
1408     clear_const(current,rs1[i]);
1409     clear_const(current,rs2[i]);
1410     clear_const(current,rt1[i]);
1411     dirty_reg(current,rt1[i]);
1412   }
1413 }
1414
1415 void alu_alloc(struct regstat *current,int i)
1416 {
1417   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418     if(rt1[i]) {
1419       if(rs1[i]&&rs2[i]) {
1420         alloc_reg(current,i,rs1[i]);
1421         alloc_reg(current,i,rs2[i]);
1422       }
1423       else {
1424         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1425         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426       }
1427       alloc_reg(current,i,rt1[i]);
1428     }
1429     current->is32|=1LL<<rt1[i];
1430   }
1431   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432     if(rt1[i]) {
1433       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434       {
1435         alloc_reg64(current,i,rs1[i]);
1436         alloc_reg64(current,i,rs2[i]);
1437         alloc_reg(current,i,rt1[i]);
1438       } else {
1439         alloc_reg(current,i,rs1[i]);
1440         alloc_reg(current,i,rs2[i]);
1441         alloc_reg(current,i,rt1[i]);
1442       }
1443     }
1444     current->is32|=1LL<<rt1[i];
1445   }
1446   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447     if(rt1[i]) {
1448       if(rs1[i]&&rs2[i]) {
1449         alloc_reg(current,i,rs1[i]);
1450         alloc_reg(current,i,rs2[i]);
1451       }
1452       else
1453       {
1454         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1455         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456       }
1457       alloc_reg(current,i,rt1[i]);
1458       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459       {
1460         if(!((current->uu>>rt1[i])&1)) {
1461           alloc_reg64(current,i,rt1[i]);
1462         }
1463         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1464           if(rs1[i]&&rs2[i]) {
1465             alloc_reg64(current,i,rs1[i]);
1466             alloc_reg64(current,i,rs2[i]);
1467           }
1468           else
1469           {
1470             // Is is really worth it to keep 64-bit values in registers?
1471             #ifdef NATIVE_64BIT
1472             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1473             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1474             #endif
1475           }
1476         }
1477         current->is32&=~(1LL<<rt1[i]);
1478       } else {
1479         current->is32|=1LL<<rt1[i];
1480       }
1481     }
1482   }
1483   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484     if(rt1[i]) {
1485       if(rs1[i]&&rs2[i]) {
1486         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1487           alloc_reg64(current,i,rs1[i]);
1488           alloc_reg64(current,i,rs2[i]);
1489           alloc_reg64(current,i,rt1[i]);
1490         } else {
1491           alloc_reg(current,i,rs1[i]);
1492           alloc_reg(current,i,rs2[i]);
1493           alloc_reg(current,i,rt1[i]);
1494         }
1495       }
1496       else {
1497         alloc_reg(current,i,rt1[i]);
1498         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1499           // DADD used as move, or zeroing
1500           // If we have a 64-bit source, then make the target 64 bits too
1501           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1502             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1503             alloc_reg64(current,i,rt1[i]);
1504           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1505             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1506             alloc_reg64(current,i,rt1[i]);
1507           }
1508           if(opcode2[i]>=0x2e&&rs2[i]) {
1509             // DSUB used as negation - 64-bit result
1510             // If we have a 32-bit register, extend it to 64 bits
1511             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512             alloc_reg64(current,i,rt1[i]);
1513           }
1514         }
1515       }
1516       if(rs1[i]&&rs2[i]) {
1517         current->is32&=~(1LL<<rt1[i]);
1518       } else if(rs1[i]) {
1519         current->is32&=~(1LL<<rt1[i]);
1520         if((current->is32>>rs1[i])&1)
1521           current->is32|=1LL<<rt1[i];
1522       } else if(rs2[i]) {
1523         current->is32&=~(1LL<<rt1[i]);
1524         if((current->is32>>rs2[i])&1)
1525           current->is32|=1LL<<rt1[i];
1526       } else {
1527         current->is32|=1LL<<rt1[i];
1528       }
1529     }
1530   }
1531   clear_const(current,rs1[i]);
1532   clear_const(current,rs2[i]);
1533   clear_const(current,rt1[i]);
1534   dirty_reg(current,rt1[i]);
1535 }
1536
1537 void imm16_alloc(struct regstat *current,int i)
1538 {
1539   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540   else lt1[i]=rs1[i];
1541   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1542   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1543     current->is32&=~(1LL<<rt1[i]);
1544     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1545       // TODO: Could preserve the 32-bit flag if the immediate is zero
1546       alloc_reg64(current,i,rt1[i]);
1547       alloc_reg64(current,i,rs1[i]);
1548     }
1549     clear_const(current,rs1[i]);
1550     clear_const(current,rt1[i]);
1551   }
1552   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1553     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1554     current->is32|=1LL<<rt1[i];
1555     clear_const(current,rs1[i]);
1556     clear_const(current,rt1[i]);
1557   }
1558   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1559     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1560       if(rs1[i]!=rt1[i]) {
1561         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1562         alloc_reg64(current,i,rt1[i]);
1563         current->is32&=~(1LL<<rt1[i]);
1564       }
1565     }
1566     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1567     if(is_const(current,rs1[i])) {
1568       int v=get_const(current,rs1[i]);
1569       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1570       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1571       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572     }
1573     else clear_const(current,rt1[i]);
1574   }
1575   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1576     if(is_const(current,rs1[i])) {
1577       int v=get_const(current,rs1[i]);
1578       set_const(current,rt1[i],v+imm[i]);
1579     }
1580     else clear_const(current,rt1[i]);
1581     current->is32|=1LL<<rt1[i];
1582   }
1583   else {
1584     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1585     current->is32|=1LL<<rt1[i];
1586   }
1587   dirty_reg(current,rt1[i]);
1588 }
1589
1590 void load_alloc(struct regstat *current,int i)
1591 {
1592   clear_const(current,rt1[i]);
1593   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1594   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1595   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1596   if(rt1[i]) {
1597     alloc_reg(current,i,rt1[i]);
1598     if(get_reg(current->regmap,rt1[i])<0) {
1599       // dummy load, but we still need a register to calculate the address
1600       alloc_reg_temp(current,i,-1);
1601       minimum_free_regs[i]=1;
1602     }
1603     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1604     {
1605       current->is32&=~(1LL<<rt1[i]);
1606       alloc_reg64(current,i,rt1[i]);
1607     }
1608     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1609     {
1610       current->is32&=~(1LL<<rt1[i]);
1611       alloc_reg64(current,i,rt1[i]);
1612       alloc_all(current,i);
1613       alloc_reg64(current,i,FTEMP);
1614       minimum_free_regs[i]=HOST_REGS;
1615     }
1616     else current->is32|=1LL<<rt1[i];
1617     dirty_reg(current,rt1[i]);
1618     // If using TLB, need a register for pointer to the mapping table
1619     if(using_tlb) alloc_reg(current,i,TLREG);
1620     // LWL/LWR need a temporary register for the old value
1621     if(opcode[i]==0x22||opcode[i]==0x26)
1622     {
1623       alloc_reg(current,i,FTEMP);
1624       alloc_reg_temp(current,i,-1);
1625       minimum_free_regs[i]=1;
1626     }
1627   }
1628   else
1629   {
1630     // Load to r0 (dummy load)
1631     // but we still need a register to calculate the address
1632     if(opcode[i]==0x22||opcode[i]==0x26)
1633     {
1634       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1635     }
1636     alloc_reg_temp(current,i,-1);
1637     minimum_free_regs[i]=1;
1638     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1639     {
1640       alloc_all(current,i);
1641       alloc_reg64(current,i,FTEMP);
1642       minimum_free_regs[i]=HOST_REGS;
1643     }
1644   }
1645 }
1646
1647 void store_alloc(struct regstat *current,int i)
1648 {
1649   clear_const(current,rs2[i]);
1650   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1651   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1652   alloc_reg(current,i,rs2[i]);
1653   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1654     alloc_reg64(current,i,rs2[i]);
1655     if(rs2[i]) alloc_reg(current,i,FTEMP);
1656   }
1657   // If using TLB, need a register for pointer to the mapping table
1658   if(using_tlb) alloc_reg(current,i,TLREG);
1659   #if defined(HOST_IMM8)
1660   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1661   else alloc_reg(current,i,INVCP);
1662   #endif
1663   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1664     alloc_reg(current,i,FTEMP);
1665   }
1666   // We need a temporary register for address generation
1667   alloc_reg_temp(current,i,-1);
1668   minimum_free_regs[i]=1;
1669 }
1670
1671 void c1ls_alloc(struct regstat *current,int i)
1672 {
1673   //clear_const(current,rs1[i]); // FIXME
1674   clear_const(current,rt1[i]);
1675   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676   alloc_reg(current,i,CSREG); // Status
1677   alloc_reg(current,i,FTEMP);
1678   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1679     alloc_reg64(current,i,FTEMP);
1680   }
1681   // If using TLB, need a register for pointer to the mapping table
1682   if(using_tlb) alloc_reg(current,i,TLREG);
1683   #if defined(HOST_IMM8)
1684   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1685   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1686     alloc_reg(current,i,INVCP);
1687   #endif
1688   // We need a temporary register for address generation
1689   alloc_reg_temp(current,i,-1);
1690 }
1691
1692 void c2ls_alloc(struct regstat *current,int i)
1693 {
1694   clear_const(current,rt1[i]);
1695   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1696   alloc_reg(current,i,FTEMP);
1697   // If using TLB, need a register for pointer to the mapping table
1698   if(using_tlb) alloc_reg(current,i,TLREG);
1699   #if defined(HOST_IMM8)
1700   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1701   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1702     alloc_reg(current,i,INVCP);
1703   #endif
1704   // We need a temporary register for address generation
1705   alloc_reg_temp(current,i,-1);
1706   minimum_free_regs[i]=1;
1707 }
1708
1709 #ifndef multdiv_alloc
1710 void multdiv_alloc(struct regstat *current,int i)
1711 {
1712   //  case 0x18: MULT
1713   //  case 0x19: MULTU
1714   //  case 0x1A: DIV
1715   //  case 0x1B: DIVU
1716   //  case 0x1C: DMULT
1717   //  case 0x1D: DMULTU
1718   //  case 0x1E: DDIV
1719   //  case 0x1F: DDIVU
1720   clear_const(current,rs1[i]);
1721   clear_const(current,rs2[i]);
1722   if(rs1[i]&&rs2[i])
1723   {
1724     if((opcode2[i]&4)==0) // 32-bit
1725     {
1726       current->u&=~(1LL<<HIREG);
1727       current->u&=~(1LL<<LOREG);
1728       alloc_reg(current,i,HIREG);
1729       alloc_reg(current,i,LOREG);
1730       alloc_reg(current,i,rs1[i]);
1731       alloc_reg(current,i,rs2[i]);
1732       current->is32|=1LL<<HIREG;
1733       current->is32|=1LL<<LOREG;
1734       dirty_reg(current,HIREG);
1735       dirty_reg(current,LOREG);
1736     }
1737     else // 64-bit
1738     {
1739       current->u&=~(1LL<<HIREG);
1740       current->u&=~(1LL<<LOREG);
1741       current->uu&=~(1LL<<HIREG);
1742       current->uu&=~(1LL<<LOREG);
1743       alloc_reg64(current,i,HIREG);
1744       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1745       alloc_reg64(current,i,rs1[i]);
1746       alloc_reg64(current,i,rs2[i]);
1747       alloc_all(current,i);
1748       current->is32&=~(1LL<<HIREG);
1749       current->is32&=~(1LL<<LOREG);
1750       dirty_reg(current,HIREG);
1751       dirty_reg(current,LOREG);
1752       minimum_free_regs[i]=HOST_REGS;
1753     }
1754   }
1755   else
1756   {
1757     // Multiply by zero is zero.
1758     // MIPS does not have a divide by zero exception.
1759     // The result is undefined, we return zero.
1760     alloc_reg(current,i,HIREG);
1761     alloc_reg(current,i,LOREG);
1762     current->is32|=1LL<<HIREG;
1763     current->is32|=1LL<<LOREG;
1764     dirty_reg(current,HIREG);
1765     dirty_reg(current,LOREG);
1766   }
1767 }
1768 #endif
1769
1770 void cop0_alloc(struct regstat *current,int i)
1771 {
1772   if(opcode2[i]==0) // MFC0
1773   {
1774     if(rt1[i]) {
1775       clear_const(current,rt1[i]);
1776       alloc_all(current,i);
1777       alloc_reg(current,i,rt1[i]);
1778       current->is32|=1LL<<rt1[i];
1779       dirty_reg(current,rt1[i]);
1780     }
1781   }
1782   else if(opcode2[i]==4) // MTC0
1783   {
1784     if(rs1[i]){
1785       clear_const(current,rs1[i]);
1786       alloc_reg(current,i,rs1[i]);
1787       alloc_all(current,i);
1788     }
1789     else {
1790       alloc_all(current,i); // FIXME: Keep r0
1791       current->u&=~1LL;
1792       alloc_reg(current,i,0);
1793     }
1794   }
1795   else
1796   {
1797     // TLBR/TLBWI/TLBWR/TLBP/ERET
1798     assert(opcode2[i]==0x10);
1799     alloc_all(current,i);
1800   }
1801   minimum_free_regs[i]=HOST_REGS;
1802 }
1803
1804 void cop1_alloc(struct regstat *current,int i)
1805 {
1806   alloc_reg(current,i,CSREG); // Load status
1807   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1808   {
1809     if(rt1[i]){
1810       clear_const(current,rt1[i]);
1811       if(opcode2[i]==1) {
1812         alloc_reg64(current,i,rt1[i]); // DMFC1
1813         current->is32&=~(1LL<<rt1[i]);
1814       }else{
1815         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1816         current->is32|=1LL<<rt1[i];
1817       }
1818       dirty_reg(current,rt1[i]);
1819     }
1820     alloc_reg_temp(current,i,-1);
1821   }
1822   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1823   {
1824     if(rs1[i]){
1825       clear_const(current,rs1[i]);
1826       if(opcode2[i]==5)
1827         alloc_reg64(current,i,rs1[i]); // DMTC1
1828       else
1829         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1830       alloc_reg_temp(current,i,-1);
1831     }
1832     else {
1833       current->u&=~1LL;
1834       alloc_reg(current,i,0);
1835       alloc_reg_temp(current,i,-1);
1836     }
1837   }
1838   minimum_free_regs[i]=1;
1839 }
1840 void fconv_alloc(struct regstat *current,int i)
1841 {
1842   alloc_reg(current,i,CSREG); // Load status
1843   alloc_reg_temp(current,i,-1);
1844   minimum_free_regs[i]=1;
1845 }
1846 void float_alloc(struct regstat *current,int i)
1847 {
1848   alloc_reg(current,i,CSREG); // Load status
1849   alloc_reg_temp(current,i,-1);
1850   minimum_free_regs[i]=1;
1851 }
1852 void c2op_alloc(struct regstat *current,int i)
1853 {
1854   alloc_reg_temp(current,i,-1);
1855 }
1856 void fcomp_alloc(struct regstat *current,int i)
1857 {
1858   alloc_reg(current,i,CSREG); // Load status
1859   alloc_reg(current,i,FSREG); // Load flags
1860   dirty_reg(current,FSREG); // Flag will be modified
1861   alloc_reg_temp(current,i,-1);
1862   minimum_free_regs[i]=1;
1863 }
1864
1865 void syscall_alloc(struct regstat *current,int i)
1866 {
1867   alloc_cc(current,i);
1868   dirty_reg(current,CCREG);
1869   alloc_all(current,i);
1870   minimum_free_regs[i]=HOST_REGS;
1871   current->isconst=0;
1872 }
1873
1874 void delayslot_alloc(struct regstat *current,int i)
1875 {
1876   switch(itype[i]) {
1877     case UJUMP:
1878     case CJUMP:
1879     case SJUMP:
1880     case RJUMP:
1881     case FJUMP:
1882     case SYSCALL:
1883     case HLECALL:
1884     case SPAN:
1885       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1886       printf("Disabled speculative precompilation\n");
1887       stop_after_jal=1;
1888       break;
1889     case IMM16:
1890       imm16_alloc(current,i);
1891       break;
1892     case LOAD:
1893     case LOADLR:
1894       load_alloc(current,i);
1895       break;
1896     case STORE:
1897     case STORELR:
1898       store_alloc(current,i);
1899       break;
1900     case ALU:
1901       alu_alloc(current,i);
1902       break;
1903     case SHIFT:
1904       shift_alloc(current,i);
1905       break;
1906     case MULTDIV:
1907       multdiv_alloc(current,i);
1908       break;
1909     case SHIFTIMM:
1910       shiftimm_alloc(current,i);
1911       break;
1912     case MOV:
1913       mov_alloc(current,i);
1914       break;
1915     case COP0:
1916       cop0_alloc(current,i);
1917       break;
1918     case COP1:
1919     case COP2:
1920       cop1_alloc(current,i);
1921       break;
1922     case C1LS:
1923       c1ls_alloc(current,i);
1924       break;
1925     case C2LS:
1926       c2ls_alloc(current,i);
1927       break;
1928     case FCONV:
1929       fconv_alloc(current,i);
1930       break;
1931     case FLOAT:
1932       float_alloc(current,i);
1933       break;
1934     case FCOMP:
1935       fcomp_alloc(current,i);
1936       break;
1937     case C2OP:
1938       c2op_alloc(current,i);
1939       break;
1940   }
1941 }
1942
1943 // Special case where a branch and delay slot span two pages in virtual memory
1944 static void pagespan_alloc(struct regstat *current,int i)
1945 {
1946   current->isconst=0;
1947   current->wasconst=0;
1948   regs[i].wasconst=0;
1949   minimum_free_regs[i]=HOST_REGS;
1950   alloc_all(current,i);
1951   alloc_cc(current,i);
1952   dirty_reg(current,CCREG);
1953   if(opcode[i]==3) // JAL
1954   {
1955     alloc_reg(current,i,31);
1956     dirty_reg(current,31);
1957   }
1958   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1959   {
1960     alloc_reg(current,i,rs1[i]);
1961     if (rt1[i]!=0) {
1962       alloc_reg(current,i,rt1[i]);
1963       dirty_reg(current,rt1[i]);
1964     }
1965   }
1966   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1967   {
1968     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1969     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1970     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1971     {
1972       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1973       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1974     }
1975   }
1976   else
1977   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1978   {
1979     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1980     if(!((current->is32>>rs1[i])&1))
1981     {
1982       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1983     }
1984   }
1985   else
1986   if(opcode[i]==0x11) // BC1
1987   {
1988     alloc_reg(current,i,FSREG);
1989     alloc_reg(current,i,CSREG);
1990   }
1991   //else ...
1992 }
1993
1994 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1995 {
1996   stubs[stubcount][0]=type;
1997   stubs[stubcount][1]=addr;
1998   stubs[stubcount][2]=retaddr;
1999   stubs[stubcount][3]=a;
2000   stubs[stubcount][4]=b;
2001   stubs[stubcount][5]=c;
2002   stubs[stubcount][6]=d;
2003   stubs[stubcount][7]=e;
2004   stubcount++;
2005 }
2006
2007 // Write out a single register
2008 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2009 {
2010   int hr;
2011   for(hr=0;hr<HOST_REGS;hr++) {
2012     if(hr!=EXCLUDE_REG) {
2013       if((regmap[hr]&63)==r) {
2014         if((dirty>>hr)&1) {
2015           if(regmap[hr]<64) {
2016             emit_storereg(r,hr);
2017 #ifndef FORCE32
2018             if((is32>>regmap[hr])&1) {
2019               emit_sarimm(hr,31,hr);
2020               emit_storereg(r|64,hr);
2021             }
2022 #endif
2023           }else{
2024             emit_storereg(r|64,hr);
2025           }
2026         }
2027       }
2028     }
2029   }
2030 }
2031
2032 int mchecksum()
2033 {
2034   //if(!tracedebug) return 0;
2035   int i;
2036   int sum=0;
2037   for(i=0;i<2097152;i++) {
2038     unsigned int temp=sum;
2039     sum<<=1;
2040     sum|=(~temp)>>31;
2041     sum^=((u_int *)rdram)[i];
2042   }
2043   return sum;
2044 }
2045 int rchecksum()
2046 {
2047   int i;
2048   int sum=0;
2049   for(i=0;i<64;i++)
2050     sum^=((u_int *)reg)[i];
2051   return sum;
2052 }
2053 void rlist()
2054 {
2055   int i;
2056   printf("TRACE: ");
2057   for(i=0;i<32;i++)
2058     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2059   printf("\n");
2060 #ifndef DISABLE_COP1
2061   printf("TRACE: ");
2062   for(i=0;i<32;i++)
2063     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2064   printf("\n");
2065 #endif
2066 }
2067
2068 void enabletrace()
2069 {
2070   tracedebug=1;
2071 }
2072
2073 void memdebug(int i)
2074 {
2075   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2076   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2077   //rlist();
2078   //if(tracedebug) {
2079   //if(Count>=-2084597794) {
2080   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2081   //if(0) {
2082     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2083     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2084     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2085     rlist();
2086     #ifdef __i386__
2087     printf("TRACE: %x\n",(&i)[-1]);
2088     #endif
2089     #ifdef __arm__
2090     int j;
2091     printf("TRACE: %x \n",(&j)[10]);
2092     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2093     #endif
2094     //fflush(stdout);
2095   }
2096   //printf("TRACE: %x\n",(&i)[-1]);
2097 }
2098
2099 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2100 {
2101   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2102 }
2103
2104 void alu_assemble(int i,struct regstat *i_regs)
2105 {
2106   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2107     if(rt1[i]) {
2108       signed char s1,s2,t;
2109       t=get_reg(i_regs->regmap,rt1[i]);
2110       if(t>=0) {
2111         s1=get_reg(i_regs->regmap,rs1[i]);
2112         s2=get_reg(i_regs->regmap,rs2[i]);
2113         if(rs1[i]&&rs2[i]) {
2114           assert(s1>=0);
2115           assert(s2>=0);
2116           if(opcode2[i]&2) emit_sub(s1,s2,t);
2117           else emit_add(s1,s2,t);
2118         }
2119         else if(rs1[i]) {
2120           if(s1>=0) emit_mov(s1,t);
2121           else emit_loadreg(rs1[i],t);
2122         }
2123         else if(rs2[i]) {
2124           if(s2>=0) {
2125             if(opcode2[i]&2) emit_neg(s2,t);
2126             else emit_mov(s2,t);
2127           }
2128           else {
2129             emit_loadreg(rs2[i],t);
2130             if(opcode2[i]&2) emit_neg(t,t);
2131           }
2132         }
2133         else emit_zeroreg(t);
2134       }
2135     }
2136   }
2137   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2138     if(rt1[i]) {
2139       signed char s1l,s2l,s1h,s2h,tl,th;
2140       tl=get_reg(i_regs->regmap,rt1[i]);
2141       th=get_reg(i_regs->regmap,rt1[i]|64);
2142       if(tl>=0) {
2143         s1l=get_reg(i_regs->regmap,rs1[i]);
2144         s2l=get_reg(i_regs->regmap,rs2[i]);
2145         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2146         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2147         if(rs1[i]&&rs2[i]) {
2148           assert(s1l>=0);
2149           assert(s2l>=0);
2150           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2151           else emit_adds(s1l,s2l,tl);
2152           if(th>=0) {
2153             #ifdef INVERTED_CARRY
2154             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2155             #else
2156             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2157             #endif
2158             else emit_add(s1h,s2h,th);
2159           }
2160         }
2161         else if(rs1[i]) {
2162           if(s1l>=0) emit_mov(s1l,tl);
2163           else emit_loadreg(rs1[i],tl);
2164           if(th>=0) {
2165             if(s1h>=0) emit_mov(s1h,th);
2166             else emit_loadreg(rs1[i]|64,th);
2167           }
2168         }
2169         else if(rs2[i]) {
2170           if(s2l>=0) {
2171             if(opcode2[i]&2) emit_negs(s2l,tl);
2172             else emit_mov(s2l,tl);
2173           }
2174           else {
2175             emit_loadreg(rs2[i],tl);
2176             if(opcode2[i]&2) emit_negs(tl,tl);
2177           }
2178           if(th>=0) {
2179             #ifdef INVERTED_CARRY
2180             if(s2h>=0) emit_mov(s2h,th);
2181             else emit_loadreg(rs2[i]|64,th);
2182             if(opcode2[i]&2) {
2183               emit_adcimm(-1,th); // x86 has inverted carry flag
2184               emit_not(th,th);
2185             }
2186             #else
2187             if(opcode2[i]&2) {
2188               if(s2h>=0) emit_rscimm(s2h,0,th);
2189               else {
2190                 emit_loadreg(rs2[i]|64,th);
2191                 emit_rscimm(th,0,th);
2192               }
2193             }else{
2194               if(s2h>=0) emit_mov(s2h,th);
2195               else emit_loadreg(rs2[i]|64,th);
2196             }
2197             #endif
2198           }
2199         }
2200         else {
2201           emit_zeroreg(tl);
2202           if(th>=0) emit_zeroreg(th);
2203         }
2204       }
2205     }
2206   }
2207   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2208     if(rt1[i]) {
2209       signed char s1l,s1h,s2l,s2h,t;
2210       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2211       {
2212         t=get_reg(i_regs->regmap,rt1[i]);
2213         //assert(t>=0);
2214         if(t>=0) {
2215           s1l=get_reg(i_regs->regmap,rs1[i]);
2216           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2217           s2l=get_reg(i_regs->regmap,rs2[i]);
2218           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2219           if(rs2[i]==0) // rx<r0
2220           {
2221             assert(s1h>=0);
2222             if(opcode2[i]==0x2a) // SLT
2223               emit_shrimm(s1h,31,t);
2224             else // SLTU (unsigned can not be less than zero)
2225               emit_zeroreg(t);
2226           }
2227           else if(rs1[i]==0) // r0<rx
2228           {
2229             assert(s2h>=0);
2230             if(opcode2[i]==0x2a) // SLT
2231               emit_set_gz64_32(s2h,s2l,t);
2232             else // SLTU (set if not zero)
2233               emit_set_nz64_32(s2h,s2l,t);
2234           }
2235           else {
2236             assert(s1l>=0);assert(s1h>=0);
2237             assert(s2l>=0);assert(s2h>=0);
2238             if(opcode2[i]==0x2a) // SLT
2239               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2240             else // SLTU
2241               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2242           }
2243         }
2244       } else {
2245         t=get_reg(i_regs->regmap,rt1[i]);
2246         //assert(t>=0);
2247         if(t>=0) {
2248           s1l=get_reg(i_regs->regmap,rs1[i]);
2249           s2l=get_reg(i_regs->regmap,rs2[i]);
2250           if(rs2[i]==0) // rx<r0
2251           {
2252             assert(s1l>=0);
2253             if(opcode2[i]==0x2a) // SLT
2254               emit_shrimm(s1l,31,t);
2255             else // SLTU (unsigned can not be less than zero)
2256               emit_zeroreg(t);
2257           }
2258           else if(rs1[i]==0) // r0<rx
2259           {
2260             assert(s2l>=0);
2261             if(opcode2[i]==0x2a) // SLT
2262               emit_set_gz32(s2l,t);
2263             else // SLTU (set if not zero)
2264               emit_set_nz32(s2l,t);
2265           }
2266           else{
2267             assert(s1l>=0);assert(s2l>=0);
2268             if(opcode2[i]==0x2a) // SLT
2269               emit_set_if_less32(s1l,s2l,t);
2270             else // SLTU
2271               emit_set_if_carry32(s1l,s2l,t);
2272           }
2273         }
2274       }
2275     }
2276   }
2277   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2278     if(rt1[i]) {
2279       signed char s1l,s1h,s2l,s2h,th,tl;
2280       tl=get_reg(i_regs->regmap,rt1[i]);
2281       th=get_reg(i_regs->regmap,rt1[i]|64);
2282       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2283       {
2284         assert(tl>=0);
2285         if(tl>=0) {
2286           s1l=get_reg(i_regs->regmap,rs1[i]);
2287           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2288           s2l=get_reg(i_regs->regmap,rs2[i]);
2289           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2290           if(rs1[i]&&rs2[i]) {
2291             assert(s1l>=0);assert(s1h>=0);
2292             assert(s2l>=0);assert(s2h>=0);
2293             if(opcode2[i]==0x24) { // AND
2294               emit_and(s1l,s2l,tl);
2295               emit_and(s1h,s2h,th);
2296             } else
2297             if(opcode2[i]==0x25) { // OR
2298               emit_or(s1l,s2l,tl);
2299               emit_or(s1h,s2h,th);
2300             } else
2301             if(opcode2[i]==0x26) { // XOR
2302               emit_xor(s1l,s2l,tl);
2303               emit_xor(s1h,s2h,th);
2304             } else
2305             if(opcode2[i]==0x27) { // NOR
2306               emit_or(s1l,s2l,tl);
2307               emit_or(s1h,s2h,th);
2308               emit_not(tl,tl);
2309               emit_not(th,th);
2310             }
2311           }
2312           else
2313           {
2314             if(opcode2[i]==0x24) { // AND
2315               emit_zeroreg(tl);
2316               emit_zeroreg(th);
2317             } else
2318             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2319               if(rs1[i]){
2320                 if(s1l>=0) emit_mov(s1l,tl);
2321                 else emit_loadreg(rs1[i],tl);
2322                 if(s1h>=0) emit_mov(s1h,th);
2323                 else emit_loadreg(rs1[i]|64,th);
2324               }
2325               else
2326               if(rs2[i]){
2327                 if(s2l>=0) emit_mov(s2l,tl);
2328                 else emit_loadreg(rs2[i],tl);
2329                 if(s2h>=0) emit_mov(s2h,th);
2330                 else emit_loadreg(rs2[i]|64,th);
2331               }
2332               else{
2333                 emit_zeroreg(tl);
2334                 emit_zeroreg(th);
2335               }
2336             } else
2337             if(opcode2[i]==0x27) { // NOR
2338               if(rs1[i]){
2339                 if(s1l>=0) emit_not(s1l,tl);
2340                 else{
2341                   emit_loadreg(rs1[i],tl);
2342                   emit_not(tl,tl);
2343                 }
2344                 if(s1h>=0) emit_not(s1h,th);
2345                 else{
2346                   emit_loadreg(rs1[i]|64,th);
2347                   emit_not(th,th);
2348                 }
2349               }
2350               else
2351               if(rs2[i]){
2352                 if(s2l>=0) emit_not(s2l,tl);
2353                 else{
2354                   emit_loadreg(rs2[i],tl);
2355                   emit_not(tl,tl);
2356                 }
2357                 if(s2h>=0) emit_not(s2h,th);
2358                 else{
2359                   emit_loadreg(rs2[i]|64,th);
2360                   emit_not(th,th);
2361                 }
2362               }
2363               else {
2364                 emit_movimm(-1,tl);
2365                 emit_movimm(-1,th);
2366               }
2367             }
2368           }
2369         }
2370       }
2371       else
2372       {
2373         // 32 bit
2374         if(tl>=0) {
2375           s1l=get_reg(i_regs->regmap,rs1[i]);
2376           s2l=get_reg(i_regs->regmap,rs2[i]);
2377           if(rs1[i]&&rs2[i]) {
2378             assert(s1l>=0);
2379             assert(s2l>=0);
2380             if(opcode2[i]==0x24) { // AND
2381               emit_and(s1l,s2l,tl);
2382             } else
2383             if(opcode2[i]==0x25) { // OR
2384               emit_or(s1l,s2l,tl);
2385             } else
2386             if(opcode2[i]==0x26) { // XOR
2387               emit_xor(s1l,s2l,tl);
2388             } else
2389             if(opcode2[i]==0x27) { // NOR
2390               emit_or(s1l,s2l,tl);
2391               emit_not(tl,tl);
2392             }
2393           }
2394           else
2395           {
2396             if(opcode2[i]==0x24) { // AND
2397               emit_zeroreg(tl);
2398             } else
2399             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2400               if(rs1[i]){
2401                 if(s1l>=0) emit_mov(s1l,tl);
2402                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2403               }
2404               else
2405               if(rs2[i]){
2406                 if(s2l>=0) emit_mov(s2l,tl);
2407                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2408               }
2409               else emit_zeroreg(tl);
2410             } else
2411             if(opcode2[i]==0x27) { // NOR
2412               if(rs1[i]){
2413                 if(s1l>=0) emit_not(s1l,tl);
2414                 else {
2415                   emit_loadreg(rs1[i],tl);
2416                   emit_not(tl,tl);
2417                 }
2418               }
2419               else
2420               if(rs2[i]){
2421                 if(s2l>=0) emit_not(s2l,tl);
2422                 else {
2423                   emit_loadreg(rs2[i],tl);
2424                   emit_not(tl,tl);
2425                 }
2426               }
2427               else emit_movimm(-1,tl);
2428             }
2429           }
2430         }
2431       }
2432     }
2433   }
2434 }
2435
2436 void imm16_assemble(int i,struct regstat *i_regs)
2437 {
2438   if (opcode[i]==0x0f) { // LUI
2439     if(rt1[i]) {
2440       signed char t;
2441       t=get_reg(i_regs->regmap,rt1[i]);
2442       //assert(t>=0);
2443       if(t>=0) {
2444         if(!((i_regs->isconst>>t)&1))
2445           emit_movimm(imm[i]<<16,t);
2446       }
2447     }
2448   }
2449   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2450     if(rt1[i]) {
2451       signed char s,t;
2452       t=get_reg(i_regs->regmap,rt1[i]);
2453       s=get_reg(i_regs->regmap,rs1[i]);
2454       if(rs1[i]) {
2455         //assert(t>=0);
2456         //assert(s>=0);
2457         if(t>=0) {
2458           if(!((i_regs->isconst>>t)&1)) {
2459             if(s<0) {
2460               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2461               emit_addimm(t,imm[i],t);
2462             }else{
2463               if(!((i_regs->wasconst>>s)&1))
2464                 emit_addimm(s,imm[i],t);
2465               else
2466                 emit_movimm(constmap[i][s]+imm[i],t);
2467             }
2468           }
2469         }
2470       } else {
2471         if(t>=0) {
2472           if(!((i_regs->isconst>>t)&1))
2473             emit_movimm(imm[i],t);
2474         }
2475       }
2476     }
2477   }
2478   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2479     if(rt1[i]) {
2480       signed char sh,sl,th,tl;
2481       th=get_reg(i_regs->regmap,rt1[i]|64);
2482       tl=get_reg(i_regs->regmap,rt1[i]);
2483       sh=get_reg(i_regs->regmap,rs1[i]|64);
2484       sl=get_reg(i_regs->regmap,rs1[i]);
2485       if(tl>=0) {
2486         if(rs1[i]) {
2487           assert(sh>=0);
2488           assert(sl>=0);
2489           if(th>=0) {
2490             emit_addimm64_32(sh,sl,imm[i],th,tl);
2491           }
2492           else {
2493             emit_addimm(sl,imm[i],tl);
2494           }
2495         } else {
2496           emit_movimm(imm[i],tl);
2497           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2498         }
2499       }
2500     }
2501   }
2502   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2503     if(rt1[i]) {
2504       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2505       signed char sh,sl,t;
2506       t=get_reg(i_regs->regmap,rt1[i]);
2507       sh=get_reg(i_regs->regmap,rs1[i]|64);
2508       sl=get_reg(i_regs->regmap,rs1[i]);
2509       //assert(t>=0);
2510       if(t>=0) {
2511         if(rs1[i]>0) {
2512           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2513           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2514             if(opcode[i]==0x0a) { // SLTI
2515               if(sl<0) {
2516                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2517                 emit_slti32(t,imm[i],t);
2518               }else{
2519                 emit_slti32(sl,imm[i],t);
2520               }
2521             }
2522             else { // SLTIU
2523               if(sl<0) {
2524                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2525                 emit_sltiu32(t,imm[i],t);
2526               }else{
2527                 emit_sltiu32(sl,imm[i],t);
2528               }
2529             }
2530           }else{ // 64-bit
2531             assert(sl>=0);
2532             if(opcode[i]==0x0a) // SLTI
2533               emit_slti64_32(sh,sl,imm[i],t);
2534             else // SLTIU
2535               emit_sltiu64_32(sh,sl,imm[i],t);
2536           }
2537         }else{
2538           // SLTI(U) with r0 is just stupid,
2539           // nonetheless examples can be found
2540           if(opcode[i]==0x0a) // SLTI
2541             if(0<imm[i]) emit_movimm(1,t);
2542             else emit_zeroreg(t);
2543           else // SLTIU
2544           {
2545             if(imm[i]) emit_movimm(1,t);
2546             else emit_zeroreg(t);
2547           }
2548         }
2549       }
2550     }
2551   }
2552   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2553     if(rt1[i]) {
2554       signed char sh,sl,th,tl;
2555       th=get_reg(i_regs->regmap,rt1[i]|64);
2556       tl=get_reg(i_regs->regmap,rt1[i]);
2557       sh=get_reg(i_regs->regmap,rs1[i]|64);
2558       sl=get_reg(i_regs->regmap,rs1[i]);
2559       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2560         if(opcode[i]==0x0c) //ANDI
2561         {
2562           if(rs1[i]) {
2563             if(sl<0) {
2564               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2565               emit_andimm(tl,imm[i],tl);
2566             }else{
2567               if(!((i_regs->wasconst>>sl)&1))
2568                 emit_andimm(sl,imm[i],tl);
2569               else
2570                 emit_movimm(constmap[i][sl]&imm[i],tl);
2571             }
2572           }
2573           else
2574             emit_zeroreg(tl);
2575           if(th>=0) emit_zeroreg(th);
2576         }
2577         else
2578         {
2579           if(rs1[i]) {
2580             if(sl<0) {
2581               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2582             }
2583             if(th>=0) {
2584               if(sh<0) {
2585                 emit_loadreg(rs1[i]|64,th);
2586               }else{
2587                 emit_mov(sh,th);
2588               }
2589             }
2590             if(opcode[i]==0x0d) //ORI
2591             if(sl<0) {
2592               emit_orimm(tl,imm[i],tl);
2593             }else{
2594               if(!((i_regs->wasconst>>sl)&1))
2595                 emit_orimm(sl,imm[i],tl);
2596               else
2597                 emit_movimm(constmap[i][sl]|imm[i],tl);
2598             }
2599             if(opcode[i]==0x0e) //XORI
2600             if(sl<0) {
2601               emit_xorimm(tl,imm[i],tl);
2602             }else{
2603               if(!((i_regs->wasconst>>sl)&1))
2604                 emit_xorimm(sl,imm[i],tl);
2605               else
2606                 emit_movimm(constmap[i][sl]^imm[i],tl);
2607             }
2608           }
2609           else {
2610             emit_movimm(imm[i],tl);
2611             if(th>=0) emit_zeroreg(th);
2612           }
2613         }
2614       }
2615     }
2616   }
2617 }
2618
2619 void shiftimm_assemble(int i,struct regstat *i_regs)
2620 {
2621   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2622   {
2623     if(rt1[i]) {
2624       signed char s,t;
2625       t=get_reg(i_regs->regmap,rt1[i]);
2626       s=get_reg(i_regs->regmap,rs1[i]);
2627       //assert(t>=0);
2628       if(t>=0){
2629         if(rs1[i]==0)
2630         {
2631           emit_zeroreg(t);
2632         }
2633         else
2634         {
2635           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2636           if(imm[i]) {
2637             if(opcode2[i]==0) // SLL
2638             {
2639               emit_shlimm(s<0?t:s,imm[i],t);
2640             }
2641             if(opcode2[i]==2) // SRL
2642             {
2643               emit_shrimm(s<0?t:s,imm[i],t);
2644             }
2645             if(opcode2[i]==3) // SRA
2646             {
2647               emit_sarimm(s<0?t:s,imm[i],t);
2648             }
2649           }else{
2650             // Shift by zero
2651             if(s>=0 && s!=t) emit_mov(s,t);
2652           }
2653         }
2654       }
2655       //emit_storereg(rt1[i],t); //DEBUG
2656     }
2657   }
2658   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2659   {
2660     if(rt1[i]) {
2661       signed char sh,sl,th,tl;
2662       th=get_reg(i_regs->regmap,rt1[i]|64);
2663       tl=get_reg(i_regs->regmap,rt1[i]);
2664       sh=get_reg(i_regs->regmap,rs1[i]|64);
2665       sl=get_reg(i_regs->regmap,rs1[i]);
2666       if(tl>=0) {
2667         if(rs1[i]==0)
2668         {
2669           emit_zeroreg(tl);
2670           if(th>=0) emit_zeroreg(th);
2671         }
2672         else
2673         {
2674           assert(sl>=0);
2675           assert(sh>=0);
2676           if(imm[i]) {
2677             if(opcode2[i]==0x38) // DSLL
2678             {
2679               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2680               emit_shlimm(sl,imm[i],tl);
2681             }
2682             if(opcode2[i]==0x3a) // DSRL
2683             {
2684               emit_shrdimm(sl,sh,imm[i],tl);
2685               if(th>=0) emit_shrimm(sh,imm[i],th);
2686             }
2687             if(opcode2[i]==0x3b) // DSRA
2688             {
2689               emit_shrdimm(sl,sh,imm[i],tl);
2690               if(th>=0) emit_sarimm(sh,imm[i],th);
2691             }
2692           }else{
2693             // Shift by zero
2694             if(sl!=tl) emit_mov(sl,tl);
2695             if(th>=0&&sh!=th) emit_mov(sh,th);
2696           }
2697         }
2698       }
2699     }
2700   }
2701   if(opcode2[i]==0x3c) // DSLL32
2702   {
2703     if(rt1[i]) {
2704       signed char sl,tl,th;
2705       tl=get_reg(i_regs->regmap,rt1[i]);
2706       th=get_reg(i_regs->regmap,rt1[i]|64);
2707       sl=get_reg(i_regs->regmap,rs1[i]);
2708       if(th>=0||tl>=0){
2709         assert(tl>=0);
2710         assert(th>=0);
2711         assert(sl>=0);
2712         emit_mov(sl,th);
2713         emit_zeroreg(tl);
2714         if(imm[i]>32)
2715         {
2716           emit_shlimm(th,imm[i]&31,th);
2717         }
2718       }
2719     }
2720   }
2721   if(opcode2[i]==0x3e) // DSRL32
2722   {
2723     if(rt1[i]) {
2724       signed char sh,tl,th;
2725       tl=get_reg(i_regs->regmap,rt1[i]);
2726       th=get_reg(i_regs->regmap,rt1[i]|64);
2727       sh=get_reg(i_regs->regmap,rs1[i]|64);
2728       if(tl>=0){
2729         assert(sh>=0);
2730         emit_mov(sh,tl);
2731         if(th>=0) emit_zeroreg(th);
2732         if(imm[i]>32)
2733         {
2734           emit_shrimm(tl,imm[i]&31,tl);
2735         }
2736       }
2737     }
2738   }
2739   if(opcode2[i]==0x3f) // DSRA32
2740   {
2741     if(rt1[i]) {
2742       signed char sh,tl;
2743       tl=get_reg(i_regs->regmap,rt1[i]);
2744       sh=get_reg(i_regs->regmap,rs1[i]|64);
2745       if(tl>=0){
2746         assert(sh>=0);
2747         emit_mov(sh,tl);
2748         if(imm[i]>32)
2749         {
2750           emit_sarimm(tl,imm[i]&31,tl);
2751         }
2752       }
2753     }
2754   }
2755 }
2756
2757 #ifndef shift_assemble
2758 void shift_assemble(int i,struct regstat *i_regs)
2759 {
2760   printf("Need shift_assemble for this architecture.\n");
2761   exit(1);
2762 }
2763 #endif
2764
2765 void load_assemble(int i,struct regstat *i_regs)
2766 {
2767   int s,th,tl,addr,map=-1;
2768   int offset;
2769   int jaddr=0;
2770   int memtarget=0,c=0;
2771   u_int hr,reglist=0;
2772   th=get_reg(i_regs->regmap,rt1[i]|64);
2773   tl=get_reg(i_regs->regmap,rt1[i]);
2774   s=get_reg(i_regs->regmap,rs1[i]);
2775   offset=imm[i];
2776   for(hr=0;hr<HOST_REGS;hr++) {
2777     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2778   }
2779   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2780   if(s>=0) {
2781     c=(i_regs->wasconst>>s)&1;
2782     if (c) {
2783       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2784       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2785     }
2786   }
2787   //printf("load_assemble: c=%d\n",c);
2788   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2789   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2790 #ifdef PCSX
2791   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2792     ||rt1[i]==0) {
2793       // could be FIFO, must perform the read
2794       // ||dummy read
2795       assem_debug("(forced read)\n");
2796       tl=get_reg(i_regs->regmap,-1);
2797       assert(tl>=0);
2798   }
2799 #endif
2800   if(offset||s<0||c) addr=tl;
2801   else addr=s;
2802   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2803  if(tl>=0) {
2804   //printf("load_assemble: c=%d\n",c);
2805   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2806   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2807   reglist&=~(1<<tl);
2808   if(th>=0) reglist&=~(1<<th);
2809   if(!using_tlb) {
2810     if(!c) {
2811       #ifdef RAM_OFFSET
2812       map=get_reg(i_regs->regmap,ROREG);
2813       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2814       #endif
2815 //#define R29_HACK 1
2816       #ifdef R29_HACK
2817       // Strmnnrmn's speed hack
2818       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2819       #endif
2820       {
2821         #ifdef PCSX
2822         if(sp_in_mirror&&rs1[i]==29) {
2823           emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2824           emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2825         }
2826         else
2827         #endif
2828         emit_cmpimm(addr,RAM_SIZE);
2829         jaddr=(int)out;
2830         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2831         // Hint to branch predictor that the branch is unlikely to be taken
2832         if(rs1[i]>=28)
2833           emit_jno_unlikely(0);
2834         else
2835         #endif
2836         emit_jno(0);
2837       }
2838     }
2839   }else{ // using tlb
2840     int x=0;
2841     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2842     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2843     map=get_reg(i_regs->regmap,TLREG);
2844     assert(map>=0);
2845     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2846     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2847   }
2848   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2849   if (opcode[i]==0x20) { // LB
2850     if(!c||memtarget) {
2851       if(!dummy) {
2852         #ifdef HOST_IMM_ADDR32
2853         if(c)
2854           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2855         else
2856         #endif
2857         {
2858           //emit_xorimm(addr,3,tl);
2859           //gen_tlb_addr_r(tl,map);
2860           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2861           int x=0,a=tl;
2862 #ifdef BIG_ENDIAN_MIPS
2863           if(!c) emit_xorimm(addr,3,tl);
2864           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2865 #else
2866           if(!c) a=addr;
2867 #endif
2868 #ifdef PCSX
2869           if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2870 #endif
2871           emit_movsbl_indexed_tlb(x,a,map,tl);
2872         }
2873       }
2874       if(jaddr)
2875         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2876     }
2877     else
2878       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2879   }
2880   if (opcode[i]==0x21) { // LH
2881     if(!c||memtarget) {
2882       if(!dummy) {
2883         #ifdef HOST_IMM_ADDR32
2884         if(c)
2885           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2886         else
2887         #endif
2888         {
2889           int x=0,a=tl;
2890 #ifdef BIG_ENDIAN_MIPS
2891           if(!c) emit_xorimm(addr,2,tl);
2892           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2893 #else
2894           if(!c) a=addr;
2895 #endif
2896 #ifdef PCSX
2897           if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2898 #endif
2899           //#ifdef
2900           //emit_movswl_indexed_tlb(x,tl,map,tl);
2901           //else
2902           if(map>=0) {
2903             gen_tlb_addr_r(a,map);
2904             emit_movswl_indexed(x,a,tl);
2905           }else{
2906             #ifdef RAM_OFFSET
2907             emit_movswl_indexed(x,a,tl);
2908             #else
2909             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2910             #endif
2911           }
2912         }
2913       }
2914       if(jaddr)
2915         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2916     }
2917     else
2918       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2919   }
2920   if (opcode[i]==0x23) { // LW
2921     if(!c||memtarget) {
2922       if(!dummy) {
2923         int a=addr;
2924 #ifdef PCSX
2925         if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2926 #endif
2927         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2928         #ifdef HOST_IMM_ADDR32
2929         if(c)
2930           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2931         else
2932         #endif
2933         emit_readword_indexed_tlb(0,a,map,tl);
2934       }
2935       if(jaddr)
2936         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937     }
2938     else
2939       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2940   }
2941   if (opcode[i]==0x24) { // LBU
2942     if(!c||memtarget) {
2943       if(!dummy) {
2944         #ifdef HOST_IMM_ADDR32
2945         if(c)
2946           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2947         else
2948         #endif
2949         {
2950           //emit_xorimm(addr,3,tl);
2951           //gen_tlb_addr_r(tl,map);
2952           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2953           int x=0,a=tl;
2954 #ifdef BIG_ENDIAN_MIPS
2955           if(!c) emit_xorimm(addr,3,tl);
2956           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2957 #else
2958           if(!c) a=addr;
2959 #endif
2960 #ifdef PCSX
2961           if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2962 #endif
2963           emit_movzbl_indexed_tlb(x,a,map,tl);
2964         }
2965       }
2966       if(jaddr)
2967         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2968     }
2969     else
2970       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2971   }
2972   if (opcode[i]==0x25) { // LHU
2973     if(!c||memtarget) {
2974       if(!dummy) {
2975         #ifdef HOST_IMM_ADDR32
2976         if(c)
2977           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2978         else
2979         #endif
2980         {
2981           int x=0,a=tl;
2982 #ifdef BIG_ENDIAN_MIPS
2983           if(!c) emit_xorimm(addr,2,tl);
2984           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2985 #else
2986           if(!c) a=addr;
2987 #endif
2988 #ifdef PCSX
2989           if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
2990 #endif
2991           //#ifdef
2992           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2993           //#else
2994           if(map>=0) {
2995             gen_tlb_addr_r(a,map);
2996             emit_movzwl_indexed(x,a,tl);
2997           }else{
2998             #ifdef RAM_OFFSET
2999             emit_movzwl_indexed(x,a,tl);
3000             #else
3001             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3002             #endif
3003           }
3004         }
3005       }
3006       if(jaddr)
3007         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3008     }
3009     else
3010       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3011   }
3012   if (opcode[i]==0x27) { // LWU
3013     assert(th>=0);
3014     if(!c||memtarget) {
3015       if(!dummy) {
3016         int a=addr;
3017 #ifdef PCSX
3018         if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3019 #endif
3020         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3021         #ifdef HOST_IMM_ADDR32
3022         if(c)
3023           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3024         else
3025         #endif
3026         emit_readword_indexed_tlb(0,a,map,tl);
3027       }
3028       if(jaddr)
3029         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3030     }
3031     else {
3032       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3033     }
3034     emit_zeroreg(th);
3035   }
3036   if (opcode[i]==0x37) { // LD
3037     if(!c||memtarget) {
3038       if(!dummy) {
3039         int a=addr;
3040 #ifdef PCSX
3041         if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3042 #endif
3043         //gen_tlb_addr_r(tl,map);
3044         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3045         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3046         #ifdef HOST_IMM_ADDR32
3047         if(c)
3048           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3049         else
3050         #endif
3051         emit_readdword_indexed_tlb(0,a,map,th,tl);
3052       }
3053       if(jaddr)
3054         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3055     }
3056     else
3057       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3058   }
3059  }
3060   //emit_storereg(rt1[i],tl); // DEBUG
3061   //if(opcode[i]==0x23)
3062   //if(opcode[i]==0x24)
3063   //if(opcode[i]==0x23||opcode[i]==0x24)
3064   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3065   {
3066     //emit_pusha();
3067     save_regs(0x100f);
3068         emit_readword((int)&last_count,ECX);
3069         #ifdef __i386__
3070         if(get_reg(i_regs->regmap,CCREG)<0)
3071           emit_loadreg(CCREG,HOST_CCREG);
3072         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3073         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3074         emit_writeword(HOST_CCREG,(int)&Count);
3075         #endif
3076         #ifdef __arm__
3077         if(get_reg(i_regs->regmap,CCREG)<0)
3078           emit_loadreg(CCREG,0);
3079         else
3080           emit_mov(HOST_CCREG,0);
3081         emit_add(0,ECX,0);
3082         emit_addimm(0,2*ccadj[i],0);
3083         emit_writeword(0,(int)&Count);
3084         #endif
3085     emit_call((int)memdebug);
3086     //emit_popa();
3087     restore_regs(0x100f);
3088   }/**/
3089 }
3090
3091 #ifndef loadlr_assemble
3092 void loadlr_assemble(int i,struct regstat *i_regs)
3093 {
3094   printf("Need loadlr_assemble for this architecture.\n");
3095   exit(1);
3096 }
3097 #endif
3098
3099 void store_assemble(int i,struct regstat *i_regs)
3100 {
3101   int s,th,tl,map=-1;
3102   int addr,temp;
3103   int offset;
3104   int jaddr=0,jaddr2,type;
3105   int memtarget=0,c=0;
3106   int agr=AGEN1+(i&1);
3107   u_int hr,reglist=0;
3108   th=get_reg(i_regs->regmap,rs2[i]|64);
3109   tl=get_reg(i_regs->regmap,rs2[i]);
3110   s=get_reg(i_regs->regmap,rs1[i]);
3111   temp=get_reg(i_regs->regmap,agr);
3112   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3113   offset=imm[i];
3114   if(s>=0) {
3115     c=(i_regs->wasconst>>s)&1;
3116     if(c) {
3117       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3118       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3119     }
3120   }
3121   assert(tl>=0);
3122   assert(temp>=0);
3123   for(hr=0;hr<HOST_REGS;hr++) {
3124     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3125   }
3126   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3127   if(offset||s<0||c) addr=temp;
3128   else addr=s;
3129   if(!using_tlb) {
3130     if(!c) {
3131       #ifdef PCSX
3132       if(sp_in_mirror&&rs1[i]==29) {
3133         emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3134         emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3135       }
3136       else
3137       #endif
3138       #ifdef R29_HACK
3139       // Strmnnrmn's speed hack
3140       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3141       #endif
3142       emit_cmpimm(addr,RAM_SIZE);
3143       #ifdef DESTRUCTIVE_SHIFT
3144       if(s==addr) emit_mov(s,temp);
3145       #endif
3146       #ifdef R29_HACK
3147       memtarget=1;
3148       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3149       #endif
3150       {
3151         jaddr=(int)out;
3152         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3153         // Hint to branch predictor that the branch is unlikely to be taken
3154         if(rs1[i]>=28)
3155           emit_jno_unlikely(0);
3156         else
3157         #endif
3158         emit_jno(0);
3159       }
3160     }
3161   }else{ // using tlb
3162     int x=0;
3163     if (opcode[i]==0x28) x=3; // SB
3164     if (opcode[i]==0x29) x=2; // SH
3165     map=get_reg(i_regs->regmap,TLREG);
3166     assert(map>=0);
3167     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3168     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3169   }
3170
3171   if (opcode[i]==0x28) { // SB
3172     if(!c||memtarget) {
3173       int x=0,a=temp;
3174 #ifdef BIG_ENDIAN_MIPS
3175       if(!c) emit_xorimm(addr,3,temp);
3176       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3177 #else
3178       if(!c) a=addr;
3179 #endif
3180 #ifdef PCSX
3181       if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3182 #endif
3183       //gen_tlb_addr_w(temp,map);
3184       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3185       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3186     }
3187     type=STOREB_STUB;
3188   }
3189   if (opcode[i]==0x29) { // SH
3190     if(!c||memtarget) {
3191       int x=0,a=temp;
3192 #ifdef BIG_ENDIAN_MIPS
3193       if(!c) emit_xorimm(addr,2,temp);
3194       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3195 #else
3196       if(!c) a=addr;
3197 #endif
3198 #ifdef PCSX
3199       if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3200 #endif
3201       //#ifdef
3202       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3203       //#else
3204       if(map>=0) {
3205         gen_tlb_addr_w(a,map);
3206         emit_writehword_indexed(tl,x,a);
3207       }else
3208         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3209     }
3210     type=STOREH_STUB;
3211   }
3212   if (opcode[i]==0x2B) { // SW
3213     if(!c||memtarget) {
3214       int a=addr;
3215 #ifdef PCSX
3216       if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3217 #endif
3218       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3219       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3220     }
3221     type=STOREW_STUB;
3222   }
3223   if (opcode[i]==0x3F) { // SD
3224     if(!c||memtarget) {
3225       int a=addr;
3226 #ifdef PCSX
3227       if(sp_in_mirror&&rs1[i]==29) a=HOST_TEMPREG;
3228 #endif
3229       if(rs2[i]) {
3230         assert(th>=0);
3231         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3232         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3233         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3234       }else{
3235         // Store zero
3236         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3237         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3238         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3239       }
3240     }
3241     type=STORED_STUB;
3242   }
3243   if(!using_tlb) {
3244     if(!c||memtarget) {
3245       #ifdef DESTRUCTIVE_SHIFT
3246       // The x86 shift operation is 'destructive'; it overwrites the
3247       // source register, so we need to make a copy first and use that.
3248       addr=temp;
3249       #endif
3250       #if defined(HOST_IMM8)
3251       int ir=get_reg(i_regs->regmap,INVCP);
3252       assert(ir>=0);
3253       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3254       #else
3255       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3256       #endif
3257       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3258       emit_callne(invalidate_addr_reg[addr]);
3259       #else
3260       jaddr2=(int)out;
3261       emit_jne(0);
3262       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3263       #endif
3264     }
3265   }
3266   if(jaddr) {
3267     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3268   } else if(c&&!memtarget) {
3269     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3270   }
3271   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3272   //if(opcode[i]==0x2B || opcode[i]==0x28)
3273   //if(opcode[i]==0x2B || opcode[i]==0x29)
3274   //if(opcode[i]==0x2B)
3275   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3276   {
3277     //emit_pusha();
3278     save_regs(0x100f);
3279         emit_readword((int)&last_count,ECX);
3280         #ifdef __i386__
3281         if(get_reg(i_regs->regmap,CCREG)<0)
3282           emit_loadreg(CCREG,HOST_CCREG);
3283         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3284         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3285         emit_writeword(HOST_CCREG,(int)&Count);
3286         #endif
3287         #ifdef __arm__
3288         if(get_reg(i_regs->regmap,CCREG)<0)
3289           emit_loadreg(CCREG,0);
3290         else
3291           emit_mov(HOST_CCREG,0);
3292         emit_add(0,ECX,0);
3293         emit_addimm(0,2*ccadj[i],0);
3294         emit_writeword(0,(int)&Count);
3295         #endif
3296     emit_call((int)memdebug);
3297     //emit_popa();
3298     restore_regs(0x100f);
3299   }/**/
3300 }
3301
3302 void storelr_assemble(int i,struct regstat *i_regs)
3303 {
3304   int s,th,tl;
3305   int temp;
3306   int temp2;
3307   int offset;
3308   int jaddr=0,jaddr2;
3309   int case1,case2,case3;
3310   int done0,done1,done2;
3311   int memtarget=0,c=0;
3312   int agr=AGEN1+(i&1);
3313   u_int hr,reglist=0;
3314   th=get_reg(i_regs->regmap,rs2[i]|64);
3315   tl=get_reg(i_regs->regmap,rs2[i]);
3316   s=get_reg(i_regs->regmap,rs1[i]);
3317   temp=get_reg(i_regs->regmap,agr);
3318   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3319   offset=imm[i];
3320   if(s>=0) {
3321     c=(i_regs->isconst>>s)&1;
3322     if(c) {
3323       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3324       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3325     }
3326   }
3327   assert(tl>=0);
3328   for(hr=0;hr<HOST_REGS;hr++) {
3329     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3330   }
3331   assert(temp>=0);
3332   if(!using_tlb) {
3333     if(!c) {
3334       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3335       if(!offset&&s!=temp) emit_mov(s,temp);
3336       jaddr=(int)out;
3337       emit_jno(0);
3338     }
3339     else
3340     {
3341       if(!memtarget||!rs1[i]) {
3342         jaddr=(int)out;
3343         emit_jmp(0);
3344       }
3345     }
3346     #ifdef RAM_OFFSET
3347     int map=get_reg(i_regs->regmap,ROREG);
3348     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3349     gen_tlb_addr_w(temp,map);
3350     #else
3351     if((u_int)rdram!=0x80000000) 
3352       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3353     #endif
3354   }else{ // using tlb
3355     int map=get_reg(i_regs->regmap,TLREG);
3356     assert(map>=0);
3357     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3358     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3359     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3360     if(!jaddr&&!memtarget) {
3361       jaddr=(int)out;
3362       emit_jmp(0);
3363     }
3364     gen_tlb_addr_w(temp,map);
3365   }
3366
3367   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3368     temp2=get_reg(i_regs->regmap,FTEMP);
3369     if(!rs2[i]) temp2=th=tl;
3370   }
3371
3372 #ifndef BIG_ENDIAN_MIPS
3373     emit_xorimm(temp,3,temp);
3374 #endif
3375   emit_testimm(temp,2);
3376   case2=(int)out;
3377   emit_jne(0);
3378   emit_testimm(temp,1);
3379   case1=(int)out;
3380   emit_jne(0);
3381   // 0
3382   if (opcode[i]==0x2A) { // SWL
3383     emit_writeword_indexed(tl,0,temp);
3384   }
3385   if (opcode[i]==0x2E) { // SWR
3386     emit_writebyte_indexed(tl,3,temp);
3387   }
3388   if (opcode[i]==0x2C) { // SDL
3389     emit_writeword_indexed(th,0,temp);
3390     if(rs2[i]) emit_mov(tl,temp2);
3391   }
3392   if (opcode[i]==0x2D) { // SDR
3393     emit_writebyte_indexed(tl,3,temp);
3394     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3395   }
3396   done0=(int)out;
3397   emit_jmp(0);
3398   // 1
3399   set_jump_target(case1,(int)out);
3400   if (opcode[i]==0x2A) { // SWL
3401     // Write 3 msb into three least significant bytes
3402     if(rs2[i]) emit_rorimm(tl,8,tl);
3403     emit_writehword_indexed(tl,-1,temp);
3404     if(rs2[i]) emit_rorimm(tl,16,tl);
3405     emit_writebyte_indexed(tl,1,temp);
3406     if(rs2[i]) emit_rorimm(tl,8,tl);
3407   }
3408   if (opcode[i]==0x2E) { // SWR
3409     // Write two lsb into two most significant bytes
3410     emit_writehword_indexed(tl,1,temp);
3411   }
3412   if (opcode[i]==0x2C) { // SDL
3413     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3414     // Write 3 msb into three least significant bytes
3415     if(rs2[i]) emit_rorimm(th,8,th);
3416     emit_writehword_indexed(th,-1,temp);
3417     if(rs2[i]) emit_rorimm(th,16,th);
3418     emit_writebyte_indexed(th,1,temp);
3419     if(rs2[i]) emit_rorimm(th,8,th);
3420   }
3421   if (opcode[i]==0x2D) { // SDR
3422     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3423     // Write two lsb into two most significant bytes
3424     emit_writehword_indexed(tl,1,temp);
3425   }
3426   done1=(int)out;
3427   emit_jmp(0);
3428   // 2
3429   set_jump_target(case2,(int)out);
3430   emit_testimm(temp,1);
3431   case3=(int)out;
3432   emit_jne(0);
3433   if (opcode[i]==0x2A) { // SWL
3434     // Write two msb into two least significant bytes
3435     if(rs2[i]) emit_rorimm(tl,16,tl);
3436     emit_writehword_indexed(tl,-2,temp);
3437     if(rs2[i]) emit_rorimm(tl,16,tl);
3438   }
3439   if (opcode[i]==0x2E) { // SWR
3440     // Write 3 lsb into three most significant bytes
3441     emit_writebyte_indexed(tl,-1,temp);
3442     if(rs2[i]) emit_rorimm(tl,8,tl);
3443     emit_writehword_indexed(tl,0,temp);
3444     if(rs2[i]) emit_rorimm(tl,24,tl);
3445   }
3446   if (opcode[i]==0x2C) { // SDL
3447     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3448     // Write two msb into two least significant bytes
3449     if(rs2[i]) emit_rorimm(th,16,th);
3450     emit_writehword_indexed(th,-2,temp);
3451     if(rs2[i]) emit_rorimm(th,16,th);
3452   }
3453   if (opcode[i]==0x2D) { // SDR
3454     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3455     // Write 3 lsb into three most significant bytes
3456     emit_writebyte_indexed(tl,-1,temp);
3457     if(rs2[i]) emit_rorimm(tl,8,tl);
3458     emit_writehword_indexed(tl,0,temp);
3459     if(rs2[i]) emit_rorimm(tl,24,tl);
3460   }
3461   done2=(int)out;
3462   emit_jmp(0);
3463   // 3
3464   set_jump_target(case3,(int)out);
3465   if (opcode[i]==0x2A) { // SWL
3466     // Write msb into least significant byte
3467     if(rs2[i]) emit_rorimm(tl,24,tl);
3468     emit_writebyte_indexed(tl,-3,temp);
3469     if(rs2[i]) emit_rorimm(tl,8,tl);
3470   }
3471   if (opcode[i]==0x2E) { // SWR
3472     // Write entire word
3473     emit_writeword_indexed(tl,-3,temp);
3474   }
3475   if (opcode[i]==0x2C) { // SDL
3476     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3477     // Write msb into least significant byte
3478     if(rs2[i]) emit_rorimm(th,24,th);
3479     emit_writebyte_indexed(th,-3,temp);
3480     if(rs2[i]) emit_rorimm(th,8,th);
3481   }
3482   if (opcode[i]==0x2D) { // SDR
3483     if(rs2[i]) emit_mov(th,temp2);
3484     // Write entire word
3485     emit_writeword_indexed(tl,-3,temp);
3486   }
3487   set_jump_target(done0,(int)out);
3488   set_jump_target(done1,(int)out);
3489   set_jump_target(done2,(int)out);
3490   if (opcode[i]==0x2C) { // SDL
3491     emit_testimm(temp,4);
3492     done0=(int)out;
3493     emit_jne(0);
3494     emit_andimm(temp,~3,temp);
3495     emit_writeword_indexed(temp2,4,temp);
3496     set_jump_target(done0,(int)out);
3497   }
3498   if (opcode[i]==0x2D) { // SDR
3499     emit_testimm(temp,4);
3500     done0=(int)out;
3501     emit_jeq(0);
3502     emit_andimm(temp,~3,temp);
3503     emit_writeword_indexed(temp2,-4,temp);
3504     set_jump_target(done0,(int)out);
3505   }
3506   if(!c||!memtarget)
3507     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3508   if(!using_tlb) {
3509     #ifdef RAM_OFFSET
3510     int map=get_reg(i_regs->regmap,ROREG);
3511     if(map<0) map=HOST_TEMPREG;
3512     gen_orig_addr_w(temp,map);
3513     #else
3514     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3515     #endif
3516     #if defined(HOST_IMM8)
3517     int ir=get_reg(i_regs->regmap,INVCP);
3518     assert(ir>=0);
3519     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3520     #else
3521     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3522     #endif
3523     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3524     emit_callne(invalidate_addr_reg[temp]);
3525     #else
3526     jaddr2=(int)out;
3527     emit_jne(0);
3528     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3529     #endif
3530   }
3531   /*
3532     emit_pusha();
3533     //save_regs(0x100f);
3534         emit_readword((int)&last_count,ECX);
3535         if(get_reg(i_regs->regmap,CCREG)<0)
3536           emit_loadreg(CCREG,HOST_CCREG);
3537         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3538         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3539         emit_writeword(HOST_CCREG,(int)&Count);
3540     emit_call((int)memdebug);
3541     emit_popa();
3542     //restore_regs(0x100f);
3543   /**/
3544 }
3545
3546 void c1ls_assemble(int i,struct regstat *i_regs)
3547 {
3548 #ifndef DISABLE_COP1
3549   int s,th,tl;
3550   int temp,ar;
3551   int map=-1;
3552   int offset;
3553   int c=0;
3554   int jaddr,jaddr2=0,jaddr3,type;
3555   int agr=AGEN1+(i&1);
3556   u_int hr,reglist=0;
3557   th=get_reg(i_regs->regmap,FTEMP|64);
3558   tl=get_reg(i_regs->regmap,FTEMP);
3559   s=get_reg(i_regs->regmap,rs1[i]);
3560   temp=get_reg(i_regs->regmap,agr);
3561   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3562   offset=imm[i];
3563   assert(tl>=0);
3564   assert(rs1[i]>0);
3565   assert(temp>=0);
3566   for(hr=0;hr<HOST_REGS;hr++) {
3567     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3568   }
3569   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3570   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3571   {
3572     // Loads use a temporary register which we need to save
3573     reglist|=1<<temp;
3574   }
3575   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3576     ar=temp;
3577   else // LWC1/LDC1
3578     ar=tl;
3579   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3580   //else c=(i_regs->wasconst>>s)&1;
3581   if(s>=0) c=(i_regs->wasconst>>s)&1;
3582   // Check cop1 unusable
3583   if(!cop1_usable) {
3584     signed char rs=get_reg(i_regs->regmap,CSREG);
3585     assert(rs>=0);
3586     emit_testimm(rs,0x20000000);
3587     jaddr=(int)out;
3588     emit_jeq(0);
3589     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3590     cop1_usable=1;
3591   }
3592   if (opcode[i]==0x39) { // SWC1 (get float address)
3593     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3594   }
3595   if (opcode[i]==0x3D) { // SDC1 (get double address)
3596     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3597   }
3598   // Generate address + offset
3599   if(!using_tlb) {
3600     if(!c)
3601       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3602   }
3603   else
3604   {
3605     map=get_reg(i_regs->regmap,TLREG);
3606     assert(map>=0);
3607     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3608       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3609     }
3610     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3611       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3612     }
3613   }
3614   if (opcode[i]==0x39) { // SWC1 (read float)
3615     emit_readword_indexed(0,tl,tl);
3616   }
3617   if (opcode[i]==0x3D) { // SDC1 (read double)
3618     emit_readword_indexed(4,tl,th);
3619     emit_readword_indexed(0,tl,tl);
3620   }
3621   if (opcode[i]==0x31) { // LWC1 (get target address)
3622     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3623   }
3624   if (opcode[i]==0x35) { // LDC1 (get target address)
3625     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3626   }
3627   if(!using_tlb) {
3628     if(!c) {
3629       jaddr2=(int)out;
3630       emit_jno(0);
3631     }
3632     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3633       jaddr2=(int)out;
3634       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3635     }
3636     #ifdef DESTRUCTIVE_SHIFT
3637     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3638       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3639     }
3640     #endif
3641   }else{
3642     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3643       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3644     }
3645     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3646       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3647     }
3648   }
3649   if (opcode[i]==0x31) { // LWC1
3650     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3651     //gen_tlb_addr_r(ar,map);
3652     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3653     #ifdef HOST_IMM_ADDR32
3654     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3655     else
3656     #endif
3657     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3658     type=LOADW_STUB;
3659   }
3660   if (opcode[i]==0x35) { // LDC1
3661     assert(th>=0);
3662     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3663     //gen_tlb_addr_r(ar,map);
3664     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3665     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3666     #ifdef HOST_IMM_ADDR32
3667     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3668     else
3669     #endif
3670     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3671     type=LOADD_STUB;
3672   }
3673   if (opcode[i]==0x39) { // SWC1
3674     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3675     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3676     type=STOREW_STUB;
3677   }
3678   if (opcode[i]==0x3D) { // SDC1
3679     assert(th>=0);
3680     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3681     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3682     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3683     type=STORED_STUB;
3684   }
3685   if(!using_tlb) {
3686     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3687       #ifndef DESTRUCTIVE_SHIFT
3688       temp=offset||c||s<0?ar:s;
3689       #endif
3690       #if defined(HOST_IMM8)
3691       int ir=get_reg(i_regs->regmap,INVCP);
3692       assert(ir>=0);
3693       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3694       #else
3695       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3696       #endif
3697       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3698       emit_callne(invalidate_addr_reg[temp]);
3699       #else
3700       jaddr3=(int)out;
3701       emit_jne(0);
3702       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3703       #endif
3704     }
3705   }
3706   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3707   if (opcode[i]==0x31) { // LWC1 (write float)
3708     emit_writeword_indexed(tl,0,temp);
3709   }
3710   if (opcode[i]==0x35) { // LDC1 (write double)
3711     emit_writeword_indexed(th,4,temp);
3712     emit_writeword_indexed(tl,0,temp);
3713   }
3714   //if(opcode[i]==0x39)
3715   /*if(opcode[i]==0x39||opcode[i]==0x31)
3716   {
3717     emit_pusha();
3718         emit_readword((int)&last_count,ECX);
3719         if(get_reg(i_regs->regmap,CCREG)<0)
3720           emit_loadreg(CCREG,HOST_CCREG);
3721         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3722         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3723         emit_writeword(HOST_CCREG,(int)&Count);
3724     emit_call((int)memdebug);
3725     emit_popa();
3726   }/**/
3727 #else
3728   cop1_unusable(i, i_regs);
3729 #endif
3730 }
3731
3732 void c2ls_assemble(int i,struct regstat *i_regs)
3733 {
3734   int s,tl;
3735   int ar;
3736   int offset;
3737   int memtarget=0,c=0;
3738   int jaddr2=0,jaddr3,type;
3739   int agr=AGEN1+(i&1);
3740   u_int hr,reglist=0;
3741   u_int copr=(source[i]>>16)&0x1f;
3742   s=get_reg(i_regs->regmap,rs1[i]);
3743   tl=get_reg(i_regs->regmap,FTEMP);
3744   offset=imm[i];
3745   assert(rs1[i]>0);
3746   assert(tl>=0);
3747   assert(!using_tlb);
3748
3749   for(hr=0;hr<HOST_REGS;hr++) {
3750     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3751   }
3752   if(i_regs->regmap[HOST_CCREG]==CCREG)
3753     reglist&=~(1<<HOST_CCREG);
3754
3755   // get the address
3756   if (opcode[i]==0x3a) { // SWC2
3757     ar=get_reg(i_regs->regmap,agr);
3758     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3759     reglist|=1<<ar;
3760   } else { // LWC2
3761     ar=tl;
3762   }
3763   if(s>=0) c=(i_regs->wasconst>>s)&1;
3764   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3765   if (!offset&&!c&&s>=0) ar=s;
3766   assert(ar>=0);
3767
3768   if (opcode[i]==0x3a) { // SWC2
3769     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3770     type=STOREW_STUB;
3771   }
3772   else
3773     type=LOADW_STUB;
3774
3775   if(c&&!memtarget) {
3776     jaddr2=(int)out;
3777     emit_jmp(0); // inline_readstub/inline_writestub?
3778   }
3779   else {
3780     if(!c) {
3781       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3782       jaddr2=(int)out;
3783       emit_jno(0);
3784     }
3785     if (opcode[i]==0x32) { // LWC2
3786       #ifdef HOST_IMM_ADDR32
3787       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3788       else
3789       #endif
3790       emit_readword_indexed(0,ar,tl);
3791     }
3792     if (opcode[i]==0x3a) { // SWC2
3793       #ifdef DESTRUCTIVE_SHIFT
3794       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3795       #endif
3796       emit_writeword_indexed(tl,0,ar);
3797     }
3798   }
3799   if(jaddr2)
3800     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3801   if (opcode[i]==0x3a) { // SWC2
3802 #if defined(HOST_IMM8)
3803     int ir=get_reg(i_regs->regmap,INVCP);
3804     assert(ir>=0);
3805     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3806 #else
3807     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3808 #endif
3809     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3810     emit_callne(invalidate_addr_reg[ar]);
3811     #else
3812     jaddr3=(int)out;
3813     emit_jne(0);
3814     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3815     #endif
3816   }
3817   if (opcode[i]==0x32) { // LWC2
3818     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3819   }
3820 }
3821
3822 #ifndef multdiv_assemble
3823 void multdiv_assemble(int i,struct regstat *i_regs)
3824 {
3825   printf("Need multdiv_assemble for this architecture.\n");
3826   exit(1);
3827 }
3828 #endif
3829
3830 void mov_assemble(int i,struct regstat *i_regs)
3831 {
3832   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3833   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3834   if(rt1[i]) {
3835     signed char sh,sl,th,tl;
3836     th=get_reg(i_regs->regmap,rt1[i]|64);
3837     tl=get_reg(i_regs->regmap,rt1[i]);
3838     //assert(tl>=0);
3839     if(tl>=0) {
3840       sh=get_reg(i_regs->regmap,rs1[i]|64);
3841       sl=get_reg(i_regs->regmap,rs1[i]);
3842       if(sl>=0) emit_mov(sl,tl);
3843       else emit_loadreg(rs1[i],tl);
3844       if(th>=0) {
3845         if(sh>=0) emit_mov(sh,th);
3846         else emit_loadreg(rs1[i]|64,th);
3847       }
3848     }
3849   }
3850 }
3851
3852 #ifndef fconv_assemble
3853 void fconv_assemble(int i,struct regstat *i_regs)
3854 {
3855   printf("Need fconv_assemble for this architecture.\n");
3856   exit(1);
3857 }
3858 #endif
3859
3860 #if 0
3861 void float_assemble(int i,struct regstat *i_regs)
3862 {
3863   printf("Need float_assemble for this architecture.\n");
3864   exit(1);
3865 }
3866 #endif
3867
3868 void syscall_assemble(int i,struct regstat *i_regs)
3869 {
3870   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3871   assert(ccreg==HOST_CCREG);
3872   assert(!is_delayslot);
3873   emit_movimm(start+i*4,EAX); // Get PC
3874   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3875   emit_jmp((int)jump_syscall_hle); // XXX
3876 }
3877
3878 void hlecall_assemble(int i,struct regstat *i_regs)
3879 {
3880   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3881   assert(ccreg==HOST_CCREG);
3882   assert(!is_delayslot);
3883   emit_movimm(start+i*4+4,0); // Get PC
3884   emit_movimm((int)psxHLEt[source[i]&7],1);
3885   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3886   emit_jmp((int)jump_hlecall);
3887 }
3888
3889 void intcall_assemble(int i,struct regstat *i_regs)
3890 {
3891   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3892   assert(ccreg==HOST_CCREG);
3893   assert(!is_delayslot);
3894   emit_movimm(start+i*4,0); // Get PC
3895   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3896   emit_jmp((int)jump_intcall);
3897 }
3898
3899 void ds_assemble(int i,struct regstat *i_regs)
3900 {
3901   is_delayslot=1;
3902   switch(itype[i]) {
3903     case ALU:
3904       alu_assemble(i,i_regs);break;
3905     case IMM16:
3906       imm16_assemble(i,i_regs);break;
3907     case SHIFT:
3908       shift_assemble(i,i_regs);break;
3909     case SHIFTIMM:
3910       shiftimm_assemble(i,i_regs);break;
3911     case LOAD:
3912       load_assemble(i,i_regs);break;
3913     case LOADLR:
3914       loadlr_assemble(i,i_regs);break;
3915     case STORE:
3916       store_assemble(i,i_regs);break;
3917     case STORELR:
3918       storelr_assemble(i,i_regs);break;
3919     case COP0:
3920       cop0_assemble(i,i_regs);break;
3921     case COP1:
3922       cop1_assemble(i,i_regs);break;
3923     case C1LS:
3924       c1ls_assemble(i,i_regs);break;
3925     case COP2:
3926       cop2_assemble(i,i_regs);break;
3927     case C2LS:
3928       c2ls_assemble(i,i_regs);break;
3929     case C2OP:
3930       c2op_assemble(i,i_regs);break;
3931     case FCONV:
3932       fconv_assemble(i,i_regs);break;
3933     case FLOAT:
3934       float_assemble(i,i_regs);break;
3935     case FCOMP:
3936       fcomp_assemble(i,i_regs);break;
3937     case MULTDIV:
3938       multdiv_assemble(i,i_regs);break;
3939     case MOV:
3940       mov_assemble(i,i_regs);break;
3941     case SYSCALL:
3942     case HLECALL:
3943     case INTCALL:
3944     case SPAN:
3945     case UJUMP:
3946     case RJUMP:
3947     case CJUMP:
3948     case SJUMP:
3949     case FJUMP:
3950       printf("Jump in the delay slot.  This is probably a bug.\n");
3951   }
3952   is_delayslot=0;
3953 }
3954
3955 // Is the branch target a valid internal jump?
3956 int internal_branch(uint64_t i_is32,int addr)
3957 {
3958   if(addr&1) return 0; // Indirect (register) jump
3959   if(addr>=start && addr<start+slen*4-4)
3960   {
3961     int t=(addr-start)>>2;
3962     // Delay slots are not valid branch targets
3963     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3964     // 64 -> 32 bit transition requires a recompile
3965     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3966     {
3967       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3968       else printf("optimizable: yes\n");
3969     }*/
3970     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3971 #ifndef FORCE32
3972     if(requires_32bit[t]&~i_is32) return 0;