9e58ef0fc90ed8221e28511825075f80d17d2c27
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2  *   Mupen64plus - new_dynarec.c                                           *
3  *   Copyright (C) 2009-2010 Ari64                                         *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21 #include <stdlib.h>
22 #include <stdint.h> //include for uint64_t
23 #include <assert.h>
24
25 #include "emu_if.h" //emulator interface
26
27 #include <sys/mman.h>
28
29 #ifdef __i386__
30 #include "assem_x86.h"
31 #endif
32 #ifdef __x86_64__
33 #include "assem_x64.h"
34 #endif
35 #ifdef __arm__
36 #include "assem_arm.h"
37 #endif
38
39 #define MAXBLOCK 4096
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
42
43 struct regstat
44 {
45   signed char regmap_entry[HOST_REGS];
46   signed char regmap[HOST_REGS];
47   uint64_t was32;
48   uint64_t is32;
49   uint64_t wasdirty;
50   uint64_t dirty;
51   uint64_t u;
52   uint64_t uu;
53   u_int wasconst;
54   u_int isconst;
55   uint64_t constmap[HOST_REGS];
56 };
57
58 struct ll_entry
59 {
60   u_int vaddr;
61   u_int reg32;
62   void *addr;
63   struct ll_entry *next;
64 };
65
66   u_int start;
67   u_int *source;
68   u_int pagelimit;
69   char insn[MAXBLOCK][10];
70   u_char itype[MAXBLOCK];
71   u_char opcode[MAXBLOCK];
72   u_char opcode2[MAXBLOCK];
73   u_char bt[MAXBLOCK];
74   u_char rs1[MAXBLOCK];
75   u_char rs2[MAXBLOCK];
76   u_char rt1[MAXBLOCK];
77   u_char rt2[MAXBLOCK];
78   u_char us1[MAXBLOCK];
79   u_char us2[MAXBLOCK];
80   u_char dep1[MAXBLOCK];
81   u_char dep2[MAXBLOCK];
82   u_char lt1[MAXBLOCK];
83   int imm[MAXBLOCK];
84   u_int ba[MAXBLOCK];
85   char likely[MAXBLOCK];
86   char is_ds[MAXBLOCK];
87   uint64_t unneeded_reg[MAXBLOCK];
88   uint64_t unneeded_reg_upper[MAXBLOCK];
89   uint64_t branch_unneeded_reg[MAXBLOCK];
90   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91   uint64_t p32[MAXBLOCK];
92   uint64_t pr32[MAXBLOCK];
93   signed char regmap_pre[MAXBLOCK][HOST_REGS];
94   signed char regmap[MAXBLOCK][HOST_REGS];
95   signed char regmap_entry[MAXBLOCK][HOST_REGS];
96   uint64_t constmap[MAXBLOCK][HOST_REGS];
97   uint64_t known_value[HOST_REGS];
98   u_int known_reg;
99   struct regstat regs[MAXBLOCK];
100   struct regstat branch_regs[MAXBLOCK];
101   u_int needed_reg[MAXBLOCK];
102   uint64_t requires_32bit[MAXBLOCK];
103   u_int wont_dirty[MAXBLOCK];
104   u_int will_dirty[MAXBLOCK];
105   int ccadj[MAXBLOCK];
106   int slen;
107   u_int instr_addr[MAXBLOCK];
108   u_int link_addr[MAXBLOCK][3];
109   int linkcount;
110   u_int stubs[MAXBLOCK*3][8];
111   int stubcount;
112   u_int literals[1024][2];
113   int literalcount;
114   int is_delayslot;
115   int cop1_usable;
116   u_char *out;
117   struct ll_entry *jump_in[4096];
118   struct ll_entry *jump_out[4096];
119   struct ll_entry *jump_dirty[4096];
120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
121   char shadow[1048576]  __attribute__((aligned(16)));
122   void *copy;
123   int expirep;
124   u_int using_tlb;
125   u_int stop_after_jal;
126   extern u_char restore_candidate[512];
127   extern int cycle_count;
128
129   /* registers that may be allocated */
130   /* 1-31 gpr */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
137 #define TEMPREG 38
138 #define FTEMP 38 // FPU temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
144 #define MAXREG 43
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
150
151   /* instruction types */
152 #define NOP 0     // No operation
153 #define LOAD 1    // Load
154 #define STORE 2   // Store
155 #define LOADLR 3  // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5     // Move 
158 #define ALU 6     // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8   // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10  // 16-bit immediate
163 #define RJUMP 11  // Unconditional jump to register
164 #define UJUMP 12  // Unconditional jump
165 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14  // Conditional branch (regimm format)
167 #define COP0 15   // Coprocessor 0
168 #define COP1 16   // Coprocessor 1
169 #define C1LS 17   // Coprocessor 1 load/store
170 #define FJUMP 18  // Conditional branch (floating point)
171 #define FLOAT 19  // Floating point unit
172 #define FCONV 20  // Convert integer to float
173 #define FCOMP 21  // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23  // Other
176 #define SPAN 24   // Branch/delay slot spans 2 pages
177 #define NI 25     // Not implemented
178
179   /* stubs */
180 #define CC_STUB 1
181 #define FP_STUB 2
182 #define LOADB_STUB 3
183 #define LOADH_STUB 4
184 #define LOADW_STUB 5
185 #define LOADD_STUB 6
186 #define LOADBU_STUB 7
187 #define LOADHU_STUB 8
188 #define STOREB_STUB 9
189 #define STOREH_STUB 10
190 #define STOREW_STUB 11
191 #define STORED_STUB 12
192 #define STORELR_STUB 13
193 #define INVCODE_STUB 14
194
195   /* branch codes */
196 #define TAKEN 1
197 #define NOTTAKEN 2
198 #define NULLDS 3
199
200 // asm linkage
201 int new_recompile_block(int addr);
202 void *get_addr_ht(u_int vaddr);
203 void invalidate_block(u_int block);
204 void invalidate_addr(u_int addr);
205 void remove_hash(int vaddr);
206 void jump_vaddr();
207 void dyna_linker();
208 void dyna_linker_ds();
209 void verify_code();
210 void verify_code_vm();
211 void verify_code_ds();
212 void cc_interrupt();
213 void fp_exception();
214 void fp_exception_ds();
215 void jump_syscall();
216 void jump_eret();
217
218 // TLB
219 void TLBWI_new();
220 void TLBWR_new();
221 void read_nomem_new();
222 void read_nomemb_new();
223 void read_nomemh_new();
224 void read_nomemd_new();
225 void write_nomem_new();
226 void write_nomemb_new();
227 void write_nomemh_new();
228 void write_nomemd_new();
229 void write_rdram_new();
230 void write_rdramb_new();
231 void write_rdramh_new();
232 void write_rdramd_new();
233 extern u_int memory_map[1048576];
234
235 // Needed by assembler
236 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
237 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
238 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
239 void load_all_regs(signed char i_regmap[]);
240 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
241 void load_regs_entry(int t);
242 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
243
244 int tracedebug=0;
245
246 //#define DEBUG_CYCLE_COUNT 1
247
248 void nullf() {}
249 //#define assem_debug printf
250 //#define inv_debug printf
251 #define assem_debug nullf
252 #define inv_debug nullf
253
254 static void tlb_hacks()
255 {
256 #ifndef DISABLE_TLB
257   // Goldeneye hack
258   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
259   {
260     u_int addr;
261     int n;
262     switch (ROM_HEADER->Country_code&0xFF) 
263     {
264       case 0x45: // U
265         addr=0x34b30;
266         break;                   
267       case 0x4A: // J 
268         addr=0x34b70;    
269         break;    
270       case 0x50: // E 
271         addr=0x329f0;
272         break;                        
273       default: 
274         // Unknown country code
275         addr=0;
276         break;
277     }
278     u_int rom_addr=(u_int)rom;
279     #ifdef ROM_COPY
280     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
281     // in the lower 4G of memory to use this hack.  Copy it if necessary.
282     if((void *)rom>(void *)0xffffffff) {
283       munmap(ROM_COPY, 67108864);
284       if(mmap(ROM_COPY, 12582912,
285               PROT_READ | PROT_WRITE,
286               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
287               -1, 0) <= 0) {printf("mmap() failed\n");}
288       memcpy(ROM_COPY,rom,12582912);
289       rom_addr=(u_int)ROM_COPY;
290     }
291     #endif
292     if(addr) {
293       for(n=0x7F000;n<0x80000;n++) {
294         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
295       }
296     }
297   }
298 #endif
299 }
300
301 static u_int get_page(u_int vaddr)
302 {
303   u_int page=(vaddr^0x80000000)>>12;
304 #ifndef DISABLE_TLB
305   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
306 #endif
307   if(page>2048) page=2048+(page&2047);
308   return page;
309 }
310
311 static u_int get_vpage(u_int vaddr)
312 {
313   u_int vpage=(vaddr^0x80000000)>>12;
314 #ifndef DISABLE_TLB
315   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
316 #endif
317   if(vpage>2048) vpage=2048+(vpage&2047);
318   return vpage;
319 }
320
321 // Get address from virtual address
322 // This is called from the recompiled JR/JALR instructions
323 void *get_addr(u_int vaddr)
324 {
325   u_int page=get_page(vaddr);
326   u_int vpage=get_vpage(vaddr);
327   struct ll_entry *head;
328   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
329   head=jump_in[page];
330   while(head!=NULL) {
331     if(head->vaddr==vaddr&&head->reg32==0) {
332   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
333       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
334       ht_bin[3]=ht_bin[1];
335       ht_bin[2]=ht_bin[0];
336       ht_bin[1]=(int)head->addr;
337       ht_bin[0]=vaddr;
338       return head->addr;
339     }
340     head=head->next;
341   }
342   head=jump_dirty[vpage];
343   while(head!=NULL) {
344     if(head->vaddr==vaddr&&head->reg32==0) {
345       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
346       // Don't restore blocks which are about to expire from the cache
347       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
348       if(verify_dirty(head->addr)) {
349         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
350         invalid_code[vaddr>>12]=0;
351         memory_map[vaddr>>12]|=0x40000000;
352         if(vpage<2048) {
353 #ifndef DISABLE_TLB
354           if(tlb_LUT_r[vaddr>>12]) {
355             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
356             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
357           }
358 #endif
359           restore_candidate[vpage>>3]|=1<<(vpage&7);
360         }
361         else restore_candidate[page>>3]|=1<<(page&7);
362         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
363         if(ht_bin[0]==vaddr) {
364           ht_bin[1]=(int)head->addr; // Replace existing entry
365         }
366         else
367         {
368           ht_bin[3]=ht_bin[1];
369           ht_bin[2]=ht_bin[0];
370           ht_bin[1]=(int)head->addr;
371           ht_bin[0]=vaddr;
372         }
373         return head->addr;
374       }
375     }
376     head=head->next;
377   }
378   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
379   int r=new_recompile_block(vaddr);
380   if(r==0) return get_addr(vaddr);
381   // Execute in unmapped page, generate pagefault execption
382   Status|=2;
383   Cause=(vaddr<<31)|0x8;
384   EPC=(vaddr&1)?vaddr-5:vaddr;
385   BadVAddr=(vaddr&~1);
386   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
387   EntryHi=BadVAddr&0xFFFFE000;
388   return get_addr_ht(0x80000000);
389 }
390 // Look up address in hash table first
391 void *get_addr_ht(u_int vaddr)
392 {
393   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
394   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
395   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
396   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
397   return get_addr(vaddr);
398 }
399
400 void *get_addr_32(u_int vaddr,u_int flags)
401 {
402   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
403   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406   u_int page=get_page(vaddr);
407   u_int vpage=get_vpage(vaddr);
408   struct ll_entry *head;
409   head=jump_in[page];
410   while(head!=NULL) {
411     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
412       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
413       if(head->reg32==0) {
414         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
415         if(ht_bin[0]==-1) {
416           ht_bin[1]=(int)head->addr;
417           ht_bin[0]=vaddr;
418         }else if(ht_bin[2]==-1) {
419           ht_bin[3]=(int)head->addr;
420           ht_bin[2]=vaddr;
421         }
422         //ht_bin[3]=ht_bin[1];
423         //ht_bin[2]=ht_bin[0];
424         //ht_bin[1]=(int)head->addr;
425         //ht_bin[0]=vaddr;
426       }
427       return head->addr;
428     }
429     head=head->next;
430   }
431   head=jump_dirty[vpage];
432   while(head!=NULL) {
433     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
434       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
435       // Don't restore blocks which are about to expire from the cache
436       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
437       if(verify_dirty(head->addr)) {
438         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
439         invalid_code[vaddr>>12]=0;
440         memory_map[vaddr>>12]|=0x40000000;
441         if(vpage<2048) {
442 #ifndef DISABLE_TLB
443           if(tlb_LUT_r[vaddr>>12]) {
444             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
445             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
446           }
447 #endif
448           restore_candidate[vpage>>3]|=1<<(vpage&7);
449         }
450         else restore_candidate[page>>3]|=1<<(page&7);
451         if(head->reg32==0) {
452           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
453           if(ht_bin[0]==-1) {
454             ht_bin[1]=(int)head->addr;
455             ht_bin[0]=vaddr;
456           }else if(ht_bin[2]==-1) {
457             ht_bin[3]=(int)head->addr;
458             ht_bin[2]=vaddr;
459           }
460           //ht_bin[3]=ht_bin[1];
461           //ht_bin[2]=ht_bin[0];
462           //ht_bin[1]=(int)head->addr;
463           //ht_bin[0]=vaddr;
464         }
465         return head->addr;
466       }
467     }
468     head=head->next;
469   }
470   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
471   int r=new_recompile_block(vaddr);
472   if(r==0) return get_addr(vaddr);
473   // Execute in unmapped page, generate pagefault execption
474   Status|=2;
475   Cause=(vaddr<<31)|0x8;
476   EPC=(vaddr&1)?vaddr-5:vaddr;
477   BadVAddr=(vaddr&~1);
478   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
479   EntryHi=BadVAddr&0xFFFFE000;
480   return get_addr_ht(0x80000000);
481 }
482
483 void clear_all_regs(signed char regmap[])
484 {
485   int hr;
486   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
487 }
488
489 signed char get_reg(signed char regmap[],int r)
490 {
491   int hr;
492   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
493   return -1;
494 }
495
496 // Find a register that is available for two consecutive cycles
497 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
498 {
499   int hr;
500   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
501   return -1;
502 }
503
504 int count_free_regs(signed char regmap[])
505 {
506   int count=0;
507   int hr;
508   for(hr=0;hr<HOST_REGS;hr++)
509   {
510     if(hr!=EXCLUDE_REG) {
511       if(regmap[hr]<0) count++;
512     }
513   }
514   return count;
515 }
516
517 void dirty_reg(struct regstat *cur,signed char reg)
518 {
519   int hr;
520   if(!reg) return;
521   for (hr=0;hr<HOST_REGS;hr++) {
522     if((cur->regmap[hr]&63)==reg) {
523       cur->dirty|=1<<hr;
524     }
525   }
526 }
527
528 // If we dirty the lower half of a 64 bit register which is now being
529 // sign-extended, we need to dump the upper half.
530 // Note: Do this only after completion of the instruction, because
531 // some instructions may need to read the full 64-bit value even if
532 // overwriting it (eg SLTI, DSRA32).
533 static void flush_dirty_uppers(struct regstat *cur)
534 {
535   int hr,reg;
536   for (hr=0;hr<HOST_REGS;hr++) {
537     if((cur->dirty>>hr)&1) {
538       reg=cur->regmap[hr];
539       if(reg>=64) 
540         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
541     }
542   }
543 }
544
545 void set_const(struct regstat *cur,signed char reg,uint64_t value)
546 {
547   int hr;
548   if(!reg) return;
549   for (hr=0;hr<HOST_REGS;hr++) {
550     if(cur->regmap[hr]==reg) {
551       cur->isconst|=1<<hr;
552       cur->constmap[hr]=value;
553     }
554     else if((cur->regmap[hr]^64)==reg) {
555       cur->isconst|=1<<hr;
556       cur->constmap[hr]=value>>32;
557     }
558   }
559 }
560
561 void clear_const(struct regstat *cur,signed char reg)
562 {
563   int hr;
564   if(!reg) return;
565   for (hr=0;hr<HOST_REGS;hr++) {
566     if((cur->regmap[hr]&63)==reg) {
567       cur->isconst&=~(1<<hr);
568     }
569   }
570 }
571
572 int is_const(struct regstat *cur,signed char reg)
573 {
574   int hr;
575   if(!reg) return 1;
576   for (hr=0;hr<HOST_REGS;hr++) {
577     if((cur->regmap[hr]&63)==reg) {
578       return (cur->isconst>>hr)&1;
579     }
580   }
581   return 0;
582 }
583 uint64_t get_const(struct regstat *cur,signed char reg)
584 {
585   int hr;
586   if(!reg) return 0;
587   for (hr=0;hr<HOST_REGS;hr++) {
588     if(cur->regmap[hr]==reg) {
589       return cur->constmap[hr];
590     }
591   }
592   printf("Unknown constant in r%d\n",reg);
593   exit(1);
594 }
595
596 // Least soon needed registers
597 // Look at the next ten instructions and see which registers
598 // will be used.  Try not to reallocate these.
599 void lsn(u_char hsn[], int i, int *preferred_reg)
600 {
601   int j;
602   int b=-1;
603   for(j=0;j<9;j++)
604   {
605     if(i+j>=slen) {
606       j=slen-i-1;
607       break;
608     }
609     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
610     {
611       // Don't go past an unconditonal jump
612       j++;
613       break;
614     }
615   }
616   for(;j>=0;j--)
617   {
618     if(rs1[i+j]) hsn[rs1[i+j]]=j;
619     if(rs2[i+j]) hsn[rs2[i+j]]=j;
620     if(rt1[i+j]) hsn[rt1[i+j]]=j;
621     if(rt2[i+j]) hsn[rt2[i+j]]=j;
622     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
623       // Stores can allocate zero
624       hsn[rs1[i+j]]=j;
625       hsn[rs2[i+j]]=j;
626     }
627     // On some architectures stores need invc_ptr
628     #if defined(HOST_IMM8)
629     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
630       hsn[INVCP]=j;
631     }
632     #endif
633     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
634     {
635       hsn[CCREG]=j;
636       b=j;
637     }
638   }
639   if(b>=0)
640   {
641     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
642     {
643       // Follow first branch
644       int t=(ba[i+b]-start)>>2;
645       j=7-b;if(t+j>=slen) j=slen-t-1;
646       for(;j>=0;j--)
647       {
648         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
649         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
650         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
651         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
652       }
653     }
654     // TODO: preferred register based on backward branch
655   }
656   // Delay slot should preferably not overwrite branch conditions or cycle count
657   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
658     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
659     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
660     hsn[CCREG]=1;
661     // ...or hash tables
662     hsn[RHASH]=1;
663     hsn[RHTBL]=1;
664   }
665   // Coprocessor load/store needs FTEMP, even if not declared
666   if(itype[i]==C1LS) {
667     hsn[FTEMP]=0;
668   }
669   // Load L/R also uses FTEMP as a temporary register
670   if(itype[i]==LOADLR) {
671     hsn[FTEMP]=0;
672   }
673   // Also 64-bit SDL/SDR
674   if(opcode[i]==0x2c||opcode[i]==0x2d) {
675     hsn[FTEMP]=0;
676   }
677   // Don't remove the TLB registers either
678   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
679     hsn[TLREG]=0;
680   }
681   // Don't remove the miniht registers
682   if(itype[i]==UJUMP||itype[i]==RJUMP)
683   {
684     hsn[RHASH]=0;
685     hsn[RHTBL]=0;
686   }
687 }
688
689 // We only want to allocate registers if we're going to use them again soon
690 int needed_again(int r, int i)
691 {
692   int j;
693   int b=-1;
694   int rn=10;
695   int hr;
696   u_char hsn[MAXREG+1];
697   int preferred_reg;
698   
699   memset(hsn,10,sizeof(hsn));
700   lsn(hsn,i,&preferred_reg);
701   
702   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
703   {
704     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
705       return 0; // Don't need any registers if exiting the block
706   }
707   for(j=0;j<9;j++)
708   {
709     if(i+j>=slen) {
710       j=slen-i-1;
711       break;
712     }
713     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
714     {
715       // Don't go past an unconditonal jump
716       j++;
717       break;
718     }
719     if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
720     {
721       break;
722     }
723   }
724   for(;j>=1;j--)
725   {
726     if(rs1[i+j]==r) rn=j;
727     if(rs2[i+j]==r) rn=j;
728     if((unneeded_reg[i+j]>>r)&1) rn=10;
729     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
730     {
731       b=j;
732     }
733   }
734   /*
735   if(b>=0)
736   {
737     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
738     {
739       // Follow first branch
740       int o=rn;
741       int t=(ba[i+b]-start)>>2;
742       j=7-b;if(t+j>=slen) j=slen-t-1;
743       for(;j>=0;j--)
744       {
745         if(!((unneeded_reg[t+j]>>r)&1)) {
746           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
747           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
748         }
749         else rn=o;
750       }
751     }
752   }*/
753   for(hr=0;hr<HOST_REGS;hr++) {
754     if(hr!=EXCLUDE_REG) {
755       if(rn<hsn[hr]) return 1;
756     }
757   }
758   return 0;
759 }
760
761 // Try to match register allocations at the end of a loop with those
762 // at the beginning
763 int loop_reg(int i, int r, int hr)
764 {
765   int j,k;
766   for(j=0;j<9;j++)
767   {
768     if(i+j>=slen) {
769       j=slen-i-1;
770       break;
771     }
772     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
773     {
774       // Don't go past an unconditonal jump
775       j++;
776       break;
777     }
778   }
779   k=0;
780   if(i>0){
781     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
782       k--;
783   }
784   for(;k<j;k++)
785   {
786     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
787     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
788     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
789     {
790       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
791       {
792         int t=(ba[i+k]-start)>>2;
793         int reg=get_reg(regs[t].regmap_entry,r);
794         if(reg>=0) return reg;
795         //reg=get_reg(regs[t+1].regmap_entry,r);
796         //if(reg>=0) return reg;
797       }
798     }
799   }
800   return hr;
801 }
802
803
804 // Allocate every register, preserving source/target regs
805 void alloc_all(struct regstat *cur,int i)
806 {
807   int hr;
808   
809   for(hr=0;hr<HOST_REGS;hr++) {
810     if(hr!=EXCLUDE_REG) {
811       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
812          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
813       {
814         cur->regmap[hr]=-1;
815         cur->dirty&=~(1<<hr);
816       }
817       // Don't need zeros
818       if((cur->regmap[hr]&63)==0)
819       {
820         cur->regmap[hr]=-1;
821         cur->dirty&=~(1<<hr);
822       }
823     }
824   }
825 }
826
827
828 void div64(int64_t dividend,int64_t divisor)
829 {
830   lo=dividend/divisor;
831   hi=dividend%divisor;
832   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
833   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
834 }
835 void divu64(uint64_t dividend,uint64_t divisor)
836 {
837   lo=dividend/divisor;
838   hi=dividend%divisor;
839   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
840   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
841 }
842
843 void mult64(uint64_t m1,uint64_t m2)
844 {
845    unsigned long long int op1, op2, op3, op4;
846    unsigned long long int result1, result2, result3, result4;
847    unsigned long long int temp1, temp2, temp3, temp4;
848    int sign = 0;
849    
850    if (m1 < 0)
851      {
852     op2 = -m1;
853     sign = 1 - sign;
854      }
855    else op2 = m1;
856    if (m2 < 0)
857      {
858     op4 = -m2;
859     sign = 1 - sign;
860      }
861    else op4 = m2;
862    
863    op1 = op2 & 0xFFFFFFFF;
864    op2 = (op2 >> 32) & 0xFFFFFFFF;
865    op3 = op4 & 0xFFFFFFFF;
866    op4 = (op4 >> 32) & 0xFFFFFFFF;
867    
868    temp1 = op1 * op3;
869    temp2 = (temp1 >> 32) + op1 * op4;
870    temp3 = op2 * op3;
871    temp4 = (temp3 >> 32) + op2 * op4;
872    
873    result1 = temp1 & 0xFFFFFFFF;
874    result2 = temp2 + (temp3 & 0xFFFFFFFF);
875    result3 = (result2 >> 32) + temp4;
876    result4 = (result3 >> 32);
877    
878    lo = result1 | (result2 << 32);
879    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
880    if (sign)
881      {
882     hi = ~hi;
883     if (!lo) hi++;
884     else lo = ~lo + 1;
885      }
886 }
887
888 void multu64(uint64_t m1,uint64_t m2)
889 {
890    unsigned long long int op1, op2, op3, op4;
891    unsigned long long int result1, result2, result3, result4;
892    unsigned long long int temp1, temp2, temp3, temp4;
893    
894    op1 = m1 & 0xFFFFFFFF;
895    op2 = (m1 >> 32) & 0xFFFFFFFF;
896    op3 = m2 & 0xFFFFFFFF;
897    op4 = (m2 >> 32) & 0xFFFFFFFF;
898    
899    temp1 = op1 * op3;
900    temp2 = (temp1 >> 32) + op1 * op4;
901    temp3 = op2 * op3;
902    temp4 = (temp3 >> 32) + op2 * op4;
903    
904    result1 = temp1 & 0xFFFFFFFF;
905    result2 = temp2 + (temp3 & 0xFFFFFFFF);
906    result3 = (result2 >> 32) + temp4;
907    result4 = (result3 >> 32);
908    
909    lo = result1 | (result2 << 32);
910    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
911    
912   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
913   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
914 }
915
916 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
917 {
918   if(bits) {
919     original<<=64-bits;
920     original>>=64-bits;
921     loaded<<=bits;
922     original|=loaded;
923   }
924   else original=loaded;
925   return original;
926 }
927 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
928 {
929   if(bits^56) {
930     original>>=64-(bits^56);
931     original<<=64-(bits^56);
932     loaded>>=bits^56;
933     original|=loaded;
934   }
935   else original=loaded;
936   return original;
937 }
938
939 #ifdef __i386__
940 #include "assem_x86.c"
941 #endif
942 #ifdef __x86_64__
943 #include "assem_x64.c"
944 #endif
945 #ifdef __arm__
946 #include "assem_arm.c"
947 #endif
948
949 // Add virtual address mapping to linked list
950 void ll_add(struct ll_entry **head,int vaddr,void *addr)
951 {
952   struct ll_entry *new_entry;
953   new_entry=malloc(sizeof(struct ll_entry));
954   assert(new_entry!=NULL);
955   new_entry->vaddr=vaddr;
956   new_entry->reg32=0;
957   new_entry->addr=addr;
958   new_entry->next=*head;
959   *head=new_entry;
960 }
961
962 // Add virtual address mapping for 32-bit compiled block
963 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
964 {
965   struct ll_entry *new_entry;
966   new_entry=malloc(sizeof(struct ll_entry));
967   assert(new_entry!=NULL);
968   new_entry->vaddr=vaddr;
969   new_entry->reg32=reg32;
970   new_entry->addr=addr;
971   new_entry->next=*head;
972   *head=new_entry;
973 }
974
975 // Check if an address is already compiled
976 // but don't return addresses which are about to expire from the cache
977 void *check_addr(u_int vaddr)
978 {
979   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
980   if(ht_bin[0]==vaddr) {
981     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
982       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
983   }
984   if(ht_bin[2]==vaddr) {
985     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
986       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
987   }
988   u_int page=get_page(vaddr);
989   struct ll_entry *head;
990   head=jump_in[page];
991   while(head!=NULL) {
992     if(head->vaddr==vaddr&&head->reg32==0) {
993       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
994         // Update existing entry with current address
995         if(ht_bin[0]==vaddr) {
996           ht_bin[1]=(int)head->addr;
997           return head->addr;
998         }
999         if(ht_bin[2]==vaddr) {
1000           ht_bin[3]=(int)head->addr;
1001           return head->addr;
1002         }
1003         // Insert into hash table with low priority.
1004         // Don't evict existing entries, as they are probably
1005         // addresses that are being accessed frequently.
1006         if(ht_bin[0]==-1) {
1007           ht_bin[1]=(int)head->addr;
1008           ht_bin[0]=vaddr;
1009         }else if(ht_bin[2]==-1) {
1010           ht_bin[3]=(int)head->addr;
1011           ht_bin[2]=vaddr;
1012         }
1013         return head->addr;
1014       }
1015     }
1016     head=head->next;
1017   }
1018   return 0;
1019 }
1020
1021 void remove_hash(int vaddr)
1022 {
1023   //printf("remove hash: %x\n",vaddr);
1024   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1025   if(ht_bin[2]==vaddr) {
1026     ht_bin[2]=ht_bin[3]=-1;
1027   }
1028   if(ht_bin[0]==vaddr) {
1029     ht_bin[0]=ht_bin[2];
1030     ht_bin[1]=ht_bin[3];
1031     ht_bin[2]=ht_bin[3]=-1;
1032   }
1033 }
1034
1035 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1036 {
1037   struct ll_entry *next;
1038   while(*head) {
1039     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
1040        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1041     {
1042       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1043       remove_hash((*head)->vaddr);
1044       next=(*head)->next;
1045       free(*head);
1046       *head=next;
1047     }
1048     else
1049     {
1050       head=&((*head)->next);
1051     }
1052   }
1053 }
1054
1055 // Remove all entries from linked list
1056 void ll_clear(struct ll_entry **head)
1057 {
1058   struct ll_entry *cur;
1059   struct ll_entry *next;
1060   if(cur=*head) {
1061     *head=0;
1062     while(cur) {
1063       next=cur->next;
1064       free(cur);
1065       cur=next;
1066     }
1067   }
1068 }
1069
1070 // Dereference the pointers and remove if it matches
1071 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1072 {
1073   while(head) {
1074     int ptr=get_pointer(head->addr);
1075     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1076     if(((ptr>>shift)==(addr>>shift)) ||
1077        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1078     {
1079       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1080       kill_pointer(head->addr);
1081     }
1082     head=head->next;
1083   }
1084 }
1085
1086 // This is called when we write to a compiled block (see do_invstub)
1087 int invalidate_page(u_int page)
1088 {
1089   int modified=0;
1090   struct ll_entry *head;
1091   struct ll_entry *next;
1092   head=jump_in[page];
1093   jump_in[page]=0;
1094   while(head!=NULL) {
1095     inv_debug("INVALIDATE: %x\n",head->vaddr);
1096     remove_hash(head->vaddr);
1097     next=head->next;
1098     free(head);
1099     head=next;
1100   }
1101   head=jump_out[page];
1102   jump_out[page]=0;
1103   while(head!=NULL) {
1104     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1105     kill_pointer(head->addr);
1106     modified=1;
1107     next=head->next;
1108     free(head);
1109     head=next;
1110   }
1111   return modified;
1112 }
1113 void invalidate_block(u_int block)
1114 {
1115   int modified;
1116   u_int page=get_page(block<<12);
1117   u_int vpage=get_vpage(block<<12);
1118   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1119   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1120   u_int first,last;
1121   first=last=page;
1122   struct ll_entry *head;
1123   head=jump_dirty[vpage];
1124   //printf("page=%d vpage=%d\n",page,vpage);
1125   while(head!=NULL) {
1126     u_int start,end;
1127     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1128       get_bounds((int)head->addr,&start,&end);
1129       //printf("start: %x end: %x\n",start,end);
1130       if(page<2048&&start>=0x80000000&&end<0x80800000) {
1131         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1132           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1133           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1134         }
1135       }
1136 #ifndef DISABLE_TLB
1137       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1138         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1139           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1140           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1141         }
1142       }
1143 #endif
1144     }
1145     head=head->next;
1146   }
1147   //printf("first=%d last=%d\n",first,last);
1148   modified=invalidate_page(page);
1149   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1150   assert(last<page+5);
1151   // Invalidate the adjacent pages if a block crosses a 4K boundary
1152   while(first<page) {
1153     invalidate_page(first);
1154     first++;
1155   }
1156   for(first=page+1;first<last;first++) {
1157     invalidate_page(first);
1158   }
1159   
1160   // Don't trap writes
1161   invalid_code[block]=1;
1162 #ifndef DISABLE_TLB
1163   // If there is a valid TLB entry for this page, remove write protect
1164   if(tlb_LUT_w[block]) {
1165     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1166     // CHECK: Is this right?
1167     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1168     u_int real_block=tlb_LUT_w[block]>>12;
1169     invalid_code[real_block]=1;
1170     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1171   }
1172   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1173 #endif
1174   #ifdef __arm__
1175   if(modified)
1176     __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1177   #endif
1178   #ifdef USE_MINI_HT
1179   memset(mini_ht,-1,sizeof(mini_ht));
1180   #endif
1181 }
1182 void invalidate_addr(u_int addr)
1183 {
1184   invalidate_block(addr>>12);
1185 }
1186 void invalidate_all_pages()
1187 {
1188   u_int page,n;
1189   for(page=0;page<4096;page++)
1190     invalidate_page(page);
1191   for(page=0;page<1048576;page++)
1192     if(!invalid_code[page]) {
1193       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1194       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1195     }
1196   #ifdef __arm__
1197   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1198   #endif
1199   #ifdef USE_MINI_HT
1200   memset(mini_ht,-1,sizeof(mini_ht));
1201   #endif
1202   #ifndef DISABLE_TLB
1203   // TLB
1204   for(page=0;page<0x100000;page++) {
1205     if(tlb_LUT_r[page]) {
1206       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1207       if(!tlb_LUT_w[page]||!invalid_code[page])
1208         memory_map[page]|=0x40000000; // Write protect
1209     }
1210     else memory_map[page]=-1;
1211     if(page==0x80000) page=0xC0000;
1212   }
1213   tlb_hacks();
1214   #endif
1215 }
1216
1217 // Add an entry to jump_out after making a link
1218 void add_link(u_int vaddr,void *src)
1219 {
1220   u_int page=get_page(vaddr);
1221   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1222   ll_add(jump_out+page,vaddr,src);
1223   //int ptr=get_pointer(src);
1224   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1225 }
1226
1227 // If a code block was found to be unmodified (bit was set in
1228 // restore_candidate) and it remains unmodified (bit is clear
1229 // in invalid_code) then move the entries for that 4K page from
1230 // the dirty list to the clean list.
1231 void clean_blocks(u_int page)
1232 {
1233   struct ll_entry *head;
1234   inv_debug("INV: clean_blocks page=%d\n",page);
1235   head=jump_dirty[page];
1236   while(head!=NULL) {
1237     if(!invalid_code[head->vaddr>>12]) {
1238       // Don't restore blocks which are about to expire from the cache
1239       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1240         u_int start,end;
1241         if(verify_dirty((int)head->addr)) {
1242           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1243           u_int i;
1244           u_int inv=0;
1245           get_bounds((int)head->addr,&start,&end);
1246           if(start-(u_int)rdram<0x800000) {
1247             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1248               inv|=invalid_code[i];
1249             }
1250           }
1251           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1252             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1253             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1254             if(addr<start||addr>=end) inv=1;
1255           }
1256           else if((signed int)head->vaddr>=(signed int)0x80800000) {
1257             inv=1;
1258           }
1259           if(!inv) {
1260             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1261             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1262               u_int ppage=page;
1263 #ifndef DISABLE_TLB
1264               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1265 #endif
1266               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1267               //printf("page=%x, addr=%x\n",page,head->vaddr);
1268               //assert(head->vaddr>>12==(page|0x80000));
1269               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1270               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1271               if(!head->reg32) {
1272                 if(ht_bin[0]==head->vaddr) {
1273                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1274                 }
1275                 if(ht_bin[2]==head->vaddr) {
1276                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1277                 }
1278               }
1279             }
1280           }
1281         }
1282       }
1283     }
1284     head=head->next;
1285   }
1286 }
1287
1288
1289 void mov_alloc(struct regstat *current,int i)
1290 {
1291   // Note: Don't need to actually alloc the source registers
1292   if((~current->is32>>rs1[i])&1) {
1293     //alloc_reg64(current,i,rs1[i]);
1294     alloc_reg64(current,i,rt1[i]);
1295     current->is32&=~(1LL<<rt1[i]);
1296   } else {
1297     //alloc_reg(current,i,rs1[i]);
1298     alloc_reg(current,i,rt1[i]);
1299     current->is32|=(1LL<<rt1[i]);
1300   }
1301   clear_const(current,rs1[i]);
1302   clear_const(current,rt1[i]);
1303   dirty_reg(current,rt1[i]);
1304 }
1305
1306 void shiftimm_alloc(struct regstat *current,int i)
1307 {
1308   clear_const(current,rs1[i]);
1309   clear_const(current,rt1[i]);
1310   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1311   {
1312     if(rt1[i]) {
1313       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1314       else lt1[i]=rs1[i];
1315       alloc_reg(current,i,rt1[i]);
1316       current->is32|=1LL<<rt1[i];
1317       dirty_reg(current,rt1[i]);
1318     }
1319   }
1320   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1321   {
1322     if(rt1[i]) {
1323       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1324       alloc_reg64(current,i,rt1[i]);
1325       current->is32&=~(1LL<<rt1[i]);
1326       dirty_reg(current,rt1[i]);
1327     }
1328   }
1329   if(opcode2[i]==0x3c) // DSLL32
1330   {
1331     if(rt1[i]) {
1332       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1333       alloc_reg64(current,i,rt1[i]);
1334       current->is32&=~(1LL<<rt1[i]);
1335       dirty_reg(current,rt1[i]);
1336     }
1337   }
1338   if(opcode2[i]==0x3e) // DSRL32
1339   {
1340     if(rt1[i]) {
1341       alloc_reg64(current,i,rs1[i]);
1342       if(imm[i]==32) {
1343         alloc_reg64(current,i,rt1[i]);
1344         current->is32&=~(1LL<<rt1[i]);
1345       } else {
1346         alloc_reg(current,i,rt1[i]);
1347         current->is32|=1LL<<rt1[i];
1348       }
1349       dirty_reg(current,rt1[i]);
1350     }
1351   }
1352   if(opcode2[i]==0x3f) // DSRA32
1353   {
1354     if(rt1[i]) {
1355       alloc_reg64(current,i,rs1[i]);
1356       alloc_reg(current,i,rt1[i]);
1357       current->is32|=1LL<<rt1[i];
1358       dirty_reg(current,rt1[i]);
1359     }
1360   }
1361 }
1362
1363 void shift_alloc(struct regstat *current,int i)
1364 {
1365   if(rt1[i]) {
1366     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1367     {
1368       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1369       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1370       alloc_reg(current,i,rt1[i]);
1371       if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1372       current->is32|=1LL<<rt1[i];
1373     } else { // DSLLV/DSRLV/DSRAV
1374       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1375       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1376       alloc_reg64(current,i,rt1[i]);
1377       current->is32&=~(1LL<<rt1[i]);
1378       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1379         alloc_reg_temp(current,i,-1);
1380     }
1381     clear_const(current,rs1[i]);
1382     clear_const(current,rs2[i]);
1383     clear_const(current,rt1[i]);
1384     dirty_reg(current,rt1[i]);
1385   }
1386 }
1387
1388 void alu_alloc(struct regstat *current,int i)
1389 {
1390   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1391     if(rt1[i]) {
1392       if(rs1[i]&&rs2[i]) {
1393         alloc_reg(current,i,rs1[i]);
1394         alloc_reg(current,i,rs2[i]);
1395       }
1396       else {
1397         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1398         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1399       }
1400       alloc_reg(current,i,rt1[i]);
1401     }
1402     current->is32|=1LL<<rt1[i];
1403   }
1404   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1405     if(rt1[i]) {
1406       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1407       {
1408         alloc_reg64(current,i,rs1[i]);
1409         alloc_reg64(current,i,rs2[i]);
1410         alloc_reg(current,i,rt1[i]);
1411       } else {
1412         alloc_reg(current,i,rs1[i]);
1413         alloc_reg(current,i,rs2[i]);
1414         alloc_reg(current,i,rt1[i]);
1415       }
1416     }
1417     current->is32|=1LL<<rt1[i];
1418   }
1419   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1420     if(rt1[i]) {
1421       if(rs1[i]&&rs2[i]) {
1422         alloc_reg(current,i,rs1[i]);
1423         alloc_reg(current,i,rs2[i]);
1424       }
1425       else
1426       {
1427         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1428         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1429       }
1430       alloc_reg(current,i,rt1[i]);
1431       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1432       {
1433         if(!((current->uu>>rt1[i])&1)) {
1434           alloc_reg64(current,i,rt1[i]);
1435         }
1436         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1437           if(rs1[i]&&rs2[i]) {
1438             alloc_reg64(current,i,rs1[i]);
1439             alloc_reg64(current,i,rs2[i]);
1440           }
1441           else
1442           {
1443             // Is is really worth it to keep 64-bit values in registers?
1444             #ifdef NATIVE_64BIT
1445             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1446             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1447             #endif
1448           }
1449         }
1450         current->is32&=~(1LL<<rt1[i]);
1451       } else {
1452         current->is32|=1LL<<rt1[i];
1453       }
1454     }
1455   }
1456   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1457     if(rt1[i]) {
1458       if(rs1[i]&&rs2[i]) {
1459         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1460           alloc_reg64(current,i,rs1[i]);
1461           alloc_reg64(current,i,rs2[i]);
1462           alloc_reg64(current,i,rt1[i]);
1463         } else {
1464           alloc_reg(current,i,rs1[i]);
1465           alloc_reg(current,i,rs2[i]);
1466           alloc_reg(current,i,rt1[i]);
1467         }
1468       }
1469       else {
1470         alloc_reg(current,i,rt1[i]);
1471         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1472           // DADD used as move, or zeroing
1473           // If we have a 64-bit source, then make the target 64 bits too
1474           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1475             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1476             alloc_reg64(current,i,rt1[i]);
1477           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1478             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1479             alloc_reg64(current,i,rt1[i]);
1480           }
1481           if(opcode2[i]>=0x2e&&rs2[i]) {
1482             // DSUB used as negation - 64-bit result
1483             // If we have a 32-bit register, extend it to 64 bits
1484             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1485             alloc_reg64(current,i,rt1[i]);
1486           }
1487         }
1488       }
1489       if(rs1[i]&&rs2[i]) {
1490         current->is32&=~(1LL<<rt1[i]);
1491       } else if(rs1[i]) {
1492         current->is32&=~(1LL<<rt1[i]);
1493         if((current->is32>>rs1[i])&1)
1494           current->is32|=1LL<<rt1[i];
1495       } else if(rs2[i]) {
1496         current->is32&=~(1LL<<rt1[i]);
1497         if((current->is32>>rs2[i])&1)
1498           current->is32|=1LL<<rt1[i];
1499       } else {
1500         current->is32|=1LL<<rt1[i];
1501       }
1502     }
1503   }
1504   clear_const(current,rs1[i]);
1505   clear_const(current,rs2[i]);
1506   clear_const(current,rt1[i]);
1507   dirty_reg(current,rt1[i]);
1508 }
1509
1510 void imm16_alloc(struct regstat *current,int i)
1511 {
1512   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1513   else lt1[i]=rs1[i];
1514   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1515   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1516     current->is32&=~(1LL<<rt1[i]);
1517     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1518       // TODO: Could preserve the 32-bit flag if the immediate is zero
1519       alloc_reg64(current,i,rt1[i]);
1520       alloc_reg64(current,i,rs1[i]);
1521     }
1522     clear_const(current,rs1[i]);
1523     clear_const(current,rt1[i]);
1524   }
1525   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1526     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1527     current->is32|=1LL<<rt1[i];
1528     clear_const(current,rs1[i]);
1529     clear_const(current,rt1[i]);
1530   }
1531   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1532     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1533       if(rs1[i]!=rt1[i]) {
1534         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1535         alloc_reg64(current,i,rt1[i]);
1536         current->is32&=~(1LL<<rt1[i]);
1537       }
1538     }
1539     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1540     if(is_const(current,rs1[i])) {
1541       int v=get_const(current,rs1[i]);
1542       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1543       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1544       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1545     }
1546     else clear_const(current,rt1[i]);
1547   }
1548   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1549     if(is_const(current,rs1[i])) {
1550       int v=get_const(current,rs1[i]);
1551       set_const(current,rt1[i],v+imm[i]);
1552     }
1553     else clear_const(current,rt1[i]);
1554     current->is32|=1LL<<rt1[i];
1555   }
1556   else {
1557     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1558     current->is32|=1LL<<rt1[i];
1559   }
1560   dirty_reg(current,rt1[i]);
1561 }
1562
1563 void load_alloc(struct regstat *current,int i)
1564 {
1565   clear_const(current,rt1[i]);
1566   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1567   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1568   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1569   if(rt1[i]) {
1570     alloc_reg(current,i,rt1[i]);
1571     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1572     {
1573       current->is32&=~(1LL<<rt1[i]);
1574       alloc_reg64(current,i,rt1[i]);
1575     }
1576     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1577     {
1578       current->is32&=~(1LL<<rt1[i]);
1579       alloc_reg64(current,i,rt1[i]);
1580       alloc_all(current,i);
1581       alloc_reg64(current,i,FTEMP);
1582     }
1583     else current->is32|=1LL<<rt1[i];
1584     dirty_reg(current,rt1[i]);
1585     // If using TLB, need a register for pointer to the mapping table
1586     if(using_tlb) alloc_reg(current,i,TLREG);
1587     // LWL/LWR need a temporary register for the old value
1588     if(opcode[i]==0x22||opcode[i]==0x26)
1589     {
1590       alloc_reg(current,i,FTEMP);
1591       alloc_reg_temp(current,i,-1);
1592     }
1593   }
1594   else
1595   {
1596     // Load to r0 (dummy load)
1597     // but we still need a register to calculate the address
1598     alloc_reg_temp(current,i,-1);
1599   }
1600 }
1601
1602 void store_alloc(struct regstat *current,int i)
1603 {
1604   clear_const(current,rs2[i]);
1605   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1606   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1607   alloc_reg(current,i,rs2[i]);
1608   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1609     alloc_reg64(current,i,rs2[i]);
1610     if(rs2[i]) alloc_reg(current,i,FTEMP);
1611   }
1612   // If using TLB, need a register for pointer to the mapping table
1613   if(using_tlb) alloc_reg(current,i,TLREG);
1614   #if defined(HOST_IMM8)
1615   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1616   else alloc_reg(current,i,INVCP);
1617   #endif
1618   if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1619     alloc_reg(current,i,FTEMP);
1620   }
1621   // We need a temporary register for address generation
1622   alloc_reg_temp(current,i,-1);
1623 }
1624
1625 void c1ls_alloc(struct regstat *current,int i)
1626 {
1627   //clear_const(current,rs1[i]); // FIXME
1628   clear_const(current,rt1[i]);
1629   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1630   alloc_reg(current,i,CSREG); // Status
1631   alloc_reg(current,i,FTEMP);
1632   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1633     alloc_reg64(current,i,FTEMP);
1634   }
1635   // If using TLB, need a register for pointer to the mapping table
1636   if(using_tlb) alloc_reg(current,i,TLREG);
1637   #if defined(HOST_IMM8)
1638   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1639   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1640     alloc_reg(current,i,INVCP);
1641   #endif
1642   // We need a temporary register for address generation
1643   alloc_reg_temp(current,i,-1);
1644 }
1645
1646 #ifndef multdiv_alloc
1647 void multdiv_alloc(struct regstat *current,int i)
1648 {
1649   //  case 0x18: MULT
1650   //  case 0x19: MULTU
1651   //  case 0x1A: DIV
1652   //  case 0x1B: DIVU
1653   //  case 0x1C: DMULT
1654   //  case 0x1D: DMULTU
1655   //  case 0x1E: DDIV
1656   //  case 0x1F: DDIVU
1657   clear_const(current,rs1[i]);
1658   clear_const(current,rs2[i]);
1659   if(rs1[i]&&rs2[i])
1660   {
1661     if((opcode2[i]&4)==0) // 32-bit
1662     {
1663       current->u&=~(1LL<<HIREG);
1664       current->u&=~(1LL<<LOREG);
1665       alloc_reg(current,i,HIREG);
1666       alloc_reg(current,i,LOREG);
1667       alloc_reg(current,i,rs1[i]);
1668       alloc_reg(current,i,rs2[i]);
1669       current->is32|=1LL<<HIREG;
1670       current->is32|=1LL<<LOREG;
1671       dirty_reg(current,HIREG);
1672       dirty_reg(current,LOREG);
1673     }
1674     else // 64-bit
1675     {
1676       current->u&=~(1LL<<HIREG);
1677       current->u&=~(1LL<<LOREG);
1678       current->uu&=~(1LL<<HIREG);
1679       current->uu&=~(1LL<<LOREG);
1680       alloc_reg64(current,i,HIREG);
1681       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1682       alloc_reg64(current,i,rs1[i]);
1683       alloc_reg64(current,i,rs2[i]);
1684       alloc_all(current,i);
1685       current->is32&=~(1LL<<HIREG);
1686       current->is32&=~(1LL<<LOREG);
1687       dirty_reg(current,HIREG);
1688       dirty_reg(current,LOREG);
1689     }
1690   }
1691   else
1692   {
1693     // Multiply by zero is zero.
1694     // MIPS does not have a divide by zero exception.
1695     // The result is undefined, we return zero.
1696     alloc_reg(current,i,HIREG);
1697     alloc_reg(current,i,LOREG);
1698     current->is32|=1LL<<HIREG;
1699     current->is32|=1LL<<LOREG;
1700     dirty_reg(current,HIREG);
1701     dirty_reg(current,LOREG);
1702   }
1703 }
1704 #endif
1705
1706 void cop0_alloc(struct regstat *current,int i)
1707 {
1708   if(opcode2[i]==0) // MFC0
1709   {
1710     if(rt1[i]) {
1711       clear_const(current,rt1[i]);
1712       alloc_all(current,i);
1713       alloc_reg(current,i,rt1[i]);
1714       current->is32|=1LL<<rt1[i];
1715       dirty_reg(current,rt1[i]);
1716     }
1717   }
1718   else if(opcode2[i]==4) // MTC0
1719   {
1720     if(rs1[i]){
1721       clear_const(current,rs1[i]);
1722       alloc_reg(current,i,rs1[i]);
1723       alloc_all(current,i);
1724     }
1725     else {
1726       alloc_all(current,i); // FIXME: Keep r0
1727       current->u&=~1LL;
1728       alloc_reg(current,i,0);
1729     }
1730   }
1731   else
1732   {
1733     // TLBR/TLBWI/TLBWR/TLBP/ERET
1734     assert(opcode2[i]==0x10);
1735     alloc_all(current,i);
1736   }
1737 }
1738
1739 void cop1_alloc(struct regstat *current,int i)
1740 {
1741   alloc_reg(current,i,CSREG); // Load status
1742   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1743   {
1744     assert(rt1[i]);
1745     clear_const(current,rt1[i]);
1746     if(opcode2[i]==1) {
1747       alloc_reg64(current,i,rt1[i]); // DMFC1
1748       current->is32&=~(1LL<<rt1[i]);
1749     }else{
1750       alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1751       current->is32|=1LL<<rt1[i];
1752     }
1753     dirty_reg(current,rt1[i]);
1754     alloc_reg_temp(current,i,-1);
1755   }
1756   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1757   {
1758     if(rs1[i]){
1759       clear_const(current,rs1[i]);
1760       if(opcode2[i]==5)
1761         alloc_reg64(current,i,rs1[i]); // DMTC1
1762       else
1763         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1764       alloc_reg_temp(current,i,-1);
1765     }
1766     else {
1767       current->u&=~1LL;
1768       alloc_reg(current,i,0);
1769       alloc_reg_temp(current,i,-1);
1770     }
1771   }
1772 }
1773 void fconv_alloc(struct regstat *current,int i)
1774 {
1775   alloc_reg(current,i,CSREG); // Load status
1776   alloc_reg_temp(current,i,-1);
1777 }
1778 void float_alloc(struct regstat *current,int i)
1779 {
1780   alloc_reg(current,i,CSREG); // Load status
1781   alloc_reg_temp(current,i,-1);
1782 }
1783 void fcomp_alloc(struct regstat *current,int i)
1784 {
1785   alloc_reg(current,i,CSREG); // Load status
1786   alloc_reg(current,i,FSREG); // Load flags
1787   dirty_reg(current,FSREG); // Flag will be modified
1788   alloc_reg_temp(current,i,-1);
1789 }
1790
1791 void syscall_alloc(struct regstat *current,int i)
1792 {
1793   alloc_cc(current,i);
1794   dirty_reg(current,CCREG);
1795   alloc_all(current,i);
1796   current->isconst=0;
1797 }
1798
1799 void delayslot_alloc(struct regstat *current,int i)
1800 {
1801   switch(itype[i]) {
1802     case UJUMP:
1803     case CJUMP:
1804     case SJUMP:
1805     case RJUMP:
1806     case FJUMP:
1807     case SYSCALL:
1808     case SPAN:
1809       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1810       printf("Disabled speculative precompilation\n");
1811       stop_after_jal=1;
1812       break;
1813     case IMM16:
1814       imm16_alloc(current,i);
1815       break;
1816     case LOAD:
1817     case LOADLR:
1818       load_alloc(current,i);
1819       break;
1820     case STORE:
1821     case STORELR:
1822       store_alloc(current,i);
1823       break;
1824     case ALU:
1825       alu_alloc(current,i);
1826       break;
1827     case SHIFT:
1828       shift_alloc(current,i);
1829       break;
1830     case MULTDIV:
1831       multdiv_alloc(current,i);
1832       break;
1833     case SHIFTIMM:
1834       shiftimm_alloc(current,i);
1835       break;
1836     case MOV:
1837       mov_alloc(current,i);
1838       break;
1839     case COP0:
1840       cop0_alloc(current,i);
1841       break;
1842     case COP1:
1843       cop1_alloc(current,i);
1844       break;
1845     case C1LS:
1846       c1ls_alloc(current,i);
1847       break;
1848     case FCONV:
1849       fconv_alloc(current,i);
1850       break;
1851     case FLOAT:
1852       float_alloc(current,i);
1853       break;
1854     case FCOMP:
1855       fcomp_alloc(current,i);
1856       break;
1857   }
1858 }
1859
1860 // Special case where a branch and delay slot span two pages in virtual memory
1861 static void pagespan_alloc(struct regstat *current,int i)
1862 {
1863   current->isconst=0;
1864   current->wasconst=0;
1865   regs[i].wasconst=0;
1866   alloc_all(current,i);
1867   alloc_cc(current,i);
1868   dirty_reg(current,CCREG);
1869   if(opcode[i]==3) // JAL
1870   {
1871     alloc_reg(current,i,31);
1872     dirty_reg(current,31);
1873   }
1874   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1875   {
1876     alloc_reg(current,i,rs1[i]);
1877     if (rt1[i]==31) {
1878       alloc_reg(current,i,31);
1879       dirty_reg(current,31);
1880     }
1881   }
1882   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1883   {
1884     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1885     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1886     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1887     {
1888       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1889       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1890     }
1891   }
1892   else
1893   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1894   {
1895     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1896     if(!((current->is32>>rs1[i])&1))
1897     {
1898       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1899     }
1900   }
1901   else
1902   if(opcode[i]==0x11) // BC1
1903   {
1904     alloc_reg(current,i,FSREG);
1905     alloc_reg(current,i,CSREG);
1906   }
1907   //else ...
1908 }
1909
1910 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1911 {
1912   stubs[stubcount][0]=type;
1913   stubs[stubcount][1]=addr;
1914   stubs[stubcount][2]=retaddr;
1915   stubs[stubcount][3]=a;
1916   stubs[stubcount][4]=b;
1917   stubs[stubcount][5]=c;
1918   stubs[stubcount][6]=d;
1919   stubs[stubcount][7]=e;
1920   stubcount++;
1921 }
1922
1923 // Write out a single register
1924 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1925 {
1926   int hr;
1927   for(hr=0;hr<HOST_REGS;hr++) {
1928     if(hr!=EXCLUDE_REG) {
1929       if((regmap[hr]&63)==r) {
1930         if((dirty>>hr)&1) {
1931           if(regmap[hr]<64) {
1932             emit_storereg(r,hr);
1933 #ifndef FORCE32
1934             if((is32>>regmap[hr])&1) {
1935               emit_sarimm(hr,31,hr);
1936               emit_storereg(r|64,hr);
1937             }
1938 #endif
1939           }else{
1940             emit_storereg(r|64,hr);
1941           }
1942         }
1943       }
1944     }
1945   }
1946 }
1947
1948 int mchecksum()
1949 {
1950   //if(!tracedebug) return 0;
1951   int i;
1952   int sum=0;
1953   for(i=0;i<2097152;i++) {
1954     unsigned int temp=sum;
1955     sum<<=1;
1956     sum|=(~temp)>>31;
1957     sum^=((u_int *)rdram)[i];
1958   }
1959   return sum;
1960 }
1961 int rchecksum()
1962 {
1963   int i;
1964   int sum=0;
1965   for(i=0;i<64;i++)
1966     sum^=((u_int *)reg)[i];
1967   return sum;
1968 }
1969 void rlist()
1970 {
1971   int i;
1972   printf("TRACE: ");
1973   for(i=0;i<32;i++)
1974     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1975   printf("\n");
1976 #ifndef DISABLE_COP1
1977   printf("TRACE: ");
1978   for(i=0;i<32;i++)
1979     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
1980   printf("\n");
1981 #endif
1982 }
1983
1984 void enabletrace()
1985 {
1986   tracedebug=1;
1987 }
1988
1989 void memdebug(int i)
1990 {
1991   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
1992   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
1993   //rlist();
1994   //if(tracedebug) {
1995   //if(Count>=-2084597794) {
1996   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
1997   //if(0) {
1998     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
1999     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2000     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2001     rlist();
2002     #ifdef __i386__
2003     printf("TRACE: %x\n",(&i)[-1]);
2004     #endif
2005     #ifdef __arm__
2006     int j;
2007     printf("TRACE: %x \n",(&j)[10]);
2008     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2009     #endif
2010     //fflush(stdout);
2011   }
2012   //printf("TRACE: %x\n",(&i)[-1]);
2013 }
2014
2015 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2016 {
2017   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2018 }
2019
2020 void alu_assemble(int i,struct regstat *i_regs)
2021 {
2022   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2023     if(rt1[i]) {
2024       signed char s1,s2,t;
2025       t=get_reg(i_regs->regmap,rt1[i]);
2026       if(t>=0) {
2027         s1=get_reg(i_regs->regmap,rs1[i]);
2028         s2=get_reg(i_regs->regmap,rs2[i]);
2029         if(rs1[i]&&rs2[i]) {
2030           assert(s1>=0);
2031           assert(s2>=0);
2032           if(opcode2[i]&2) emit_sub(s1,s2,t);
2033           else emit_add(s1,s2,t);
2034         }
2035         else if(rs1[i]) {
2036           if(s1>=0) emit_mov(s1,t);
2037           else emit_loadreg(rs1[i],t);
2038         }
2039         else if(rs2[i]) {
2040           if(s2>=0) {
2041             if(opcode2[i]&2) emit_neg(s2,t);
2042             else emit_mov(s2,t);
2043           }
2044           else {
2045             emit_loadreg(rs2[i],t);
2046             if(opcode2[i]&2) emit_neg(t,t);
2047           }
2048         }
2049         else emit_zeroreg(t);
2050       }
2051     }
2052   }
2053   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2054     if(rt1[i]) {
2055       signed char s1l,s2l,s1h,s2h,tl,th;
2056       tl=get_reg(i_regs->regmap,rt1[i]);
2057       th=get_reg(i_regs->regmap,rt1[i]|64);
2058       if(tl>=0) {
2059         s1l=get_reg(i_regs->regmap,rs1[i]);
2060         s2l=get_reg(i_regs->regmap,rs2[i]);
2061         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2062         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2063         if(rs1[i]&&rs2[i]) {
2064           assert(s1l>=0);
2065           assert(s2l>=0);
2066           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2067           else emit_adds(s1l,s2l,tl);
2068           if(th>=0) {
2069             #ifdef INVERTED_CARRY
2070             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2071             #else
2072             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2073             #endif
2074             else emit_add(s1h,s2h,th);
2075           }
2076         }
2077         else if(rs1[i]) {
2078           if(s1l>=0) emit_mov(s1l,tl);
2079           else emit_loadreg(rs1[i],tl);
2080           if(th>=0) {
2081             if(s1h>=0) emit_mov(s1h,th);
2082             else emit_loadreg(rs1[i]|64,th);
2083           }
2084         }
2085         else if(rs2[i]) {
2086           if(s2l>=0) {
2087             if(opcode2[i]&2) emit_negs(s2l,tl);
2088             else emit_mov(s2l,tl);
2089           }
2090           else {
2091             emit_loadreg(rs2[i],tl);
2092             if(opcode2[i]&2) emit_negs(tl,tl);
2093           }
2094           if(th>=0) {
2095             #ifdef INVERTED_CARRY
2096             if(s2h>=0) emit_mov(s2h,th);
2097             else emit_loadreg(rs2[i]|64,th);
2098             if(opcode2[i]&2) {
2099               emit_adcimm(-1,th); // x86 has inverted carry flag
2100               emit_not(th,th);
2101             }
2102             #else
2103             if(opcode2[i]&2) {
2104               if(s2h>=0) emit_rscimm(s2h,0,th);
2105               else {
2106                 emit_loadreg(rs2[i]|64,th);
2107                 emit_rscimm(th,0,th);
2108               }
2109             }else{
2110               if(s2h>=0) emit_mov(s2h,th);
2111               else emit_loadreg(rs2[i]|64,th);
2112             }
2113             #endif
2114           }
2115         }
2116         else {
2117           emit_zeroreg(tl);
2118           if(th>=0) emit_zeroreg(th);
2119         }
2120       }
2121     }
2122   }
2123   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2124     if(rt1[i]) {
2125       signed char s1l,s1h,s2l,s2h,t;
2126       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2127       {
2128         t=get_reg(i_regs->regmap,rt1[i]);
2129         //assert(t>=0);
2130         if(t>=0) {
2131           s1l=get_reg(i_regs->regmap,rs1[i]);
2132           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2133           s2l=get_reg(i_regs->regmap,rs2[i]);
2134           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2135           if(rs2[i]==0) // rx<r0
2136           {
2137             assert(s1h>=0);
2138             if(opcode2[i]==0x2a) // SLT
2139               emit_shrimm(s1h,31,t);
2140             else // SLTU (unsigned can not be less than zero)
2141               emit_zeroreg(t);
2142           }
2143           else if(rs1[i]==0) // r0<rx
2144           {
2145             assert(s2h>=0);
2146             if(opcode2[i]==0x2a) // SLT
2147               emit_set_gz64_32(s2h,s2l,t);
2148             else // SLTU (set if not zero)
2149               emit_set_nz64_32(s2h,s2l,t);
2150           }
2151           else {
2152             assert(s1l>=0);assert(s1h>=0);
2153             assert(s2l>=0);assert(s2h>=0);
2154             if(opcode2[i]==0x2a) // SLT
2155               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2156             else // SLTU
2157               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2158           }
2159         }
2160       } else {
2161         t=get_reg(i_regs->regmap,rt1[i]);
2162         //assert(t>=0);
2163         if(t>=0) {
2164           s1l=get_reg(i_regs->regmap,rs1[i]);
2165           s2l=get_reg(i_regs->regmap,rs2[i]);
2166           if(rs2[i]==0) // rx<r0
2167           {
2168             assert(s1l>=0);
2169             if(opcode2[i]==0x2a) // SLT
2170               emit_shrimm(s1l,31,t);
2171             else // SLTU (unsigned can not be less than zero)
2172               emit_zeroreg(t);
2173           }
2174           else if(rs1[i]==0) // r0<rx
2175           {
2176             assert(s2l>=0);
2177             if(opcode2[i]==0x2a) // SLT
2178               emit_set_gz32(s2l,t);
2179             else // SLTU (set if not zero)
2180               emit_set_nz32(s2l,t);
2181           }
2182           else{
2183             assert(s1l>=0);assert(s2l>=0);
2184             if(opcode2[i]==0x2a) // SLT
2185               emit_set_if_less32(s1l,s2l,t);
2186             else // SLTU
2187               emit_set_if_carry32(s1l,s2l,t);
2188           }
2189         }
2190       }
2191     }
2192   }
2193   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2194     if(rt1[i]) {
2195       signed char s1l,s1h,s2l,s2h,th,tl;
2196       tl=get_reg(i_regs->regmap,rt1[i]);
2197       th=get_reg(i_regs->regmap,rt1[i]|64);
2198       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2199       {
2200         assert(tl>=0);
2201         if(tl>=0) {
2202           s1l=get_reg(i_regs->regmap,rs1[i]);
2203           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2204           s2l=get_reg(i_regs->regmap,rs2[i]);
2205           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2206           if(rs1[i]&&rs2[i]) {
2207             assert(s1l>=0);assert(s1h>=0);
2208             assert(s2l>=0);assert(s2h>=0);
2209             if(opcode2[i]==0x24) { // AND
2210               emit_and(s1l,s2l,tl);
2211               emit_and(s1h,s2h,th);
2212             } else
2213             if(opcode2[i]==0x25) { // OR
2214               emit_or(s1l,s2l,tl);
2215               emit_or(s1h,s2h,th);
2216             } else
2217             if(opcode2[i]==0x26) { // XOR
2218               emit_xor(s1l,s2l,tl);
2219               emit_xor(s1h,s2h,th);
2220             } else
2221             if(opcode2[i]==0x27) { // NOR
2222               emit_or(s1l,s2l,tl);
2223               emit_or(s1h,s2h,th);
2224               emit_not(tl,tl);
2225               emit_not(th,th);
2226             }
2227           }
2228           else
2229           {
2230             if(opcode2[i]==0x24) { // AND
2231               emit_zeroreg(tl);
2232               emit_zeroreg(th);
2233             } else
2234             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2235               if(rs1[i]){
2236                 if(s1l>=0) emit_mov(s1l,tl);
2237                 else emit_loadreg(rs1[i],tl);
2238                 if(s1h>=0) emit_mov(s1h,th);
2239                 else emit_loadreg(rs1[i]|64,th);
2240               }
2241               else
2242               if(rs2[i]){
2243                 if(s2l>=0) emit_mov(s2l,tl);
2244                 else emit_loadreg(rs2[i],tl);
2245                 if(s2h>=0) emit_mov(s2h,th);
2246                 else emit_loadreg(rs2[i]|64,th);
2247               }
2248               else{
2249                 emit_zeroreg(tl);
2250                 emit_zeroreg(th);
2251               }
2252             } else
2253             if(opcode2[i]==0x27) { // NOR
2254               if(rs1[i]){
2255                 if(s1l>=0) emit_not(s1l,tl);
2256                 else{
2257                   emit_loadreg(rs1[i],tl);
2258                   emit_not(tl,tl);
2259                 }
2260                 if(s1h>=0) emit_not(s1h,th);
2261                 else{
2262                   emit_loadreg(rs1[i]|64,th);
2263                   emit_not(th,th);
2264                 }
2265               }
2266               else
2267               if(rs2[i]){
2268                 if(s2l>=0) emit_not(s2l,tl);
2269                 else{
2270                   emit_loadreg(rs2[i],tl);
2271                   emit_not(tl,tl);
2272                 }
2273                 if(s2h>=0) emit_not(s2h,th);
2274                 else{
2275                   emit_loadreg(rs2[i]|64,th);
2276                   emit_not(th,th);
2277                 }
2278               }
2279               else {
2280                 emit_movimm(-1,tl);
2281                 emit_movimm(-1,th);
2282               }
2283             }
2284           }
2285         }
2286       }
2287       else
2288       {
2289         // 32 bit
2290         if(tl>=0) {
2291           s1l=get_reg(i_regs->regmap,rs1[i]);
2292           s2l=get_reg(i_regs->regmap,rs2[i]);
2293           if(rs1[i]&&rs2[i]) {
2294             assert(s1l>=0);
2295             assert(s2l>=0);
2296             if(opcode2[i]==0x24) { // AND
2297               emit_and(s1l,s2l,tl);
2298             } else
2299             if(opcode2[i]==0x25) { // OR
2300               emit_or(s1l,s2l,tl);
2301             } else
2302             if(opcode2[i]==0x26) { // XOR
2303               emit_xor(s1l,s2l,tl);
2304             } else
2305             if(opcode2[i]==0x27) { // NOR
2306               emit_or(s1l,s2l,tl);
2307               emit_not(tl,tl);
2308             }
2309           }
2310           else
2311           {
2312             if(opcode2[i]==0x24) { // AND
2313               emit_zeroreg(tl);
2314             } else
2315             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2316               if(rs1[i]){
2317                 if(s1l>=0) emit_mov(s1l,tl);
2318                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2319               }
2320               else
2321               if(rs2[i]){
2322                 if(s2l>=0) emit_mov(s2l,tl);
2323                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2324               }
2325               else emit_zeroreg(tl);
2326             } else
2327             if(opcode2[i]==0x27) { // NOR
2328               if(rs1[i]){
2329                 if(s1l>=0) emit_not(s1l,tl);
2330                 else {
2331                   emit_loadreg(rs1[i],tl);
2332                   emit_not(tl,tl);
2333                 }
2334               }
2335               else
2336               if(rs2[i]){
2337                 if(s2l>=0) emit_not(s2l,tl);
2338                 else {
2339                   emit_loadreg(rs2[i],tl);
2340                   emit_not(tl,tl);
2341                 }
2342               }
2343               else emit_movimm(-1,tl);
2344             }
2345           }
2346         }
2347       }
2348     }
2349   }
2350 }
2351
2352 void imm16_assemble(int i,struct regstat *i_regs)
2353 {
2354   if (opcode[i]==0x0f) { // LUI
2355     if(rt1[i]) {
2356       signed char t;
2357       t=get_reg(i_regs->regmap,rt1[i]);
2358       //assert(t>=0);
2359       if(t>=0) {
2360         if(!((i_regs->isconst>>t)&1))
2361           emit_movimm(imm[i]<<16,t);
2362       }
2363     }
2364   }
2365   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2366     if(rt1[i]) {
2367       signed char s,t;
2368       t=get_reg(i_regs->regmap,rt1[i]);
2369       s=get_reg(i_regs->regmap,rs1[i]);
2370       if(rs1[i]) {
2371         //assert(t>=0);
2372         //assert(s>=0);
2373         if(t>=0) {
2374           if(!((i_regs->isconst>>t)&1)) {
2375             if(s<0) {
2376               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2377               emit_addimm(t,imm[i],t);
2378             }else{
2379               if(!((i_regs->wasconst>>s)&1))
2380                 emit_addimm(s,imm[i],t);
2381               else
2382                 emit_movimm(constmap[i][s]+imm[i],t);
2383             }
2384           }
2385         }
2386       } else {
2387         if(t>=0) {
2388           if(!((i_regs->isconst>>t)&1))
2389             emit_movimm(imm[i],t);
2390         }
2391       }
2392     }
2393   }
2394   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2395     if(rt1[i]) {
2396       signed char sh,sl,th,tl;
2397       th=get_reg(i_regs->regmap,rt1[i]|64);
2398       tl=get_reg(i_regs->regmap,rt1[i]);
2399       sh=get_reg(i_regs->regmap,rs1[i]|64);
2400       sl=get_reg(i_regs->regmap,rs1[i]);
2401       if(tl>=0) {
2402         if(rs1[i]) {
2403           assert(sh>=0);
2404           assert(sl>=0);
2405           if(th>=0) {
2406             emit_addimm64_32(sh,sl,imm[i],th,tl);
2407           }
2408           else {
2409             emit_addimm(sl,imm[i],tl);
2410           }
2411         } else {
2412           emit_movimm(imm[i],tl);
2413           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2414         }
2415       }
2416     }
2417   }
2418   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2419     if(rt1[i]) {
2420       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2421       signed char sh,sl,t;
2422       t=get_reg(i_regs->regmap,rt1[i]);
2423       sh=get_reg(i_regs->regmap,rs1[i]|64);
2424       sl=get_reg(i_regs->regmap,rs1[i]);
2425       //assert(t>=0);
2426       if(t>=0) {
2427         if(rs1[i]>0) {
2428           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2429           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2430             if(opcode[i]==0x0a) { // SLTI
2431               if(sl<0) {
2432                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2433                 emit_slti32(t,imm[i],t);
2434               }else{
2435                 emit_slti32(sl,imm[i],t);
2436               }
2437             }
2438             else { // SLTIU
2439               if(sl<0) {
2440                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2441                 emit_sltiu32(t,imm[i],t);
2442               }else{
2443                 emit_sltiu32(sl,imm[i],t);
2444               }
2445             }
2446           }else{ // 64-bit
2447             assert(sl>=0);
2448             if(opcode[i]==0x0a) // SLTI
2449               emit_slti64_32(sh,sl,imm[i],t);
2450             else // SLTIU
2451               emit_sltiu64_32(sh,sl,imm[i],t);
2452           }
2453         }else{
2454           // SLTI(U) with r0 is just stupid,
2455           // nonetheless examples can be found
2456           if(opcode[i]==0x0a) // SLTI
2457             if(0<imm[i]) emit_movimm(1,t);
2458             else emit_zeroreg(t);
2459           else // SLTIU
2460           {
2461             if(imm[i]) emit_movimm(1,t);
2462             else emit_zeroreg(t);
2463           }
2464         }
2465       }
2466     }
2467   }
2468   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2469     if(rt1[i]) {
2470       signed char sh,sl,th,tl;
2471       th=get_reg(i_regs->regmap,rt1[i]|64);
2472       tl=get_reg(i_regs->regmap,rt1[i]);
2473       sh=get_reg(i_regs->regmap,rs1[i]|64);
2474       sl=get_reg(i_regs->regmap,rs1[i]);
2475       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2476         if(opcode[i]==0x0c) //ANDI
2477         {
2478           if(rs1[i]) {
2479             if(sl<0) {
2480               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2481               emit_andimm(tl,imm[i],tl);
2482             }else{
2483               if(!((i_regs->wasconst>>sl)&1))
2484                 emit_andimm(sl,imm[i],tl);
2485               else
2486                 emit_movimm(constmap[i][sl]&imm[i],tl);
2487             }
2488           }
2489           else
2490             emit_zeroreg(tl);
2491           if(th>=0) emit_zeroreg(th);
2492         }
2493         else
2494         {
2495           if(rs1[i]) {
2496             if(sl<0) {
2497               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2498             }
2499             if(th>=0) {
2500               if(sh<0) {
2501                 emit_loadreg(rs1[i]|64,th);
2502               }else{
2503                 emit_mov(sh,th);
2504               }
2505             }
2506             if(opcode[i]==0x0d) //ORI
2507             if(sl<0) {
2508               emit_orimm(tl,imm[i],tl);
2509             }else{
2510               if(!((i_regs->wasconst>>sl)&1))
2511                 emit_orimm(sl,imm[i],tl);
2512               else
2513                 emit_movimm(constmap[i][sl]|imm[i],tl);
2514             }
2515             if(opcode[i]==0x0e) //XORI
2516             if(sl<0) {
2517               emit_xorimm(tl,imm[i],tl);
2518             }else{
2519               if(!((i_regs->wasconst>>sl)&1))
2520                 emit_xorimm(sl,imm[i],tl);
2521               else
2522                 emit_movimm(constmap[i][sl]^imm[i],tl);
2523             }
2524           }
2525           else {
2526             emit_movimm(imm[i],tl);
2527             if(th>=0) emit_zeroreg(th);
2528           }
2529         }
2530       }
2531     }
2532   }
2533 }
2534
2535 void shiftimm_assemble(int i,struct regstat *i_regs)
2536 {
2537   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2538   {
2539     if(rt1[i]) {
2540       signed char s,t;
2541       t=get_reg(i_regs->regmap,rt1[i]);
2542       s=get_reg(i_regs->regmap,rs1[i]);
2543       //assert(t>=0);
2544       if(t>=0){
2545         if(rs1[i]==0)
2546         {
2547           emit_zeroreg(t);
2548         }
2549         else
2550         {
2551           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2552           if(imm[i]) {
2553             if(opcode2[i]==0) // SLL
2554             {
2555               emit_shlimm(s<0?t:s,imm[i],t);
2556             }
2557             if(opcode2[i]==2) // SRL
2558             {
2559               emit_shrimm(s<0?t:s,imm[i],t);
2560             }
2561             if(opcode2[i]==3) // SRA
2562             {
2563               emit_sarimm(s<0?t:s,imm[i],t);
2564             }
2565           }else{
2566             // Shift by zero
2567             if(s>=0 && s!=t) emit_mov(s,t);
2568           }
2569         }
2570       }
2571       //emit_storereg(rt1[i],t); //DEBUG
2572     }
2573   }
2574   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2575   {
2576     if(rt1[i]) {
2577       signed char sh,sl,th,tl;
2578       th=get_reg(i_regs->regmap,rt1[i]|64);
2579       tl=get_reg(i_regs->regmap,rt1[i]);
2580       sh=get_reg(i_regs->regmap,rs1[i]|64);
2581       sl=get_reg(i_regs->regmap,rs1[i]);
2582       if(tl>=0) {
2583         if(rs1[i]==0)
2584         {
2585           emit_zeroreg(tl);
2586           if(th>=0) emit_zeroreg(th);
2587         }
2588         else
2589         {
2590           assert(sl>=0);
2591           assert(sh>=0);
2592           if(imm[i]) {
2593             if(opcode2[i]==0x38) // DSLL
2594             {
2595               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2596               emit_shlimm(sl,imm[i],tl);
2597             }
2598             if(opcode2[i]==0x3a) // DSRL
2599             {
2600               emit_shrdimm(sl,sh,imm[i],tl);
2601               if(th>=0) emit_shrimm(sh,imm[i],th);
2602             }
2603             if(opcode2[i]==0x3b) // DSRA
2604             {
2605               emit_shrdimm(sl,sh,imm[i],tl);
2606               if(th>=0) emit_sarimm(sh,imm[i],th);
2607             }
2608           }else{
2609             // Shift by zero
2610             if(sl!=tl) emit_mov(sl,tl);
2611             if(th>=0&&sh!=th) emit_mov(sh,th);
2612           }
2613         }
2614       }
2615     }
2616   }
2617   if(opcode2[i]==0x3c) // DSLL32
2618   {
2619     if(rt1[i]) {
2620       signed char sl,tl,th;
2621       tl=get_reg(i_regs->regmap,rt1[i]);
2622       th=get_reg(i_regs->regmap,rt1[i]|64);
2623       sl=get_reg(i_regs->regmap,rs1[i]);
2624       if(th>=0||tl>=0){
2625         assert(tl>=0);
2626         assert(th>=0);
2627         assert(sl>=0);
2628         emit_mov(sl,th);
2629         emit_zeroreg(tl);
2630         if(imm[i]>32)
2631         {
2632           emit_shlimm(th,imm[i]&31,th);
2633         }
2634       }
2635     }
2636   }
2637   if(opcode2[i]==0x3e) // DSRL32
2638   {
2639     if(rt1[i]) {
2640       signed char sh,tl,th;
2641       tl=get_reg(i_regs->regmap,rt1[i]);
2642       th=get_reg(i_regs->regmap,rt1[i]|64);
2643       sh=get_reg(i_regs->regmap,rs1[i]|64);
2644       if(tl>=0){
2645         assert(sh>=0);
2646         emit_mov(sh,tl);
2647         if(th>=0) emit_zeroreg(th);
2648         if(imm[i]>32)
2649         {
2650           emit_shrimm(tl,imm[i]&31,tl);
2651         }
2652       }
2653     }
2654   }
2655   if(opcode2[i]==0x3f) // DSRA32
2656   {
2657     if(rt1[i]) {
2658       signed char sh,tl;
2659       tl=get_reg(i_regs->regmap,rt1[i]);
2660       sh=get_reg(i_regs->regmap,rs1[i]|64);
2661       if(tl>=0){
2662         assert(sh>=0);
2663         emit_mov(sh,tl);
2664         if(imm[i]>32)
2665         {
2666           emit_sarimm(tl,imm[i]&31,tl);
2667         }
2668       }
2669     }
2670   }
2671 }
2672
2673 #ifndef shift_assemble
2674 void shift_assemble(int i,struct regstat *i_regs)
2675 {
2676   printf("Need shift_assemble for this architecture.\n");
2677   exit(1);
2678 }
2679 #endif
2680
2681 void load_assemble(int i,struct regstat *i_regs)
2682 {
2683   int s,th,tl,addr,map=-1;
2684   int offset;
2685   int jaddr=0;
2686   int memtarget,c=0;
2687   u_int hr,reglist=0;
2688   th=get_reg(i_regs->regmap,rt1[i]|64);
2689   tl=get_reg(i_regs->regmap,rt1[i]);
2690   s=get_reg(i_regs->regmap,rs1[i]);
2691   offset=imm[i];
2692   for(hr=0;hr<HOST_REGS;hr++) {
2693     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2694   }
2695   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2696   if(s>=0) {
2697     c=(i_regs->wasconst>>s)&1;
2698     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2699     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2700   }
2701   if(offset||s<0||c) addr=tl;
2702   else addr=s;
2703   //printf("load_assemble: c=%d\n",c);
2704   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2705   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2706   if(tl>=0) {
2707     //assert(tl>=0);
2708     //assert(rt1[i]);
2709     reglist&=~(1<<tl);
2710     if(th>=0) reglist&=~(1<<th);
2711     if(!using_tlb) {
2712       if(!c) {
2713 //#define R29_HACK 1
2714         #ifdef R29_HACK
2715         // Strmnnrmn's speed hack
2716         if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2717         #endif
2718         {
2719           emit_cmpimm(addr,0x800000);
2720           jaddr=(int)out;
2721           #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2722           // Hint to branch predictor that the branch is unlikely to be taken
2723           if(rs1[i]>=28)
2724             emit_jno_unlikely(0);
2725           else
2726           #endif
2727           emit_jno(0);
2728         }
2729       }
2730     }else{ // using tlb
2731       int x=0;
2732       if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2733       if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2734       map=get_reg(i_regs->regmap,TLREG);
2735       assert(map>=0);
2736       map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2737       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2738     }
2739     if (opcode[i]==0x20) { // LB
2740       if(!c||memtarget) {
2741         #ifdef HOST_IMM_ADDR32
2742         if(c)
2743           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2744         else
2745         #endif
2746         {
2747           //emit_xorimm(addr,3,tl);
2748           //gen_tlb_addr_r(tl,map);
2749           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2750           int x=0;
2751           if(!c) emit_xorimm(addr,3,tl);
2752           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2753           emit_movsbl_indexed_tlb(x,tl,map,tl);
2754         }
2755         if(jaddr)
2756           add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2757       }
2758       else
2759         inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2760     }
2761     if (opcode[i]==0x21) { // LH
2762       if(!c||memtarget) {
2763         #ifdef HOST_IMM_ADDR32
2764         if(c)
2765           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2766         else
2767         #endif
2768         {
2769           int x=0;
2770           if(!c) emit_xorimm(addr,2,tl);
2771           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2772           //#ifdef
2773           //emit_movswl_indexed_tlb(x,tl,map,tl);
2774           //else
2775           if(map>=0) {
2776             gen_tlb_addr_r(tl,map);
2777             emit_movswl_indexed(x,tl,tl);
2778           }else
2779             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2780         }
2781         if(jaddr)
2782           add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2783       }
2784       else
2785         inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2786     }
2787     if (opcode[i]==0x23) { // LW
2788       if(!c||memtarget) {
2789         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2790         #ifdef HOST_IMM_ADDR32
2791         if(c)
2792           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2793         else
2794         #endif
2795         emit_readword_indexed_tlb(0,addr,map,tl);
2796         if(jaddr)
2797           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2798       }
2799       else
2800         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2801     }
2802     if (opcode[i]==0x24) { // LBU
2803       if(!c||memtarget) {
2804         #ifdef HOST_IMM_ADDR32
2805         if(c)
2806           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2807         else
2808         #endif
2809         {
2810           //emit_xorimm(addr,3,tl);
2811           //gen_tlb_addr_r(tl,map);
2812           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2813           int x=0;
2814           if(!c) emit_xorimm(addr,3,tl);
2815           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2816           emit_movzbl_indexed_tlb(x,tl,map,tl);
2817         }
2818         if(jaddr)
2819           add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2820       }
2821       else
2822         inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2823     }
2824     if (opcode[i]==0x25) { // LHU
2825       if(!c||memtarget) {
2826         #ifdef HOST_IMM_ADDR32
2827         if(c)
2828           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2829         else
2830         #endif
2831         {
2832           int x=0;
2833           if(!c) emit_xorimm(addr,2,tl);
2834           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2835           //#ifdef
2836           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2837           //#else
2838           if(map>=0) {
2839             gen_tlb_addr_r(tl,map);
2840             emit_movzwl_indexed(x,tl,tl);
2841           }else
2842             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2843           if(jaddr)
2844             add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2845         }
2846       }
2847       else
2848         inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2849     }
2850     if (opcode[i]==0x27) { // LWU
2851       assert(th>=0);
2852       if(!c||memtarget) {
2853         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2854         #ifdef HOST_IMM_ADDR32
2855         if(c)
2856           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2857         else
2858         #endif
2859         emit_readword_indexed_tlb(0,addr,map,tl);
2860         if(jaddr)
2861           add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2862       }
2863       else {
2864         inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2865       }
2866       emit_zeroreg(th);
2867     }
2868     if (opcode[i]==0x37) { // LD
2869       if(!c||memtarget) {
2870         //gen_tlb_addr_r(tl,map);
2871         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2872         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2873         #ifdef HOST_IMM_ADDR32
2874         if(c)
2875           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2876         else
2877         #endif
2878         emit_readdword_indexed_tlb(0,addr,map,th,tl);
2879         if(jaddr)
2880           add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2881       }
2882       else
2883         inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2884     }
2885     //emit_storereg(rt1[i],tl); // DEBUG
2886   }
2887   //if(opcode[i]==0x23)
2888   //if(opcode[i]==0x24)
2889   //if(opcode[i]==0x23||opcode[i]==0x24)
2890   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2891   {
2892     //emit_pusha();
2893     save_regs(0x100f);
2894         emit_readword((int)&last_count,ECX);
2895         #ifdef __i386__
2896         if(get_reg(i_regs->regmap,CCREG)<0)
2897           emit_loadreg(CCREG,HOST_CCREG);
2898         emit_add(HOST_CCREG,ECX,HOST_CCREG);
2899         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2900         emit_writeword(HOST_CCREG,(int)&Count);
2901         #endif
2902         #ifdef __arm__
2903         if(get_reg(i_regs->regmap,CCREG)<0)
2904           emit_loadreg(CCREG,0);
2905         else
2906           emit_mov(HOST_CCREG,0);
2907         emit_add(0,ECX,0);
2908         emit_addimm(0,2*ccadj[i],0);
2909         emit_writeword(0,(int)&Count);
2910         #endif
2911     emit_call((int)memdebug);
2912     //emit_popa();
2913     restore_regs(0x100f);
2914   }/**/
2915 }
2916
2917 #ifndef loadlr_assemble
2918 void loadlr_assemble(int i,struct regstat *i_regs)
2919 {
2920   printf("Need loadlr_assemble for this architecture.\n");
2921   exit(1);
2922 }
2923 #endif
2924
2925 void store_assemble(int i,struct regstat *i_regs)
2926 {
2927   int s,th,tl,map=-1;
2928   int addr,temp;
2929   int offset;
2930   int jaddr=0,jaddr2,type;
2931   int memtarget,c=0;
2932   int agr=AGEN1+(i&1);
2933   u_int hr,reglist=0;
2934   th=get_reg(i_regs->regmap,rs2[i]|64);
2935   tl=get_reg(i_regs->regmap,rs2[i]);
2936   s=get_reg(i_regs->regmap,rs1[i]);
2937   temp=get_reg(i_regs->regmap,agr);
2938   if(temp<0) temp=get_reg(i_regs->regmap,-1);
2939   offset=imm[i];
2940   if(s>=0) {
2941     c=(i_regs->wasconst>>s)&1;
2942     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2943     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2944   }
2945   assert(tl>=0);
2946   assert(temp>=0);
2947   for(hr=0;hr<HOST_REGS;hr++) {
2948     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2949   }
2950   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2951   if(offset||s<0||c) addr=temp;
2952   else addr=s;
2953   if(!using_tlb) {
2954     if(!c) {
2955       #ifdef R29_HACK
2956       // Strmnnrmn's speed hack
2957       memtarget=1;
2958       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2959       #endif
2960       emit_cmpimm(addr,0x800000);
2961       #ifdef DESTRUCTIVE_SHIFT
2962       if(s==addr) emit_mov(s,temp);
2963       #endif
2964       #ifdef R29_HACK
2965       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2966       #endif
2967       {
2968         jaddr=(int)out;
2969         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2970         // Hint to branch predictor that the branch is unlikely to be taken
2971         if(rs1[i]>=28)
2972           emit_jno_unlikely(0);
2973         else
2974         #endif
2975         emit_jno(0);
2976       }
2977     }
2978   }else{ // using tlb
2979     int x=0;
2980     if (opcode[i]==0x28) x=3; // SB
2981     if (opcode[i]==0x29) x=2; // SH
2982     map=get_reg(i_regs->regmap,TLREG);
2983     assert(map>=0);
2984     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
2985     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
2986   }
2987
2988   if (opcode[i]==0x28) { // SB
2989     if(!c||memtarget) {
2990       int x=0;
2991       if(!c) emit_xorimm(addr,3,temp);
2992       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2993       //gen_tlb_addr_w(temp,map);
2994       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
2995       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
2996     }
2997     type=STOREB_STUB;
2998   }
2999   if (opcode[i]==0x29) { // SH
3000     if(!c||memtarget) {
3001       int x=0;
3002       if(!c) emit_xorimm(addr,2,temp);
3003       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3004       //#ifdef
3005       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3006       //#else
3007       if(map>=0) {
3008         gen_tlb_addr_w(temp,map);
3009         emit_writehword_indexed(tl,x,temp);
3010       }else
3011         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3012     }
3013     type=STOREH_STUB;
3014   }
3015   if (opcode[i]==0x2B) { // SW
3016     if(!c||memtarget)
3017       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3018       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3019     type=STOREW_STUB;
3020   }
3021   if (opcode[i]==0x3F) { // SD
3022     if(!c||memtarget) {
3023       if(rs2[i]) {
3024         assert(th>=0);
3025         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3026         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3027         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3028       }else{
3029         // Store zero
3030         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3031         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3032         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3033       }
3034     }
3035     type=STORED_STUB;
3036   }
3037   if(jaddr) {
3038     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3039   } else if(!memtarget) {
3040     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3041   }
3042   if(!using_tlb) {
3043     if(!c||memtarget) {
3044       #ifdef DESTRUCTIVE_SHIFT
3045       // The x86 shift operation is 'destructive'; it overwrites the
3046       // source register, so we need to make a copy first and use that.
3047       addr=temp;
3048       #endif
3049       #if defined(HOST_IMM8)
3050       int ir=get_reg(i_regs->regmap,INVCP);
3051       assert(ir>=0);
3052       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3053       #else
3054       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3055       #endif
3056       jaddr2=(int)out;
3057       emit_jne(0);
3058       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3059     }
3060   }
3061   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3062   //if(opcode[i]==0x2B || opcode[i]==0x28)
3063   //if(opcode[i]==0x2B || opcode[i]==0x29)
3064   //if(opcode[i]==0x2B)
3065   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3066   {
3067     //emit_pusha();
3068     save_regs(0x100f);
3069         emit_readword((int)&last_count,ECX);
3070         #ifdef __i386__
3071         if(get_reg(i_regs->regmap,CCREG)<0)
3072           emit_loadreg(CCREG,HOST_CCREG);
3073         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3074         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3075         emit_writeword(HOST_CCREG,(int)&Count);
3076         #endif
3077         #ifdef __arm__
3078         if(get_reg(i_regs->regmap,CCREG)<0)
3079           emit_loadreg(CCREG,0);
3080         else
3081           emit_mov(HOST_CCREG,0);
3082         emit_add(0,ECX,0);
3083         emit_addimm(0,2*ccadj[i],0);
3084         emit_writeword(0,(int)&Count);
3085         #endif
3086     emit_call((int)memdebug);
3087     //emit_popa();
3088     restore_regs(0x100f);
3089   }/**/
3090 }
3091
3092 void storelr_assemble(int i,struct regstat *i_regs)
3093 {
3094   int s,th,tl;
3095   int temp;
3096   int temp2;
3097   int offset;
3098   int jaddr=0,jaddr2;
3099   int case1,case2,case3;
3100   int done0,done1,done2;
3101   int memtarget,c=0;
3102   u_int hr,reglist=0;
3103   th=get_reg(i_regs->regmap,rs2[i]|64);
3104   tl=get_reg(i_regs->regmap,rs2[i]);
3105   s=get_reg(i_regs->regmap,rs1[i]);
3106   temp=get_reg(i_regs->regmap,-1);
3107   offset=imm[i];
3108   if(s>=0) {
3109     c=(i_regs->isconst>>s)&1;
3110     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3111     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3112   }
3113   assert(tl>=0);
3114   for(hr=0;hr<HOST_REGS;hr++) {
3115     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3116   }
3117   if(tl>=0) {
3118     assert(temp>=0);
3119     if(!using_tlb) {
3120       if(!c) {
3121         emit_cmpimm(s<0||offset?temp:s,0x800000);
3122         if(!offset&&s!=temp) emit_mov(s,temp);
3123         jaddr=(int)out;
3124         emit_jno(0);
3125       }
3126       else
3127       {
3128         if(!memtarget||!rs1[i]) {
3129           jaddr=(int)out;
3130           emit_jmp(0);
3131         }
3132       }
3133       if((u_int)rdram!=0x80000000) 
3134         emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3135     }else{ // using tlb
3136       int map=get_reg(i_regs->regmap,TLREG);
3137       assert(map>=0);
3138       map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3139       if(!c&&!offset&&s>=0) emit_mov(s,temp);
3140       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3141       if(!jaddr&&!memtarget) {
3142         jaddr=(int)out;
3143         emit_jmp(0);
3144       }
3145       gen_tlb_addr_w(temp,map);
3146     }
3147
3148     if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3149       temp2=get_reg(i_regs->regmap,FTEMP);
3150       if(!rs2[i]) temp2=th=tl;
3151     }
3152
3153     emit_testimm(temp,2);
3154     case2=(int)out;
3155     emit_jne(0);
3156     emit_testimm(temp,1);
3157     case1=(int)out;
3158     emit_jne(0);
3159     // 0
3160     if (opcode[i]==0x2A) { // SWL
3161       emit_writeword_indexed(tl,0,temp);
3162     }
3163     if (opcode[i]==0x2E) { // SWR
3164       emit_writebyte_indexed(tl,3,temp);
3165     }
3166     if (opcode[i]==0x2C) { // SDL
3167       emit_writeword_indexed(th,0,temp);
3168       if(rs2[i]) emit_mov(tl,temp2);
3169     }
3170     if (opcode[i]==0x2D) { // SDR
3171       emit_writebyte_indexed(tl,3,temp);
3172       if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3173     }
3174     done0=(int)out;
3175     emit_jmp(0);
3176     // 1
3177     set_jump_target(case1,(int)out);
3178     if (opcode[i]==0x2A) { // SWL
3179       // Write 3 msb into three least significant bytes
3180       if(rs2[i]) emit_rorimm(tl,8,tl);
3181       emit_writehword_indexed(tl,-1,temp);
3182       if(rs2[i]) emit_rorimm(tl,16,tl);
3183       emit_writebyte_indexed(tl,1,temp);
3184       if(rs2[i]) emit_rorimm(tl,8,tl);
3185     }
3186     if (opcode[i]==0x2E) { // SWR
3187       // Write two lsb into two most significant bytes
3188       emit_writehword_indexed(tl,1,temp);
3189     }
3190     if (opcode[i]==0x2C) { // SDL
3191       if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3192       // Write 3 msb into three least significant bytes
3193       if(rs2[i]) emit_rorimm(th,8,th);
3194       emit_writehword_indexed(th,-1,temp);
3195       if(rs2[i]) emit_rorimm(th,16,th);
3196       emit_writebyte_indexed(th,1,temp);
3197       if(rs2[i]) emit_rorimm(th,8,th);
3198     }
3199     if (opcode[i]==0x2D) { // SDR
3200       if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3201       // Write two lsb into two most significant bytes
3202       emit_writehword_indexed(tl,1,temp);
3203     }
3204     done1=(int)out;
3205     emit_jmp(0);
3206     // 2
3207     set_jump_target(case2,(int)out);
3208     emit_testimm(temp,1);
3209     case3=(int)out;
3210     emit_jne(0);
3211     if (opcode[i]==0x2A) { // SWL
3212       // Write two msb into two least significant bytes
3213       if(rs2[i]) emit_rorimm(tl,16,tl);
3214       emit_writehword_indexed(tl,-2,temp);
3215       if(rs2[i]) emit_rorimm(tl,16,tl);
3216     }
3217     if (opcode[i]==0x2E) { // SWR
3218       // Write 3 lsb into three most significant bytes
3219       emit_writebyte_indexed(tl,-1,temp);
3220       if(rs2[i]) emit_rorimm(tl,8,tl);
3221       emit_writehword_indexed(tl,0,temp);
3222       if(rs2[i]) emit_rorimm(tl,24,tl);
3223     }
3224     if (opcode[i]==0x2C) { // SDL
3225       if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3226       // Write two msb into two least significant bytes
3227       if(rs2[i]) emit_rorimm(th,16,th);
3228       emit_writehword_indexed(th,-2,temp);
3229       if(rs2[i]) emit_rorimm(th,16,th);
3230     }
3231     if (opcode[i]==0x2D) { // SDR
3232       if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3233       // Write 3 lsb into three most significant bytes
3234       emit_writebyte_indexed(tl,-1,temp);
3235       if(rs2[i]) emit_rorimm(tl,8,tl);
3236       emit_writehword_indexed(tl,0,temp);
3237       if(rs2[i]) emit_rorimm(tl,24,tl);
3238     }
3239     done2=(int)out;
3240     emit_jmp(0);
3241     // 3
3242     set_jump_target(case3,(int)out);
3243     if (opcode[i]==0x2A) { // SWL
3244       // Write msb into least significant byte
3245       if(rs2[i]) emit_rorimm(tl,24,tl);
3246       emit_writebyte_indexed(tl,-3,temp);
3247       if(rs2[i]) emit_rorimm(tl,8,tl);
3248     }
3249     if (opcode[i]==0x2E) { // SWR
3250       // Write entire word
3251       emit_writeword_indexed(tl,-3,temp);
3252     }
3253     if (opcode[i]==0x2C) { // SDL
3254       if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3255       // Write msb into least significant byte
3256       if(rs2[i]) emit_rorimm(th,24,th);
3257       emit_writebyte_indexed(th,-3,temp);
3258       if(rs2[i]) emit_rorimm(th,8,th);
3259     }
3260     if (opcode[i]==0x2D) { // SDR
3261       if(rs2[i]) emit_mov(th,temp2);
3262       // Write entire word
3263       emit_writeword_indexed(tl,-3,temp);
3264     }
3265     set_jump_target(done0,(int)out);
3266     set_jump_target(done1,(int)out);
3267     set_jump_target(done2,(int)out);
3268     if (opcode[i]==0x2C) { // SDL
3269       emit_testimm(temp,4);
3270       done0=(int)out;
3271       emit_jne(0);
3272       emit_andimm(temp,~3,temp);
3273       emit_writeword_indexed(temp2,4,temp);
3274       set_jump_target(done0,(int)out);
3275     }
3276     if (opcode[i]==0x2D) { // SDR
3277       emit_testimm(temp,4);
3278       done0=(int)out;
3279       emit_jeq(0);
3280       emit_andimm(temp,~3,temp);
3281       emit_writeword_indexed(temp2,-4,temp);
3282       set_jump_target(done0,(int)out);
3283     }
3284     if(!c||!memtarget)
3285       add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3286   }
3287   if(!using_tlb) {
3288     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3289     #if defined(HOST_IMM8)
3290     int ir=get_reg(i_regs->regmap,INVCP);
3291     assert(ir>=0);
3292     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3293     #else
3294     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3295     #endif
3296     jaddr2=(int)out;
3297     emit_jne(0);
3298     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3299   }
3300   /*
3301     emit_pusha();
3302     //save_regs(0x100f);
3303         emit_readword((int)&last_count,ECX);
3304         if(get_reg(i_regs->regmap,CCREG)<0)
3305           emit_loadreg(CCREG,HOST_CCREG);
3306         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3307         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3308         emit_writeword(HOST_CCREG,(int)&Count);
3309     emit_call((int)memdebug);
3310     emit_popa();
3311     //restore_regs(0x100f);
3312   /**/
3313 }
3314
3315 void c1ls_assemble(int i,struct regstat *i_regs)
3316 {
3317 #ifndef DISABLE_COP1
3318   int s,th,tl;
3319   int temp,ar;
3320   int map=-1;
3321   int offset;
3322   int c=0;
3323   int jaddr,jaddr2=0,jaddr3,type;
3324   int agr=AGEN1+(i&1);
3325   u_int hr,reglist=0;
3326   th=get_reg(i_regs->regmap,FTEMP|64);
3327   tl=get_reg(i_regs->regmap,FTEMP);
3328   s=get_reg(i_regs->regmap,rs1[i]);
3329   temp=get_reg(i_regs->regmap,agr);
3330   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3331   offset=imm[i];
3332   assert(tl>=0);
3333   assert(rs1[i]>0);
3334   assert(temp>=0);
3335   for(hr=0;hr<HOST_REGS;hr++) {
3336     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3337   }
3338   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3339   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3340   {
3341     // Loads use a temporary register which we need to save
3342     reglist|=1<<temp;
3343   }
3344   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3345     ar=temp;
3346   else // LWC1/LDC1
3347     ar=tl;
3348   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3349   //else c=(i_regs->wasconst>>s)&1;
3350   if(s>=0) c=(i_regs->wasconst>>s)&1;
3351   // Check cop1 unusable
3352   if(!cop1_usable) {
3353     signed char rs=get_reg(i_regs->regmap,CSREG);
3354     assert(rs>=0);
3355     emit_testimm(rs,0x20000000);
3356     jaddr=(int)out;
3357     emit_jeq(0);
3358     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3359     cop1_usable=1;
3360   }
3361   if (opcode[i]==0x39) { // SWC1 (get float address)
3362     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3363   }
3364   if (opcode[i]==0x3D) { // SDC1 (get double address)
3365     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3366   }
3367   // Generate address + offset
3368   if(!using_tlb) {
3369     if(!c)
3370       emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3371   }
3372   else
3373   {
3374     map=get_reg(i_regs->regmap,TLREG);
3375     assert(map>=0);
3376     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3377       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3378     }
3379     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3380       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3381     }
3382   }
3383   if (opcode[i]==0x39) { // SWC1 (read float)
3384     emit_readword_indexed(0,tl,tl);
3385   }
3386   if (opcode[i]==0x3D) { // SDC1 (read double)
3387     emit_readword_indexed(4,tl,th);
3388     emit_readword_indexed(0,tl,tl);
3389   }
3390   if (opcode[i]==0x31) { // LWC1 (get target address)
3391     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3392   }
3393   if (opcode[i]==0x35) { // LDC1 (get target address)
3394     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3395   }
3396   if(!using_tlb) {
3397     if(!c) {
3398       jaddr2=(int)out;
3399       emit_jno(0);
3400     }
3401     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3402       jaddr2=(int)out;
3403       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3404     }
3405     #ifdef DESTRUCTIVE_SHIFT
3406     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3407       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3408     }
3409     #endif
3410   }else{
3411     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3412       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3413     }
3414     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3415       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3416     }
3417   }
3418   if (opcode[i]==0x31) { // LWC1
3419     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3420     //gen_tlb_addr_r(ar,map);
3421     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3422     #ifdef HOST_IMM_ADDR32
3423     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3424     else
3425     #endif
3426     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3427     type=LOADW_STUB;
3428   }
3429   if (opcode[i]==0x35) { // LDC1
3430     assert(th>=0);
3431     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3432     //gen_tlb_addr_r(ar,map);
3433     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3434     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3435     #ifdef HOST_IMM_ADDR32
3436     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3437     else
3438     #endif
3439     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3440     type=LOADD_STUB;
3441   }
3442   if (opcode[i]==0x39) { // SWC1
3443     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3444     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3445     type=STOREW_STUB;
3446   }
3447   if (opcode[i]==0x3D) { // SDC1
3448     assert(th>=0);
3449     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3450     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3451     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3452     type=STORED_STUB;
3453   }
3454   if(!using_tlb) {
3455     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3456       #ifndef DESTRUCTIVE_SHIFT
3457       temp=offset||c||s<0?ar:s;
3458       #endif
3459       #if defined(HOST_IMM8)
3460       int ir=get_reg(i_regs->regmap,INVCP);
3461       assert(ir>=0);
3462       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3463       #else
3464       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3465       #endif
3466       jaddr3=(int)out;
3467       emit_jne(0);
3468       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3469     }
3470   }
3471   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3472   if (opcode[i]==0x31) { // LWC1 (write float)
3473     emit_writeword_indexed(tl,0,temp);
3474   }
3475   if (opcode[i]==0x35) { // LDC1 (write double)
3476     emit_writeword_indexed(th,4,temp);
3477     emit_writeword_indexed(tl,0,temp);
3478   }
3479   //if(opcode[i]==0x39)
3480   /*if(opcode[i]==0x39||opcode[i]==0x31)
3481   {
3482     emit_pusha();
3483         emit_readword((int)&last_count,ECX);
3484         if(get_reg(i_regs->regmap,CCREG)<0)
3485           emit_loadreg(CCREG,HOST_CCREG);
3486         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3487         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3488         emit_writeword(HOST_CCREG,(int)&Count);
3489     emit_call((int)memdebug);
3490     emit_popa();
3491   }/**/
3492 #else
3493   cop1_unusable(i, i_regs);
3494 #endif
3495 }
3496
3497 #ifndef multdiv_assemble
3498 void multdiv_assemble(int i,struct regstat *i_regs)
3499 {
3500   printf("Need multdiv_assemble for this architecture.\n");
3501   exit(1);
3502 }
3503 #endif
3504
3505 void mov_assemble(int i,struct regstat *i_regs)
3506 {
3507   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3508   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3509   assert(rt1[i]>0);
3510   if(rt1[i]) {
3511     signed char sh,sl,th,tl;
3512     th=get_reg(i_regs->regmap,rt1[i]|64);
3513     tl=get_reg(i_regs->regmap,rt1[i]);
3514     //assert(tl>=0);
3515     if(tl>=0) {
3516       sh=get_reg(i_regs->regmap,rs1[i]|64);
3517       sl=get_reg(i_regs->regmap,rs1[i]);
3518       if(sl>=0) emit_mov(sl,tl);
3519       else emit_loadreg(rs1[i],tl);
3520       if(th>=0) {
3521         if(sh>=0) emit_mov(sh,th);
3522         else emit_loadreg(rs1[i]|64,th);
3523       }
3524     }
3525   }
3526 }
3527
3528 #ifndef fconv_assemble
3529 void fconv_assemble(int i,struct regstat *i_regs)
3530 {
3531   printf("Need fconv_assemble for this architecture.\n");
3532   exit(1);
3533 }
3534 #endif
3535
3536 #if 0
3537 void float_assemble(int i,struct regstat *i_regs)
3538 {
3539   printf("Need float_assemble for this architecture.\n");
3540   exit(1);
3541 }
3542 #endif
3543
3544 void syscall_assemble(int i,struct regstat *i_regs)
3545 {
3546   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3547   assert(ccreg==HOST_CCREG);
3548   assert(!is_delayslot);
3549   emit_movimm(start+i*4,EAX); // Get PC
3550   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3551   emit_jmp((int)jump_syscall);
3552 }
3553
3554 void ds_assemble(int i,struct regstat *i_regs)
3555 {
3556   is_delayslot=1;
3557   switch(itype[i]) {
3558     case ALU:
3559       alu_assemble(i,i_regs);break;
3560     case IMM16:
3561       imm16_assemble(i,i_regs);break;
3562     case SHIFT:
3563       shift_assemble(i,i_regs);break;
3564     case SHIFTIMM:
3565       shiftimm_assemble(i,i_regs);break;
3566     case LOAD:
3567       load_assemble(i,i_regs);break;
3568     case LOADLR:
3569       loadlr_assemble(i,i_regs);break;
3570     case STORE:
3571       store_assemble(i,i_regs);break;
3572     case STORELR:
3573       storelr_assemble(i,i_regs);break;
3574     case COP0:
3575       cop0_assemble(i,i_regs);break;
3576     case COP1:
3577       cop1_assemble(i,i_regs);break;
3578     case C1LS:
3579       c1ls_assemble(i,i_regs);break;
3580     case FCONV:
3581       fconv_assemble(i,i_regs);break;
3582     case FLOAT:
3583       float_assemble(i,i_regs);break;
3584     case FCOMP:
3585       fcomp_assemble(i,i_regs);break;
3586     case MULTDIV:
3587       multdiv_assemble(i,i_regs);break;
3588     case MOV:
3589       mov_assemble(i,i_regs);break;
3590     case SYSCALL:
3591     case SPAN:
3592     case UJUMP:
3593     case RJUMP:
3594     case CJUMP:
3595     case SJUMP:
3596     case FJUMP:
3597       printf("Jump in the delay slot.  This is probably a bug.\n");
3598   }
3599   is_delayslot=0;
3600 }
3601
3602 // Is the branch target a valid internal jump?
3603 int internal_branch(uint64_t i_is32,int addr)
3604 {
3605   if(addr&1) return 0; // Indirect (register) jump
3606   if(addr>=start && addr<start+slen*4-4)
3607   {
3608     int t=(addr-start)>>2;
3609     // Delay slots are not valid branch targets
3610     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3611     // 64 -> 32 bit transition requires a recompile
3612     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3613     {
3614       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3615       else printf("optimizable: yes\n");
3616     }*/
3617     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3618     if(requires_32bit[t]&~i_is32) return 0;
3619     else return 1;
3620   }
3621   return 0;
3622 }
3623
3624 #ifndef wb_invalidate
3625 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3626   uint64_t u,uint64_t uu)
3627 {
3628   int hr;
3629   for(hr=0;hr<HOST_REGS;hr++) {
3630     if(hr!=EXCLUDE_REG) {
3631       if(pre[hr]!=entry[hr]) {
3632         if(pre[hr]>=0) {
3633           if((dirty>>hr)&1) {
3634             if(get_reg(entry,pre[hr])<0) {
3635               if(pre[hr]<64) {
3636                 if(!((u>>pre[hr])&1)) {
3637                   emit_storereg(pre[hr],hr);
3638                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3639                     emit_sarimm(hr,31,hr);
3640                     emit_storereg(pre[hr]|64,hr);
3641                   }
3642                 }
3643               }else{
3644                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3645                   emit_storereg(pre[hr],hr);
3646                 }
3647               }
3648             }
3649           }
3650         }
3651       }
3652     }
3653   }
3654   // Move from one register to another (no writeback)
3655   for(hr=0;hr<HOST_REGS;hr++) {
3656     if(hr!=EXCLUDE_REG) {
3657       if(pre[hr]!=entry[hr]) {
3658         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3659           int nr;
3660           if((nr=get_reg(entry,pre[hr]))>=0) {
3661             emit_mov(hr,nr);
3662           }
3663         }
3664       }
3665     }
3666   }
3667 }
3668 #endif
3669
3670 // Load the specified registers
3671 // This only loads the registers given as arguments because
3672 // we don't want to load things that will be overwritten
3673 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3674 {
3675   int hr;
3676   // Load 32-bit regs
3677   for(hr=0;hr<HOST_REGS;hr++) {
3678     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3679       if(entry[hr]!=regmap[hr]) {
3680         if(regmap[hr]==rs1||regmap[hr]==rs2)
3681         {
3682           if(regmap[hr]==0) {
3683             emit_zeroreg(hr);
3684           }
3685           else
3686           {
3687             emit_loadreg(regmap[hr],hr);
3688           }
3689         }
3690       }
3691     }
3692   }
3693   //Load 64-bit regs
3694   for(hr=0;hr<HOST_REGS;hr++) {
3695     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3696       if(entry[hr]!=regmap[hr]) {
3697         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3698         {
3699           assert(regmap[hr]!=64);
3700           if((is32>>(regmap[hr]&63))&1) {
3701             int lr=get_reg(regmap,regmap[hr]-64);
3702             if(lr>=0)
3703               emit_sarimm(lr,31,hr);
3704             else
3705               emit_loadreg(regmap[hr],hr);
3706           }
3707           else
3708           {
3709             emit_loadreg(regmap[hr],hr);
3710           }
3711         }
3712       }
3713     }
3714   }
3715 }
3716
3717 // Load registers prior to the start of a loop
3718 // so that they are not loaded within the loop
3719 static void loop_preload(signed char pre[],signed char entry[])
3720 {
3721   int hr;
3722   for(hr=0;hr<HOST_REGS;hr++) {
3723     if(hr!=EXCLUDE_REG) {
3724       if(pre[hr]!=entry[hr]) {
3725         if(entry[hr]>=0) {
3726           if(get_reg(pre,entry[hr])<0) {
3727             assem_debug("loop preload:\n");
3728             //printf("loop preload: %d\n",hr);
3729             if(entry[hr]==0) {
3730               emit_zeroreg(hr);
3731             }
3732             else if(entry[hr]<TEMPREG)
3733             {
3734               emit_loadreg(entry[hr],hr);
3735             }
3736             else if(entry[hr]-64<TEMPREG)
3737             {
3738               emit_loadreg(entry[hr],hr);
3739             }
3740           }
3741         }
3742       }
3743     }
3744   }
3745 }
3746
3747 // Generate address for load/store instruction
3748 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3749 {
3750   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3751     int ra;
3752     int agr=AGEN1+(i&1);
3753     int mgr=MGEN1+(i&1);
3754     if(itype[i]==LOAD) {
3755       ra=get_reg(i_regs->regmap,rt1[i]);
3756       //if(rt1[i]) assert(ra>=0);
3757     }
3758     if(itype[i]==LOADLR) {
3759       ra=get_reg(i_regs->regmap,FTEMP);
3760     }
3761     if(itype[i]==STORE||itype[i]==STORELR) {
3762       ra=get_reg(i_regs->regmap,agr);
3763       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3764     }
3765     if(itype[i]==C1LS) {
3766       if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3767         ra=get_reg(i_regs->regmap,FTEMP);
3768       else { // SWC1/SDC1
3769         ra=get_reg(i_regs->regmap,agr);
3770         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3771       }
3772     }
3773     int rs=get_reg(i_regs->regmap,rs1[i]);
3774     int rm=get_reg(i_regs->regmap,TLREG);
3775     if(ra>=0) {
3776       int offset=imm[i];
3777       int c=(i_regs->wasconst>>rs)&1;
3778       if(rs1[i]==0) {
3779         // Using r0 as a base address
3780         /*if(rm>=0) {
3781           if(!entry||entry[rm]!=mgr) {
3782             generate_map_const(offset,rm);
3783           } // else did it in the previous cycle
3784         }*/
3785         if(!entry||entry[ra]!=agr) {
3786           if (opcode[i]==0x22||opcode[i]==0x26) {
3787             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3788           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3789             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3790           }else{
3791             emit_movimm(offset,ra);
3792           }
3793         } // else did it in the previous cycle
3794       }
3795       else if(rs<0) {
3796         if(!entry||entry[ra]!=rs1[i])
3797           emit_loadreg(rs1[i],ra);
3798         //if(!entry||entry[ra]!=rs1[i])
3799         //  printf("poor load scheduling!\n");
3800       }
3801       else if(c) {
3802         if(rm>=0) {
3803           if(!entry||entry[rm]!=mgr) {
3804             if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3805               // Stores to memory go thru the mapper to detect self-modifying
3806               // code, loads don't.
3807               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3808                  (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3809                 generate_map_const(constmap[i][rs]+offset,rm);
3810             }else{
3811               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3812                 generate_map_const(constmap[i][rs]+offset,rm);
3813             }
3814           }
3815         }
3816         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3817           if(!entry||entry[ra]!=agr) {
3818             if (opcode[i]==0x22||opcode[i]==0x26) {
3819               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3820             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3821               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3822             }else{
3823               #ifdef HOST_IMM_ADDR32
3824               if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
3825                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
3826               #endif
3827               emit_movimm(constmap[i][rs]+offset,ra);
3828             }
3829           } // else did it in the previous cycle
3830         } // else load_consts already did it
3831       }
3832       if(offset&&!c&&rs1[i]) {
3833         if(rs>=0) {
3834           emit_addimm(rs,offset,ra);
3835         }else{
3836           emit_addimm(ra,offset,ra);
3837         }
3838       }
3839     }
3840   }
3841   // Preload constants for next instruction
3842   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
3843     int agr,ra;
3844     #ifndef HOST_IMM_ADDR32
3845     // Mapper entry
3846     agr=MGEN1+((i+1)&1);
3847     ra=get_reg(i_regs->regmap,agr);
3848     if(ra>=0) {
3849       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3850       int offset=imm[i+1];
3851       int c=(regs[i+1].wasconst>>rs)&1;
3852       if(c) {
3853         if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
3854           // Stores to memory go thru the mapper to detect self-modifying
3855           // code, loads don't.
3856           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
3857              (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
3858             generate_map_const(constmap[i+1][rs]+offset,ra);
3859         }else{
3860           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
3861             generate_map_const(constmap[i+1][rs]+offset,ra);
3862         }
3863       }
3864       /*else if(rs1[i]==0) {
3865         generate_map_const(offset,ra);
3866       }*/
3867     }
3868     #endif
3869     // Actual address
3870     agr=AGEN1+((i+1)&1);
3871     ra=get_reg(i_regs->regmap,agr);
3872     if(ra>=0) {
3873       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3874       int offset=imm[i+1];
3875       int c=(regs[i+1].wasconst>>rs)&1;
3876       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3877         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3878           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3879         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3880           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3881         }else{
3882           #ifdef HOST_IMM_ADDR32
3883           if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) ||
3884              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
3885           #endif
3886           emit_movimm(constmap[i+1][rs]+offset,ra);
3887         }
3888       }
3889       else if(rs1[i+1]==0) {
3890         // Using r0 as a base address
3891         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3892           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3893         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3894           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3895         }else{
3896           emit_movimm(offset,ra);
3897         }
3898       }
3899     }
3900   }
3901 }
3902
3903 int get_final_value(int hr, int i, int *value)
3904 {
3905   int reg=regs[i].regmap[hr];
3906   while(i<slen-1) {
3907     if(regs[i+1].regmap[hr]!=reg) break;
3908     if(!((regs[i+1].isconst>>hr)&1)) break;
3909     if(bt[i+1]) break;
3910     i++;
3911   }
3912   if(i<slen-1) {
3913     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3914       *value=constmap[i][hr];
3915       return 1;
3916     }
3917     if(!bt[i+1]) {
3918       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
3919         // Load in delay slot, out-of-order execution
3920         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
3921         {
3922           #ifdef HOST_IMM_ADDR32
3923           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
3924           #endif
3925           // Precompute load address
3926           *value=constmap[i][hr]+imm[i+2];
3927           return 1;
3928         }
3929       }
3930       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)