libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24
  25 #include "emu_if.h" //emulator interface
  26
  27 #include <sys/mman.h>
  28
  29 #ifdef __i386__
  30 #include "assem_x86.h"
  31 #endif
  32 #ifdef __x86_64__
  33 #include "assem_x64.h"
  34 #endif
  35 #ifdef __arm__
  36 #include "assem_arm.h"
  37 #endif
  38
  39 #define MAXBLOCK 4096
  40 #define MAX_OUTPUT_BLOCK_SIZE 262144
  41 #define CLOCK_DIVIDER 2
  42
  43 struct regstat
  44 {
  45   signed char regmap_entry[HOST_REGS];
  46   signed char regmap[HOST_REGS];
  47   uint64_t was32;
  48   uint64_t is32;
  49   uint64_t wasdirty;
  50   uint64_t dirty;
  51   uint64_t u;
  52   uint64_t uu;
  53   u_int wasconst;
  54   u_int isconst;
  55   uint64_t constmap[HOST_REGS];
  56 };
  57
  58 struct ll_entry
  59 {
  60   u_int vaddr;
  61   u_int reg32;
  62   void *addr;
  63   struct ll_entry *next;
  64 };
  65
  66   u_int start;
  67   u_int *source;
  68   u_int pagelimit;
  69   char insn[MAXBLOCK][10];
  70   u_char itype[MAXBLOCK];
  71   u_char opcode[MAXBLOCK];
  72   u_char opcode2[MAXBLOCK];
  73   u_char bt[MAXBLOCK];
  74   u_char rs1[MAXBLOCK];
  75   u_char rs2[MAXBLOCK];
  76   u_char rt1[MAXBLOCK];
  77   u_char rt2[MAXBLOCK];
  78   u_char us1[MAXBLOCK];
  79   u_char us2[MAXBLOCK];
  80   u_char dep1[MAXBLOCK];
  81   u_char dep2[MAXBLOCK];
  82   u_char lt1[MAXBLOCK];
  83   int imm[MAXBLOCK];
  84   u_int ba[MAXBLOCK];
  85   char likely[MAXBLOCK];
  86   char is_ds[MAXBLOCK];
  87   char ooo[MAXBLOCK];
  88   uint64_t unneeded_reg[MAXBLOCK];
  89   uint64_t unneeded_reg_upper[MAXBLOCK];
  90   uint64_t branch_unneeded_reg[MAXBLOCK];
  91   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
  92   uint64_t p32[MAXBLOCK];
  93   uint64_t pr32[MAXBLOCK];
  94   signed char regmap_pre[MAXBLOCK][HOST_REGS];
  95   signed char regmap[MAXBLOCK][HOST_REGS];
  96   signed char regmap_entry[MAXBLOCK][HOST_REGS];
  97   uint64_t constmap[MAXBLOCK][HOST_REGS];
  98   struct regstat regs[MAXBLOCK];
  99   struct regstat branch_regs[MAXBLOCK];
 100   signed char minimum_free_regs[MAXBLOCK];
 101   u_int needed_reg[MAXBLOCK];
 102   uint64_t requires_32bit[MAXBLOCK];
 103   u_int wont_dirty[MAXBLOCK];
 104   u_int will_dirty[MAXBLOCK];
 105   int ccadj[MAXBLOCK];
 106   int slen;
 107   u_int instr_addr[MAXBLOCK];
 108   u_int link_addr[MAXBLOCK][3];
 109   int linkcount;
 110   u_int stubs[MAXBLOCK*3][8];
 111   int stubcount;
 112   u_int literals[1024][2];
 113   int literalcount;
 114   int is_delayslot;
 115   int cop1_usable;
 116   u_char *out;
 117   struct ll_entry *jump_in[4096];
 118   struct ll_entry *jump_out[4096];
 119   struct ll_entry *jump_dirty[4096];
 120   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 121   char shadow[1048576]  __attribute__((aligned(16)));
 122   void *copy;
 123   int expirep;
 124 #ifndef PCSX
 125   u_int using_tlb;
 126 #else
 127   static const u_int using_tlb=0;
 128 #endif
 129   static u_int sp_in_mirror;
 130   u_int stop_after_jal;
 131   extern u_char restore_candidate[512];
 132   extern int cycle_count;
 133
 134   /* registers that may be allocated */
 135   /* 1-31 gpr */
 136 #define HIREG 32 // hi
 137 #define LOREG 33 // lo
 138 #define FSREG 34 // FPU status (FCSR)
 139 #define CSREG 35 // Coprocessor status
 140 #define CCREG 36 // Cycle count
 141 #define INVCP 37 // Pointer to invalid_code
 142 #define MMREG 38 // Pointer to memory_map
 143 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 144 #define TEMPREG 40
 145 #define FTEMP 40 // FPU temporary register
 146 #define PTEMP 41 // Prefetch temporary register
 147 #define TLREG 42 // TLB mapping offset
 148 #define RHASH 43 // Return address hash
 149 #define RHTBL 44 // Return address hash table address
 150 #define RTEMP 45 // JR/JALR address register
 151 #define MAXREG 45
 152 #define AGEN1 46 // Address generation temporary register
 153 #define AGEN2 47 // Address generation temporary register
 154 #define MGEN1 48 // Maptable address generation temporary register
 155 #define MGEN2 49 // Maptable address generation temporary register
 156 #define BTREG 50 // Branch target temporary register
 157
 158   /* instruction types */
 159 #define NOP 0     // No operation
 160 #define LOAD 1    // Load
 161 #define STORE 2   // Store
 162 #define LOADLR 3  // Unaligned load
 163 #define STORELR 4 // Unaligned store
 164 #define MOV 5     // Move
 165 #define ALU 6     // Arithmetic/logic
 166 #define MULTDIV 7 // Multiply/divide
 167 #define SHIFT 8   // Shift by register
 168 #define SHIFTIMM 9// Shift by immediate
 169 #define IMM16 10  // 16-bit immediate
 170 #define RJUMP 11  // Unconditional jump to register
 171 #define UJUMP 12  // Unconditional jump
 172 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 173 #define SJUMP 14  // Conditional branch (regimm format)
 174 #define COP0 15   // Coprocessor 0
 175 #define COP1 16   // Coprocessor 1
 176 #define C1LS 17   // Coprocessor 1 load/store
 177 #define FJUMP 18  // Conditional branch (floating point)
 178 #define FLOAT 19  // Floating point unit
 179 #define FCONV 20  // Convert integer to float
 180 #define FCOMP 21  // Floating point compare (sets FSREG)
 181 #define SYSCALL 22// SYSCALL
 182 #define OTHER 23  // Other
 183 #define SPAN 24   // Branch/delay slot spans 2 pages
 184 #define NI 25     // Not implemented
 185 #define HLECALL 26// PCSX fake opcodes for HLE
 186 #define COP2 27   // Coprocessor 2 move
 187 #define C2LS 28   // Coprocessor 2 load/store
 188 #define C2OP 29   // Coprocessor 2 operation
 189 #define INTCALL 30// Call interpreter to handle rare corner cases
 190
 191   /* stubs */
 192 #define CC_STUB 1
 193 #define FP_STUB 2
 194 #define LOADB_STUB 3
 195 #define LOADH_STUB 4
 196 #define LOADW_STUB 5
 197 #define LOADD_STUB 6
 198 #define LOADBU_STUB 7
 199 #define LOADHU_STUB 8
 200 #define STOREB_STUB 9
 201 #define STOREH_STUB 10
 202 #define STOREW_STUB 11
 203 #define STORED_STUB 12
 204 #define STORELR_STUB 13
 205 #define INVCODE_STUB 14
 206
 207   /* branch codes */
 208 #define TAKEN 1
 209 #define NOTTAKEN 2
 210 #define NULLDS 3
 211
 212 // asm linkage
 213 int new_recompile_block(int addr);
 214 void *get_addr_ht(u_int vaddr);
 215 void invalidate_block(u_int block);
 216 void invalidate_addr(u_int addr);
 217 void remove_hash(int vaddr);
 218 void jump_vaddr();
 219 void dyna_linker();
 220 void dyna_linker_ds();
 221 void verify_code();
 222 void verify_code_vm();
 223 void verify_code_ds();
 224 void cc_interrupt();
 225 void fp_exception();
 226 void fp_exception_ds();
 227 void jump_syscall();
 228 void jump_syscall_hle();
 229 void jump_eret();
 230 void jump_hlecall();
 231 void jump_intcall();
 232 void new_dyna_leave();
 233
 234 // TLB
 235 void TLBWI_new();
 236 void TLBWR_new();
 237 void read_nomem_new();
 238 void read_nomemb_new();
 239 void read_nomemh_new();
 240 void read_nomemd_new();
 241 void write_nomem_new();
 242 void write_nomemb_new();
 243 void write_nomemh_new();
 244 void write_nomemd_new();
 245 void write_rdram_new();
 246 void write_rdramb_new();
 247 void write_rdramh_new();
 248 void write_rdramd_new();
 249 extern u_int memory_map[1048576];
 250
 251 // Needed by assembler
 252 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 253 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 254 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 255 void load_all_regs(signed char i_regmap[]);
 256 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 257 void load_regs_entry(int t);
 258 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 259
 260 int tracedebug=0;
 261
 262 //#define DEBUG_CYCLE_COUNT 1
 263
 264 void nullf() {}
 265 //#define assem_debug printf
 266 //#define inv_debug printf
 267 #define assem_debug nullf
 268 #define inv_debug nullf
 269
 270 static void tlb_hacks()
 271 {
 272 #ifndef DISABLE_TLB
 273   // Goldeneye hack
 274   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 275   {
 276     u_int addr;
 277     int n;
 278     switch (ROM_HEADER->Country_code&0xFF)
 279     {
 280       case 0x45: // U
 281         addr=0x34b30;
 282         break;
 283       case 0x4A: // J
 284         addr=0x34b70;
 285         break;
 286       case 0x50: // E
 287         addr=0x329f0;
 288         break;
 289       default:
 290         // Unknown country code
 291         addr=0;
 292         break;
 293     }
 294     u_int rom_addr=(u_int)rom;
 295     #ifdef ROM_COPY
 296     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 297     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 298     if((void *)rom>(void *)0xffffffff) {
 299       munmap(ROM_COPY, 67108864);
 300       if(mmap(ROM_COPY, 12582912,
 301               PROT_READ | PROT_WRITE,
 302               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 303               -1, 0) <= 0) {printf("mmap() failed\n");}
 304       memcpy(ROM_COPY,rom,12582912);
 305       rom_addr=(u_int)ROM_COPY;
 306     }
 307     #endif
 308     if(addr) {
 309       for(n=0x7F000;n<0x80000;n++) {
 310         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 311       }
 312     }
 313   }
 314 #endif
 315 }
 316
 317 static u_int get_page(u_int vaddr)
 318 {
 319 #ifndef PCSX
 320   u_int page=(vaddr^0x80000000)>>12;
 321 #else
 322   u_int page=vaddr&~0xe0000000;
 323   if (page < 0x1000000)
 324     page &= ~0x0e00000; // RAM mirrors
 325   page>>=12;
 326 #endif
 327 #ifndef DISABLE_TLB
 328   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 329 #endif
 330   if(page>2048) page=2048+(page&2047);
 331   return page;
 332 }
 333
 334 static u_int get_vpage(u_int vaddr)
 335 {
 336   u_int vpage=(vaddr^0x80000000)>>12;
 337 #ifndef DISABLE_TLB
 338   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 339 #endif
 340   if(vpage>2048) vpage=2048+(vpage&2047);
 341   return vpage;
 342 }
 343
 344 // Get address from virtual address
 345 // This is called from the recompiled JR/JALR instructions
 346 void *get_addr(u_int vaddr)
 347 {
 348   u_int page=get_page(vaddr);
 349   u_int vpage=get_vpage(vaddr);
 350   struct ll_entry *head;
 351   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 352   head=jump_in[page];
 353   while(head!=NULL) {
 354     if(head->vaddr==vaddr&&head->reg32==0) {
 355   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 356       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 357       ht_bin[3]=ht_bin[1];
 358       ht_bin[2]=ht_bin[0];
 359       ht_bin[1]=(int)head->addr;
 360       ht_bin[0]=vaddr;
 361       return head->addr;
 362     }
 363     head=head->next;
 364   }
 365   head=jump_dirty[vpage];
 366   while(head!=NULL) {
 367     if(head->vaddr==vaddr&&head->reg32==0) {
 368       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 369       // Don't restore blocks which are about to expire from the cache
 370       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 371       if(verify_dirty(head->addr)) {
 372         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 373         invalid_code[vaddr>>12]=0;
 374         memory_map[vaddr>>12]|=0x40000000;
 375         if(vpage<2048) {
 376 #ifndef DISABLE_TLB
 377           if(tlb_LUT_r[vaddr>>12]) {
 378             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 379             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 380           }
 381 #endif
 382           restore_candidate[vpage>>3]|=1<<(vpage&7);
 383         }
 384         else restore_candidate[page>>3]|=1<<(page&7);
 385         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 386         if(ht_bin[0]==vaddr) {
 387           ht_bin[1]=(int)head->addr; // Replace existing entry
 388         }
 389         else
 390         {
 391           ht_bin[3]=ht_bin[1];
 392           ht_bin[2]=ht_bin[0];
 393           ht_bin[1]=(int)head->addr;
 394           ht_bin[0]=vaddr;
 395         }
 396         return head->addr;
 397       }
 398     }
 399     head=head->next;
 400   }
 401   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 402   int r=new_recompile_block(vaddr);
 403   if(r==0) return get_addr(vaddr);
 404   // Execute in unmapped page, generate pagefault execption
 405   Status|=2;
 406   Cause=(vaddr<<31)|0x8;
 407   EPC=(vaddr&1)?vaddr-5:vaddr;
 408   BadVAddr=(vaddr&~1);
 409   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 410   EntryHi=BadVAddr&0xFFFFE000;
 411   return get_addr_ht(0x80000000);
 412 }
 413 // Look up address in hash table first
 414 void *get_addr_ht(u_int vaddr)
 415 {
 416   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 417   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 418   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 419   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 420   return get_addr(vaddr);
 421 }
 422
 423 void *get_addr_32(u_int vaddr,u_int flags)
 424 {
 425 #ifdef FORCE32
 426   return get_addr(vaddr);
 427 #else
 428   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 429   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 430   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 431   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 432   u_int page=get_page(vaddr);
 433   u_int vpage=get_vpage(vaddr);
 434   struct ll_entry *head;
 435   head=jump_in[page];
 436   while(head!=NULL) {
 437     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 438       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 439       if(head->reg32==0) {
 440         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 441         if(ht_bin[0]==-1) {
 442           ht_bin[1]=(int)head->addr;
 443           ht_bin[0]=vaddr;
 444         }else if(ht_bin[2]==-1) {
 445           ht_bin[3]=(int)head->addr;
 446           ht_bin[2]=vaddr;
 447         }
 448         //ht_bin[3]=ht_bin[1];
 449         //ht_bin[2]=ht_bin[0];
 450         //ht_bin[1]=(int)head->addr;
 451         //ht_bin[0]=vaddr;
 452       }
 453       return head->addr;
 454     }
 455     head=head->next;
 456   }
 457   head=jump_dirty[vpage];
 458   while(head!=NULL) {
 459     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 460       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 461       // Don't restore blocks which are about to expire from the cache
 462       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 463       if(verify_dirty(head->addr)) {
 464         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 465         invalid_code[vaddr>>12]=0;
 466         memory_map[vaddr>>12]|=0x40000000;
 467         if(vpage<2048) {
 468 #ifndef DISABLE_TLB
 469           if(tlb_LUT_r[vaddr>>12]) {
 470             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 471             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 472           }
 473 #endif
 474           restore_candidate[vpage>>3]|=1<<(vpage&7);
 475         }
 476         else restore_candidate[page>>3]|=1<<(page&7);
 477         if(head->reg32==0) {
 478           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 479           if(ht_bin[0]==-1) {
 480             ht_bin[1]=(int)head->addr;
 481             ht_bin[0]=vaddr;
 482           }else if(ht_bin[2]==-1) {
 483             ht_bin[3]=(int)head->addr;
 484             ht_bin[2]=vaddr;
 485           }
 486           //ht_bin[3]=ht_bin[1];
 487           //ht_bin[2]=ht_bin[0];
 488           //ht_bin[1]=(int)head->addr;
 489           //ht_bin[0]=vaddr;
 490         }
 491         return head->addr;
 492       }
 493     }
 494     head=head->next;
 495   }
 496   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 497   int r=new_recompile_block(vaddr);
 498   if(r==0) return get_addr(vaddr);
 499   // Execute in unmapped page, generate pagefault execption
 500   Status|=2;
 501   Cause=(vaddr<<31)|0x8;
 502   EPC=(vaddr&1)?vaddr-5:vaddr;
 503   BadVAddr=(vaddr&~1);
 504   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 505   EntryHi=BadVAddr&0xFFFFE000;
 506   return get_addr_ht(0x80000000);
 507 #endif
 508 }
 509
 510 void clear_all_regs(signed char regmap[])
 511 {
 512   int hr;
 513   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 514 }
 515
 516 signed char get_reg(signed char regmap[],int r)
 517 {
 518   int hr;
 519   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 520   return -1;
 521 }
 522
 523 // Find a register that is available for two consecutive cycles
 524 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 525 {
 526   int hr;
 527   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 528   return -1;
 529 }
 530
 531 int count_free_regs(signed char regmap[])
 532 {
 533   int count=0;
 534   int hr;
 535   for(hr=0;hr<HOST_REGS;hr++)
 536   {
 537     if(hr!=EXCLUDE_REG) {
 538       if(regmap[hr]<0) count++;
 539     }
 540   }
 541   return count;
 542 }
 543
 544 void dirty_reg(struct regstat *cur,signed char reg)
 545 {
 546   int hr;
 547   if(!reg) return;
 548   for (hr=0;hr<HOST_REGS;hr++) {
 549     if((cur->regmap[hr]&63)==reg) {
 550       cur->dirty|=1<<hr;
 551     }
 552   }
 553 }
 554
 555 // If we dirty the lower half of a 64 bit register which is now being
 556 // sign-extended, we need to dump the upper half.
 557 // Note: Do this only after completion of the instruction, because
 558 // some instructions may need to read the full 64-bit value even if
 559 // overwriting it (eg SLTI, DSRA32).
 560 static void flush_dirty_uppers(struct regstat *cur)
 561 {
 562   int hr,reg;
 563   for (hr=0;hr<HOST_REGS;hr++) {
 564     if((cur->dirty>>hr)&1) {
 565       reg=cur->regmap[hr];
 566       if(reg>=64)
 567         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 568     }
 569   }
 570 }
 571
 572 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 573 {
 574   int hr;
 575   if(!reg) return;
 576   for (hr=0;hr<HOST_REGS;hr++) {
 577     if(cur->regmap[hr]==reg) {
 578       cur->isconst|=1<<hr;
 579       cur->constmap[hr]=value;
 580     }
 581     else if((cur->regmap[hr]^64)==reg) {
 582       cur->isconst|=1<<hr;
 583       cur->constmap[hr]=value>>32;
 584     }
 585   }
 586 }
 587
 588 void clear_const(struct regstat *cur,signed char reg)
 589 {
 590   int hr;
 591   if(!reg) return;
 592   for (hr=0;hr<HOST_REGS;hr++) {
 593     if((cur->regmap[hr]&63)==reg) {
 594       cur->isconst&=~(1<<hr);
 595     }
 596   }
 597 }
 598
 599 int is_const(struct regstat *cur,signed char reg)
 600 {
 601   int hr;
 602   if(reg<0) return 0;
 603   if(!reg) return 1;
 604   for (hr=0;hr<HOST_REGS;hr++) {
 605     if((cur->regmap[hr]&63)==reg) {
 606       return (cur->isconst>>hr)&1;
 607     }
 608   }
 609   return 0;
 610 }
 611 uint64_t get_const(struct regstat *cur,signed char reg)
 612 {
 613   int hr;
 614   if(!reg) return 0;
 615   for (hr=0;hr<HOST_REGS;hr++) {
 616     if(cur->regmap[hr]==reg) {
 617       return cur->constmap[hr];
 618     }
 619   }
 620   printf("Unknown constant in r%d\n",reg);
 621   exit(1);
 622 }
 623
 624 // Least soon needed registers
 625 // Look at the next ten instructions and see which registers
 626 // will be used.  Try not to reallocate these.
 627 void lsn(u_char hsn[], int i, int *preferred_reg)
 628 {
 629   int j;
 630   int b=-1;
 631   for(j=0;j<9;j++)
 632   {
 633     if(i+j>=slen) {
 634       j=slen-i-1;
 635       break;
 636     }
 637     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 638     {
 639       // Don't go past an unconditonal jump
 640       j++;
 641       break;
 642     }
 643   }
 644   for(;j>=0;j--)
 645   {
 646     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 647     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 648     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 649     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 650     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 651       // Stores can allocate zero
 652       hsn[rs1[i+j]]=j;
 653       hsn[rs2[i+j]]=j;
 654     }
 655     // On some architectures stores need invc_ptr
 656     #if defined(HOST_IMM8)
 657     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 658       hsn[INVCP]=j;
 659     }
 660     #endif
 661     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 662     {
 663       hsn[CCREG]=j;
 664       b=j;
 665     }
 666   }
 667   if(b>=0)
 668   {
 669     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 670     {
 671       // Follow first branch
 672       int t=(ba[i+b]-start)>>2;
 673       j=7-b;if(t+j>=slen) j=slen-t-1;
 674       for(;j>=0;j--)
 675       {
 676         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 677         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 678         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 679         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 680       }
 681     }
 682     // TODO: preferred register based on backward branch
 683   }
 684   // Delay slot should preferably not overwrite branch conditions or cycle count
 685   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 686     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 687     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 688     hsn[CCREG]=1;
 689     // ...or hash tables
 690     hsn[RHASH]=1;
 691     hsn[RHTBL]=1;
 692   }
 693   // Coprocessor load/store needs FTEMP, even if not declared
 694   if(itype[i]==C1LS||itype[i]==C2LS) {
 695     hsn[FTEMP]=0;
 696   }
 697   // Load L/R also uses FTEMP as a temporary register
 698   if(itype[i]==LOADLR) {
 699     hsn[FTEMP]=0;
 700   }
 701   // Also SWL/SWR/SDL/SDR
 702   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 703     hsn[FTEMP]=0;
 704   }
 705   // Don't remove the TLB registers either
 706   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 707     hsn[TLREG]=0;
 708   }
 709   // Don't remove the miniht registers
 710   if(itype[i]==UJUMP||itype[i]==RJUMP)
 711   {
 712     hsn[RHASH]=0;
 713     hsn[RHTBL]=0;
 714   }
 715 }
 716
 717 // We only want to allocate registers if we're going to use them again soon
 718 int needed_again(int r, int i)
 719 {
 720   int j;
 721   int b=-1;
 722   int rn=10;
 723
 724   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 725   {
 726     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 727       return 0; // Don't need any registers if exiting the block
 728   }
 729   for(j=0;j<9;j++)
 730   {
 731     if(i+j>=slen) {
 732       j=slen-i-1;
 733       break;
 734     }
 735     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 736     {
 737       // Don't go past an unconditonal jump
 738       j++;
 739       break;
 740     }
 741     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 742     {
 743       break;
 744     }
 745   }
 746   for(;j>=1;j--)
 747   {
 748     if(rs1[i+j]==r) rn=j;
 749     if(rs2[i+j]==r) rn=j;
 750     if((unneeded_reg[i+j]>>r)&1) rn=10;
 751     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 752     {
 753       b=j;
 754     }
 755   }
 756   /*
 757   if(b>=0)
 758   {
 759     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 760     {
 761       // Follow first branch
 762       int o=rn;
 763       int t=(ba[i+b]-start)>>2;
 764       j=7-b;if(t+j>=slen) j=slen-t-1;
 765       for(;j>=0;j--)
 766       {
 767         if(!((unneeded_reg[t+j]>>r)&1)) {
 768           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 769           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 770         }
 771         else rn=o;
 772       }
 773     }
 774   }*/
 775   if(rn<10) return 1;
 776   return 0;
 777 }
 778
 779 // Try to match register allocations at the end of a loop with those
 780 // at the beginning
 781 int loop_reg(int i, int r, int hr)
 782 {
 783   int j,k;
 784   for(j=0;j<9;j++)
 785   {
 786     if(i+j>=slen) {
 787       j=slen-i-1;
 788       break;
 789     }
 790     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 791     {
 792       // Don't go past an unconditonal jump
 793       j++;
 794       break;
 795     }
 796   }
 797   k=0;
 798   if(i>0){
 799     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 800       k--;
 801   }
 802   for(;k<j;k++)
 803   {
 804     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 805     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 806     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 807     {
 808       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 809       {
 810         int t=(ba[i+k]-start)>>2;
 811         int reg=get_reg(regs[t].regmap_entry,r);
 812         if(reg>=0) return reg;
 813         //reg=get_reg(regs[t+1].regmap_entry,r);
 814         //if(reg>=0) return reg;
 815       }
 816     }
 817   }
 818   return hr;
 819 }
 820
 821
 822 // Allocate every register, preserving source/target regs
 823 void alloc_all(struct regstat *cur,int i)
 824 {
 825   int hr;
 826
 827   for(hr=0;hr<HOST_REGS;hr++) {
 828     if(hr!=EXCLUDE_REG) {
 829       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 830          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 831       {
 832         cur->regmap[hr]=-1;
 833         cur->dirty&=~(1<<hr);
 834       }
 835       // Don't need zeros
 836       if((cur->regmap[hr]&63)==0)
 837       {
 838         cur->regmap[hr]=-1;
 839         cur->dirty&=~(1<<hr);
 840       }
 841     }
 842   }
 843 }
 844
 845
 846 void div64(int64_t dividend,int64_t divisor)
 847 {
 848   lo=dividend/divisor;
 849   hi=dividend%divisor;
 850   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 851   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 852 }
 853 void divu64(uint64_t dividend,uint64_t divisor)
 854 {
 855   lo=dividend/divisor;
 856   hi=dividend%divisor;
 857   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 858   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 859 }
 860
 861 void mult64(uint64_t m1,uint64_t m2)
 862 {
 863    unsigned long long int op1, op2, op3, op4;
 864    unsigned long long int result1, result2, result3, result4;
 865    unsigned long long int temp1, temp2, temp3, temp4;
 866    int sign = 0;
 867
 868    if (m1 < 0)
 869      {
 870     op2 = -m1;
 871     sign = 1 - sign;
 872      }
 873    else op2 = m1;
 874    if (m2 < 0)
 875      {
 876     op4 = -m2;
 877     sign = 1 - sign;
 878      }
 879    else op4 = m2;
 880
 881    op1 = op2 & 0xFFFFFFFF;
 882    op2 = (op2 >> 32) & 0xFFFFFFFF;
 883    op3 = op4 & 0xFFFFFFFF;
 884    op4 = (op4 >> 32) & 0xFFFFFFFF;
 885
 886    temp1 = op1 * op3;
 887    temp2 = (temp1 >> 32) + op1 * op4;
 888    temp3 = op2 * op3;
 889    temp4 = (temp3 >> 32) + op2 * op4;
 890
 891    result1 = temp1 & 0xFFFFFFFF;
 892    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 893    result3 = (result2 >> 32) + temp4;
 894    result4 = (result3 >> 32);
 895
 896    lo = result1 | (result2 << 32);
 897    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 898    if (sign)
 899      {
 900     hi = ~hi;
 901     if (!lo) hi++;
 902     else lo = ~lo + 1;
 903      }
 904 }
 905
 906 void multu64(uint64_t m1,uint64_t m2)
 907 {
 908    unsigned long long int op1, op2, op3, op4;
 909    unsigned long long int result1, result2, result3, result4;
 910    unsigned long long int temp1, temp2, temp3, temp4;
 911
 912    op1 = m1 & 0xFFFFFFFF;
 913    op2 = (m1 >> 32) & 0xFFFFFFFF;
 914    op3 = m2 & 0xFFFFFFFF;
 915    op4 = (m2 >> 32) & 0xFFFFFFFF;
 916
 917    temp1 = op1 * op3;
 918    temp2 = (temp1 >> 32) + op1 * op4;
 919    temp3 = op2 * op3;
 920    temp4 = (temp3 >> 32) + op2 * op4;
 921
 922    result1 = temp1 & 0xFFFFFFFF;
 923    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 924    result3 = (result2 >> 32) + temp4;
 925    result4 = (result3 >> 32);
 926
 927    lo = result1 | (result2 << 32);
 928    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 929
 930   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 931   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 932 }
 933
 934 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 935 {
 936   if(bits) {
 937     original<<=64-bits;
 938     original>>=64-bits;
 939     loaded<<=bits;
 940     original|=loaded;
 941   }
 942   else original=loaded;
 943   return original;
 944 }
 945 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 946 {
 947   if(bits^56) {
 948     original>>=64-(bits^56);
 949     original<<=64-(bits^56);
 950     loaded>>=bits^56;
 951     original|=loaded;
 952   }
 953   else original=loaded;
 954   return original;
 955 }
 956
 957 #ifdef __i386__
 958 #include "assem_x86.c"
 959 #endif
 960 #ifdef __x86_64__
 961 #include "assem_x64.c"
 962 #endif
 963 #ifdef __arm__
 964 #include "assem_arm.c"
 965 #endif
 966
 967 // Add virtual address mapping to linked list
 968 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 969 {
 970   struct ll_entry *new_entry;
 971   new_entry=malloc(sizeof(struct ll_entry));
 972   assert(new_entry!=NULL);
 973   new_entry->vaddr=vaddr;
 974   new_entry->reg32=0;
 975   new_entry->addr=addr;
 976   new_entry->next=*head;
 977   *head=new_entry;
 978 }
 979
 980 // Add virtual address mapping for 32-bit compiled block
 981 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 982 {
 983   ll_add(head,vaddr,addr);
 984 #ifndef FORCE32
 985   (*head)->reg32=reg32;
 986 #endif
 987 }
 988
 989 // Check if an address is already compiled
 990 // but don't return addresses which are about to expire from the cache
 991 void *check_addr(u_int vaddr)
 992 {
 993   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 994   if(ht_bin[0]==vaddr) {
 995     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 996       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 997   }
 998   if(ht_bin[2]==vaddr) {
 999     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1000       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1001   }
1002   u_int page=get_page(vaddr);
1003   struct ll_entry *head;
1004   head=jump_in[page];
1005   while(head!=NULL) {
1006     if(head->vaddr==vaddr&&head->reg32==0) {
1007       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1008         // Update existing entry with current address
1009         if(ht_bin[0]==vaddr) {
1010           ht_bin[1]=(int)head->addr;
1011           return head->addr;
1012         }
1013         if(ht_bin[2]==vaddr) {
1014           ht_bin[3]=(int)head->addr;
1015           return head->addr;
1016         }
1017         // Insert into hash table with low priority.
1018         // Don't evict existing entries, as they are probably
1019         // addresses that are being accessed frequently.
1020         if(ht_bin[0]==-1) {
1021           ht_bin[1]=(int)head->addr;
1022           ht_bin[0]=vaddr;
1023         }else if(ht_bin[2]==-1) {
1024           ht_bin[3]=(int)head->addr;
1025           ht_bin[2]=vaddr;
1026         }
1027         return head->addr;
1028       }
1029     }
1030     head=head->next;
1031   }
1032   return 0;
1033 }
1034
1035 void remove_hash(int vaddr)
1036 {
1037   //printf("remove hash: %x\n",vaddr);
1038   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1039   if(ht_bin[2]==vaddr) {
1040     ht_bin[2]=ht_bin[3]=-1;
1041   }
1042   if(ht_bin[0]==vaddr) {
1043     ht_bin[0]=ht_bin[2];
1044     ht_bin[1]=ht_bin[3];
1045     ht_bin[2]=ht_bin[3]=-1;
1046   }
1047 }
1048
1049 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1050 {
1051   struct ll_entry *next;
1052   while(*head) {
1053     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1054        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1055     {
1056       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1057       remove_hash((*head)->vaddr);
1058       next=(*head)->next;
1059       free(*head);
1060       *head=next;
1061     }
1062     else
1063     {
1064       head=&((*head)->next);
1065     }
1066   }
1067 }
1068
1069 // Remove all entries from linked list
1070 void ll_clear(struct ll_entry **head)
1071 {
1072   struct ll_entry *cur;
1073   struct ll_entry *next;
1074   if(cur=*head) {
1075     *head=0;
1076     while(cur) {
1077       next=cur->next;
1078       free(cur);
1079       cur=next;
1080     }
1081   }
1082 }
1083
1084 // Dereference the pointers and remove if it matches
1085 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1086 {
1087   while(head) {
1088     int ptr=get_pointer(head->addr);
1089     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1090     if(((ptr>>shift)==(addr>>shift)) ||
1091        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1092     {
1093       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1094       u_int host_addr=(u_int)kill_pointer(head->addr);
1095       #ifdef __arm__
1096         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1097       #endif
1098     }
1099     head=head->next;
1100   }
1101 }
1102
1103 // This is called when we write to a compiled block (see do_invstub)
1104 void invalidate_page(u_int page)
1105 {
1106   struct ll_entry *head;
1107   struct ll_entry *next;
1108   head=jump_in[page];
1109   jump_in[page]=0;
1110   while(head!=NULL) {
1111     inv_debug("INVALIDATE: %x\n",head->vaddr);
1112     remove_hash(head->vaddr);
1113     next=head->next;
1114     free(head);
1115     head=next;
1116   }
1117   head=jump_out[page];
1118   jump_out[page]=0;
1119   while(head!=NULL) {
1120     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1121     u_int host_addr=(u_int)kill_pointer(head->addr);
1122     #ifdef __arm__
1123       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1124     #endif
1125     next=head->next;
1126     free(head);
1127     head=next;
1128   }
1129 }
1130 void invalidate_block(u_int block)
1131 {
1132   u_int page=get_page(block<<12);
1133   u_int vpage=get_vpage(block<<12);
1134   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1135   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1136   u_int first,last;
1137   first=last=page;
1138   struct ll_entry *head;
1139   head=jump_dirty[vpage];
1140   //printf("page=%d vpage=%d\n",page,vpage);
1141   while(head!=NULL) {
1142     u_int start,end;
1143     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1144       get_bounds((int)head->addr,&start,&end);
1145       //printf("start: %x end: %x\n",start,end);
1146       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1147         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1148           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1149           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1150         }
1151       }
1152 #ifndef DISABLE_TLB
1153       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1154         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1155           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1156           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1157         }
1158       }
1159 #endif
1160     }
1161     head=head->next;
1162   }
1163   //printf("first=%d last=%d\n",first,last);
1164   invalidate_page(page);
1165   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166   assert(last<page+5);
1167   // Invalidate the adjacent pages if a block crosses a 4K boundary
1168   while(first<page) {
1169     invalidate_page(first);
1170     first++;
1171   }
1172   for(first=page+1;first<last;first++) {
1173     invalidate_page(first);
1174   }
1175   #ifdef __arm__
1176     do_clear_cache();
1177   #endif
1178
1179   // Don't trap writes
1180   invalid_code[block]=1;
1181 #ifdef PCSX
1182   invalid_code[((u_int)0x80000000>>12)|page]=1;
1183 #endif
1184 #ifndef DISABLE_TLB
1185   // If there is a valid TLB entry for this page, remove write protect
1186   if(tlb_LUT_w[block]) {
1187     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1188     // CHECK: Is this right?
1189     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1190     u_int real_block=tlb_LUT_w[block]>>12;
1191     invalid_code[real_block]=1;
1192     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1193   }
1194   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1195 #endif
1196
1197   #ifdef USE_MINI_HT
1198   memset(mini_ht,-1,sizeof(mini_ht));
1199   #endif
1200 }
1201 void invalidate_addr(u_int addr)
1202 {
1203   invalidate_block(addr>>12);
1204 }
1205 // This is called when loading a save state.
1206 // Anything could have changed, so invalidate everything.
1207 void invalidate_all_pages()
1208 {
1209   u_int page,n;
1210   for(page=0;page<4096;page++)
1211     invalidate_page(page);
1212   for(page=0;page<1048576;page++)
1213     if(!invalid_code[page]) {
1214       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1215       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1216     }
1217   #ifdef __arm__
1218   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1219   #endif
1220   #ifdef USE_MINI_HT
1221   memset(mini_ht,-1,sizeof(mini_ht));
1222   #endif
1223   #ifndef DISABLE_TLB
1224   // TLB
1225   for(page=0;page<0x100000;page++) {
1226     if(tlb_LUT_r[page]) {
1227       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1228       if(!tlb_LUT_w[page]||!invalid_code[page])
1229         memory_map[page]|=0x40000000; // Write protect
1230     }
1231     else memory_map[page]=-1;
1232     if(page==0x80000) page=0xC0000;
1233   }
1234   tlb_hacks();
1235   #endif
1236 }
1237
1238 // Add an entry to jump_out after making a link
1239 void add_link(u_int vaddr,void *src)
1240 {
1241   u_int page=get_page(vaddr);
1242   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1243   ll_add(jump_out+page,vaddr,src);
1244   //int ptr=get_pointer(src);
1245   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1246 }
1247
1248 // If a code block was found to be unmodified (bit was set in
1249 // restore_candidate) and it remains unmodified (bit is clear
1250 // in invalid_code) then move the entries for that 4K page from
1251 // the dirty list to the clean list.
1252 void clean_blocks(u_int page)
1253 {
1254   struct ll_entry *head;
1255   inv_debug("INV: clean_blocks page=%d\n",page);
1256   head=jump_dirty[page];
1257   while(head!=NULL) {
1258     if(!invalid_code[head->vaddr>>12]) {
1259       // Don't restore blocks which are about to expire from the cache
1260       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1261         u_int start,end;
1262         if(verify_dirty((int)head->addr)) {
1263           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1264           u_int i;
1265           u_int inv=0;
1266           get_bounds((int)head->addr,&start,&end);
1267           if(start-(u_int)rdram<RAM_SIZE) {
1268             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1269               inv|=invalid_code[i];
1270             }
1271           }
1272           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1273             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1274             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1275             if(addr<start||addr>=end) inv=1;
1276           }
1277           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1278             inv=1;
1279           }
1280           if(!inv) {
1281             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1282             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1283               u_int ppage=page;
1284 #ifndef DISABLE_TLB
1285               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1286 #endif
1287               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1288               //printf("page=%x, addr=%x\n",page,head->vaddr);
1289               //assert(head->vaddr>>12==(page|0x80000));
1290               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1291               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1292               if(!head->reg32) {
1293                 if(ht_bin[0]==head->vaddr) {
1294                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1295                 }
1296                 if(ht_bin[2]==head->vaddr) {
1297                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1298                 }
1299               }
1300             }
1301           }
1302         }
1303       }
1304     }
1305     head=head->next;
1306   }
1307 }
1308
1309
1310 void mov_alloc(struct regstat *current,int i)
1311 {
1312   // Note: Don't need to actually alloc the source registers
1313   if((~current->is32>>rs1[i])&1) {
1314     //alloc_reg64(current,i,rs1[i]);
1315     alloc_reg64(current,i,rt1[i]);
1316     current->is32&=~(1LL<<rt1[i]);
1317   } else {
1318     //alloc_reg(current,i,rs1[i]);
1319     alloc_reg(current,i,rt1[i]);
1320     current->is32|=(1LL<<rt1[i]);
1321   }
1322   clear_const(current,rs1[i]);
1323   clear_const(current,rt1[i]);
1324   dirty_reg(current,rt1[i]);
1325 }
1326
1327 void shiftimm_alloc(struct regstat *current,int i)
1328 {
1329   clear_const(current,rs1[i]);
1330   clear_const(current,rt1[i]);
1331   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1332   {
1333     if(rt1[i]) {
1334       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1335       else lt1[i]=rs1[i];
1336       alloc_reg(current,i,rt1[i]);
1337       current->is32|=1LL<<rt1[i];
1338       dirty_reg(current,rt1[i]);
1339     }
1340   }
1341   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1342   {
1343     if(rt1[i]) {
1344       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1345       alloc_reg64(current,i,rt1[i]);
1346       current->is32&=~(1LL<<rt1[i]);
1347       dirty_reg(current,rt1[i]);
1348     }
1349   }
1350   if(opcode2[i]==0x3c) // DSLL32
1351   {
1352     if(rt1[i]) {
1353       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1354       alloc_reg64(current,i,rt1[i]);
1355       current->is32&=~(1LL<<rt1[i]);
1356       dirty_reg(current,rt1[i]);
1357     }
1358   }
1359   if(opcode2[i]==0x3e) // DSRL32
1360   {
1361     if(rt1[i]) {
1362       alloc_reg64(current,i,rs1[i]);
1363       if(imm[i]==32) {
1364         alloc_reg64(current,i,rt1[i]);
1365         current->is32&=~(1LL<<rt1[i]);
1366       } else {
1367         alloc_reg(current,i,rt1[i]);
1368         current->is32|=1LL<<rt1[i];
1369       }
1370       dirty_reg(current,rt1[i]);
1371     }
1372   }
1373   if(opcode2[i]==0x3f) // DSRA32
1374   {
1375     if(rt1[i]) {
1376       alloc_reg64(current,i,rs1[i]);
1377       alloc_reg(current,i,rt1[i]);
1378       current->is32|=1LL<<rt1[i];
1379       dirty_reg(current,rt1[i]);
1380     }
1381   }
1382 }
1383
1384 void shift_alloc(struct regstat *current,int i)
1385 {
1386   if(rt1[i]) {
1387     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1388     {
1389       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1390       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1391       alloc_reg(current,i,rt1[i]);
1392       if(rt1[i]==rs2[i]) {
1393         alloc_reg_temp(current,i,-1);
1394         minimum_free_regs[i]=1;
1395       }
1396       current->is32|=1LL<<rt1[i];
1397     } else { // DSLLV/DSRLV/DSRAV
1398       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1399       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1400       alloc_reg64(current,i,rt1[i]);
1401       current->is32&=~(1LL<<rt1[i]);
1402       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1403       {
1404         alloc_reg_temp(current,i,-1);
1405         minimum_free_regs[i]=1;
1406       }
1407     }
1408     clear_const(current,rs1[i]);
1409     clear_const(current,rs2[i]);
1410     clear_const(current,rt1[i]);
1411     dirty_reg(current,rt1[i]);
1412   }
1413 }
1414
1415 void alu_alloc(struct regstat *current,int i)
1416 {
1417   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418     if(rt1[i]) {
1419       if(rs1[i]&&rs2[i]) {
1420         alloc_reg(current,i,rs1[i]);
1421         alloc_reg(current,i,rs2[i]);
1422       }
1423       else {
1424         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1425         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426       }
1427       alloc_reg(current,i,rt1[i]);
1428     }
1429     current->is32|=1LL<<rt1[i];
1430   }
1431   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432     if(rt1[i]) {
1433       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434       {
1435         alloc_reg64(current,i,rs1[i]);
1436         alloc_reg64(current,i,rs2[i]);
1437         alloc_reg(current,i,rt1[i]);
1438       } else {
1439         alloc_reg(current,i,rs1[i]);
1440         alloc_reg(current,i,rs2[i]);
1441         alloc_reg(current,i,rt1[i]);
1442       }
1443     }
1444     current->is32|=1LL<<rt1[i];
1445   }
1446   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447     if(rt1[i]) {
1448       if(rs1[i]&&rs2[i]) {
1449         alloc_reg(current,i,rs1[i]);
1450         alloc_reg(current,i,rs2[i]);
1451       }
1452       else
1453       {
1454         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1455         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456       }
1457       alloc_reg(current,i,rt1[i]);
1458       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459       {
1460         if(!((current->uu>>rt1[i])&1)) {
1461           alloc_reg64(current,i,rt1[i]);
1462         }
1463         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1464           if(rs1[i]&&rs2[i]) {
1465             alloc_reg64(current,i,rs1[i]);
1466             alloc_reg64(current,i,rs2[i]);
1467           }
1468           else
1469           {
1470             // Is is really worth it to keep 64-bit values in registers?
1471             #ifdef NATIVE_64BIT
1472             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1473             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1474             #endif
1475           }
1476         }
1477         current->is32&=~(1LL<<rt1[i]);
1478       } else {
1479         current->is32|=1LL<<rt1[i];
1480       }
1481     }
1482   }
1483   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484     if(rt1[i]) {
1485       if(rs1[i]&&rs2[i]) {
1486         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1487           alloc_reg64(current,i,rs1[i]);
1488           alloc_reg64(current,i,rs2[i]);
1489           alloc_reg64(current,i,rt1[i]);
1490         } else {
1491           alloc_reg(current,i,rs1[i]);
1492           alloc_reg(current,i,rs2[i]);
1493           alloc_reg(current,i,rt1[i]);
1494         }
1495       }
1496       else {
1497         alloc_reg(current,i,rt1[i]);
1498         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1499           // DADD used as move, or zeroing
1500           // If we have a 64-bit source, then make the target 64 bits too
1501           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1502             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1503             alloc_reg64(current,i,rt1[i]);
1504           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1505             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1506             alloc_reg64(current,i,rt1[i]);
1507           }
1508           if(opcode2[i]>=0x2e&&rs2[i]) {
1509             // DSUB used as negation - 64-bit result
1510             // If we have a 32-bit register, extend it to 64 bits
1511             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1512             alloc_reg64(current,i,rt1[i]);
1513           }
1514         }
1515       }
1516       if(rs1[i]&&rs2[i]) {
1517         current->is32&=~(1LL<<rt1[i]);
1518       } else if(rs1[i]) {
1519         current->is32&=~(1LL<<rt1[i]);
1520         if((current->is32>>rs1[i])&1)
1521           current->is32|=1LL<<rt1[i];
1522       } else if(rs2[i]) {
1523         current->is32&=~(1LL<<rt1[i]);
1524         if((current->is32>>rs2[i])&1)
1525           current->is32|=1LL<<rt1[i];
1526       } else {
1527         current->is32|=1LL<<rt1[i];
1528       }
1529     }
1530   }
1531   clear_const(current,rs1[i]);
1532   clear_const(current,rs2[i]);
1533   clear_const(current,rt1[i]);
1534   dirty_reg(current,rt1[i]);
1535 }
1536
1537 void imm16_alloc(struct regstat *current,int i)
1538 {
1539   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540   else lt1[i]=rs1[i];
1541   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1542   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1543     current->is32&=~(1LL<<rt1[i]);
1544     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1545       // TODO: Could preserve the 32-bit flag if the immediate is zero
1546       alloc_reg64(current,i,rt1[i]);
1547       alloc_reg64(current,i,rs1[i]);
1548     }
1549     clear_const(current,rs1[i]);
1550     clear_const(current,rt1[i]);
1551   }
1552   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1553     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1554     current->is32|=1LL<<rt1[i];
1555     clear_const(current,rs1[i]);
1556     clear_const(current,rt1[i]);
1557   }
1558   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1559     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1560       if(rs1[i]!=rt1[i]) {
1561         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1562         alloc_reg64(current,i,rt1[i]);
1563         current->is32&=~(1LL<<rt1[i]);
1564       }
1565     }
1566     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1567     if(is_const(current,rs1[i])) {
1568       int v=get_const(current,rs1[i]);
1569       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1570       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1571       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572     }
1573     else clear_const(current,rt1[i]);
1574   }
1575   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1576     if(is_const(current,rs1[i])) {
1577       int v=get_const(current,rs1[i]);
1578       set_const(current,rt1[i],v+imm[i]);
1579     }
1580     else clear_const(current,rt1[i]);
1581     current->is32|=1LL<<rt1[i];
1582   }
1583   else {
1584     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1585     current->is32|=1LL<<rt1[i];
1586   }
1587   dirty_reg(current,rt1[i]);
1588 }
1589
1590 void load_alloc(struct regstat *current,int i)
1591 {
1592   clear_const(current,rt1[i]);
1593   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1594   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1595   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1596   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1597     alloc_reg(current,i,rt1[i]);
1598     assert(get_reg(current->regmap,rt1[i])>=0);
1599     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1600     {
1601       current->is32&=~(1LL<<rt1[i]);
1602       alloc_reg64(current,i,rt1[i]);
1603     }
1604     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1605     {
1606       current->is32&=~(1LL<<rt1[i]);
1607       alloc_reg64(current,i,rt1[i]);
1608       alloc_all(current,i);
1609       alloc_reg64(current,i,FTEMP);
1610       minimum_free_regs[i]=HOST_REGS;
1611     }
1612     else current->is32|=1LL<<rt1[i];
1613     dirty_reg(current,rt1[i]);
1614     // If using TLB, need a register for pointer to the mapping table
1615     if(using_tlb) alloc_reg(current,i,TLREG);
1616     // LWL/LWR need a temporary register for the old value
1617     if(opcode[i]==0x22||opcode[i]==0x26)
1618     {
1619       alloc_reg(current,i,FTEMP);
1620       alloc_reg_temp(current,i,-1);
1621       minimum_free_regs[i]=1;
1622     }
1623   }
1624   else
1625   {
1626     // Load to r0 or unneeded register (dummy load)
1627     // but we still need a register to calculate the address
1628     if(opcode[i]==0x22||opcode[i]==0x26)
1629     {
1630       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1631     }
1632     // If using TLB, need a register for pointer to the mapping table
1633     if(using_tlb) alloc_reg(current,i,TLREG);
1634     alloc_reg_temp(current,i,-1);
1635     minimum_free_regs[i]=1;
1636     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1637     {
1638       alloc_all(current,i);
1639       alloc_reg64(current,i,FTEMP);
1640       minimum_free_regs[i]=HOST_REGS;
1641     }
1642   }
1643 }
1644
1645 void store_alloc(struct regstat *current,int i)
1646 {
1647   clear_const(current,rs2[i]);
1648   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1649   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1650   alloc_reg(current,i,rs2[i]);
1651   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1652     alloc_reg64(current,i,rs2[i]);
1653     if(rs2[i]) alloc_reg(current,i,FTEMP);
1654   }
1655   // If using TLB, need a register for pointer to the mapping table
1656   if(using_tlb) alloc_reg(current,i,TLREG);
1657   #if defined(HOST_IMM8)
1658   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1659   else alloc_reg(current,i,INVCP);
1660   #endif
1661   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1662     alloc_reg(current,i,FTEMP);
1663   }
1664   // We need a temporary register for address generation
1665   alloc_reg_temp(current,i,-1);
1666   minimum_free_regs[i]=1;
1667 }
1668
1669 void c1ls_alloc(struct regstat *current,int i)
1670 {
1671   //clear_const(current,rs1[i]); // FIXME
1672   clear_const(current,rt1[i]);
1673   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1674   alloc_reg(current,i,CSREG); // Status
1675   alloc_reg(current,i,FTEMP);
1676   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1677     alloc_reg64(current,i,FTEMP);
1678   }
1679   // If using TLB, need a register for pointer to the mapping table
1680   if(using_tlb) alloc_reg(current,i,TLREG);
1681   #if defined(HOST_IMM8)
1682   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1683   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1684     alloc_reg(current,i,INVCP);
1685   #endif
1686   // We need a temporary register for address generation
1687   alloc_reg_temp(current,i,-1);
1688 }
1689
1690 void c2ls_alloc(struct regstat *current,int i)
1691 {
1692   clear_const(current,rt1[i]);
1693   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1694   alloc_reg(current,i,FTEMP);
1695   // If using TLB, need a register for pointer to the mapping table
1696   if(using_tlb) alloc_reg(current,i,TLREG);
1697   #if defined(HOST_IMM8)
1698   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1699   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1700     alloc_reg(current,i,INVCP);
1701   #endif
1702   // We need a temporary register for address generation
1703   alloc_reg_temp(current,i,-1);
1704   minimum_free_regs[i]=1;
1705 }
1706
1707 #ifndef multdiv_alloc
1708 void multdiv_alloc(struct regstat *current,int i)
1709 {
1710   //  case 0x18: MULT
1711   //  case 0x19: MULTU
1712   //  case 0x1A: DIV
1713   //  case 0x1B: DIVU
1714   //  case 0x1C: DMULT
1715   //  case 0x1D: DMULTU
1716   //  case 0x1E: DDIV
1717   //  case 0x1F: DDIVU
1718   clear_const(current,rs1[i]);
1719   clear_const(current,rs2[i]);
1720   if(rs1[i]&&rs2[i])
1721   {
1722     if((opcode2[i]&4)==0) // 32-bit
1723     {
1724       current->u&=~(1LL<<HIREG);
1725       current->u&=~(1LL<<LOREG);
1726       alloc_reg(current,i,HIREG);
1727       alloc_reg(current,i,LOREG);
1728       alloc_reg(current,i,rs1[i]);
1729       alloc_reg(current,i,rs2[i]);
1730       current->is32|=1LL<<HIREG;
1731       current->is32|=1LL<<LOREG;
1732       dirty_reg(current,HIREG);
1733       dirty_reg(current,LOREG);
1734     }
1735     else // 64-bit
1736     {
1737       current->u&=~(1LL<<HIREG);
1738       current->u&=~(1LL<<LOREG);
1739       current->uu&=~(1LL<<HIREG);
1740       current->uu&=~(1LL<<LOREG);
1741       alloc_reg64(current,i,HIREG);
1742       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1743       alloc_reg64(current,i,rs1[i]);
1744       alloc_reg64(current,i,rs2[i]);
1745       alloc_all(current,i);
1746       current->is32&=~(1LL<<HIREG);
1747       current->is32&=~(1LL<<LOREG);
1748       dirty_reg(current,HIREG);
1749       dirty_reg(current,LOREG);
1750       minimum_free_regs[i]=HOST_REGS;
1751     }
1752   }
1753   else
1754   {
1755     // Multiply by zero is zero.
1756     // MIPS does not have a divide by zero exception.
1757     // The result is undefined, we return zero.
1758     alloc_reg(current,i,HIREG);
1759     alloc_reg(current,i,LOREG);
1760     current->is32|=1LL<<HIREG;
1761     current->is32|=1LL<<LOREG;
1762     dirty_reg(current,HIREG);
1763     dirty_reg(current,LOREG);
1764   }
1765 }
1766 #endif
1767
1768 void cop0_alloc(struct regstat *current,int i)
1769 {
1770   if(opcode2[i]==0) // MFC0
1771   {
1772     if(rt1[i]) {
1773       clear_const(current,rt1[i]);
1774       alloc_all(current,i);
1775       alloc_reg(current,i,rt1[i]);
1776       current->is32|=1LL<<rt1[i];
1777       dirty_reg(current,rt1[i]);
1778     }
1779   }
1780   else if(opcode2[i]==4) // MTC0
1781   {
1782     if(rs1[i]){
1783       clear_const(current,rs1[i]);
1784       alloc_reg(current,i,rs1[i]);
1785       alloc_all(current,i);
1786     }
1787     else {
1788       alloc_all(current,i); // FIXME: Keep r0
1789       current->u&=~1LL;
1790       alloc_reg(current,i,0);
1791     }
1792   }
1793   else
1794   {
1795     // TLBR/TLBWI/TLBWR/TLBP/ERET
1796     assert(opcode2[i]==0x10);
1797     alloc_all(current,i);
1798   }
1799   minimum_free_regs[i]=HOST_REGS;
1800 }
1801
1802 void cop1_alloc(struct regstat *current,int i)
1803 {
1804   alloc_reg(current,i,CSREG); // Load status
1805   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1806   {
1807     if(rt1[i]){
1808       clear_const(current,rt1[i]);
1809       if(opcode2[i]==1) {
1810         alloc_reg64(current,i,rt1[i]); // DMFC1
1811         current->is32&=~(1LL<<rt1[i]);
1812       }else{
1813         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1814         current->is32|=1LL<<rt1[i];
1815       }
1816       dirty_reg(current,rt1[i]);
1817     }
1818     alloc_reg_temp(current,i,-1);
1819   }
1820   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1821   {
1822     if(rs1[i]){
1823       clear_const(current,rs1[i]);
1824       if(opcode2[i]==5)
1825         alloc_reg64(current,i,rs1[i]); // DMTC1
1826       else
1827         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1828       alloc_reg_temp(current,i,-1);
1829     }
1830     else {
1831       current->u&=~1LL;
1832       alloc_reg(current,i,0);
1833       alloc_reg_temp(current,i,-1);
1834     }
1835   }
1836   minimum_free_regs[i]=1;
1837 }
1838 void fconv_alloc(struct regstat *current,int i)
1839 {
1840   alloc_reg(current,i,CSREG); // Load status
1841   alloc_reg_temp(current,i,-1);
1842   minimum_free_regs[i]=1;
1843 }
1844 void float_alloc(struct regstat *current,int i)
1845 {
1846   alloc_reg(current,i,CSREG); // Load status
1847   alloc_reg_temp(current,i,-1);
1848   minimum_free_regs[i]=1;
1849 }
1850 void c2op_alloc(struct regstat *current,int i)
1851 {
1852   alloc_reg_temp(current,i,-1);
1853 }
1854 void fcomp_alloc(struct regstat *current,int i)
1855 {
1856   alloc_reg(current,i,CSREG); // Load status
1857   alloc_reg(current,i,FSREG); // Load flags
1858   dirty_reg(current,FSREG); // Flag will be modified
1859   alloc_reg_temp(current,i,-1);
1860   minimum_free_regs[i]=1;
1861 }
1862
1863 void syscall_alloc(struct regstat *current,int i)
1864 {
1865   alloc_cc(current,i);
1866   dirty_reg(current,CCREG);
1867   alloc_all(current,i);
1868   minimum_free_regs[i]=HOST_REGS;
1869   current->isconst=0;
1870 }
1871
1872 void delayslot_alloc(struct regstat *current,int i)
1873 {
1874   switch(itype[i]) {
1875     case UJUMP:
1876     case CJUMP:
1877     case SJUMP:
1878     case RJUMP:
1879     case FJUMP:
1880     case SYSCALL:
1881     case HLECALL:
1882     case SPAN:
1883       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1884       printf("Disabled speculative precompilation\n");
1885       stop_after_jal=1;
1886       break;
1887     case IMM16:
1888       imm16_alloc(current,i);
1889       break;
1890     case LOAD:
1891     case LOADLR:
1892       load_alloc(current,i);
1893       break;
1894     case STORE:
1895     case STORELR:
1896       store_alloc(current,i);
1897       break;
1898     case ALU:
1899       alu_alloc(current,i);
1900       break;
1901     case SHIFT:
1902       shift_alloc(current,i);
1903       break;
1904     case MULTDIV:
1905       multdiv_alloc(current,i);
1906       break;
1907     case SHIFTIMM:
1908       shiftimm_alloc(current,i);
1909       break;
1910     case MOV:
1911       mov_alloc(current,i);
1912       break;
1913     case COP0:
1914       cop0_alloc(current,i);
1915       break;
1916     case COP1:
1917     case COP2:
1918       cop1_alloc(current,i);
1919       break;
1920     case C1LS:
1921       c1ls_alloc(current,i);
1922       break;
1923     case C2LS:
1924       c2ls_alloc(current,i);
1925       break;
1926     case FCONV:
1927       fconv_alloc(current,i);
1928       break;
1929     case FLOAT:
1930       float_alloc(current,i);
1931       break;
1932     case FCOMP:
1933       fcomp_alloc(current,i);
1934       break;
1935     case C2OP:
1936       c2op_alloc(current,i);
1937       break;
1938   }
1939 }
1940
1941 // Special case where a branch and delay slot span two pages in virtual memory
1942 static void pagespan_alloc(struct regstat *current,int i)
1943 {
1944   current->isconst=0;
1945   current->wasconst=0;
1946   regs[i].wasconst=0;
1947   minimum_free_regs[i]=HOST_REGS;
1948   alloc_all(current,i);
1949   alloc_cc(current,i);
1950   dirty_reg(current,CCREG);
1951   if(opcode[i]==3) // JAL
1952   {
1953     alloc_reg(current,i,31);
1954     dirty_reg(current,31);
1955   }
1956   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1957   {
1958     alloc_reg(current,i,rs1[i]);
1959     if (rt1[i]!=0) {
1960       alloc_reg(current,i,rt1[i]);
1961       dirty_reg(current,rt1[i]);
1962     }
1963   }
1964   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1965   {
1966     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1967     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1968     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1969     {
1970       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1971       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1972     }
1973   }
1974   else
1975   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1976   {
1977     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1978     if(!((current->is32>>rs1[i])&1))
1979     {
1980       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1981     }
1982   }
1983   else
1984   if(opcode[i]==0x11) // BC1
1985   {
1986     alloc_reg(current,i,FSREG);
1987     alloc_reg(current,i,CSREG);
1988   }
1989   //else ...
1990 }
1991
1992 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1993 {
1994   stubs[stubcount][0]=type;
1995   stubs[stubcount][1]=addr;
1996   stubs[stubcount][2]=retaddr;
1997   stubs[stubcount][3]=a;
1998   stubs[stubcount][4]=b;
1999   stubs[stubcount][5]=c;
2000   stubs[stubcount][6]=d;
2001   stubs[stubcount][7]=e;
2002   stubcount++;
2003 }
2004
2005 // Write out a single register
2006 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2007 {
2008   int hr;
2009   for(hr=0;hr<HOST_REGS;hr++) {
2010     if(hr!=EXCLUDE_REG) {
2011       if((regmap[hr]&63)==r) {
2012         if((dirty>>hr)&1) {
2013           if(regmap[hr]<64) {
2014             emit_storereg(r,hr);
2015 #ifndef FORCE32
2016             if((is32>>regmap[hr])&1) {
2017               emit_sarimm(hr,31,hr);
2018               emit_storereg(r|64,hr);
2019             }
2020 #endif
2021           }else{
2022             emit_storereg(r|64,hr);
2023           }
2024         }
2025       }
2026     }
2027   }
2028 }
2029
2030 int mchecksum()
2031 {
2032   //if(!tracedebug) return 0;
2033   int i;
2034   int sum=0;
2035   for(i=0;i<2097152;i++) {
2036     unsigned int temp=sum;
2037     sum<<=1;
2038     sum|=(~temp)>>31;
2039     sum^=((u_int *)rdram)[i];
2040   }
2041   return sum;
2042 }
2043 int rchecksum()
2044 {
2045   int i;
2046   int sum=0;
2047   for(i=0;i<64;i++)
2048     sum^=((u_int *)reg)[i];
2049   return sum;
2050 }
2051 void rlist()
2052 {
2053   int i;
2054   printf("TRACE: ");
2055   for(i=0;i<32;i++)
2056     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2057   printf("\n");
2058 #ifndef DISABLE_COP1
2059   printf("TRACE: ");
2060   for(i=0;i<32;i++)
2061     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2062   printf("\n");
2063 #endif
2064 }
2065
2066 void enabletrace()
2067 {
2068   tracedebug=1;
2069 }
2070
2071 void memdebug(int i)
2072 {
2073   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2074   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2075   //rlist();
2076   //if(tracedebug) {
2077   //if(Count>=-2084597794) {
2078   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2079   //if(0) {
2080     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2081     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2082     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2083     rlist();
2084     #ifdef __i386__
2085     printf("TRACE: %x\n",(&i)[-1]);
2086     #endif
2087     #ifdef __arm__
2088     int j;
2089     printf("TRACE: %x \n",(&j)[10]);
2090     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2091     #endif
2092     //fflush(stdout);
2093   }
2094   //printf("TRACE: %x\n",(&i)[-1]);
2095 }
2096
2097 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2098 {
2099   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2100 }
2101
2102 void alu_assemble(int i,struct regstat *i_regs)
2103 {
2104   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2105     if(rt1[i]) {
2106       signed char s1,s2,t;
2107       t=get_reg(i_regs->regmap,rt1[i]);
2108       if(t>=0) {
2109         s1=get_reg(i_regs->regmap,rs1[i]);
2110         s2=get_reg(i_regs->regmap,rs2[i]);
2111         if(rs1[i]&&rs2[i]) {
2112           assert(s1>=0);
2113           assert(s2>=0);
2114           if(opcode2[i]&2) emit_sub(s1,s2,t);
2115           else emit_add(s1,s2,t);
2116         }
2117         else if(rs1[i]) {
2118           if(s1>=0) emit_mov(s1,t);
2119           else emit_loadreg(rs1[i],t);
2120         }
2121         else if(rs2[i]) {
2122           if(s2>=0) {
2123             if(opcode2[i]&2) emit_neg(s2,t);
2124             else emit_mov(s2,t);
2125           }
2126           else {
2127             emit_loadreg(rs2[i],t);
2128             if(opcode2[i]&2) emit_neg(t,t);
2129           }
2130         }
2131         else emit_zeroreg(t);
2132       }
2133     }
2134   }
2135   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2136     if(rt1[i]) {
2137       signed char s1l,s2l,s1h,s2h,tl,th;
2138       tl=get_reg(i_regs->regmap,rt1[i]);
2139       th=get_reg(i_regs->regmap,rt1[i]|64);
2140       if(tl>=0) {
2141         s1l=get_reg(i_regs->regmap,rs1[i]);
2142         s2l=get_reg(i_regs->regmap,rs2[i]);
2143         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2144         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2145         if(rs1[i]&&rs2[i]) {
2146           assert(s1l>=0);
2147           assert(s2l>=0);
2148           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2149           else emit_adds(s1l,s2l,tl);
2150           if(th>=0) {
2151             #ifdef INVERTED_CARRY
2152             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2153             #else
2154             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2155             #endif
2156             else emit_add(s1h,s2h,th);
2157           }
2158         }
2159         else if(rs1[i]) {
2160           if(s1l>=0) emit_mov(s1l,tl);
2161           else emit_loadreg(rs1[i],tl);
2162           if(th>=0) {
2163             if(s1h>=0) emit_mov(s1h,th);
2164             else emit_loadreg(rs1[i]|64,th);
2165           }
2166         }
2167         else if(rs2[i]) {
2168           if(s2l>=0) {
2169             if(opcode2[i]&2) emit_negs(s2l,tl);
2170             else emit_mov(s2l,tl);
2171           }
2172           else {
2173             emit_loadreg(rs2[i],tl);
2174             if(opcode2[i]&2) emit_negs(tl,tl);
2175           }
2176           if(th>=0) {
2177             #ifdef INVERTED_CARRY
2178             if(s2h>=0) emit_mov(s2h,th);
2179             else emit_loadreg(rs2[i]|64,th);
2180             if(opcode2[i]&2) {
2181               emit_adcimm(-1,th); // x86 has inverted carry flag
2182               emit_not(th,th);
2183             }
2184             #else
2185             if(opcode2[i]&2) {
2186               if(s2h>=0) emit_rscimm(s2h,0,th);
2187               else {
2188                 emit_loadreg(rs2[i]|64,th);
2189                 emit_rscimm(th,0,th);
2190               }
2191             }else{
2192               if(s2h>=0) emit_mov(s2h,th);
2193               else emit_loadreg(rs2[i]|64,th);
2194             }
2195             #endif
2196           }
2197         }
2198         else {
2199           emit_zeroreg(tl);
2200           if(th>=0) emit_zeroreg(th);
2201         }
2202       }
2203     }
2204   }
2205   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2206     if(rt1[i]) {
2207       signed char s1l,s1h,s2l,s2h,t;
2208       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2209       {
2210         t=get_reg(i_regs->regmap,rt1[i]);
2211         //assert(t>=0);
2212         if(t>=0) {
2213           s1l=get_reg(i_regs->regmap,rs1[i]);
2214           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2215           s2l=get_reg(i_regs->regmap,rs2[i]);
2216           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2217           if(rs2[i]==0) // rx<r0
2218           {
2219             assert(s1h>=0);
2220             if(opcode2[i]==0x2a) // SLT
2221               emit_shrimm(s1h,31,t);
2222             else // SLTU (unsigned can not be less than zero)
2223               emit_zeroreg(t);
2224           }
2225           else if(rs1[i]==0) // r0<rx
2226           {
2227             assert(s2h>=0);
2228             if(opcode2[i]==0x2a) // SLT
2229               emit_set_gz64_32(s2h,s2l,t);
2230             else // SLTU (set if not zero)
2231               emit_set_nz64_32(s2h,s2l,t);
2232           }
2233           else {
2234             assert(s1l>=0);assert(s1h>=0);
2235             assert(s2l>=0);assert(s2h>=0);
2236             if(opcode2[i]==0x2a) // SLT
2237               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2238             else // SLTU
2239               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2240           }
2241         }
2242       } else {
2243         t=get_reg(i_regs->regmap,rt1[i]);
2244         //assert(t>=0);
2245         if(t>=0) {
2246           s1l=get_reg(i_regs->regmap,rs1[i]);
2247           s2l=get_reg(i_regs->regmap,rs2[i]);
2248           if(rs2[i]==0) // rx<r0
2249           {
2250             assert(s1l>=0);
2251             if(opcode2[i]==0x2a) // SLT
2252               emit_shrimm(s1l,31,t);
2253             else // SLTU (unsigned can not be less than zero)
2254               emit_zeroreg(t);
2255           }
2256           else if(rs1[i]==0) // r0<rx
2257           {
2258             assert(s2l>=0);
2259             if(opcode2[i]==0x2a) // SLT
2260               emit_set_gz32(s2l,t);
2261             else // SLTU (set if not zero)
2262               emit_set_nz32(s2l,t);
2263           }
2264           else{
2265             assert(s1l>=0);assert(s2l>=0);
2266             if(opcode2[i]==0x2a) // SLT
2267               emit_set_if_less32(s1l,s2l,t);
2268             else // SLTU
2269               emit_set_if_carry32(s1l,s2l,t);
2270           }
2271         }
2272       }
2273     }
2274   }
2275   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2276     if(rt1[i]) {
2277       signed char s1l,s1h,s2l,s2h,th,tl;
2278       tl=get_reg(i_regs->regmap,rt1[i]);
2279       th=get_reg(i_regs->regmap,rt1[i]|64);
2280       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2281       {
2282         assert(tl>=0);
2283         if(tl>=0) {
2284           s1l=get_reg(i_regs->regmap,rs1[i]);
2285           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2286           s2l=get_reg(i_regs->regmap,rs2[i]);
2287           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2288           if(rs1[i]&&rs2[i]) {
2289             assert(s1l>=0);assert(s1h>=0);
2290             assert(s2l>=0);assert(s2h>=0);
2291             if(opcode2[i]==0x24) { // AND
2292               emit_and(s1l,s2l,tl);
2293               emit_and(s1h,s2h,th);
2294             } else
2295             if(opcode2[i]==0x25) { // OR
2296               emit_or(s1l,s2l,tl);
2297               emit_or(s1h,s2h,th);
2298             } else
2299             if(opcode2[i]==0x26) { // XOR
2300               emit_xor(s1l,s2l,tl);
2301               emit_xor(s1h,s2h,th);
2302             } else
2303             if(opcode2[i]==0x27) { // NOR
2304               emit_or(s1l,s2l,tl);
2305               emit_or(s1h,s2h,th);
2306               emit_not(tl,tl);
2307               emit_not(th,th);
2308             }
2309           }
2310           else
2311           {
2312             if(opcode2[i]==0x24) { // AND
2313               emit_zeroreg(tl);
2314               emit_zeroreg(th);
2315             } else
2316             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2317               if(rs1[i]){
2318                 if(s1l>=0) emit_mov(s1l,tl);
2319                 else emit_loadreg(rs1[i],tl);
2320                 if(s1h>=0) emit_mov(s1h,th);
2321                 else emit_loadreg(rs1[i]|64,th);
2322               }
2323               else
2324               if(rs2[i]){
2325                 if(s2l>=0) emit_mov(s2l,tl);
2326                 else emit_loadreg(rs2[i],tl);
2327                 if(s2h>=0) emit_mov(s2h,th);
2328                 else emit_loadreg(rs2[i]|64,th);
2329               }
2330               else{
2331                 emit_zeroreg(tl);
2332                 emit_zeroreg(th);
2333               }
2334             } else
2335             if(opcode2[i]==0x27) { // NOR
2336               if(rs1[i]){
2337                 if(s1l>=0) emit_not(s1l,tl);
2338                 else{
2339                   emit_loadreg(rs1[i],tl);
2340                   emit_not(tl,tl);
2341                 }
2342                 if(s1h>=0) emit_not(s1h,th);
2343                 else{
2344                   emit_loadreg(rs1[i]|64,th);
2345                   emit_not(th,th);
2346                 }
2347               }
2348               else
2349               if(rs2[i]){
2350                 if(s2l>=0) emit_not(s2l,tl);
2351                 else{
2352                   emit_loadreg(rs2[i],tl);
2353                   emit_not(tl,tl);
2354                 }
2355                 if(s2h>=0) emit_not(s2h,th);
2356                 else{
2357                   emit_loadreg(rs2[i]|64,th);
2358                   emit_not(th,th);
2359                 }
2360               }
2361               else {
2362                 emit_movimm(-1,tl);
2363                 emit_movimm(-1,th);
2364               }
2365             }
2366           }
2367         }
2368       }
2369       else
2370       {
2371         // 32 bit
2372         if(tl>=0) {
2373           s1l=get_reg(i_regs->regmap,rs1[i]);
2374           s2l=get_reg(i_regs->regmap,rs2[i]);
2375           if(rs1[i]&&rs2[i]) {
2376             assert(s1l>=0);
2377             assert(s2l>=0);
2378             if(opcode2[i]==0x24) { // AND
2379               emit_and(s1l,s2l,tl);
2380             } else
2381             if(opcode2[i]==0x25) { // OR
2382               emit_or(s1l,s2l,tl);
2383             } else
2384             if(opcode2[i]==0x26) { // XOR
2385               emit_xor(s1l,s2l,tl);
2386             } else
2387             if(opcode2[i]==0x27) { // NOR
2388               emit_or(s1l,s2l,tl);
2389               emit_not(tl,tl);
2390             }
2391           }
2392           else
2393           {
2394             if(opcode2[i]==0x24) { // AND
2395               emit_zeroreg(tl);
2396             } else
2397             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2398               if(rs1[i]){
2399                 if(s1l>=0) emit_mov(s1l,tl);
2400                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2401               }
2402               else
2403               if(rs2[i]){
2404                 if(s2l>=0) emit_mov(s2l,tl);
2405                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2406               }
2407               else emit_zeroreg(tl);
2408             } else
2409             if(opcode2[i]==0x27) { // NOR
2410               if(rs1[i]){
2411                 if(s1l>=0) emit_not(s1l,tl);
2412                 else {
2413                   emit_loadreg(rs1[i],tl);
2414                   emit_not(tl,tl);
2415                 }
2416               }
2417               else
2418               if(rs2[i]){
2419                 if(s2l>=0) emit_not(s2l,tl);
2420                 else {
2421                   emit_loadreg(rs2[i],tl);
2422                   emit_not(tl,tl);
2423                 }
2424               }
2425               else emit_movimm(-1,tl);
2426             }
2427           }
2428         }
2429       }
2430     }
2431   }
2432 }
2433
2434 void imm16_assemble(int i,struct regstat *i_regs)
2435 {
2436   if (opcode[i]==0x0f) { // LUI
2437     if(rt1[i]) {
2438       signed char t;
2439       t=get_reg(i_regs->regmap,rt1[i]);
2440       //assert(t>=0);
2441       if(t>=0) {
2442         if(!((i_regs->isconst>>t)&1))
2443           emit_movimm(imm[i]<<16,t);
2444       }
2445     }
2446   }
2447   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2448     if(rt1[i]) {
2449       signed char s,t;
2450       t=get_reg(i_regs->regmap,rt1[i]);
2451       s=get_reg(i_regs->regmap,rs1[i]);
2452       if(rs1[i]) {
2453         //assert(t>=0);
2454         //assert(s>=0);
2455         if(t>=0) {
2456           if(!((i_regs->isconst>>t)&1)) {
2457             if(s<0) {
2458               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2459               emit_addimm(t,imm[i],t);
2460             }else{
2461               if(!((i_regs->wasconst>>s)&1))
2462                 emit_addimm(s,imm[i],t);
2463               else
2464                 emit_movimm(constmap[i][s]+imm[i],t);
2465             }
2466           }
2467         }
2468       } else {
2469         if(t>=0) {
2470           if(!((i_regs->isconst>>t)&1))
2471             emit_movimm(imm[i],t);
2472         }
2473       }
2474     }
2475   }
2476   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2477     if(rt1[i]) {
2478       signed char sh,sl,th,tl;
2479       th=get_reg(i_regs->regmap,rt1[i]|64);
2480       tl=get_reg(i_regs->regmap,rt1[i]);
2481       sh=get_reg(i_regs->regmap,rs1[i]|64);
2482       sl=get_reg(i_regs->regmap,rs1[i]);
2483       if(tl>=0) {
2484         if(rs1[i]) {
2485           assert(sh>=0);
2486           assert(sl>=0);
2487           if(th>=0) {
2488             emit_addimm64_32(sh,sl,imm[i],th,tl);
2489           }
2490           else {
2491             emit_addimm(sl,imm[i],tl);
2492           }
2493         } else {
2494           emit_movimm(imm[i],tl);
2495           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2496         }
2497       }
2498     }
2499   }
2500   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2501     if(rt1[i]) {
2502       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2503       signed char sh,sl,t;
2504       t=get_reg(i_regs->regmap,rt1[i]);
2505       sh=get_reg(i_regs->regmap,rs1[i]|64);
2506       sl=get_reg(i_regs->regmap,rs1[i]);
2507       //assert(t>=0);
2508       if(t>=0) {
2509         if(rs1[i]>0) {
2510           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2511           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2512             if(opcode[i]==0x0a) { // SLTI
2513               if(sl<0) {
2514                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2515                 emit_slti32(t,imm[i],t);
2516               }else{
2517                 emit_slti32(sl,imm[i],t);
2518               }
2519             }
2520             else { // SLTIU
2521               if(sl<0) {
2522                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2523                 emit_sltiu32(t,imm[i],t);
2524               }else{
2525                 emit_sltiu32(sl,imm[i],t);
2526               }
2527             }
2528           }else{ // 64-bit
2529             assert(sl>=0);
2530             if(opcode[i]==0x0a) // SLTI
2531               emit_slti64_32(sh,sl,imm[i],t);
2532             else // SLTIU
2533               emit_sltiu64_32(sh,sl,imm[i],t);
2534           }
2535         }else{
2536           // SLTI(U) with r0 is just stupid,
2537           // nonetheless examples can be found
2538           if(opcode[i]==0x0a) // SLTI
2539             if(0<imm[i]) emit_movimm(1,t);
2540             else emit_zeroreg(t);
2541           else // SLTIU
2542           {
2543             if(imm[i]) emit_movimm(1,t);
2544             else emit_zeroreg(t);
2545           }
2546         }
2547       }
2548     }
2549   }
2550   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2551     if(rt1[i]) {
2552       signed char sh,sl,th,tl;
2553       th=get_reg(i_regs->regmap,rt1[i]|64);
2554       tl=get_reg(i_regs->regmap,rt1[i]);
2555       sh=get_reg(i_regs->regmap,rs1[i]|64);
2556       sl=get_reg(i_regs->regmap,rs1[i]);
2557       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2558         if(opcode[i]==0x0c) //ANDI
2559         {
2560           if(rs1[i]) {
2561             if(sl<0) {
2562               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2563               emit_andimm(tl,imm[i],tl);
2564             }else{
2565               if(!((i_regs->wasconst>>sl)&1))
2566                 emit_andimm(sl,imm[i],tl);
2567               else
2568                 emit_movimm(constmap[i][sl]&imm[i],tl);
2569             }
2570           }
2571           else
2572             emit_zeroreg(tl);
2573           if(th>=0) emit_zeroreg(th);
2574         }
2575         else
2576         {
2577           if(rs1[i]) {
2578             if(sl<0) {
2579               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2580             }
2581             if(th>=0) {
2582               if(sh<0) {
2583                 emit_loadreg(rs1[i]|64,th);
2584               }else{
2585                 emit_mov(sh,th);
2586               }
2587             }
2588             if(opcode[i]==0x0d) //ORI
2589             if(sl<0) {
2590               emit_orimm(tl,imm[i],tl);
2591             }else{
2592               if(!((i_regs->wasconst>>sl)&1))
2593                 emit_orimm(sl,imm[i],tl);
2594               else
2595                 emit_movimm(constmap[i][sl]|imm[i],tl);
2596             }
2597             if(opcode[i]==0x0e) //XORI
2598             if(sl<0) {
2599               emit_xorimm(tl,imm[i],tl);
2600             }else{
2601               if(!((i_regs->wasconst>>sl)&1))
2602                 emit_xorimm(sl,imm[i],tl);
2603               else
2604                 emit_movimm(constmap[i][sl]^imm[i],tl);
2605             }
2606           }
2607           else {
2608             emit_movimm(imm[i],tl);
2609             if(th>=0) emit_zeroreg(th);
2610           }
2611         }
2612       }
2613     }
2614   }
2615 }
2616
2617 void shiftimm_assemble(int i,struct regstat *i_regs)
2618 {
2619   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2620   {
2621     if(rt1[i]) {
2622       signed char s,t;
2623       t=get_reg(i_regs->regmap,rt1[i]);
2624       s=get_reg(i_regs->regmap,rs1[i]);
2625       //assert(t>=0);
2626       if(t>=0){
2627         if(rs1[i]==0)
2628         {
2629           emit_zeroreg(t);
2630         }
2631         else
2632         {
2633           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2634           if(imm[i]) {
2635             if(opcode2[i]==0) // SLL
2636             {
2637               emit_shlimm(s<0?t:s,imm[i],t);
2638             }
2639             if(opcode2[i]==2) // SRL
2640             {
2641               emit_shrimm(s<0?t:s,imm[i],t);
2642             }
2643             if(opcode2[i]==3) // SRA
2644             {
2645               emit_sarimm(s<0?t:s,imm[i],t);
2646             }
2647           }else{
2648             // Shift by zero
2649             if(s>=0 && s!=t) emit_mov(s,t);
2650           }
2651         }
2652       }
2653       //emit_storereg(rt1[i],t); //DEBUG
2654     }
2655   }
2656   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2657   {
2658     if(rt1[i]) {
2659       signed char sh,sl,th,tl;
2660       th=get_reg(i_regs->regmap,rt1[i]|64);
2661       tl=get_reg(i_regs->regmap,rt1[i]);
2662       sh=get_reg(i_regs->regmap,rs1[i]|64);
2663       sl=get_reg(i_regs->regmap,rs1[i]);
2664       if(tl>=0) {
2665         if(rs1[i]==0)
2666         {
2667           emit_zeroreg(tl);
2668           if(th>=0) emit_zeroreg(th);
2669         }
2670         else
2671         {
2672           assert(sl>=0);
2673           assert(sh>=0);
2674           if(imm[i]) {
2675             if(opcode2[i]==0x38) // DSLL
2676             {
2677               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2678               emit_shlimm(sl,imm[i],tl);
2679             }
2680             if(opcode2[i]==0x3a) // DSRL
2681             {
2682               emit_shrdimm(sl,sh,imm[i],tl);
2683               if(th>=0) emit_shrimm(sh,imm[i],th);
2684             }
2685             if(opcode2[i]==0x3b) // DSRA
2686             {
2687               emit_shrdimm(sl,sh,imm[i],tl);
2688               if(th>=0) emit_sarimm(sh,imm[i],th);
2689             }
2690           }else{
2691             // Shift by zero
2692             if(sl!=tl) emit_mov(sl,tl);
2693             if(th>=0&&sh!=th) emit_mov(sh,th);
2694           }
2695         }
2696       }
2697     }
2698   }
2699   if(opcode2[i]==0x3c) // DSLL32
2700   {
2701     if(rt1[i]) {
2702       signed char sl,tl,th;
2703       tl=get_reg(i_regs->regmap,rt1[i]);
2704       th=get_reg(i_regs->regmap,rt1[i]|64);
2705       sl=get_reg(i_regs->regmap,rs1[i]);
2706       if(th>=0||tl>=0){
2707         assert(tl>=0);
2708         assert(th>=0);
2709         assert(sl>=0);
2710         emit_mov(sl,th);
2711         emit_zeroreg(tl);
2712         if(imm[i]>32)
2713         {
2714           emit_shlimm(th,imm[i]&31,th);
2715         }
2716       }
2717     }
2718   }
2719   if(opcode2[i]==0x3e) // DSRL32
2720   {
2721     if(rt1[i]) {
2722       signed char sh,tl,th;
2723       tl=get_reg(i_regs->regmap,rt1[i]);
2724       th=get_reg(i_regs->regmap,rt1[i]|64);
2725       sh=get_reg(i_regs->regmap,rs1[i]|64);
2726       if(tl>=0){
2727         assert(sh>=0);
2728         emit_mov(sh,tl);
2729         if(th>=0) emit_zeroreg(th);
2730         if(imm[i]>32)
2731         {
2732           emit_shrimm(tl,imm[i]&31,tl);
2733         }
2734       }
2735     }
2736   }
2737   if(opcode2[i]==0x3f) // DSRA32
2738   {
2739     if(rt1[i]) {
2740       signed char sh,tl;
2741       tl=get_reg(i_regs->regmap,rt1[i]);
2742       sh=get_reg(i_regs->regmap,rs1[i]|64);
2743       if(tl>=0){
2744         assert(sh>=0);
2745         emit_mov(sh,tl);
2746         if(imm[i]>32)
2747         {
2748           emit_sarimm(tl,imm[i]&31,tl);
2749         }
2750       }
2751     }
2752   }
2753 }
2754
2755 #ifndef shift_assemble
2756 void shift_assemble(int i,struct regstat *i_regs)
2757 {
2758   printf("Need shift_assemble for this architecture.\n");
2759   exit(1);
2760 }
2761 #endif
2762
2763 void load_assemble(int i,struct regstat *i_regs)
2764 {
2765   int s,th,tl,addr,map=-1;
2766   int offset;
2767   int jaddr=0;
2768   int memtarget=0,c=0;
2769   int fastload_reg_override=0;
2770   u_int hr,reglist=0;
2771   th=get_reg(i_regs->regmap,rt1[i]|64);
2772   tl=get_reg(i_regs->regmap,rt1[i]);
2773   s=get_reg(i_regs->regmap,rs1[i]);
2774   offset=imm[i];
2775   for(hr=0;hr<HOST_REGS;hr++) {
2776     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2777   }
2778   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2779   if(s>=0) {
2780     c=(i_regs->wasconst>>s)&1;
2781     if (c) {
2782       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2783       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2784     }
2785   }
2786   //printf("load_assemble: c=%d\n",c);
2787   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2788   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2789 #ifdef PCSX
2790   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2791     ||rt1[i]==0) {
2792       // could be FIFO, must perform the read
2793       // ||dummy read
2794       assem_debug("(forced read)\n");
2795       tl=get_reg(i_regs->regmap,-1);
2796       assert(tl>=0);
2797   }
2798 #endif
2799   if(offset||s<0||c) addr=tl;
2800   else addr=s;
2801   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2802  if(tl>=0) {
2803   //printf("load_assemble: c=%d\n",c);
2804   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2805   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2806   reglist&=~(1<<tl);
2807   if(th>=0) reglist&=~(1<<th);
2808   if(!using_tlb) {
2809     if(!c) {
2810       #ifdef RAM_OFFSET
2811       map=get_reg(i_regs->regmap,ROREG);
2812       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2813       #endif
2814 //#define R29_HACK 1
2815       #ifdef R29_HACK
2816       // Strmnnrmn's speed hack
2817       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2818       #endif
2819       {
2820         #ifdef PCSX
2821         if(sp_in_mirror&&rs1[i]==29) {
2822           emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2823           emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
2824           fastload_reg_override=HOST_TEMPREG;
2825         }
2826         else
2827         #endif
2828         emit_cmpimm(addr,RAM_SIZE);
2829         jaddr=(int)out;
2830         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2831         // Hint to branch predictor that the branch is unlikely to be taken
2832         if(rs1[i]>=28)
2833           emit_jno_unlikely(0);
2834         else
2835         #endif
2836         emit_jno(0);
2837       }
2838     }
2839   }else{ // using tlb
2840     int x=0;
2841     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2842     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2843     map=get_reg(i_regs->regmap,TLREG);
2844     assert(map>=0);
2845     reglist&=~(1<<map);
2846     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2847     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2848   }
2849   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2850   if (opcode[i]==0x20) { // LB
2851     if(!c||memtarget) {
2852       if(!dummy) {
2853         #ifdef HOST_IMM_ADDR32
2854         if(c)
2855           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2856         else
2857         #endif
2858         {
2859           //emit_xorimm(addr,3,tl);
2860           //gen_tlb_addr_r(tl,map);
2861           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2862           int x=0,a=tl;
2863 #ifdef BIG_ENDIAN_MIPS
2864           if(!c) emit_xorimm(addr,3,tl);
2865           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2866 #else
2867           if(!c) a=addr;
2868 #endif
2869           if(fastload_reg_override) a=fastload_reg_override;
2870
2871           emit_movsbl_indexed_tlb(x,a,map,tl);
2872         }
2873       }
2874       if(jaddr)
2875         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2876     }
2877     else
2878       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2879   }
2880   if (opcode[i]==0x21) { // LH
2881     if(!c||memtarget) {
2882       if(!dummy) {
2883         #ifdef HOST_IMM_ADDR32
2884         if(c)
2885           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2886         else
2887         #endif
2888         {
2889           int x=0,a=tl;
2890 #ifdef BIG_ENDIAN_MIPS
2891           if(!c) emit_xorimm(addr,2,tl);
2892           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2893 #else
2894           if(!c) a=addr;
2895 #endif
2896           if(fastload_reg_override) a=fastload_reg_override;
2897           //#ifdef
2898           //emit_movswl_indexed_tlb(x,tl,map,tl);
2899           //else
2900           if(map>=0) {
2901             gen_tlb_addr_r(a,map);
2902             emit_movswl_indexed(x,a,tl);
2903           }else{
2904             #ifdef RAM_OFFSET
2905             emit_movswl_indexed(x,a,tl);
2906             #else
2907             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2908             #endif
2909           }
2910         }
2911       }
2912       if(jaddr)
2913         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2914     }
2915     else
2916       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2917   }
2918   if (opcode[i]==0x23) { // LW
2919     if(!c||memtarget) {
2920       if(!dummy) {
2921         int a=addr;
2922         if(fastload_reg_override) a=fastload_reg_override;
2923         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2924         #ifdef HOST_IMM_ADDR32
2925         if(c)
2926           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2927         else
2928         #endif
2929         emit_readword_indexed_tlb(0,a,map,tl);
2930       }
2931       if(jaddr)
2932         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2933     }
2934     else
2935       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2936   }
2937   if (opcode[i]==0x24) { // LBU
2938     if(!c||memtarget) {
2939       if(!dummy) {
2940         #ifdef HOST_IMM_ADDR32
2941         if(c)
2942           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2943         else
2944         #endif
2945         {
2946           //emit_xorimm(addr,3,tl);
2947           //gen_tlb_addr_r(tl,map);
2948           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2949           int x=0,a=tl;
2950 #ifdef BIG_ENDIAN_MIPS
2951           if(!c) emit_xorimm(addr,3,tl);
2952           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2953 #else
2954           if(!c) a=addr;
2955 #endif
2956           if(fastload_reg_override) a=fastload_reg_override;
2957
2958           emit_movzbl_indexed_tlb(x,a,map,tl);
2959         }
2960       }
2961       if(jaddr)
2962         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2963     }
2964     else
2965       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2966   }
2967   if (opcode[i]==0x25) { // LHU
2968     if(!c||memtarget) {
2969       if(!dummy) {
2970         #ifdef HOST_IMM_ADDR32
2971         if(c)
2972           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2973         else
2974         #endif
2975         {
2976           int x=0,a=tl;
2977 #ifdef BIG_ENDIAN_MIPS
2978           if(!c) emit_xorimm(addr,2,tl);
2979           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2980 #else
2981           if(!c) a=addr;
2982 #endif
2983           if(fastload_reg_override) a=fastload_reg_override;
2984           //#ifdef
2985           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2986           //#else
2987           if(map>=0) {
2988             gen_tlb_addr_r(a,map);
2989             emit_movzwl_indexed(x,a,tl);
2990           }else{
2991             #ifdef RAM_OFFSET
2992             emit_movzwl_indexed(x,a,tl);
2993             #else
2994             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2995             #endif
2996           }
2997         }
2998       }
2999       if(jaddr)
3000         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3001     }
3002     else
3003       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3004   }
3005   if (opcode[i]==0x27) { // LWU
3006     assert(th>=0);
3007     if(!c||memtarget) {
3008       if(!dummy) {
3009         int a=addr;
3010         if(fastload_reg_override) a=fastload_reg_override;
3011         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3012         #ifdef HOST_IMM_ADDR32
3013         if(c)
3014           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3015         else
3016         #endif
3017         emit_readword_indexed_tlb(0,a,map,tl);
3018       }
3019       if(jaddr)
3020         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3021     }
3022     else {
3023       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3024     }
3025     emit_zeroreg(th);
3026   }
3027   if (opcode[i]==0x37) { // LD
3028     if(!c||memtarget) {
3029       if(!dummy) {
3030         int a=addr;
3031         if(fastload_reg_override) a=fastload_reg_override;
3032         //gen_tlb_addr_r(tl,map);
3033         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3034         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3035         #ifdef HOST_IMM_ADDR32
3036         if(c)
3037           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3038         else
3039         #endif
3040         emit_readdword_indexed_tlb(0,a,map,th,tl);
3041       }
3042       if(jaddr)
3043         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3044     }
3045     else
3046       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3047   }
3048  }
3049   //emit_storereg(rt1[i],tl); // DEBUG
3050   //if(opcode[i]==0x23)
3051   //if(opcode[i]==0x24)
3052   //if(opcode[i]==0x23||opcode[i]==0x24)
3053   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3054   {
3055     //emit_pusha();
3056     save_regs(0x100f);
3057         emit_readword((int)&last_count,ECX);
3058         #ifdef __i386__
3059         if(get_reg(i_regs->regmap,CCREG)<0)
3060           emit_loadreg(CCREG,HOST_CCREG);
3061         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3062         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3063         emit_writeword(HOST_CCREG,(int)&Count);
3064         #endif
3065         #ifdef __arm__
3066         if(get_reg(i_regs->regmap,CCREG)<0)
3067           emit_loadreg(CCREG,0);
3068         else
3069           emit_mov(HOST_CCREG,0);
3070         emit_add(0,ECX,0);
3071         emit_addimm(0,2*ccadj[i],0);
3072         emit_writeword(0,(int)&Count);
3073         #endif
3074     emit_call((int)memdebug);
3075     //emit_popa();
3076     restore_regs(0x100f);
3077   }/**/
3078 }
3079
3080 #ifndef loadlr_assemble
3081 void loadlr_assemble(int i,struct regstat *i_regs)
3082 {
3083   printf("Need loadlr_assemble for this architecture.\n");
3084   exit(1);
3085 }
3086 #endif
3087
3088 void store_assemble(int i,struct regstat *i_regs)
3089 {
3090   int s,th,tl,map=-1;
3091   int addr,temp;
3092   int offset;
3093   int jaddr=0,jaddr2,type;
3094   int memtarget=0,c=0;
3095   int agr=AGEN1+(i&1);
3096   int faststore_reg_override=0;
3097   u_int hr,reglist=0;
3098   th=get_reg(i_regs->regmap,rs2[i]|64);
3099   tl=get_reg(i_regs->regmap,rs2[i]);
3100   s=get_reg(i_regs->regmap,rs1[i]);
3101   temp=get_reg(i_regs->regmap,agr);
3102   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3103   offset=imm[i];
3104   if(s>=0) {
3105     c=(i_regs->wasconst>>s)&1;
3106     if(c) {
3107       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3108       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3109     }
3110   }
3111   assert(tl>=0);
3112   assert(temp>=0);
3113   for(hr=0;hr<HOST_REGS;hr++) {
3114     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3115   }
3116   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3117   if(offset||s<0||c) addr=temp;
3118   else addr=s;
3119   if(!using_tlb) {
3120     if(!c) {
3121       #ifdef PCSX
3122       if(sp_in_mirror&&rs1[i]==29) {
3123         emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3124         emit_cmpimm(HOST_TEMPREG,RAM_SIZE);
3125         faststore_reg_override=HOST_TEMPREG;
3126       }
3127       else
3128       #endif
3129       #ifdef R29_HACK
3130       // Strmnnrmn's speed hack
3131       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3132       #endif
3133       emit_cmpimm(addr,RAM_SIZE);
3134       #ifdef DESTRUCTIVE_SHIFT
3135       if(s==addr) emit_mov(s,temp);
3136       #endif
3137       #ifdef R29_HACK
3138       memtarget=1;
3139       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3140       #endif
3141       {
3142         jaddr=(int)out;
3143         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3144         // Hint to branch predictor that the branch is unlikely to be taken
3145         if(rs1[i]>=28)
3146           emit_jno_unlikely(0);
3147         else
3148         #endif
3149         emit_jno(0);
3150       }
3151     }
3152   }else{ // using tlb
3153     int x=0;
3154     if (opcode[i]==0x28) x=3; // SB
3155     if (opcode[i]==0x29) x=2; // SH
3156     map=get_reg(i_regs->regmap,TLREG);
3157     assert(map>=0);
3158     reglist&=~(1<<map);
3159     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3160     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3161   }
3162
3163   if (opcode[i]==0x28) { // SB
3164     if(!c||memtarget) {
3165       int x=0,a=temp;
3166 #ifdef BIG_ENDIAN_MIPS
3167       if(!c) emit_xorimm(addr,3,temp);
3168       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3169 #else
3170       if(!c) a=addr;
3171 #endif
3172       if(faststore_reg_override) a=faststore_reg_override;
3173       //gen_tlb_addr_w(temp,map);
3174       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3175       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3176     }
3177     type=STOREB_STUB;
3178   }
3179   if (opcode[i]==0x29) { // SH
3180     if(!c||memtarget) {
3181       int x=0,a=temp;
3182 #ifdef BIG_ENDIAN_MIPS
3183       if(!c) emit_xorimm(addr,2,temp);
3184       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3185 #else
3186       if(!c) a=addr;
3187 #endif
3188       if(faststore_reg_override) a=faststore_reg_override;
3189       //#ifdef
3190       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3191       //#else
3192       if(map>=0) {
3193         gen_tlb_addr_w(a,map);
3194         emit_writehword_indexed(tl,x,a);
3195       }else
3196         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3197     }
3198     type=STOREH_STUB;
3199   }
3200   if (opcode[i]==0x2B) { // SW
3201     if(!c||memtarget) {
3202       int a=addr;
3203       if(faststore_reg_override) a=faststore_reg_override;
3204       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3205       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3206     }
3207     type=STOREW_STUB;
3208   }
3209   if (opcode[i]==0x3F) { // SD
3210     if(!c||memtarget) {
3211       int a=addr;
3212       if(faststore_reg_override) a=faststore_reg_override;
3213       if(rs2[i]) {
3214         assert(th>=0);
3215         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3216         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3217         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3218       }else{
3219         // Store zero
3220         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3221         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3222         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3223       }
3224     }
3225     type=STORED_STUB;
3226   }
3227   if(!using_tlb) {
3228     if(!c||memtarget) {
3229       #ifdef DESTRUCTIVE_SHIFT
3230       // The x86 shift operation is 'destructive'; it overwrites the
3231       // source register, so we need to make a copy first and use that.
3232       addr=temp;
3233       #endif
3234       #if defined(HOST_IMM8)
3235       int ir=get_reg(i_regs->regmap,INVCP);
3236       assert(ir>=0);
3237       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3238       #else
3239       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3240       #endif
3241       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3242       emit_callne(invalidate_addr_reg[addr]);
3243       #else
3244       jaddr2=(int)out;
3245       emit_jne(0);
3246       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3247       #endif
3248     }
3249   }
3250   if(jaddr) {
3251     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3252   } else if(c&&!memtarget) {
3253     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3254   }
3255   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3256   //if(opcode[i]==0x2B || opcode[i]==0x28)
3257   //if(opcode[i]==0x2B || opcode[i]==0x29)
3258   //if(opcode[i]==0x2B)
3259   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3260   {
3261     #ifdef __i386__
3262     emit_pusha();
3263     #endif
3264     #ifdef __arm__
3265     save_regs(0x100f);
3266     #endif
3267         emit_readword((int)&last_count,ECX);
3268         #ifdef __i386__
3269         if(get_reg(i_regs->regmap,CCREG)<0)
3270           emit_loadreg(CCREG,HOST_CCREG);
3271         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3272         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3273         emit_writeword(HOST_CCREG,(int)&Count);
3274         #endif
3275         #ifdef __arm__
3276         if(get_reg(i_regs->regmap,CCREG)<0)
3277           emit_loadreg(CCREG,0);
3278         else
3279           emit_mov(HOST_CCREG,0);
3280         emit_add(0,ECX,0);
3281         emit_addimm(0,2*ccadj[i],0);
3282         emit_writeword(0,(int)&Count);
3283         #endif
3284     emit_call((int)memdebug);
3285     #ifdef __i386__
3286     emit_popa();
3287     #endif
3288     #ifdef __arm__
3289     restore_regs(0x100f);
3290     #endif
3291   }/**/
3292 }
3293
3294 void storelr_assemble(int i,struct regstat *i_regs)
3295 {
3296   int s,th,tl;
3297   int temp;
3298   int temp2;
3299   int offset;
3300   int jaddr=0,jaddr2;
3301   int case1,case2,case3;
3302   int done0,done1,done2;
3303   int memtarget=0,c=0;
3304   int agr=AGEN1+(i&1);
3305   u_int hr,reglist=0;
3306   th=get_reg(i_regs->regmap,rs2[i]|64);
3307   tl=get_reg(i_regs->regmap,rs2[i]);
3308   s=get_reg(i_regs->regmap,rs1[i]);
3309   temp=get_reg(i_regs->regmap,agr);
3310   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3311   offset=imm[i];
3312   if(s>=0) {
3313     c=(i_regs->isconst>>s)&1;
3314     if(c) {
3315       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3316       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3317     }
3318   }
3319   assert(tl>=0);
3320   for(hr=0;hr<HOST_REGS;hr++) {
3321     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3322   }
3323   assert(temp>=0);
3324   if(!using_tlb) {
3325     if(!c) {
3326       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3327       if(!offset&&s!=temp) emit_mov(s,temp);
3328       jaddr=(int)out;
3329       emit_jno(0);
3330     }
3331     else
3332     {
3333       if(!memtarget||!rs1[i]) {
3334         jaddr=(int)out;
3335         emit_jmp(0);
3336       }
3337     }
3338     #ifdef RAM_OFFSET
3339     int map=get_reg(i_regs->regmap,ROREG);
3340     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3341     gen_tlb_addr_w(temp,map);
3342     #else
3343     if((u_int)rdram!=0x80000000)
3344       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3345     #endif
3346   }else{ // using tlb
3347     int map=get_reg(i_regs->regmap,TLREG);
3348     assert(map>=0);
3349     reglist&=~(1<<map);
3350     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3351     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3352     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3353     if(!jaddr&&!memtarget) {
3354       jaddr=(int)out;
3355       emit_jmp(0);
3356     }
3357     gen_tlb_addr_w(temp,map);
3358   }
3359
3360   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3361     temp2=get_reg(i_regs->regmap,FTEMP);
3362     if(!rs2[i]) temp2=th=tl;
3363   }
3364
3365 #ifndef BIG_ENDIAN_MIPS
3366     emit_xorimm(temp,3,temp);
3367 #endif
3368   emit_testimm(temp,2);
3369   case2=(int)out;
3370   emit_jne(0);
3371   emit_testimm(temp,1);
3372   case1=(int)out;
3373   emit_jne(0);
3374   // 0
3375   if (opcode[i]==0x2A) { // SWL
3376     emit_writeword_indexed(tl,0,temp);
3377   }
3378   if (opcode[i]==0x2E) { // SWR
3379     emit_writebyte_indexed(tl,3,temp);
3380   }
3381   if (opcode[i]==0x2C) { // SDL
3382     emit_writeword_indexed(th,0,temp);
3383     if(rs2[i]) emit_mov(tl,temp2);
3384   }
3385   if (opcode[i]==0x2D) { // SDR
3386     emit_writebyte_indexed(tl,3,temp);
3387     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3388   }
3389   done0=(int)out;
3390   emit_jmp(0);
3391   // 1
3392   set_jump_target(case1,(int)out);
3393   if (opcode[i]==0x2A) { // SWL
3394     // Write 3 msb into three least significant bytes
3395     if(rs2[i]) emit_rorimm(tl,8,tl);
3396     emit_writehword_indexed(tl,-1,temp);
3397     if(rs2[i]) emit_rorimm(tl,16,tl);
3398     emit_writebyte_indexed(tl,1,temp);
3399     if(rs2[i]) emit_rorimm(tl,8,tl);
3400   }
3401   if (opcode[i]==0x2E) { // SWR
3402     // Write two lsb into two most significant bytes
3403     emit_writehword_indexed(tl,1,temp);
3404   }
3405   if (opcode[i]==0x2C) { // SDL
3406     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3407     // Write 3 msb into three least significant bytes
3408     if(rs2[i]) emit_rorimm(th,8,th);
3409     emit_writehword_indexed(th,-1,temp);
3410     if(rs2[i]) emit_rorimm(th,16,th);
3411     emit_writebyte_indexed(th,1,temp);
3412     if(rs2[i]) emit_rorimm(th,8,th);
3413   }
3414   if (opcode[i]==0x2D) { // SDR
3415     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3416     // Write two lsb into two most significant bytes
3417     emit_writehword_indexed(tl,1,temp);
3418   }
3419   done1=(int)out;
3420   emit_jmp(0);
3421   // 2
3422   set_jump_target(case2,(int)out);
3423   emit_testimm(temp,1);
3424   case3=(int)out;
3425   emit_jne(0);
3426   if (opcode[i]==0x2A) { // SWL
3427     // Write two msb into two least significant bytes
3428     if(rs2[i]) emit_rorimm(tl,16,tl);
3429     emit_writehword_indexed(tl,-2,temp);
3430     if(rs2[i]) emit_rorimm(tl,16,tl);
3431   }
3432   if (opcode[i]==0x2E) { // SWR
3433     // Write 3 lsb into three most significant bytes
3434     emit_writebyte_indexed(tl,-1,temp);
3435     if(rs2[i]) emit_rorimm(tl,8,tl);
3436     emit_writehword_indexed(tl,0,temp);
3437     if(rs2[i]) emit_rorimm(tl,24,tl);
3438   }
3439   if (opcode[i]==0x2C) { // SDL
3440     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3441     // Write two msb into two least significant bytes
3442     if(rs2[i]) emit_rorimm(th,16,th);
3443     emit_writehword_indexed(th,-2,temp);
3444     if(rs2[i]) emit_rorimm(th,16,th);
3445   }
3446   if (opcode[i]==0x2D) { // SDR
3447     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3448     // Write 3 lsb into three most significant bytes
3449     emit_writebyte_indexed(tl,-1,temp);
3450     if(rs2[i]) emit_rorimm(tl,8,tl);
3451     emit_writehword_indexed(tl,0,temp);
3452     if(rs2[i]) emit_rorimm(tl,24,tl);
3453   }
3454   done2=(int)out;
3455   emit_jmp(0);
3456   // 3
3457   set_jump_target(case3,(int)out);
3458   if (opcode[i]==0x2A) { // SWL
3459     // Write msb into least significant byte
3460     if(rs2[i]) emit_rorimm(tl,24,tl);
3461     emit_writebyte_indexed(tl,-3,temp);
3462     if(rs2[i]) emit_rorimm(tl,8,tl);
3463   }
3464   if (opcode[i]==0x2E) { // SWR
3465     // Write entire word
3466     emit_writeword_indexed(tl,-3,temp);
3467   }
3468   if (opcode[i]==0x2C) { // SDL
3469     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3470     // Write msb into least significant byte
3471     if(rs2[i]) emit_rorimm(th,24,th);
3472     emit_writebyte_indexed(th,-3,temp);
3473     if(rs2[i]) emit_rorimm(th,8,th);
3474   }
3475   if (opcode[i]==0x2D) { // SDR
3476     if(rs2[i]) emit_mov(th,temp2);
3477     // Write entire word
3478     emit_writeword_indexed(tl,-3,temp);
3479   }
3480   set_jump_target(done0,(int)out);
3481   set_jump_target(done1,(int)out);
3482   set_jump_target(done2,(int)out);
3483   if (opcode[i]==0x2C) { // SDL
3484     emit_testimm(temp,4);
3485     done0=(int)out;
3486     emit_jne(0);
3487     emit_andimm(temp,~3,temp);
3488     emit_writeword_indexed(temp2,4,temp);
3489     set_jump_target(done0,(int)out);
3490   }
3491   if (opcode[i]==0x2D) { // SDR
3492     emit_testimm(temp,4);
3493     done0=(int)out;
3494     emit_jeq(0);
3495     emit_andimm(temp,~3,temp);
3496     emit_writeword_indexed(temp2,-4,temp);
3497     set_jump_target(done0,(int)out);
3498   }
3499   if(!c||!memtarget)
3500     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3501   if(!using_tlb) {
3502     #ifdef RAM_OFFSET
3503     int map=get_reg(i_regs->regmap,ROREG);
3504     if(map<0) map=HOST_TEMPREG;
3505     gen_orig_addr_w(temp,map);
3506     #else
3507     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3508     #endif
3509     #if defined(HOST_IMM8)
3510     int ir=get_reg(i_regs->regmap,INVCP);
3511     assert(ir>=0);
3512     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3513     #else
3514     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3515     #endif
3516     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3517     emit_callne(invalidate_addr_reg[temp]);
3518     #else
3519     jaddr2=(int)out;
3520     emit_jne(0);
3521     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3522     #endif
3523   }
3524   /*
3525     emit_pusha();
3526     //save_regs(0x100f);
3527         emit_readword((int)&last_count,ECX);
3528         if(get_reg(i_regs->regmap,CCREG)<0)
3529           emit_loadreg(CCREG,HOST_CCREG);
3530         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3531         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3532         emit_writeword(HOST_CCREG,(int)&Count);
3533     emit_call((int)memdebug);
3534     emit_popa();
3535     //restore_regs(0x100f);
3536   /**/
3537 }
3538
3539 void c1ls_assemble(int i,struct regstat *i_regs)
3540 {
3541 #ifndef DISABLE_COP1
3542   int s,th,tl;
3543   int temp,ar;
3544   int map=-1;
3545   int offset;
3546   int c=0;
3547   int jaddr,jaddr2=0,jaddr3,type;
3548   int agr=AGEN1+(i&1);
3549   u_int hr,reglist=0;
3550   th=get_reg(i_regs->regmap,FTEMP|64);
3551   tl=get_reg(i_regs->regmap,FTEMP);
3552   s=get_reg(i_regs->regmap,rs1[i]);
3553   temp=get_reg(i_regs->regmap,agr);
3554   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3555   offset=imm[i];
3556   assert(tl>=0);
3557   assert(rs1[i]>0);
3558   assert(temp>=0);
3559   for(hr=0;hr<HOST_REGS;hr++) {
3560     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3561   }
3562   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3563   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3564   {
3565     // Loads use a temporary register which we need to save
3566     reglist|=1<<temp;
3567   }
3568   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3569     ar=temp;
3570   else // LWC1/LDC1
3571     ar=tl;
3572   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3573   //else c=(i_regs->wasconst>>s)&1;
3574   if(s>=0) c=(i_regs->wasconst>>s)&1;
3575   // Check cop1 unusable
3576   if(!cop1_usable) {
3577     signed char rs=get_reg(i_regs->regmap,CSREG);
3578     assert(rs>=0);
3579     emit_testimm(rs,0x20000000);
3580     jaddr=(int)out;
3581     emit_jeq(0);
3582     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3583     cop1_usable=1;
3584   }
3585   if (opcode[i]==0x39) { // SWC1 (get float address)
3586     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3587   }
3588   if (opcode[i]==0x3D) { // SDC1 (get double address)
3589     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3590   }
3591   // Generate address + offset
3592   if(!using_tlb) {
3593     if(!c)
3594       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3595   }
3596   else
3597   {
3598     map=get_reg(i_regs->regmap,TLREG);
3599     assert(map>=0);
3600     reglist&=~(1<<map);
3601     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3602       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3603     }
3604     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3605       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3606     }
3607   }
3608   if (opcode[i]==0x39) { // SWC1 (read float)
3609     emit_readword_indexed(0,tl,tl);
3610   }
3611   if (opcode[i]==0x3D) { // SDC1 (read double)
3612     emit_readword_indexed(4,tl,th);
3613     emit_readword_indexed(0,tl,tl);
3614   }
3615   if (opcode[i]==0x31) { // LWC1 (get target address)
3616     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3617   }
3618   if (opcode[i]==0x35) { // LDC1 (get target address)
3619     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3620   }
3621   if(!using_tlb) {
3622     if(!c) {
3623       jaddr2=(int)out;
3624       emit_jno(0);
3625     }
3626     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3627       jaddr2=(int)out;
3628       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3629     }
3630     #ifdef DESTRUCTIVE_SHIFT
3631     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3632       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3633     }
3634     #endif
3635   }else{
3636     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3637       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3638     }
3639     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3640       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3641     }
3642   }
3643   if (opcode[i]==0x31) { // LWC1
3644     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3645     //gen_tlb_addr_r(ar,map);
3646     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3647     #ifdef HOST_IMM_ADDR32
3648     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3649     else
3650     #endif
3651     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3652     type=LOADW_STUB;
3653   }
3654   if (opcode[i]==0x35) { // LDC1
3655     assert(th>=0);
3656     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3657     //gen_tlb_addr_r(ar,map);
3658     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3659     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3660     #ifdef HOST_IMM_ADDR32
3661     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3662     else
3663     #endif
3664     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3665     type=LOADD_STUB;
3666   }
3667   if (opcode[i]==0x39) { // SWC1
3668     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3669     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3670     type=STOREW_STUB;
3671   }
3672   if (opcode[i]==0x3D) { // SDC1
3673     assert(th>=0);
3674     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3675     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3676     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3677     type=STORED_STUB;
3678   }
3679   if(!using_tlb) {
3680     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3681       #ifndef DESTRUCTIVE_SHIFT
3682       temp=offset||c||s<0?ar:s;
3683       #endif
3684       #if defined(HOST_IMM8)
3685       int ir=get_reg(i_regs->regmap,INVCP);
3686       assert(ir>=0);
3687       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3688       #else
3689       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3690       #endif
3691       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3692       emit_callne(invalidate_addr_reg[temp]);
3693       #else
3694       jaddr3=(int)out;
3695       emit_jne(0);
3696       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3697       #endif
3698     }
3699   }
3700   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3701   if (opcode[i]==0x31) { // LWC1 (write float)
3702     emit_writeword_indexed(tl,0,temp);
3703   }
3704   if (opcode[i]==0x35) { // LDC1 (write double)
3705     emit_writeword_indexed(th,4,temp);
3706     emit_writeword_indexed(tl,0,temp);
3707   }
3708   //if(opcode[i]==0x39)
3709   /*if(opcode[i]==0x39||opcode[i]==0x31)
3710   {
3711     emit_pusha();
3712         emit_readword((int)&last_count,ECX);
3713         if(get_reg(i_regs->regmap,CCREG)<0)
3714           emit_loadreg(CCREG,HOST_CCREG);
3715         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3716         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3717         emit_writeword(HOST_CCREG,(int)&Count);
3718     emit_call((int)memdebug);
3719     emit_popa();
3720   }/**/
3721 #else
3722   cop1_unusable(i, i_regs);
3723 #endif
3724 }
3725
3726 void c2ls_assemble(int i,struct regstat *i_regs)
3727 {
3728   int s,tl;
3729   int ar;
3730   int offset;
3731   int memtarget=0,c=0;
3732   int jaddr2=0,jaddr3,type;
3733   int agr=AGEN1+(i&1);
3734   u_int hr,reglist=0;
3735   u_int copr=(source[i]>>16)&0x1f;
3736   s=get_reg(i_regs->regmap,rs1[i]);
3737   tl=get_reg(i_regs->regmap,FTEMP);
3738   offset=imm[i];
3739   assert(rs1[i]>0);
3740   assert(tl>=0);
3741   assert(!using_tlb);
3742
3743   for(hr=0;hr<HOST_REGS;hr++) {
3744     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3745   }
3746   if(i_regs->regmap[HOST_CCREG]==CCREG)
3747     reglist&=~(1<<HOST_CCREG);
3748
3749   // get the address
3750   if (opcode[i]==0x3a) { // SWC2
3751     ar=get_reg(i_regs->regmap,agr);
3752     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3753     reglist|=1<<ar;
3754   } else { // LWC2
3755     ar=tl;
3756   }
3757   if(s>=0) c=(i_regs->wasconst>>s)&1;
3758   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3759   if (!offset&&!c&&s>=0) ar=s;
3760   assert(ar>=0);
3761
3762   if (opcode[i]==0x3a) { // SWC2
3763     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3764     type=STOREW_STUB;
3765   }
3766   else
3767     type=LOADW_STUB;
3768
3769   if(c&&!memtarget) {
3770     jaddr2=(int)out;
3771     emit_jmp(0); // inline_readstub/inline_writestub?
3772   }
3773   else {
3774     if(!c) {
3775       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3776       jaddr2=(int)out;
3777       emit_jno(0);
3778     }
3779     if (opcode[i]==0x32) { // LWC2
3780       #ifdef HOST_IMM_ADDR32
3781       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3782       else
3783       #endif
3784       emit_readword_indexed(0,ar,tl);
3785     }
3786     if (opcode[i]==0x3a) { // SWC2
3787       #ifdef DESTRUCTIVE_SHIFT
3788       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3789       #endif
3790       emit_writeword_indexed(tl,0,ar);
3791     }
3792   }
3793   if(jaddr2)
3794     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3795   if (opcode[i]==0x3a) { // SWC2
3796 #if defined(HOST_IMM8)
3797     int ir=get_reg(i_regs->regmap,INVCP);
3798     assert(ir>=0);
3799     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3800 #else
3801     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3802 #endif
3803     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3804     emit_callne(invalidate_addr_reg[ar]);
3805     #else
3806     jaddr3=(int)out;
3807     emit_jne(0);
3808     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3809     #endif
3810   }
3811   if (opcode[i]==0x32) { // LWC2
3812     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3813   }
3814 }
3815
3816 #ifndef multdiv_assemble
3817 void multdiv_assemble(int i,struct regstat *i_regs)
3818 {
3819   printf("Need multdiv_assemble for this architecture.\n");
3820   exit(1);
3821 }
3822 #endif
3823
3824 void mov_assemble(int i,struct regstat *i_regs)
3825 {
3826   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3827   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3828   if(rt1[i]) {
3829     signed char sh,sl,th,tl;
3830     th=get_reg(i_regs->regmap,rt1[i]|64);
3831     tl=get_reg(i_regs->regmap,rt1[i]);
3832     //assert(tl>=0);
3833     if(tl>=0) {
3834       sh=get_reg(i_regs->regmap,rs1[i]|64);
3835       sl=get_reg(i_regs->regmap,rs1[i]);
3836       if(sl>=0) emit_mov(sl,tl);
3837       else emit_loadreg(rs1[i],tl);
3838       if(th>=0) {
3839         if(sh>=0) emit_mov(sh,th);
3840         else emit_loadreg(rs1[i]|64,th);
3841       }
3842     }
3843   }
3844 }
3845
3846 #ifndef fconv_assemble
3847 void fconv_assemble(int i,struct regstat *i_regs)
3848 {
3849   printf("Need fconv_assemble for this architecture.\n");
3850   exit(1);
3851 }
3852 #endif
3853
3854 #if 0
3855 void float_assemble(int i,struct regstat *i_regs)
3856 {
3857   printf("Need float_assemble for this architecture.\n");
3858   exit(1);
3859 }
3860 #endif
3861
3862 void syscall_assemble(int i,struct regstat *i_regs)
3863 {
3864   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3865   assert(ccreg==HOST_CCREG);
3866   assert(!is_delayslot);
3867   emit_movimm(start+i*4,EAX); // Get PC
3868   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3869   emit_jmp((int)jump_syscall_hle); // XXX
3870 }
3871
3872 void hlecall_assemble(int i,struct regstat *i_regs)
3873 {
3874   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3875   assert(ccreg==HOST_CCREG);
3876   assert(!is_delayslot);
3877   emit_movimm(start+i*4+4,0); // Get PC
3878   emit_movimm((int)psxHLEt[source[i]&7],1);
3879   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3880   emit_jmp((int)jump_hlecall);
3881 }
3882
3883 void intcall_assemble(int i,struct regstat *i_regs)
3884 {
3885   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3886   assert(ccreg==HOST_CCREG);
3887   assert(!is_delayslot);
3888   emit_movimm(start+i*4,0); // Get PC
3889   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3890   emit_jmp((int)jump_intcall);
3891 }
3892
3893 void ds_assemble(int i,struct regstat *i_regs)
3894 {
3895   is_delayslot=1;
3896   switch(itype[i]) {
3897     case ALU:
3898       alu_assemble(i,i_regs);break;
3899     case IMM16:
3900       imm16_assemble(i,i_regs);break;
3901     case SHIFT:
3902       shift_assemble(i,i_regs);break;
3903     case SHIFTIMM:
3904       shiftimm_assemble(i,i_regs);break;
3905     case LOAD:
3906       load_assemble(i,i_regs);break;
3907     case LOADLR:
3908       loadlr_assemble(i,i_regs);break;
3909     case STORE:
3910       store_assemble(i,i_regs);break;
3911     case STORELR:
3912       storelr_assemble(i,i_regs);break;
3913     case COP0:
3914       cop0_assemble(i,i_regs);break;
3915     case COP1:
3916       cop1_assemble(i,i_regs);break;
3917     case C1LS:
3918       c1ls_assemble(i,i_regs);break;
3919     case COP2:
3920       cop2_assemble(i,i_regs);break;
3921     case C2LS:
3922       c2ls_assemble(i,i_regs);break;
3923     case C2OP:
3924       c2op_assemble(i,i_regs);break;
3925     case FCONV:
3926       fconv_assemble(i,i_regs);break;
3927     case FLOAT:
3928       float_assemble(i,i_regs);break;
3929     case FCOMP:
3930       fcomp_assemble(i,i_regs);break;
3931     case MULTDIV:
3932       multdiv_assemble(i,i_regs);break;
3933     case MOV:
3934       mov_assemble(i,i_regs);break;
3935     case SYSCALL:
3936     case HLECALL:
3937     case INTCALL:
3938     case SPAN:
3939     case UJUMP:
3940     case RJUMP:
3941     case CJUMP:
3942     case SJUMP:
3943     case FJUMP:
3944       printf("Jump in the delay slot.  This is probably a bug.\n");
3945   }
3946   is_delayslot=0;
3947 }
3948
3949 // Is the branch target a valid internal jump?
3950 int internal_branch(uint64_t i_is32,int addr)
3951 {
3952   if(addr&1) return 0; // Indirect (register) jump
3953   if(addr>=start && addr<start+slen*4-4)
3954   {
3955     int t=(addr-start)>>2;
3956     // Delay slots are not valid branch targets
3957     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3958     // 64 -> 32 bit transition requires a recompile
3959     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3960     {
3961       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3962       else printf("optimizable: yes\n");
3963     }*/
3964     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3965 #ifndef FORCE32
3966     if(requires_32bit[t]&~i_is32) return 0;
3967     else
3968 #endif
3969       return 1;
3970   }
3971   return 0;
3972 }
3973
3974 #ifndef wb_invalidate
3975 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3976   uint64_t u,uint64_t uu)
3977 {
3978   int hr;
3979   for(hr=0;hr<HOST_REGS;hr++) {
3980     if(hr!=EXCLUDE_REG) {
3981       if(pre[hr]!=entry[hr]) {
3982         if(pre[hr]>=0) {
3983           if((dirty>>hr)&1) {
3984             if(get_reg(entry,pre[hr])<0) {
3985               if(pre[hr]<64) {
3986                 if(!((u>>pre[hr])&1)) {
3987                   emit_storereg(pre[hr],hr);
3988                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3989                     emit_sarimm(hr,31,hr);
3990                     emit_storereg(pre[hr]|64,hr);
3991                   }
3992                 }
3993               }else{
3994                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3995                   emit_storereg(pre[hr],hr);
3996                 }
3997               }
3998             }
3999           }
4000         }
4001       }
4002     }
4003   }
4004   // Move from one register to another (no writeback)
4005   for(hr=0;hr<HOST_REGS;hr++) {
4006     if(hr!=EXCLUDE_REG) {
4007       if(pre[hr]!=entry[hr]) {
4008         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4009           int nr;
4010           if((nr=get_reg(entry,pre[hr]))>=0) {
4011             emit_mov(hr,nr);
4012           }
4013         }
4014       }
4015     }
4016   }
4017 }
4018 #endif
4019
4020 // Load the specified registers
4021 // This only loads the registers given as arguments because
4022 // we don't want to load things that will be overwritten
4023 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4024 {
4025   int hr;
4026   // Load 32-bit regs
4027   for(hr=0;hr<HOST_REGS;hr++) {
4028     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4029       if(entry[hr]!=regmap[hr]) {
4030         if(regmap[hr]==rs1||regmap[hr]==rs2)
4031         {
4032           if(regmap[hr]==0) {
4033             emit_zeroreg(hr);
4034           }
4035           else
4036           {
4037             emit_loadreg(regmap[hr],hr);
4038           }
4039         }
4040       }
4041     }
4042   }
4043   //Load 64-bit regs
4044   for(hr=0;hr<HOST_REGS;hr++) {
4045     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4046       if(entry[hr]!=regmap[hr]) {
4047         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4048         {
4049           assert(regmap[hr]!=64);
4050           if((is32>>(regmap[hr]&63))&1) {
4051             int lr=get_reg(regmap,regmap[hr]-64);
4052             if(lr>=0)
4053               emit_sarimm(lr,31,hr);
4054             else
4055               emit_loadreg(regmap[hr],hr);
4056           }
4057           else
4058           {
4059             emit_loadreg(regmap[hr],hr);
4060           }
4061         }
4062       }
4063     }
4064   }
4065 }
4066
4067 // Load registers prior to the start of a loop
4068 // so that they are not loaded within the loop
4069 static void loop_preload(signed char pre[],signed char entry[])
4070 {
4071   int hr;
4072   for(hr=0;hr<HOST_REGS;hr++) {
4073     if(hr!=EXCLUDE_REG) {
4074       if(pre[hr]!=entry[hr]) {
4075         if(entry[hr]>=0) {
4076           if(get_reg(pre,entry[hr])<0) {
4077             assem_debug("loop preload:\n");
4078             //printf("loop preload: %d\n",hr);
4079             if(entry[hr]==0) {
4080               emit_zeroreg(hr);
4081             }
4082             else if(entry[hr]<TEMPREG)
4083             {
4084               emit_loadreg(entry[hr],hr);
4085             }
4086             else if(entry[hr]-64<TEMPREG)
4087             {
4088               emit_loadreg(entry[hr],hr);
4089             }
4090           }
4091         }
4092       }
4093     }
4094   }
4095 }
4096
4097 // Generate address for load/store instruction
4098 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4099 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4100 {
4101   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4102     int ra=-1;
4103     int agr=AGEN1+(i&1);
4104     int mgr=MGEN1+(i&1);
4105     if(itype[i]==LOAD) {
4106       ra=get_reg(i_regs->regmap,rt1[i]);
4107       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4108       assert(ra>=0);
4109     }
4110     if(itype[i]==LOADLR) {
4111       ra=get_reg(i_regs->regmap,FTEMP);
4112     }
4113     if(itype[i]==STORE||itype[i]==STORELR) {
4114       ra=get_reg(i_regs->regmap,agr);
4115       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4116     }
4117     if(itype[i]==C1LS||itype[i]==C2LS) {
4118       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4119         ra=get_reg(i_regs->regmap,FTEMP);
4120       else { // SWC1/SDC1/SWC2/SDC2
4121         ra=get_reg(i_regs->regmap,agr);
4122         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4123       }
4124     }
4125     int rs=get_reg(i_regs->regmap,rs1[i]);
4126     int rm=get_reg(i_regs->regmap,TLREG);
4127     if(ra>=0) {
4128       int offset=imm[i];
4129       int c=(i_regs->wasconst>>rs)&1;
4130       if(rs1[i]==0) {
4131         // Using r0 as a base address
4132         /*if(rm>=0) {
4133           if(!entry||entry[rm]!=mgr) {
4134             generate_map_const(offset,rm);
4135           } // else did it in the previous cycle
4136         }*/
4137         if(!entry||entry[ra]!=agr) {
4138           if (opcode[i]==0x22||opcode[i]==0x26) {
4139             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4140           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4141             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4142           }else{
4143             emit_movimm(offset,ra);
4144           }
4145         } // else did it in the previous cycle
4146       }
4147       else if(rs<0) {
4148         if(!entry||entry[ra]!=rs1[i])
4149           emit_loadreg(rs1[i],ra);
4150         //if(!entry||entry[ra]!=rs1[i])
4151         //  printf("poor load scheduling!\n");
4152       }
4153       else if(c) {
4154         if(rm>=0) {
4155           if(!entry||entry[rm]!=mgr) {
4156             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4157               // Stores to memory go thru the mapper to detect self-modifying
4158               // code, loads don't.
4159               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4160                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4161                 generate_map_const(constmap[i][rs]+offset,rm);
4162             }else{
4163               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4164                 generate_map_const(constmap[i][rs]+offset,rm);
4165             }
4166           }
4167         }
4168         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4169           if(!entry||entry[ra]!=agr) {
4170             if (opcode[i]==0x22||opcode[i]==0x26) {
4171               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4172             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4173               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4174             }else{
4175               #ifdef HOST_IMM_ADDR32
4176               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4177                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4178               #endif
4179               emit_movimm(constmap[i][rs]+offset,ra);
4180             }
4181           } // else did it in the previous cycle
4182         } // else load_consts already did it
4183       }
4184       if(offset&&!c&&rs1[i]) {
4185         if(rs>=0) {
4186           emit_addimm(rs,offset,ra);
4187         }else{
4188           emit_addimm(ra,offset,ra);
4189         }
4190       }
4191     }
4192   }
4193   // Preload constants for next instruction
4194   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4195     int agr,ra;
4196     #ifndef HOST_IMM_ADDR32
4197     // Mapper entry
4198     agr=MGEN1+((i+1)&1);
4199     ra=get_reg(i_regs->regmap,agr);
4200     if(ra>=0) {
4201       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4202       int offset=imm[i+1];
4203       int c=(regs[i+1].wasconst>>rs)&1;
4204       if(c) {
4205         if(itype[i+1]==STORE||itype[i+1]==STORELR
4206            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4207           // Stores to memory go thru the mapper to detect self-modifying
4208           // code, loads don't.
4209           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4210              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4211             generate_map_const(constmap[i+1][rs]+offset,ra);
4212         }else{
4213           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4214             generate_map_const(constmap[i+1][rs]+offset,ra);
4215         }
4216       }
4217       /*else if(rs1[i]==0) {
4218         generate_map_const(offset,ra);
4219       }*/
4220     }
4221     #endif
4222     // Actual address
4223     agr=AGEN1+((i+1)&1);
4224     ra=get_reg(i_regs->regmap,agr);
4225     if(ra>=0) {
4226       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4227       int offset=imm[i+1];
4228       int c=(regs[i+1].wasconst>>rs)&1;
4229       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4230         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4231           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4232         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4233           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4234         }else{
4235           #ifdef HOST_IMM_ADDR32
4236           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4237              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4238           #endif
4239           emit_movimm(constmap[i+1][rs]+offset,ra);
4240         }
4241       }
4242       else if(rs1[i+1]==0) {
4243         // Using r0 as a base address
4244         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4245           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4246         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4247           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4248         }else{
4249           emit_movimm(offset,ra);
4250         }
4251       }
4252     }
4253   }
4254 }
4255
4256 int get_final_value(int hr, int i, int *value)
4257 {
4258   int reg=regs[i].regmap[hr];
4259   while(i<slen-1) {
4260     if(regs[i+1].regmap[hr]!=reg) break;
4261     if(!((regs[i+1].isconst>>hr)&1)) break;
4262     if(bt[i+1]) break;
4263     i++;
4264   }
4265   if(i<slen-1) {
4266     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4267       *value=constmap[i][hr];
4268       return 1;
4269     }
4270     if(!bt[i+1]) {
4271       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4272         // Load in delay slot, out-of-order execution
4273         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4274         {
4275           #ifdef HOST_IMM_ADDR32
4276           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4277           #endif
4278           // Precompute load address
4279           *value=constmap[i][hr]+imm[i+2];
4280           return 1;
4281         }
4282       }
4283       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4284       {
4285         #ifdef HOST_IMM_ADDR32
4286         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4287         #endif
4288         // Precompute load address
4289         *value=constmap[i][hr]+imm[i+1];
4290         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4291         return 1;
4292       }
4293     }
4294   }
4295   *value=constmap[i][hr];
4296   //printf("c=%x\n",(int)constmap[i][hr]);
4297   if(i==slen-1) return 1;
4298   if(reg<64) {
4299     return !((unneeded_reg[i+1]>>reg)&1);
4300   }else{
4301     return !((unneeded_reg_upper[i+1]>>reg)&1);
4302   }
4303 }
4304
4305 // Load registers with known constants
4306 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4307 {
4308   int hr;
4309   // Load 32-bit regs
4310   for(hr=0;hr<HOST_REGS;hr++) {
4311     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4312       //if(entry[hr]!=regmap[hr]) {
4313       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4314         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4315           int value;
4316           if(get_final_value(hr,i,&value)) {
4317             if(value==0) {
4318               emit_zeroreg(hr);
4319             }
4320             else {
4321               emit_movimm(value,hr);
4322             }
4323           }
4324         }
4325       }
4326     }
4327   }
4328   // Load 64-bit regs
4329   for(hr=0;hr<HOST_REGS;hr++) {
4330     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4331       //if(entry[hr]!=regmap[hr]) {
4332       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4333         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4334           if((is32>>(regmap[hr]&63))&1) {
4335             int lr=get_reg(regmap,regmap[hr]-64);
4336             assert(lr>=0);
4337             emit_sarimm(lr,31,hr);
4338           }
4339           else
4340           {
4341             int value;
4342             if(get_final_value(hr,i,&value)) {
4343               if(value==0) {
4344                 emit_zeroreg(hr);
4345               }
4346               else {
4347                 emit_movimm(value,hr);
4348               }
4349             }
4350           }
4351         }
4352       }
4353     }
4354   }
4355 }
4356 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4357 {
4358   int hr;
4359   // Load 32-bit regs
4360   for(hr=0;hr<HOST_REGS;hr++) {
4361     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4362       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4363         int value=constmap[i][hr];
4364         if(value==0) {
4365           emit_zeroreg(hr);
4366         }
4367         else {
4368           emit_movimm(value,hr);
4369         }
4370       }
4371     }
4372   }
4373   // Load 64-bit regs
4374   for(hr=0;hr<HOST_REGS;hr++) {
4375     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4376       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4377         if((is32>>(regmap[hr]&63))&1) {
4378           int lr=get_reg(regmap,regmap[hr]-64);
4379           assert(lr>=0);
4380           emit_sarimm(lr,31,hr);
4381         }
4382         else
4383         {
4384           int value=constmap[i][hr];
4385           if(value==0) {
4386             emit_zeroreg(hr);
4387           }
4388           else {
4389             emit_movimm(value,hr);
4390           }
4391         }
4392       }
4393     }
4394   }
4395 }
4396
4397 // Write out all dirty registers (except cycle count)
4398 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4399 {
4400   int hr;
4401   for(hr=0;hr<HOST_REGS;hr++) {
4402     if(hr!=EXCLUDE_REG) {
4403       if(i_regmap[hr]>0) {
4404         if(i_regmap[hr]!=CCREG) {
4405           if((i_dirty>>hr)&1) {
4406             if(i_regmap[hr]<64) {
4407               emit_storereg(i_regmap[hr],hr);
4408 #ifndef FORCE32
4409               if( ((i_is32>>i_regmap[hr])&1) ) {
4410                 #ifdef DESTRUCTIVE_WRITEBACK
4411                 emit_sarimm(hr,31,hr);
4412                 emit_storereg(i_regmap[hr]|64,hr);
4413                 #else
4414                 emit_sarimm(hr,31,HOST_TEMPREG);
4415                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4416                 #endif
4417               }
4418 #endif
4419             }else{
4420               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4421                 emit_storereg(i_regmap[hr],hr);
4422               }
4423             }
4424           }
4425         }
4426       }
4427     }
4428   }
4429 }
4430 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4431 // This writes the registers not written by store_regs_bt
4432 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4433 {
4434   int hr;
4435   int t=(addr-start)>>2;
4436   for(hr=0;hr<HOST_REGS;hr++) {
4437     if(hr!=EXCLUDE_REG) {
4438       if(i_regmap[hr]>0) {
4439         if(i_regmap[hr]!=CCREG) {
4440           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4441             if((i_dirty>>hr)&1) {
4442               if(i_regmap[hr]<64) {
4443                 emit_storereg(i_regmap[hr],hr);
4444 #ifndef FORCE32
4445                 if( ((i_is32>>i_regmap[hr])&1) ) {
4446                   #ifdef DESTRUCTIVE_WRITEBACK
4447                   emit_sarimm(hr,31,hr);
4448                   emit_storereg(i_regmap[hr]|64,hr);
4449                   #else
4450                   emit_sarimm(hr,31,HOST_TEMPREG);
4451                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4452                   #endif
4453                 }
4454 #endif
4455               }else{
4456                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4457                   emit_storereg(i_regmap[hr],hr);
4458                 }
4459               }
4460             }
4461           }
4462         }
4463       }
4464     }
4465   }
4466 }
4467
4468 // Load all registers (except cycle count)
4469 void load_all_regs(signed char i_regmap[])
4470 {
4471   int hr;
4472   for(hr=0;hr<HOST_REGS;hr++) {
4473     if(hr!=EXCLUDE_REG) {
4474       if(i_regmap[hr]==0) {
4475         emit_zeroreg(hr);
4476       }
4477       else
4478       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4479       {
4480         emit_loadreg(i_regmap[hr],hr);
4481       }
4482     }
4483   }
4484 }
4485
4486 // Load all current registers also needed by next instruction
4487 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4488 {
4489   int hr;
4490   for(hr=0;hr<HOST_REGS;hr++) {
4491     if(hr!=EXCLUDE_REG) {
4492       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4493         if(i_regmap[hr]==0) {
4494           emit_zeroreg(hr);
4495         }
4496         else
4497         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4498         {
4499           emit_loadreg(i_regmap[hr],hr);
4500         }
4501       }
4502     }
4503   }
4504 }
4505
4506 // Load all regs, storing cycle count if necessary
4507 void load_regs_entry(int t)
4508 {
4509   int hr;
4510   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4511   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4512   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4513     emit_storereg(CCREG,HOST_CCREG);
4514   }
4515   // Load 32-bit regs
4516   for(hr=0;hr<HOST_REGS;hr++) {
4517     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4518       if(regs[t].regmap_entry[hr]==0) {
4519         emit_zeroreg(hr);
4520       }
4521       else if(regs[t].regmap_entry[hr]!=CCREG)
4522       {
4523         emit_loadreg(regs[t].regmap_entry[hr],hr);
4524       }
4525     }
4526   }
4527   // Load 64-bit regs
4528   for(hr=0;hr<HOST_REGS;hr++) {
4529     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4530       assert(regs[t].regmap_entry[hr]!=64);
4531       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4532         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4533         if(lr<0) {
4534           emit_loadreg(regs[t].regmap_entry[hr],hr);
4535         }
4536         else
4537         {
4538           emit_sarimm(lr,31,hr);
4539         }
4540       }
4541       else
4542       {
4543         emit_loadreg(regs[t].regmap_entry[hr],hr);
4544       }
4545     }
4546   }
4547 }
4548
4549 // Store dirty registers prior to branch
4550 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4551 {
4552   if(internal_branch(i_is32,addr))
4553   {
4554     int t=(addr-start)>>2;
4555     int hr;
4556     for(hr=0;hr<HOST_REGS;hr++) {
4557       if(hr!=EXCLUDE_REG) {
4558         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4559           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4560             if((i_dirty>>hr)&1) {
4561               if(i_regmap[hr]<64) {
4562                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4563                   emit_storereg(i_regmap[hr],hr);
4564                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4565                     #ifdef DESTRUCTIVE_WRITEBACK
4566                     emit_sarimm(hr,31,hr);
4567                     emit_storereg(i_regmap[hr]|64,hr);
4568                     #else
4569                     emit_sarimm(hr,31,HOST_TEMPREG);
4570                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4571                     #endif
4572                   }
4573                 }
4574               }else{
4575                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4576                   emit_storereg(i_regmap[hr],hr);
4577                 }
4578               }
4579             }
4580           }
4581         }
4582       }
4583     }
4584   }
4585   else
4586   {
4587     // Branch out of this block, write out all dirty regs
4588     wb_dirtys(i_regmap,i_is32,i_dirty);
4589   }
4590 }
4591
4592 // Load all needed registers for branch target
4593 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4594 {
4595   //if(addr>=start && addr<(start+slen*4))
4596   if(internal_branch(i_is32,addr))
4597   {
4598     int t=(addr-start)>>2;
4599     int hr;
4600     // Store the cycle count before loading something else
4601     if(i_regmap[HOST_CCREG]!=CCREG) {
4602       assert(i_regmap[HOST_CCREG]==-1);
4603     }
4604     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4605       emit_storereg(CCREG,HOST_CCREG);
4606     }
4607     // Load 32-bit regs
4608     for(hr=0;hr<HOST_REGS;hr++) {
4609       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4610         #ifdef DESTRUCTIVE_WRITEBACK
4611         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4612         #else
4613         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4614         #endif
4615           if(regs[t].regmap_entry[hr]==0) {
4616             emit_zeroreg(hr);
4617           }
4618           else if(regs[t].regmap_entry[hr]!=CCREG)
4619           {
4620             emit_loadreg(regs[t].regmap_entry[hr],hr);
4621           }
4622         }
4623       }
4624     }
4625     //Load 64-bit regs
4626     for(hr=0;hr<HOST_REGS;hr++) {
4627       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4628         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4629           assert(regs[t].regmap_entry[hr]!=64);
4630           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4631             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4632             if(lr<0) {
4633               emit_loadreg(regs[t].regmap_entry[hr],hr);
4634             }
4635             else
4636             {
4637               emit_sarimm(lr,31,hr);
4638             }
4639           }
4640           else
4641           {
4642             emit_loadreg(regs[t].regmap_entry[hr],hr);
4643           }
4644         }
4645         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4646           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4647           assert(lr>=0);
4648           emit_sarimm(lr,31,hr);
4649         }
4650       }
4651     }
4652   }
4653 }
4654
4655 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4656 {
4657   if(addr>=start && addr<start+slen*4-4)
4658   {
4659     int t=(addr-start)>>2;
4660     int hr;
4661     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4662     for(hr=0;hr<HOST_REGS;hr++)
4663     {
4664       if(hr!=EXCLUDE_REG)
4665       {
4666         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4667         {
4668           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4669           {
4670             return 0;
4671           }
4672           else
4673           if((i_dirty>>hr)&1)
4674           {
4675             if(i_regmap[hr]<TEMPREG)
4676             {
4677               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4678                 return 0;
4679             }
4680             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4681             {
4682               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4683                 return 0;
4684             }
4685           }
4686         }
4687         else // Same register but is it 32-bit or dirty?
4688         if(i_regmap[hr]>=0)
4689         {
4690           if(!((regs[t].dirty>>hr)&1))
4691           {
4692             if((i_dirty>>hr)&1)
4693             {
4694               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4695               {
4696                 //printf("%x: dirty no match\n",addr);
4697                 return 0;
4698               }
4699             }
4700           }
4701           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4702           {
4703             //printf("%x: is32 no match\n",addr);
4704             return 0;
4705           }
4706         }
4707       }
4708     }
4709     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4710 #ifndef FORCE32
4711     if(requires_32bit[t]&~i_is32) return 0;
4712 #endif
4713     // Delay slots are not valid branch targets
4714     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4715     // Delay slots require additional processing, so do not match
4716     if(is_ds[t]) return 0;
4717   }
4718   else
4719   {
4720     int hr;
4721     for(hr=0;hr<HOST_REGS;hr++)
4722     {
4723       if(hr!=EXCLUDE_REG)
4724       {
4725         if(i_regmap[hr]>=0)
4726         {
4727           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4728           {
4729             if((i_dirty>>hr)&1)
4730             {
4731               return 0;
4732             }
4733           }
4734         }
4735       }
4736     }
4737   }
4738   return 1;
4739 }
4740
4741 // Used when a branch jumps into the delay slot of another branch
4742 void ds_assemble_entry(int i)
4743 {
4744   int t=(ba[i]-start)>>2;
4745   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4746   assem_debug("Assemble delay slot at %x\n",ba[i]);
4747   assem_debug("<->\n");
4748   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4749     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4750   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4751   address_generation(t,&regs[t],regs[t].regmap_entry);
4752   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4753     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4754   cop1_usable=0;
4755   is_delayslot=0;
4756   switch(itype[t]) {
4757     case ALU:
4758       alu_assemble(t,&regs[t]);break;
4759     case IMM16:
4760       imm16_assemble(t,&regs[t]);break;
4761     case SHIFT:
4762       shift_assemble(t,&regs[t]);break;
4763     case SHIFTIMM:
4764       shiftimm_assemble(t,&regs[t]);break;
4765     case LOAD:
4766       load_assemble(t,&regs[t]);break;
4767     case LOADLR:
4768       loadlr_assemble(t,&regs[t]);break;
4769     case STORE:
4770       store_assemble(t,&regs[t]);break;
4771     case STORELR:
4772       storelr_assemble(t,&regs[t]);break;
4773     case COP0:
4774       cop0_assemble(t,&regs[t]);break;
4775     case COP1:
4776       cop1_assemble(t,&regs[t]);break;
4777     case C1LS:
4778       c1ls_assemble(t,&regs[t]);break;
4779     case COP2:
4780       cop2_assemble(t,&regs[t]);break;
4781     case C2LS:
4782       c2ls_assemble(t,&regs[t]);break;
4783     case C2OP:
4784       c2op_assemble(t,&regs[t]);break;
4785     case FCONV:
4786       fconv_assemble(t,&regs[t]);break;
4787     case FLOAT:
4788       float_assemble(t,&regs[t]);break;
4789     case FCOMP:
4790       fcomp_assemble(t,&regs[t]);break;
4791     case MULTDIV:
4792       multdiv_assemble(t,&regs[t]);break;
4793     case MOV:
4794       mov_assemble(t,&regs[t]);break;
4795     case SYSCALL:
4796     case HLECALL:
4797     case INTCALL:
4798     case SPAN:
4799     case UJUMP:
4800     case RJUMP:
4801     case CJUMP:
4802     case SJUMP:
4803     case FJUMP:
4804       printf("Jump in the delay slot.  This is probably a bug.\n");
4805   }
4806   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4807   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4808   if(internal_branch(regs[t].is32,ba[i]+4))
4809     assem_debug("branch: internal\n");
4810   else
4811     assem_debug("branch: external\n");
4812   assert(internal_branch(regs[t].is32,ba[i]+4));
4813   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4814   emit_jmp(0);
4815 }
4816
4817 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4818 {
4819   int count;
4820   int jaddr;
4821   int idle=0;
4822   if(itype[i]==RJUMP)
4823   {
4824     *adj=0;
4825   }
4826   //if(ba[i]>=start && ba[i]<(start+slen*4))
4827   if(internal_branch(branch_regs[i].is32,ba[i]))
4828   {
4829     int t=(ba[i]-start)>>2;
4830     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4831     else *adj=ccadj[t];
4832   }
4833   else
4834   {
4835     *adj=0;
4836   }
4837   count=ccadj[i];
4838   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4839     // Idle loop
4840     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4841     idle=(int)out;
4842     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4843     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4844     jaddr=(int)out;
4845     emit_jmp(0);
4846   }
4847   else if(*adj==0||invert) {
4848     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4849     jaddr=(int)out;
4850     emit_jns(0);
4851   }
4852   else
4853   {
4854     emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4855     jaddr=(int)out;
4856     emit_jns(0);
4857   }
4858   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4859 }
4860
4861 void do_ccstub(int n)
4862 {
4863   literal_pool(256);
4864   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4865   set_jump_target(stubs[n][1],(int)out);
4866   int i=stubs[n][4];
4867   if(stubs[n][6]==NULLDS) {
4868     // Delay slot instruction is nullified ("likely" branch)
4869     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4870   }
4871   else if(stubs[n][6]!=TAKEN) {
4872     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4873   }
4874   else {
4875     if(internal_branch(branch_regs[i].is32,ba[i]))
4876       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4877   }
4878   if(stubs[n][5]!=-1)
4879   {
4880     // Save PC as return address
4881     emit_movimm(stubs[n][5],EAX);
4882     emit_writeword(EAX,(int)&pcaddr);
4883   }
4884   else
4885   {
4886     // Return address depends on which way the branch goes
4887     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4888     {
4889       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4890       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4891       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4892       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4893       if(rs1[i]==0)
4894       {
4895         s1l=s2l;s1h=s2h;
4896         s2l=s2h=-1;
4897       }
4898       else if(rs2[i]==0)
4899       {
4900         s2l=s2h=-1;
4901       }
4902       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4903         s1h=s2h=-1;
4904       }
4905       assert(s1l>=0);
4906       #ifdef DESTRUCTIVE_WRITEBACK
4907       if(rs1[i]) {
4908         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4909           emit_loadreg(rs1[i],s1l);
4910       }
4911       else {
4912         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4913           emit_loadreg(rs2[i],s1l);
4914       }
4915       if(s2l>=0)
4916         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4917           emit_loadreg(rs2[i],s2l);
4918       #endif
4919       int hr=0;
4920       int addr=-1,alt=-1,ntaddr=-1;
4921       while(hr<HOST_REGS)
4922       {
4923         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4924            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4925            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4926         {
4927           addr=hr++;break;
4928         }
4929         hr++;
4930       }
4931       while(hr<HOST_REGS)
4932       {
4933         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4934            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4935            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4936         {
4937           alt=hr++;break;
4938         }
4939         hr++;
4940       }
4941       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4942       {
4943         while(hr<HOST_REGS)
4944         {
4945           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4946              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4947              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4948           {
4949             ntaddr=hr;break;
4950           }
4951           hr++;
4952         }
4953         assert(hr<HOST_REGS);
4954       }
4955       if((opcode[i]&0x2f)==4) // BEQ
4956       {
4957         #ifdef HAVE_CMOV_IMM
4958         if(s1h<0) {
4959           if(s2l>=0) emit_cmp(s1l,s2l);
4960           else emit_test(s1l,s1l);
4961           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4962         }
4963         else
4964         #endif
4965         {
4966           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4967           if(s1h>=0) {
4968             if(s2h>=0) emit_cmp(s1h,s2h);
4969             else emit_test(s1h,s1h);
4970             emit_cmovne_reg(alt,addr);
4971           }
4972           if(s2l>=0) emit_cmp(s1l,s2l);
4973           else emit_test(s1l,s1l);
4974           emit_cmovne_reg(alt,addr);
4975         }
4976       }
4977       if((opcode[i]&0x2f)==5) // BNE
4978       {
4979         #ifdef HAVE_CMOV_IMM
4980         if(s1h<0) {
4981           if(s2l>=0) emit_cmp(s1l,s2l);
4982           else emit_test(s1l,s1l);
4983           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4984         }
4985         else
4986         #endif
4987         {
4988           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4989           if(s1h>=0) {
4990             if(s2h>=0) emit_cmp(s1h,s2h);
4991             else emit_test(s1h,s1h);
4992             emit_cmovne_reg(alt,addr);
4993           }
4994           if(s2l>=0) emit_cmp(s1l,s2l);
4995           else emit_test(s1l,s1l);
4996           emit_cmovne_reg(alt,addr);
4997         }
4998       }
4999       if((opcode[i]&0x2f)==6) // BLEZ
5000       {
5001         //emit_movimm(ba[i],alt);
5002         //emit_movimm(start+i*4+8,addr);
5003         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5004         emit_cmpimm(s1l,1);
5005         if(s1h>=0) emit_mov(addr,ntaddr);
5006         emit_cmovl_reg(alt,addr);
5007         if(s1h>=0) {
5008           emit_test(s1h,s1h);
5009           emit_cmovne_reg(ntaddr,addr);
5010           emit_cmovs_reg(alt,addr);
5011         }
5012       }
5013       if((opcode[i]&0x2f)==7) // BGTZ
5014       {
5015         //emit_movimm(ba[i],addr);
5016         //emit_movimm(start+i*4+8,ntaddr);
5017         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5018         emit_cmpimm(s1l,1);
5019         if(s1h>=0) emit_mov(addr,alt);
5020         emit_cmovl_reg(ntaddr,addr);
5021         if(s1h>=0) {
5022           emit_test(s1h,s1h);
5023           emit_cmovne_reg(alt,addr);
5024           emit_cmovs_reg(ntaddr,addr);
5025         }
5026       }
5027       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5028       {
5029         //emit_movimm(ba[i],alt);
5030         //emit_movimm(start+i*4+8,addr);
5031         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5032         if(s1h>=0) emit_test(s1h,s1h);
5033         else emit_test(s1l,s1l);
5034         emit_cmovs_reg(alt,addr);
5035       }
5036       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5037       {
5038         //emit_movimm(ba[i],addr);
5039         //emit_movimm(start+i*4+8,alt);
5040         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5041         if(s1h>=0) emit_test(s1h,s1h);
5042         else emit_test(s1l,s1l);
5043         emit_cmovs_reg(alt,addr);
5044       }
5045       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5046         if(source[i]&0x10000) // BC1T
5047         {
5048           //emit_movimm(ba[i],alt);
5049           //emit_movimm(start+i*4+8,addr);
5050           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5051           emit_testimm(s1l,0x800000);
5052           emit_cmovne_reg(alt,addr);
5053         }
5054         else // BC1F
5055         {
5056           //emit_movimm(ba[i],addr);
5057           //emit_movimm(start+i*4+8,alt);
5058           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5059           emit_testimm(s1l,0x800000);
5060           emit_cmovne_reg(alt,addr);
5061         }
5062       }
5063       emit_writeword(addr,(int)&pcaddr);
5064     }
5065     else
5066     if(itype[i]==RJUMP)
5067     {
5068       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5069       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5070         r=get_reg(branch_regs[i].regmap,RTEMP);
5071       }
5072       emit_writeword(r,(int)&pcaddr);
5073     }
5074     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5075   }
5076   // Update cycle count
5077   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5078   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5079   emit_call((int)cc_interrupt);
5080   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
5081   if(stubs[n][6]==TAKEN) {
5082     if(internal_branch(branch_regs[i].is32,ba[i]))
5083       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5084     else if(itype[i]==RJUMP) {
5085       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5086         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5087       else
5088         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5089     }
5090   }else if(stubs[n][6]==NOTTAKEN) {
5091     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5092     else load_all_regs(branch_regs[i].regmap);
5093   }else if(stubs[n][6]==NULLDS) {
5094     // Delay slot instruction is nullified ("likely" branch)
5095     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5096     else load_all_regs(regs[i].regmap);
5097   }else{
5098     load_all_regs(branch_regs[i].regmap);
5099   }
5100   emit_jmp(stubs[n][2]); // return address
5101
5102   /* This works but uses a lot of memory...
5103   emit_readword((int)&last_count,ECX);
5104   emit_add(HOST_CCREG,ECX,EAX);
5105   emit_writeword(EAX,(int)&Count);
5106   emit_call((int)gen_interupt);
5107   emit_readword((int)&Count,HOST_CCREG);
5108   emit_readword((int)&next_interupt,EAX);
5109   emit_readword((int)&pending_exception,EBX);
5110   emit_writeword(EAX,(int)&last_count);
5111   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5112   emit_test(EBX,EBX);
5113   int jne_instr=(int)out;
5114   emit_jne(0);
5115   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5116   load_all_regs(branch_regs[i].regmap);
5117   emit_jmp(stubs[n][2]); // return address
5118   set_jump_target(jne_instr,(int)out);
5119   emit_readword((int)&pcaddr,EAX);
5120   // Call get_addr_ht instead of doing the hash table here.
5121   // This code is executed infrequently and takes up a lot of space
5122   // so smaller is better.
5123   emit_storereg(CCREG,HOST_CCREG);
5124   emit_pushreg(EAX);
5125   emit_call((int)get_addr_ht);
5126   emit_loadreg(CCREG,HOST_CCREG);
5127   emit_addimm(ESP,4,ESP);
5128   emit_jmpreg(EAX);*/
5129 }
5130
5131 add_to_linker(int addr,int target,int ext)
5132 {
5133   link_addr[linkcount][0]=addr;
5134   link_addr[linkcount][1]=target;
5135   link_addr[linkcount][2]=ext;
5136   linkcount++;
5137 }
5138
5139 static void ujump_assemble_write_ra(int i)
5140 {
5141   int rt;
5142   unsigned int return_address;
5143   rt=get_reg(branch_regs[i].regmap,31);
5144   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5145   //assert(rt>=0);
5146   return_address=start+i*4+8;
5147   if(rt>=0) {
5148     #ifdef USE_MINI_HT
5149     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5150       int temp=-1; // note: must be ds-safe
5151       #ifdef HOST_TEMPREG
5152       temp=HOST_TEMPREG;
5153       #endif
5154       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5155       else emit_movimm(return_address,rt);
5156     }
5157     else
5158     #endif
5159     {
5160       #ifdef REG_PREFETCH
5161       if(temp>=0)
5162       {
5163         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5164       }
5165       #endif
5166       emit_movimm(return_address,rt); // PC into link register
5167       #ifdef IMM_PREFETCH
5168       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5169       #endif
5170     }
5171   }
5172 }
5173
5174 void ujump_assemble(int i,struct regstat *i_regs)
5175 {
5176   signed char *i_regmap=i_regs->regmap;
5177   int ra_done=0;
5178   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5179   address_generation(i+1,i_regs,regs[i].regmap_entry);
5180   #ifdef REG_PREFETCH
5181   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5182   if(rt1[i]==31&&temp>=0)
5183   {
5184     int return_address=start+i*4+8;
5185     if(get_reg(branch_regs[i].regmap,31)>0)
5186     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5187   }
5188   #endif
5189   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5190     ujump_assemble_write_ra(i); // writeback ra for DS
5191     ra_done=1;
5192   }
5193   ds_assemble(i+1,i_regs);
5194   uint64_t bc_unneeded=branch_regs[i].u;
5195   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5196   bc_unneeded|=1|(1LL<<rt1[i]);
5197   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5198   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5199                 bc_unneeded,bc_unneeded_upper);
5200   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5201   if(!ra_done&&rt1[i]==31)
5202     ujump_assemble_write_ra(i);
5203   int cc,adj;
5204   cc=get_reg(branch_regs[i].regmap,CCREG);
5205   assert(cc==HOST_CCREG);
5206   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5207   #ifdef REG_PREFETCH
5208   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5209   #endif
5210   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5211   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5212   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5213   if(internal_branch(branch_regs[i].is32,ba[i]))
5214     assem_debug("branch: internal\n");
5215   else
5216     assem_debug("branch: external\n");
5217   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5218     ds_assemble_entry(i);
5219   }
5220   else {
5221     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5222     emit_jmp(0);
5223   }
5224 }
5225
5226 static void rjump_assemble_write_ra(int i)
5227 {
5228   int rt,return_address;
5229   assert(rt1[i+1]!=rt1[i]);
5230   assert(rt2[i+1]!=rt1[i]);
5231   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5232   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5233   assert(rt>=0);
5234   return_address=start+i*4+8;
5235   #ifdef REG_PREFETCH
5236   if(temp>=0)
5237   {
5238     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5239   }
5240   #endif
5241   emit_movimm(return_address,rt); // PC into link register
5242   #ifdef IMM_PREFETCH
5243   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5244   #endif
5245 }
5246
5247 void rjump_assemble(int i,struct regstat *i_regs)
5248 {
5249   signed char *i_regmap=i_regs->regmap;
5250   int temp;
5251   int rs,cc,adj;
5252   int ra_done=0;
5253   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5254   assert(rs>=0);
5255   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5256     // Delay slot abuse, make a copy of the branch address register
5257     temp=get_reg(branch_regs[i].regmap,RTEMP);
5258     assert(temp>=0);
5259     assert(regs[i].regmap[temp]==RTEMP);
5260     emit_mov(rs,temp);
5261     rs=temp;
5262   }
5263   address_generation(i+1,i_regs,regs[i].regmap_entry);
5264   #ifdef REG_PREFETCH
5265   if(rt1[i]==31)
5266   {
5267     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5268       int return_address=start+i*4+8;
5269       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5270     }
5271   }
5272   #endif
5273   #ifdef USE_MINI_HT
5274   if(rs1[i]==31) {
5275     int rh=get_reg(regs[i].regmap,RHASH);
5276     if(rh>=0) do_preload_rhash(rh);
5277   }
5278   #endif
5279   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5280     rjump_assemble_write_ra(i);
5281     ra_done=1;
5282   }
5283   ds_assemble(i+1,i_regs);
5284   uint64_t bc_unneeded=branch_regs[i].u;
5285   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5286   bc_unneeded|=1|(1LL<<rt1[i]);
5287   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5288   bc_unneeded&=~(1LL<<rs1[i]);
5289   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5290                 bc_unneeded,bc_unneeded_upper);
5291   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5292   if(!ra_done&&rt1[i]!=0)
5293     rjump_assemble_write_ra(i);
5294   cc=get_reg(branch_regs[i].regmap,CCREG);
5295   assert(cc==HOST_CCREG);
5296   #ifdef USE_MINI_HT
5297   int rh=get_reg(branch_regs[i].regmap,RHASH);
5298   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5299   if(rs1[i]==31) {
5300     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5301     do_preload_rhtbl(ht);
5302     do_rhash(rs,rh);
5303   }
5304   #endif
5305   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5306   #ifdef DESTRUCTIVE_WRITEBACK
5307   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5308     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5309       emit_loadreg(rs1[i],rs);
5310     }
5311   }
5312   #endif
5313   #ifdef REG_PREFETCH
5314   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5315   #endif
5316   #ifdef USE_MINI_HT
5317   if(rs1[i]==31) {
5318     do_miniht_load(ht,rh);
5319   }
5320   #endif
5321   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5322   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5323   //assert(adj==0);
5324   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5325   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5326   emit_jns(0);
5327   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5328   #ifdef USE_MINI_HT
5329   if(rs1[i]==31) {
5330     do_miniht_jump(rs,rh,ht);
5331   }
5332   else
5333   #endif
5334   {
5335     //if(rs!=EAX) emit_mov(rs,EAX);
5336     //emit_jmp((int)jump_vaddr_eax);
5337     emit_jmp(jump_vaddr_reg[rs]);
5338   }
5339   /* Check hash table
5340   temp=!rs;
5341   emit_mov(rs,temp);
5342   emit_shrimm(rs,16,rs);
5343   emit_xor(temp,rs,rs);
5344   emit_movzwl_reg(rs,rs);
5345   emit_shlimm(rs,4,rs);
5346   emit_cmpmem_indexed((int)hash_table,rs,temp);
5347   emit_jne((int)out+14);
5348   emit_readword_indexed((int)hash_table+4,rs,rs);
5349   emit_jmpreg(rs);
5350   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5351   emit_addimm_no_flags(8,rs);
5352   emit_jeq((int)out-17);
5353   // No hit on hash table, call compiler
5354   emit_pushreg(temp);
5355 //DEBUG >
5356 #ifdef DEBUG_CYCLE_COUNT
5357   emit_readword((int)&last_count,ECX);
5358   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5359   emit_readword((int)&next_interupt,ECX);
5360   emit_writeword(HOST_CCREG,(int)&Count);
5361   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5362   emit_writeword(ECX,(int)&last_count);
5363 #endif
5364 //DEBUG <
5365   emit_storereg(CCREG,HOST_CCREG);
5366   emit_call((int)get_addr);
5367   emit_loadreg(CCREG,HOST_CCREG);
5368   emit_addimm(ESP,4,ESP);
5369   emit_jmpreg(EAX);*/
5370   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5371   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5372   #endif
5373 }
5374
5375 void cjump_assemble(int i,struct regstat *i_regs)
5376 {
5377   signed char *i_regmap=i_regs->regmap;
5378   int cc;
5379   int match;
5380   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5381   assem_debug("match=%d\n",match);
5382   int s1h,s1l,s2h,s2l;
5383   int prev_cop1_usable=cop1_usable;
5384   int unconditional=0,nop=0;
5385   int only32=0;
5386   int invert=0;
5387   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5388   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5389   if(!match) invert=1;
5390   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5391   if(i>(ba[i]-start)>>2) invert=1;
5392   #endif
5393
5394   if(ooo[i]) {
5395     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5396     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5397     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5398     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5399   }
5400   else {
5401     s1l=get_reg(i_regmap,rs1[i]);
5402     s1h=get_reg(i_regmap,rs1[i]|64);
5403     s2l=get_reg(i_regmap,rs2[i]);
5404     s2h=get_reg(i_regmap,rs2[i]|64);
5405   }
5406   if(rs1[i]==0&&rs2[i]==0)
5407   {
5408     if(opcode[i]&1) nop=1;
5409     else unconditional=1;
5410     //assert(opcode[i]!=5);
5411     //assert(opcode[i]!=7);
5412     //assert(opcode[i]!=0x15);
5413     //assert(opcode[i]!=0x17);
5414   }
5415   else if(rs1[i]==0)
5416   {
5417     s1l=s2l;s1h=s2h;
5418     s2l=s2h=-1;
5419     only32=(regs[i].was32>>rs2[i])&1;
5420   }
5421   else if(rs2[i]==0)
5422   {
5423     s2l=s2h=-1;
5424     only32=(regs[i].was32>>rs1[i])&1;
5425   }
5426   else {
5427     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5428   }
5429
5430   if(ooo[i]) {
5431     // Out of order execution (delay slot first)
5432     //printf("OOOE\n");
5433     address_generation(i+1,i_regs,regs[i].regmap_entry);
5434     ds_assemble(i+1,i_regs);
5435     int adj;
5436     uint64_t bc_unneeded=branch_regs[i].u;
5437     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5438     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5439     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5440     bc_unneeded|=1;
5441     bc_unneeded_upper|=1;
5442     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5443                   bc_unneeded,bc_unneeded_upper);
5444     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5445     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5446     cc=get_reg(branch_regs[i].regmap,CCREG);
5447     assert(cc==HOST_CCREG);
5448     if(unconditional)
5449       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5450     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5451     //assem_debug("cycle count (adj)\n");
5452     if(unconditional) {
5453       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5454       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5455         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5456         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5457         if(internal)
5458           assem_debug("branch: internal\n");
5459         else
5460           assem_debug("branch: external\n");
5461         if(internal&&is_ds[(ba[i]-start)>>2]) {
5462           ds_assemble_entry(i);
5463         }
5464         else {
5465           add_to_linker((int)out,ba[i],internal);
5466           emit_jmp(0);
5467         }
5468         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5469         if(((u_int)out)&7) emit_addnop(0);
5470         #endif
5471       }
5472     }
5473     else if(nop) {
5474       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5475       int jaddr=(int)out;
5476       emit_jns(0);
5477       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5478     }
5479     else {
5480       int taken=0,nottaken=0,nottaken1=0;
5481       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5482       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5483       if(!only32)
5484       {
5485         assert(s1h>=0);
5486         if(opcode[i]==4) // BEQ
5487         {
5488           if(s2h>=0) emit_cmp(s1h,s2h);
5489           else emit_test(s1h,s1h);
5490           nottaken1=(int)out;
5491           emit_jne(1);
5492         }
5493         if(opcode[i]==5) // BNE
5494         {
5495           if(s2h>=0) emit_cmp(s1h,s2h);
5496           else emit_test(s1h,s1h);
5497           if(invert) taken=(int)out;
5498           else add_to_linker((int)out,ba[i],internal);
5499           emit_jne(0);
5500         }
5501         if(opcode[i]==6) // BLEZ
5502         {
5503           emit_test(s1h,s1h);
5504           if(invert) taken=(int)out;
5505           else add_to_linker((int)out,ba[i],internal);
5506           emit_js(0);
5507           nottaken1=(int)out;
5508           emit_jne(1);
5509         }
5510         if(opcode[i]==7) // BGTZ
5511         {
5512           emit_test(s1h,s1h);
5513           nottaken1=(int)out;
5514           emit_js(1);
5515           if(invert) taken=(int)out;
5516           else add_to_linker((int)out,ba[i],internal);
5517           emit_jne(0);
5518         }
5519       } // if(!only32)
5520
5521       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5522       assert(s1l>=0);
5523       if(opcode[i]==4) // BEQ
5524       {
5525         if(s2l>=0) emit_cmp(s1l,s2l);
5526         else emit_test(s1l,s1l);
5527         if(invert){
5528           nottaken=(int)out;
5529           emit_jne(1);
5530         }else{
5531           add_to_linker((int)out,ba[i],internal);
5532           emit_jeq(0);
5533         }
5534       }
5535       if(opcode[i]==5) // BNE
5536       {
5537         if(s2l>=0) emit_cmp(s1l,s2l);
5538         else emit_test(s1l,s1l);
5539         if(invert){
5540           nottaken=(int)out;
5541           emit_jeq(1);
5542         }else{
5543           add_to_linker((int)out,ba[i],internal);
5544           emit_jne(0);
5545         }
5546       }
5547       if(opcode[i]==6) // BLEZ
5548       {
5549         emit_cmpimm(s1l,1);
5550         if(invert){
5551           nottaken=(int)out;
5552           emit_jge(1);
5553         }else{
5554           add_to_linker((int)out,ba[i],internal);
5555           emit_jl(0);
5556         }
5557       }
5558       if(opcode[i]==7) // BGTZ
5559       {
5560         emit_cmpimm(s1l,1);
5561         if(invert){
5562           nottaken=(int)out;
5563           emit_jl(1);
5564         }else{
5565           add_to_linker((int)out,ba[i],internal);
5566           emit_jge(0);
5567         }
5568       }
5569       if(invert) {
5570         if(taken) set_jump_target(taken,(int)out);
5571         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5572         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5573           if(adj) {
5574             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5575             add_to_linker((int)out,ba[i],internal);
5576           }else{
5577             emit_addnop(13);
5578             add_to_linker((int)out,ba[i],internal*2);
5579           }
5580           emit_jmp(0);
5581         }else
5582         #endif
5583         {
5584           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5585           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5586           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5587           if(internal)
5588             assem_debug("branch: internal\n");
5589           else
5590             assem_debug("branch: external\n");
5591           if(internal&&is_ds[(ba[i]-start)>>2]) {
5592             ds_assemble_entry(i);
5593           }
5594           else {
5595             add_to_linker((int)out,ba[i],internal);
5596             emit_jmp(0);
5597           }
5598         }
5599         set_jump_target(nottaken,(int)out);
5600       }
5601
5602       if(nottaken1) set_jump_target(nottaken1,(int)out);
5603       if(adj) {
5604         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5605       }
5606     } // (!unconditional)
5607   } // if(ooo)
5608   else
5609   {
5610     // In-order execution (branch first)
5611     //if(likely[i]) printf("IOL\n");
5612     //else
5613     //printf("IOE\n");
5614     int taken=0,nottaken=0,nottaken1=0;
5615     if(!unconditional&&!nop) {
5616       if(!only32)
5617       {
5618         assert(s1h>=0);
5619         if((opcode[i]&0x2f)==4) // BEQ
5620         {
5621           if(s2h>=0) emit_cmp(s1h,s2h);
5622           else emit_test(s1h,s1h);
5623           nottaken1=(int)out;
5624           emit_jne(2);
5625         }
5626         if((opcode[i]&0x2f)==5) // BNE
5627         {
5628           if(s2h>=0) emit_cmp(s1h,s2h);
5629           else emit_test(s1h,s1h);
5630           taken=(int)out;
5631           emit_jne(1);
5632         }
5633         if((opcode[i]&0x2f)==6) // BLEZ
5634         {
5635           emit_test(s1h,s1h);
5636           taken=(int)out;
5637           emit_js(1);
5638           nottaken1=(int)out;
5639           emit_jne(2);
5640         }
5641         if((opcode[i]&0x2f)==7) // BGTZ
5642         {
5643           emit_test(s1h,s1h);
5644           nottaken1=(int)out;
5645           emit_js(2);
5646           taken=(int)out;
5647           emit_jne(1);
5648         }
5649       } // if(!only32)
5650
5651       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5652       assert(s1l>=0);
5653       if((opcode[i]&0x2f)==4) // BEQ
5654       {
5655         if(s2l>=0) emit_cmp(s1l,s2l);
5656         else emit_test(s1l,s1l);
5657         nottaken=(int)out;
5658         emit_jne(2);
5659       }
5660       if((opcode[i]&0x2f)==5) // BNE
5661       {
5662         if(s2l>=0) emit_cmp(s1l,s2l);
5663         else emit_test(s1l,s1l);
5664         nottaken=(int)out;
5665         emit_jeq(2);
5666       }
5667       if((opcode[i]&0x2f)==6) // BLEZ
5668       {
5669         emit_cmpimm(s1l,1);
5670         nottaken=(int)out;
5671         emit_jge(2);
5672       }
5673       if((opcode[i]&0x2f)==7) // BGTZ
5674       {
5675         emit_cmpimm(s1l,1);
5676         nottaken=(int)out;
5677         emit_jl(2);
5678       }
5679     } // if(!unconditional)
5680     int adj;
5681     uint64_t ds_unneeded=branch_regs[i].u;
5682     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5683     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5684     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5685     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5686     ds_unneeded|=1;
5687     ds_unneeded_upper|=1;
5688     // branch taken
5689     if(!nop) {
5690       if(taken) set_jump_target(taken,(int)out);
5691       assem_debug("1:\n");
5692       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5693                     ds_unneeded,ds_unneeded_upper);
5694       // load regs
5695       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5696       address_generation(i+1,&branch_regs[i],0);
5697       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5698       ds_assemble(i+1,&branch_regs[i]);
5699       cc=get_reg(branch_regs[i].regmap,CCREG);
5700       if(cc==-1) {
5701         emit_loadreg(CCREG,cc=HOST_CCREG);
5702         // CHECK: Is the following instruction (fall thru) allocated ok?
5703       }
5704       assert(cc==HOST_CCREG);
5705       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5706       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5707       assem_debug("cycle count (adj)\n");
5708       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5709       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5710       if(internal)
5711         assem_debug("branch: internal\n");
5712       else
5713         assem_debug("branch: external\n");
5714       if(internal&&is_ds[(ba[i]-start)>>2]) {
5715         ds_assemble_entry(i);
5716       }
5717       else {
5718         add_to_linker((int)out,ba[i],internal);
5719         emit_jmp(0);
5720       }
5721     }
5722     // branch not taken
5723     cop1_usable=prev_cop1_usable;
5724     if(!unconditional) {
5725       if(nottaken1) set_jump_target(nottaken1,(int)out);
5726       set_jump_target(nottaken,(int)out);
5727       assem_debug("2:\n");
5728       if(!likely[i]) {
5729         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5730                       ds_unneeded,ds_unneeded_upper);
5731         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5732         address_generation(i+1,&branch_regs[i],0);
5733         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5734         ds_assemble(i+1,&branch_regs[i]);
5735       }
5736       cc=get_reg(branch_regs[i].regmap,CCREG);
5737       if(cc==-1&&!likely[i]) {
5738         // Cycle count isn't in a register, temporarily load it then write it out
5739         emit_loadreg(CCREG,HOST_CCREG);
5740         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5741         int jaddr=(int)out;
5742         emit_jns(0);
5743         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5744         emit_storereg(CCREG,HOST_CCREG);
5745       }
5746       else{
5747         cc=get_reg(i_regmap,CCREG);
5748         assert(cc==HOST_CCREG);
5749         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5750         int jaddr=(int)out;
5751         emit_jns(0);
5752         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5753       }
5754     }
5755   }
5756 }
5757
5758 void sjump_assemble(int i,struct regstat *i_regs)
5759 {
5760   signed char *i_regmap=i_regs->regmap;
5761   int cc;
5762   int match;
5763   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5764   assem_debug("smatch=%d\n",match);
5765   int s1h,s1l;
5766   int prev_cop1_usable=cop1_usable;
5767   int unconditional=0,nevertaken=0;
5768   int only32=0;
5769   int invert=0;
5770   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5771   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5772   if(!match) invert=1;
5773   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5774   if(i>(ba[i]-start)>>2) invert=1;
5775   #endif
5776
5777   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5778   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5779
5780   if(ooo[i]) {
5781     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5782     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5783   }
5784   else {
5785     s1l=get_reg(i_regmap,rs1[i]);
5786     s1h=get_reg(i_regmap,rs1[i]|64);
5787   }
5788   if(rs1[i]==0)
5789   {
5790     if(opcode2[i]&1) unconditional=1;
5791     else nevertaken=1;
5792     // These are never taken (r0 is never less than zero)
5793     //assert(opcode2[i]!=0);
5794     //assert(opcode2[i]!=2);
5795     //assert(opcode2[i]!=0x10);
5796     //assert(opcode2[i]!=0x12);
5797   }
5798   else {
5799     only32=(regs[i].was32>>rs1[i])&1;
5800   }
5801
5802   if(ooo[i]) {
5803     // Out of order execution (delay slot first)
5804     //printf("OOOE\n");
5805     address_generation(i+1,i_regs,regs[i].regmap_entry);
5806     ds_assemble(i+1,i_regs);
5807     int adj;
5808     uint64_t bc_unneeded=branch_regs[i].u;
5809     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5810     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5811     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5812     bc_unneeded|=1;
5813     bc_unneeded_upper|=1;
5814     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5815                   bc_unneeded,bc_unneeded_upper);
5816     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5817     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5818     if(rt1[i]==31) {
5819       int rt,return_address;
5820       rt=get_reg(branch_regs[i].regmap,31);
5821       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5822       if(rt>=0) {
5823         // Save the PC even if the branch is not taken
5824         return_address=start+i*4+8;
5825         emit_movimm(return_address,rt); // PC into link register
5826         #ifdef IMM_PREFETCH
5827         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5828         #endif
5829       }
5830     }
5831     cc=get_reg(branch_regs[i].regmap,CCREG);
5832     assert(cc==HOST_CCREG);
5833     if(unconditional)
5834       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5835     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5836     assem_debug("cycle count (adj)\n");
5837     if(unconditional) {
5838       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5839       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5840         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5841         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5842         if(internal)
5843           assem_debug("branch: internal\n");
5844         else
5845           assem_debug("branch: external\n");
5846         if(internal&&is_ds[(ba[i]-start)>>2]) {
5847           ds_assemble_entry(i);
5848         }
5849         else {
5850           add_to_linker((int)out,ba[i],internal);
5851           emit_jmp(0);
5852         }
5853         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5854         if(((u_int)out)&7) emit_addnop(0);
5855         #endif
5856       }
5857     }
5858     else if(nevertaken) {
5859       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5860       int jaddr=(int)out;
5861       emit_jns(0);
5862       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5863     }
5864     else {
5865       int nottaken=0;
5866       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5867       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5868       if(!only32)
5869       {
5870         assert(s1h>=0);
5871         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5872         {
5873           emit_test(s1h,s1h);
5874           if(invert){
5875             nottaken=(int)out;
5876             emit_jns(1);
5877           }else{
5878             add_to_linker((int)out,ba[i],internal);
5879             emit_js(0);
5880           }
5881         }
5882         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5883         {
5884           emit_test(s1h,s1h);
5885           if(invert){
5886             nottaken=(int)out;
5887             emit_js(1);
5888           }else{
5889             add_to_linker((int)out,ba[i],internal);
5890             emit_jns(0);
5891           }
5892         }
5893       } // if(!only32)
5894       else
5895       {
5896         assert(s1l>=0);
5897         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5898         {
5899           emit_test(s1l,s1l);
5900           if(invert){
5901             nottaken=(int)out;
5902             emit_jns(1);
5903           }else{
5904             add_to_linker((int)out,ba[i],internal);
5905             emit_js(0);
5906           }
5907         }
5908         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5909         {
5910           emit_test(s1l,s1l);
5911           if(invert){
5912             nottaken=(int)out;
5913             emit_js(1);
5914           }else{
5915             add_to_linker((int)out,ba[i],internal);
5916             emit_jns(0);
5917           }
5918         }
5919       } // if(!only32)
5920
5921       if(invert) {
5922         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5923         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5924           if(adj) {
5925             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5926             add_to_linker((int)out,ba[i],internal);
5927           }else{
5928             emit_addnop(13);
5929             add_to_linker((int)out,ba[i],internal*2);
5930           }
5931           emit_jmp(0);
5932         }else
5933         #endif
5934         {
5935           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5936           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5937           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5938           if(internal)
5939             assem_debug("branch: internal\n");
5940           else
5941             assem_debug("branch: external\n");
5942           if(internal&&is_ds[(ba[i]-start)>>2]) {
5943             ds_assemble_entry(i);
5944           }
5945           else {
5946             add_to_linker((int)out,ba[i],internal);
5947             emit_jmp(0);
5948           }
5949         }
5950         set_jump_target(nottaken,(int)out);
5951       }
5952
5953       if(adj) {
5954         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5955       }
5956     } // (!unconditional)
5957   } // if(ooo)
5958   else
5959   {
5960     // In-order execution (branch first)
5961     //printf("IOE\n");
5962     int nottaken=0;
5963     if(rt1[i]==31) {
5964       int rt,return_address;
5965       rt=get_reg(branch_regs[i].regmap,31);
5966       if(rt>=0) {
5967         // Save the PC even if the branch is not taken
5968         return_address=start+i*4+8;
5969         emit_movimm(return_address,rt); // PC into link register
5970         #ifdef IMM_PREFETCH
5971         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5972         #endif
5973       }
5974     }
5975     if(!unconditional) {
5976       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5977       if(!only32)
5978       {
5979         assert(s1h>=0);
5980         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5981         {
5982           emit_test(s1h,s1h);
5983           nottaken=(int)out;
5984           emit_jns(1);
5985         }
5986         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5987         {
5988           emit_test(s1h,s1h);
5989           nottaken=(int)out;
5990           emit_js(1);
5991         }
5992       } // if(!only32)
5993       else
5994       {
5995         assert(s1l>=0);
5996         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5997         {
5998           emit_test(s1l,s1l);
5999           nottaken=(int)out;
6000           emit_jns(1);
6001         }
6002         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6003         {
6004           emit_test(s1l,s1l);
6005           nottaken=(int)out;
6006           emit_js(1);
6007         }
6008       }
6009     } // if(!unconditional)
6010     int adj;
6011     uint64_t ds_unneeded=branch_regs[i].u;
6012     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6013     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6014     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6015     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6016     ds_unneeded|=1;
6017     ds_unneeded_upper|=1;
6018     // branch taken
6019     if(!nevertaken) {
6020       //assem_debug("1:\n");
6021       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6022                     ds_unneeded,ds_unneeded_upper);
6023       // load regs
6024       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6025       address_generation(i+1,&branch_regs[i],0);
6026       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6027       ds_assemble(i+1,&branch_regs[i]);
6028       cc=get_reg(branch_regs[i].regmap,CCREG);
6029       if(cc==-1) {
6030         emit_loadreg(CCREG,cc=HOST_CCREG);
6031         // CHECK: Is the following instruction (fall thru) allocated ok?
6032       }
6033       assert(cc==HOST_CCREG);
6034       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6035       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6036       assem_debug("cycle count (adj)\n");
6037       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6038       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6039       if(internal)
6040         assem_debug("branch: internal\n");
6041       else
6042         assem_debug("branch: external\n");
6043       if(internal&&is_ds[(ba[i]-start)>>2]) {
6044         ds_assemble_entry(i);
6045       }
6046       else {
6047         add_to_linker((int)out,ba[i],internal);
6048         emit_jmp(0);
6049       }
6050     }
6051     // branch not taken
6052     cop1_usable=prev_cop1_usable;
6053     if(!unconditional) {
6054       set_jump_target(nottaken,(int)out);
6055       assem_debug("1:\n");
6056       if(!likely[i]) {
6057         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6058                       ds_unneeded,ds_unneeded_upper);
6059         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6060         address_generation(i+1,&branch_regs[i],0);
6061         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6062         ds_assemble(i+1,&branch_regs[i]);
6063       }
6064       cc=get_reg(branch_regs[i].regmap,CCREG);
6065       if(cc==-1&&!likely[i]) {
6066         // Cycle count isn't in a register, temporarily load it then write it out
6067         emit_loadreg(CCREG,HOST_CCREG);
6068         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6069         int jaddr=(int)out;
6070         emit_jns(0);
6071         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6072         emit_storereg(CCREG,HOST_CCREG);
6073       }
6074       else{
6075         cc=get_reg(i_regmap,CCREG);
6076         assert(cc==HOST_CCREG);
6077         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6078         int jaddr=(int)out;
6079         emit_jns(0);
6080         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6081       }
6082     }
6083   }
6084 }
6085
6086 void fjump_assemble(int i,struct regstat *i_regs)
6087 {
6088   signed char *i_regmap=i_regs->regmap;
6089   int cc;
6090   int match;
6091   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6092   assem_debug("fmatch=%d\n",match);
6093   int fs,cs;
6094   int eaddr;
6095   int invert=0;
6096   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6097   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6098   if(!match) invert=1;
6099   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6100   if(i>(ba[i]-start)>>2) invert=1;
6101   #endif
6102
6103   if(ooo[i]) {
6104     fs=get_reg(branch_regs[i].regmap,FSREG);
6105     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6106   }
6107   else {
6108     fs=get_reg(i_regmap,FSREG);
6109   }
6110
6111   // Check cop1 unusable
6112   if(!cop1_usable) {
6113     cs=get_reg(i_regmap,CSREG);
6114     assert(cs>=0);
6115     emit_testimm(cs,0x20000000);
6116     eaddr=(int)out;
6117     emit_jeq(0);
6118     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6119     cop1_usable=1;
6120   }
6121
6122   if(ooo[i]) {
6123     // Out of order execution (delay slot first)
6124     //printf("OOOE\n");
6125     ds_assemble(i+1,i_regs);
6126     int adj;
6127     uint64_t bc_unneeded=branch_regs[i].u;
6128     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6129     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6130     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6131     bc_unneeded|=1;
6132     bc_unneeded_upper|=1;
6133     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6134                   bc_unneeded,bc_unneeded_upper);
6135     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6136     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6137     cc=get_reg(branch_regs[i].regmap,CCREG);
6138     assert(cc==HOST_CCREG);
6139     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6140     assem_debug("cycle count (adj)\n");
6141     if(1) {
6142       int nottaken=0;
6143       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6144       if(1) {
6145         assert(fs>=0);
6146         emit_testimm(fs,0x800000);
6147         if(source[i]&0x10000) // BC1T
6148         {
6149           if(invert){
6150             nottaken=(int)out;
6151             emit_jeq(1);
6152           }else{
6153             add_to_linker((int)out,ba[i],internal);
6154             emit_jne(0);
6155           }
6156         }
6157         else // BC1F
6158           if(invert){
6159             nottaken=(int)out;
6160             emit_jne(1);
6161           }else{
6162             add_to_linker((int)out,ba[i],internal);
6163             emit_jeq(0);
6164           }
6165         {
6166         }
6167       } // if(!only32)
6168
6169       if(invert) {
6170         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6171         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6172         else if(match) emit_addnop(13);
6173         #endif
6174         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6175         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6176         if(internal)
6177           assem_debug("branch: internal\n");
6178         else
6179           assem_debug("branch: external\n");
6180         if(internal&&is_ds[(ba[i]-start)>>2]) {
6181           ds_assemble_entry(i);
6182         }
6183         else {
6184           add_to_linker((int)out,ba[i],internal);
6185           emit_jmp(0);
6186         }
6187         set_jump_target(nottaken,(int)out);
6188       }
6189
6190       if(adj) {
6191         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6192       }
6193     } // (!unconditional)
6194   } // if(ooo)
6195   else
6196   {
6197     // In-order execution (branch first)
6198     //printf("IOE\n");
6199     int nottaken=0;
6200     if(1) {
6201       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6202       if(1) {
6203         assert(fs>=0);
6204         emit_testimm(fs,0x800000);
6205         if(source[i]&0x10000) // BC1T
6206         {
6207           nottaken=(int)out;
6208           emit_jeq(1);
6209         }
6210         else // BC1F
6211         {
6212           nottaken=(int)out;
6213           emit_jne(1);
6214         }
6215       }
6216     } // if(!unconditional)
6217     int adj;
6218     uint64_t ds_unneeded=branch_regs[i].u;
6219     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6220     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6221     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6222     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6223     ds_unneeded|=1;
6224     ds_unneeded_upper|=1;
6225     // branch taken
6226     //assem_debug("1:\n");
6227     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6228                   ds_unneeded,ds_unneeded_upper);
6229     // load regs
6230     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6231     address_generation(i+1,&branch_regs[i],0);
6232     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6233     ds_assemble(i+1,&branch_regs[i]);
6234     cc=get_reg(branch_regs[i].regmap,CCREG);
6235     if(cc==-1) {
6236       emit_loadreg(CCREG,cc=HOST_CCREG);
6237       // CHECK: Is the following instruction (fall thru) allocated ok?
6238     }
6239     assert(cc==HOST_CCREG);
6240     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6241     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6242     assem_debug("cycle count (adj)\n");
6243     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6244     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6245     if(internal)
6246       assem_debug("branch: internal\n");
6247     else
6248       assem_debug("branch: external\n");
6249     if(internal&&is_ds[(ba[i]-start)>>2]) {
6250       ds_assemble_entry(i);
6251     }
6252     else {
6253       add_to_linker((int)out,ba[i],internal);
6254       emit_jmp(0);
6255     }
6256
6257     // branch not taken
6258     if(1) { // <- FIXME (don't need this)
6259       set_jump_target(nottaken,(int)out);
6260       assem_debug("1:\n");
6261       if(!likely[i]) {
6262         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6263                       ds_unneeded,ds_unneeded_upper);
6264         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6265         address_generation(i+1,&branch_regs[i],0);
6266         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6267         ds_assemble(i+1,&branch_regs[i]);
6268       }
6269       cc=get_reg(branch_regs[i].regmap,CCREG);
6270       if(cc==-1&&!likely[i]) {
6271         // Cycle count isn't in a register, temporarily load it then write it out
6272         emit_loadreg(CCREG,HOST_CCREG);
6273         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6274         int jaddr=(int)out;
6275         emit_jns(0);
6276         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6277         emit_storereg(CCREG,HOST_CCREG);
6278       }
6279       else{
6280         cc=get_reg(i_regmap,CCREG);
6281         assert(cc==HOST_CCREG);
6282         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6283         int jaddr=(int)out;
6284         emit_jns(0);
6285         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6286       }
6287     }
6288   }
6289 }
6290
6291 static void pagespan_assemble(int i,struct regstat *i_regs)
6292 {
6293   int s1l=get_reg(i_regs->regmap,rs1[i]);
6294   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6295   int s2l=get_reg(i_regs->regmap,rs2[i]);
6296   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6297   void *nt_branch=NULL;
6298   int taken=0;
6299   int nottaken=0;
6300   int unconditional=0;
6301   if(rs1[i]==0)
6302   {
6303     s1l=s2l;s1h=s2h;
6304     s2l=s2h=-1;
6305   }
6306   else if(rs2[i]==0)
6307   {
6308     s2l=s2h=-1;
6309   }
6310   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6311     s1h=s2h=-1;
6312   }
6313   int hr=0;
6314   int addr,alt,ntaddr;
6315   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6316   else {
6317     while(hr<HOST_REGS)
6318     {
6319       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6320          (i_regs->regmap[hr]&63)!=rs1[i] &&
6321          (i_regs->regmap[hr]&63)!=rs2[i] )
6322       {
6323         addr=hr++;break;
6324       }
6325       hr++;
6326     }
6327   }
6328   while(hr<HOST_REGS)
6329   {
6330     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6331        (i_regs->regmap[hr]&63)!=rs1[i] &&
6332        (i_regs->regmap[hr]&63)!=rs2[i] )
6333     {
6334       alt=hr++;break;
6335     }
6336     hr++;
6337   }
6338   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6339   {
6340     while(hr<HOST_REGS)
6341     {
6342       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6343          (i_regs->regmap[hr]&63)!=rs1[i] &&
6344          (i_regs->regmap[hr]&63)!=rs2[i] )
6345       {
6346         ntaddr=hr;break;
6347       }
6348       hr++;
6349     }
6350   }
6351   assert(hr<HOST_REGS);
6352   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6353     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6354   }
6355   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6356   if(opcode[i]==2) // J
6357   {
6358     unconditional=1;
6359   }
6360   if(opcode[i]==3) // JAL
6361   {
6362     // TODO: mini_ht
6363     int rt=get_reg(i_regs->regmap,31);
6364     emit_movimm(start+i*4+8,rt);
6365     unconditional=1;
6366   }
6367   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6368   {
6369     emit_mov(s1l,addr);
6370     if(opcode2[i]==9) // JALR
6371     {
6372       int rt=get_reg(i_regs->regmap,rt1[i]);
6373       emit_movimm(start+i*4+8,rt);
6374     }
6375   }
6376   if((opcode[i]&0x3f)==4) // BEQ
6377   {
6378     if(rs1[i]==rs2[i])
6379     {
6380       unconditional=1;
6381     }
6382     else
6383     #ifdef HAVE_CMOV_IMM
6384     if(s1h<0) {
6385       if(s2l>=0) emit_cmp(s1l,s2l);
6386       else emit_test(s1l,s1l);
6387       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6388     }
6389     else
6390     #endif
6391     {
6392       assert(s1l>=0);
6393       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6394       if(s1h>=0) {
6395         if(s2h>=0) emit_cmp(s1h,s2h);
6396         else emit_test(s1h,s1h);
6397         emit_cmovne_reg(alt,addr);
6398       }
6399       if(s2l>=0) emit_cmp(s1l,s2l);
6400       else emit_test(s1l,s1l);
6401       emit_cmovne_reg(alt,addr);
6402     }
6403   }
6404   if((opcode[i]&0x3f)==5) // BNE
6405   {
6406     #ifdef HAVE_CMOV_IMM
6407     if(s1h<0) {
6408       if(s2l>=0) emit_cmp(s1l,s2l);
6409       else emit_test(s1l,s1l);
6410       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6411     }
6412     else
6413     #endif
6414     {
6415       assert(s1l>=0);
6416       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6417       if(s1h>=0) {
6418         if(s2h>=0) emit_cmp(s1h,s2h);
6419         else emit_test(s1h,s1h);
6420         emit_cmovne_reg(alt,addr);
6421       }
6422       if(s2l>=0) emit_cmp(s1l,s2l);
6423       else emit_test(s1l,s1l);
6424       emit_cmovne_reg(alt,addr);
6425     }
6426   }
6427   if((opcode[i]&0x3f)==0x14) // BEQL
6428   {
6429     if(s1h>=0) {
6430       if(s2h>=0) emit_cmp(s1h,s2h);
6431       else emit_test(s1h,s1h);
6432       nottaken=(int)out;
6433       emit_jne(0);
6434     }
6435     if(s2l>=0) emit_cmp(s1l,s2l);
6436     else emit_test(s1l,s1l);
6437     if(nottaken) set_jump_target(nottaken,(int)out);
6438     nottaken=(int)out;
6439     emit_jne(0);
6440   }
6441   if((opcode[i]&0x3f)==0x15) // BNEL
6442   {
6443     if(s1h>=0) {
6444       if(s2h>=0) emit_cmp(s1h,s2h);
6445       else emit_test(s1h,s1h);
6446       taken=(int)out;
6447       emit_jne(0);
6448     }
6449     if(s2l>=0) emit_cmp(s1l,s2l);
6450     else emit_test(s1l,s1l);
6451     nottaken=(int)out;
6452     emit_jeq(0);
6453     if(taken) set_jump_target(taken,(int)out);
6454   }
6455   if((opcode[i]&0x3f)==6) // BLEZ
6456   {
6457     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6458     emit_cmpimm(s1l,1);
6459     if(s1h>=0) emit_mov(addr,ntaddr);
6460     emit_cmovl_reg(alt,addr);
6461     if(s1h>=0) {
6462       emit_test(s1h,s1h);
6463       emit_cmovne_reg(ntaddr,addr);
6464       emit_cmovs_reg(alt,addr);
6465     }
6466   }
6467   if((opcode[i]&0x3f)==7) // BGTZ
6468   {
6469     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6470     emit_cmpimm(s1l,1);
6471     if(s1h>=0) emit_mov(addr,alt);
6472     emit_cmovl_reg(ntaddr,addr);
6473     if(s1h>=0) {
6474       emit_test(s1h,s1h);
6475       emit_cmovne_reg(alt,addr);
6476       emit_cmovs_reg(ntaddr,addr);
6477     }
6478   }
6479   if((opcode[i]&0x3f)==0x16) // BLEZL
6480   {
6481     assert((opcode[i]&0x3f)!=0x16);
6482   }
6483   if((opcode[i]&0x3f)==0x17) // BGTZL
6484   {
6485     assert((opcode[i]&0x3f)!=0x17);
6486   }
6487   assert(opcode[i]!=1); // BLTZ/BGEZ
6488
6489   //FIXME: Check CSREG
6490   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6491     if((source[i]&0x30000)==0) // BC1F
6492     {
6493       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6494       emit_testimm(s1l,0x800000);
6495       emit_cmovne_reg(alt,addr);
6496     }
6497     if((source[i]&0x30000)==0x10000) // BC1T
6498     {
6499       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6500       emit_testimm(s1l,0x800000);
6501       emit_cmovne_reg(alt,addr);
6502     }
6503     if((source[i]&0x30000)==0x20000) // BC1FL
6504     {
6505       emit_testimm(s1l,0x800000);
6506       nottaken=(int)out;
6507       emit_jne(0);
6508     }
6509     if((source[i]&0x30000)==0x30000) // BC1TL
6510     {
6511       emit_testimm(s1l,0x800000);
6512       nottaken=(int)out;
6513       emit_jeq(0);
6514     }
6515   }
6516
6517   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6518   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6519   if(likely[i]||unconditional)
6520   {
6521     emit_movimm(ba[i],HOST_BTREG);
6522   }
6523   else if(addr!=HOST_BTREG)
6524   {
6525     emit_mov(addr,HOST_BTREG);
6526   }
6527   void *branch_addr=out;
6528   emit_jmp(0);
6529   int target_addr=start+i*4+5;
6530   void *stub=out;
6531   void *compiled_target_addr=check_addr(target_addr);
6532   emit_extjump_ds((int)branch_addr,target_addr);
6533   if(compiled_target_addr) {
6534     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6535     add_link(target_addr,stub);
6536   }
6537   else set_jump_target((int)branch_addr,(int)stub);
6538   if(likely[i]) {
6539     // Not-taken path
6540     set_jump_target((int)nottaken,(int)out);
6541     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6542     void *branch_addr=out;
6543     emit_jmp(0);
6544     int target_addr=start+i*4+8;
6545     void *stub=out;
6546     void *compiled_target_addr=check_addr(target_addr);
6547     emit_extjump_ds((int)branch_addr,target_addr);
6548     if(compiled_target_addr) {
6549       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6550       add_link(target_addr,stub);
6551     }
6552     else set_jump_target((int)branch_addr,(int)stub);
6553   }
6554 }
6555
6556 // Assemble the delay slot for the above
6557 static void pagespan_ds()
6558 {
6559   assem_debug("initial delay slot:\n");
6560   u_int vaddr=start+1;
6561   u_int page=get_page(vaddr);
6562   u_int vpage=get_vpage(vaddr);
6563   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6564   do_dirty_stub_ds();
6565   ll_add(jump_in+page,vaddr,(void *)out);
6566   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6567   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6568     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6569   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6570     emit_writeword(HOST_BTREG,(int)&branch_target);
6571   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6572   address_generation(0,&regs[0],regs[0].regmap_entry);
6573   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6574     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6575   cop1_usable=0;
6576   is_delayslot=0;
6577   switch(itype[0]) {
6578     case ALU:
6579       alu_assemble(0,&regs[0]);break;
6580     case IMM16:
6581       imm16_assemble(0,&regs[0]);break;
6582     case SHIFT:
6583       shift_assemble(0,&regs[0]);break;
6584     case SHIFTIMM:
6585       shiftimm_assemble(0,&regs[0]);break;
6586     case LOAD:
6587       load_assemble(0,&regs[0]);break;
6588     case LOADLR:
6589       loadlr_assemble(0,&regs[0]);break;
6590     case STORE:
6591       store_assemble(0,&regs[0]);break;
6592     case STORELR:
6593       storelr_assemble(0,&regs[0]);break;
6594     case COP0:
6595       cop0_assemble(0,&regs[0]);break;
6596     case COP1:
6597       cop1_assemble(0,&regs[0]);break;
6598     case C1LS:
6599       c1ls_assemble(0,&regs[0]);break;
6600     case COP2:
6601       cop2_assemble(0,&regs[0]);break;
6602     case C2LS:
6603       c2ls_assemble(0,&regs[0]);break;
6604     case C2OP:
6605       c2op_assemble(0,&regs[0]);break;
6606     case FCONV:
6607       fconv_assemble(0,&regs[0]);break;
6608     case FLOAT:
6609       float_assemble(0,&regs[0]);break;
6610     case FCOMP:
6611       fcomp_assemble(0,&regs[0]);break;
6612     case MULTDIV:
6613       multdiv_assemble(0,&regs[0]);break;
6614     case MOV:
6615       mov_assemble(0,&regs[0]);break;
6616     case SYSCALL:
6617     case HLECALL:
6618     case INTCALL:
6619     case SPAN:
6620     case UJUMP:
6621     case RJUMP:
6622     case CJUMP:
6623     case SJUMP:
6624     case FJUMP:
6625       printf("Jump in the delay slot.  This is probably a bug.\n");
6626   }
6627   int btaddr=get_reg(regs[0].regmap,BTREG);
6628   if(btaddr<0) {
6629     btaddr=get_reg(regs[0].regmap,-1);
6630     emit_readword((int)&branch_target,btaddr);
6631   }
6632   assert(btaddr!=HOST_CCREG);
6633   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6634 #ifdef HOST_IMM8
6635   emit_movimm(start+4,HOST_TEMPREG);
6636   emit_cmp(btaddr,HOST_TEMPREG);
6637 #else
6638   emit_cmpimm(btaddr,start+4);
6639 #endif
6640   int branch=(int)out;
6641   emit_jeq(0);
6642   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6643   emit_jmp(jump_vaddr_reg[btaddr]);
6644   set_jump_target(branch,(int)out);
6645   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6646   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6647 }
6648
6649 // Basic liveness analysis for MIPS registers
6650 void unneeded_registers(int istart,int iend,int r)
6651 {
6652   int i;
6653   uint64_t u,uu,b,bu;
6654   uint64_t temp_u,temp_uu;
6655   uint64_t tdep;
6656   if(iend==slen-1) {
6657     u=1;uu=1;
6658   }else{
6659     u=unneeded_reg[iend+1];
6660     uu=unneeded_reg_upper[iend+1];
6661     u=1;uu=1;
6662   }
6663   for (i=iend;i>=istart;i--)
6664   {
6665     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6666     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6667     {
6668       // If subroutine call, flag return address as a possible branch target
6669       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6670
6671       if(ba[i]<start || ba[i]>=(start+slen*4))
6672       {
6673         // Branch out of this block, flush all regs
6674         u=1;
6675         uu=1;
6676         /* Hexagon hack
6677         if(itype[i]==UJUMP&&rt1[i]==31)
6678         {
6679           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6680         }
6681         if(itype[i]==RJUMP&&rs1[i]==31)
6682         {
6683           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6684         }
6685         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6686           if(itype[i]==UJUMP&&rt1[i]==31)
6687           {
6688             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6689             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6690           }
6691           if(itype[i]==RJUMP&&rs1[i]==31)
6692           {
6693             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6694             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6695           }
6696         }*/
6697         branch_unneeded_reg[i]=u;
6698         branch_unneeded_reg_upper[i]=uu;
6699         // Merge in delay slot
6700         tdep=(~uu>>rt1[i+1])&1;
6701         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6702         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6703         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6704         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6705         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6706         u|=1;uu|=1;
6707         // If branch is "likely" (and conditional)
6708         // then we skip the delay slot on the fall-thru path
6709         if(likely[i]) {
6710           if(i<slen-1) {
6711             u&=unneeded_reg[i+2];
6712             uu&=unneeded_reg_upper[i+2];
6713           }
6714           else
6715           {
6716             u=1;
6717             uu=1;
6718           }
6719         }
6720       }
6721       else
6722       {
6723         // Internal branch, flag target
6724         bt[(ba[i]-start)>>2]=1;
6725         if(ba[i]<=start+i*4) {
6726           // Backward branch
6727           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6728           {
6729             // Unconditional branch
6730             temp_u=1;temp_uu=1;
6731           } else {
6732             // Conditional branch (not taken case)
6733             temp_u=unneeded_reg[i+2];
6734             temp_uu=unneeded_reg_upper[i+2];
6735           }
6736           // Merge in delay slot
6737           tdep=(~temp_uu>>rt1[i+1])&1;
6738           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6739           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6740           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6741           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6742           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6743           temp_u|=1;temp_uu|=1;
6744           // If branch is "likely" (and conditional)
6745           // then we skip the delay slot on the fall-thru path
6746           if(likely[i]) {
6747             if(i<slen-1) {
6748               temp_u&=unneeded_reg[i+2];
6749               temp_uu&=unneeded_reg_upper[i+2];
6750             }
6751             else
6752             {
6753               temp_u=1;
6754               temp_uu=1;
6755             }
6756           }
6757           tdep=(~temp_uu>>rt1[i])&1;
6758           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6759           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6760           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6761           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6762           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6763           temp_u|=1;temp_uu|=1;
6764           unneeded_reg[i]=temp_u;
6765           unneeded_reg_upper[i]=temp_uu;
6766           // Only go three levels deep.  This recursion can take an
6767           // excessive amount of time if there are a lot of nested loops.
6768           if(r<2) {
6769             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6770           }else{
6771             unneeded_reg[(ba[i]-start)>>2]=1;
6772             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6773           }
6774         } /*else*/ if(1) {
6775           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6776           {
6777             // Unconditional branch
6778             u=unneeded_reg[(ba[i]-start)>>2];
6779             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6780             branch_unneeded_reg[i]=u;
6781             branch_unneeded_reg_upper[i]=uu;
6782         //u=1;
6783         //uu=1;
6784         //branch_unneeded_reg[i]=u;
6785         //branch_unneeded_reg_upper[i]=uu;
6786             // Merge in delay slot
6787             tdep=(~uu>>rt1[i+1])&1;
6788             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6789             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6790             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6791             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6792             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6793             u|=1;uu|=1;
6794           } else {
6795             // Conditional branch
6796             b=unneeded_reg[(ba[i]-start)>>2];
6797             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6798             branch_unneeded_reg[i]=b;
6799             branch_unneeded_reg_upper[i]=bu;
6800         //b=1;
6801         //bu=1;
6802         //branch_unneeded_reg[i]=b;
6803         //branch_unneeded_reg_upper[i]=bu;
6804             // Branch delay slot
6805             tdep=(~uu>>rt1[i+1])&1;
6806             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6807             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6808             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6809             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6810             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6811             b|=1;bu|=1;
6812             // If branch is "likely" then we skip the
6813             // delay slot on the fall-thru path
6814             if(likely[i]) {
6815               u=b;
6816               uu=bu;
6817               if(i<slen-1) {
6818                 u&=unneeded_reg[i+2];
6819                 uu&=unneeded_reg_upper[i+2];
6820         //u=1;
6821         //uu=1;
6822               }
6823             } else {
6824               u&=b;
6825               uu&=bu;
6826         //u=1;
6827         //uu=1;
6828             }
6829             if(i<slen-1) {
6830               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6831               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6832         //branch_unneeded_reg[i]=1;
6833         //branch_unneeded_reg_upper[i]=1;
6834             } else {
6835               branch_unneeded_reg[i]=1;
6836               branch_unneeded_reg_upper[i]=1;
6837             }
6838           }
6839         }
6840       }
6841     }
6842     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6843     {
6844       // SYSCALL instruction (software interrupt)
6845       u=1;
6846       uu=1;
6847     }
6848     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6849     {
6850       // ERET instruction (return from interrupt)
6851       u=1;
6852       uu=1;
6853     }
6854     //u=uu=1; // DEBUG
6855     tdep=(~uu>>rt1[i])&1;
6856     // Written registers are unneeded
6857     u|=1LL<<rt1[i];
6858     u|=1LL<<rt2[i];
6859     uu|=1LL<<rt1[i];
6860     uu|=1LL<<rt2[i];
6861     // Accessed registers are needed
6862     u&=~(1LL<<rs1[i]);
6863     u&=~(1LL<<rs2[i]);
6864     uu&=~(1LL<<us1[i]);
6865     uu&=~(1LL<<us2[i]);
6866     // Source-target dependencies
6867     uu&=~(tdep<<dep1[i]);
6868     uu&=~(tdep<<dep2[i]);
6869     // R0 is always unneeded
6870     u|=1;uu|=1;
6871     // Save it
6872     unneeded_reg[i]=u;
6873     unneeded_reg_upper[i]=uu;
6874     /*
6875     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6876     printf("U:");
6877     int r;
6878     for(r=1;r<=CCREG;r++) {
6879       if((unneeded_reg[i]>>r)&1) {
6880         if(r==HIREG) printf(" HI");
6881         else if(r==LOREG) printf(" LO");
6882         else printf(" r%d",r);
6883       }
6884     }
6885     printf(" UU:");
6886     for(r=1;r<=CCREG;r++) {
6887       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6888         if(r==HIREG) printf(" HI");
6889         else if(r==LOREG) printf(" LO");
6890         else printf(" r%d",r);
6891       }
6892     }
6893     printf("\n");*/
6894   }
6895 #ifdef FORCE32
6896   for (i=iend;i>=istart;i--)
6897   {
6898     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6899   }
6900 #endif
6901 }
6902
6903 // Identify registers which are likely to contain 32-bit values
6904 // This is used to predict whether any branches will jump to a
6905 // location with 64-bit values in registers.
6906 static void provisional_32bit()
6907 {
6908   int i,j;
6909   uint64_t is32=1;
6910   uint64_t lastbranch=1;
6911
6912   for(i=0;i<slen;i++)
6913   {
6914     if(i>0) {
6915       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6916         if(i>1) is32=lastbranch;
6917         else is32=1;
6918       }
6919     }
6920     if(i>1)
6921     {
6922       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6923         if(likely[i-2]) {
6924           if(i>2) is32=lastbranch;
6925           else is32=1;
6926         }
6927       }
6928       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6929       {
6930         if(rs1[i-2]==0||rs2[i-2]==0)
6931         {
6932           if(rs1[i-2]) {
6933             is32|=1LL<<rs1[i-2];
6934           }
6935           if(rs2[i-2]) {
6936             is32|=1LL<<rs2[i-2];
6937           }
6938         }
6939       }
6940     }
6941     // If something jumps here with 64-bit values
6942     // then promote those registers to 64 bits
6943     if(bt[i])
6944     {
6945       uint64_t temp_is32=is32;
6946       for(j=i-1;j>=0;j--)
6947       {
6948         if(ba[j]==start+i*4)
6949           //temp_is32&=branch_regs[j].is32;
6950           temp_is32&=p32[j];
6951       }
6952       for(j=i;j<slen;j++)
6953       {
6954         if(ba[j]==start+i*4)
6955           temp_is32=1;
6956       }
6957       is32=temp_is32;
6958     }
6959     int type=itype[i];
6960     int op=opcode[i];
6961     int op2=opcode2[i];
6962     int rt=rt1[i];
6963     int s1=rs1[i];
6964     int s2=rs2[i];
6965     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6966       // Branches don't write registers, consider the delay slot instead.
6967       type=itype[i+1];
6968       op=opcode[i+1];
6969       op2=opcode2[i+1];
6970       rt=rt1[i+1];
6971       s1=rs1[i+1];
6972       s2=rs2[i+1];
6973       lastbranch=is32;
6974     }
6975     switch(type) {
6976       case LOAD:
6977         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6978            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6979           is32&=~(1LL<<rt);
6980         else
6981           is32|=1LL<<rt;
6982         break;
6983       case STORE:
6984       case STORELR:
6985         break;
6986       case LOADLR:
6987         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6988         if(op==0x22) is32|=1LL<<rt; // LWL
6989         break;
6990       case IMM16:
6991         if (op==0x08||op==0x09|| // ADDI/ADDIU
6992             op==0x0a||op==0x0b|| // SLTI/SLTIU
6993             op==0x0c|| // ANDI
6994             op==0x0f)  // LUI
6995         {
6996           is32|=1LL<<rt;
6997         }
6998         if(op==0x18||op==0x19) { // DADDI/DADDIU
6999           is32&=~(1LL<<rt);
7000           //if(imm[i]==0)
7001           //  is32|=((is32>>s1)&1LL)<<rt;
7002         }
7003         if(op==0x0d||op==0x0e) { // ORI/XORI
7004           uint64_t sr=((is32>>s1)&1LL);
7005           is32&=~(1LL<<rt);
7006           is32|=sr<<rt;
7007         }
7008         break;
7009       case UJUMP:
7010         break;
7011       case RJUMP:
7012         break;
7013       case CJUMP:
7014         break;
7015       case SJUMP:
7016         break;
7017       case FJUMP:
7018         break;
7019       case ALU:
7020         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7021           is32|=1LL<<rt;
7022         }
7023         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7024           is32|=1LL<<rt;
7025         }
7026         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7027           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7028           is32&=~(1LL<<rt);
7029           is32|=sr<<rt;
7030         }
7031         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7032           if(s1==0&&s2==0) {
7033             is32|=1LL<<rt;
7034           }
7035           else if(s2==0) {
7036             uint64_t sr=((is32>>s1)&1LL);
7037             is32&=~(1LL<<rt);
7038             is32|=sr<<rt;
7039           }
7040           else if(s1==0) {
7041             uint64_t sr=((is32>>s2)&1LL);
7042             is32&=~(1LL<<rt);
7043             is32|=sr<<rt;
7044           }
7045           else {
7046             is32&=~(1LL<<rt);
7047           }
7048         }
7049         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7050           if(s1==0&&s2==0) {
7051             is32|=1LL<<rt;
7052           }
7053           else if(s2==0) {
7054             uint64_t sr=((is32>>s1)&1LL);
7055             is32&=~(1LL<<rt);
7056             is32|=sr<<rt;
7057           }
7058           else {
7059             is32&=~(1LL<<rt);
7060           }
7061         }
7062         break;
7063       case MULTDIV:
7064         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7065           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7066         }
7067         else {
7068           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7069         }
7070         break;
7071       case MOV:
7072         {
7073           uint64_t sr=((is32>>s1)&1LL);
7074           is32&=~(1LL<<rt);
7075           is32|=sr<<rt;
7076         }
7077         break;
7078       case SHIFT:
7079         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7080         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7081         break;
7082       case SHIFTIMM:
7083         is32|=1LL<<rt;
7084         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7085         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7086         break;
7087       case COP0:
7088         if(op2==0) is32|=1LL<<rt; // MFC0
7089         break;
7090       case COP1:
7091       case COP2:
7092         if(op2==0) is32|=1LL<<rt; // MFC1
7093         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7094         if(op2==2) is32|=1LL<<rt; // CFC1
7095         break;
7096       case C1LS:
7097       case C2LS:
7098         break;
7099       case FLOAT:
7100       case FCONV:
7101         break;
7102       case FCOMP:
7103         break;
7104       case C2OP:
7105       case SYSCALL:
7106       case HLECALL:
7107         break;
7108       default:
7109         break;
7110     }
7111     is32|=1;
7112     p32[i]=is32;
7113
7114     if(i>0)
7115     {
7116       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7117       {
7118         if(rt1[i-1]==31) // JAL/JALR
7119         {
7120           // Subroutine call will return here, don't alloc any registers
7121           is32=1;
7122         }
7123         else if(i+1<slen)
7124         {
7125           // Internal branch will jump here, match registers to caller
7126           is32=0x3FFFFFFFFLL;
7127         }
7128       }
7129     }
7130   }
7131 }
7132
7133 // Identify registers which may be assumed to contain 32-bit values
7134 // and where optimizations will rely on this.
7135 // This is used to determine whether backward branches can safely
7136 // jump to a location with 64-bit values in registers.
7137 static void provisional_r32()
7138 {
7139   u_int r32=0;
7140   int i;
7141
7142   for (i=slen-1;i>=0;i--)
7143   {
7144     int hr;
7145     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7146     {
7147       if(ba[i]<start || ba[i]>=(start+slen*4))
7148       {
7149         // Branch out of this block, don't need anything
7150         r32=0;
7151       }
7152       else
7153       {
7154         // Internal branch
7155         // Need whatever matches the target
7156         // (and doesn't get overwritten by the delay slot instruction)
7157         r32=0;
7158         int t=(ba[i]-start)>>2;
7159         if(ba[i]>start+i*4) {
7160           // Forward branch
7161           //if(!(requires_32bit[t]&~regs[i].was32))
7162           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7163           if(!(pr32[t]&~regs[i].was32))
7164             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7165         }else{
7166           // Backward branch
7167           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7168             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7169         }
7170       }
7171       // Conditional branch may need registers for following instructions
7172       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7173       {
7174         if(i<slen-2) {
7175           //r32|=requires_32bit[i+2];
7176           r32|=pr32[i+2];
7177           r32&=regs[i].was32;
7178           // Mark this address as a branch target since it may be called
7179           // upon return from interrupt
7180           //bt[i+2]=1;
7181         }
7182       }
7183       // Merge in delay slot
7184       if(!likely[i]) {
7185         // These are overwritten unless the branch is "likely"
7186         // and the delay slot is nullified if not taken
7187         r32&=~(1LL<<rt1[i+1]);
7188         r32&=~(1LL<<rt2[i+1]);
7189       }
7190       // Assume these are needed (delay slot)
7191       if(us1[i+1]>0)
7192       {
7193         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7194       }
7195       if(us2[i+1]>0)
7196       {
7197         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7198       }
7199       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7200       {
7201         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7202       }
7203       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7204       {
7205         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7206       }
7207     }
7208     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7209     {
7210       // SYSCALL instruction (software interrupt)
7211       r32=0;
7212     }
7213     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7214     {
7215       // ERET instruction (return from interrupt)
7216       r32=0;
7217     }
7218     // Check 32 bits
7219     r32&=~(1LL<<rt1[i]);
7220     r32&=~(1LL<<rt2[i]);
7221     if(us1[i]>0)
7222     {
7223       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7224     }
7225     if(us2[i]>0)
7226     {
7227       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7228     }
7229     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7230     {
7231       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7232     }
7233     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7234     {
7235       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7236     }
7237     //requires_32bit[i]=r32;
7238     pr32[i]=r32;
7239
7240     // Dirty registers which are 32-bit, require 32-bit input
7241     // as they will be written as 32-bit values
7242     for(hr=0;hr<HOST_REGS;hr++)
7243     {
7244       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7245         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7246           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7247           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7248           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7249         }
7250       }
7251     }
7252   }
7253 }
7254
7255 // Write back dirty registers as soon as we will no longer modify them,
7256 // so that we don't end up with lots of writes at the branches.
7257 void clean_registers(int istart,int iend,int wr)
7258 {
7259   int i;
7260   int r;
7261   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7262   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7263   if(iend==slen-1) {
7264     will_dirty_i=will_dirty_next=0;
7265     wont_dirty_i=wont_dirty_next=0;
7266   }else{
7267     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7268     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7269   }
7270   for (i=iend;i>=istart;i--)
7271   {
7272     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7273     {
7274       if(ba[i]<start || ba[i]>=(start+slen*4))
7275       {
7276         // Branch out of this block, flush all regs
7277         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7278         {
7279           // Unconditional branch
7280           will_dirty_i=0;
7281           wont_dirty_i=0;
7282           // Merge in delay slot (will dirty)
7283           for(r=0;r<HOST_REGS;r++) {
7284             if(r!=EXCLUDE_REG) {
7285               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7286               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7287               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7288               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7289               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7290               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7291               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7292               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7293               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7294               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7295               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7296               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7297               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7298               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7299             }
7300           }
7301         }
7302         else
7303         {
7304           // Conditional branch
7305           will_dirty_i=0;
7306           wont_dirty_i=wont_dirty_next;
7307           // Merge in delay slot (will dirty)
7308           for(r=0;r<HOST_REGS;r++) {
7309             if(r!=EXCLUDE_REG) {
7310               if(!likely[i]) {
7311                 // Might not dirty if likely branch is not taken
7312                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7313                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7314                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7315                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7316                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7317                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7318                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7319                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7320                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7321                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7322                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7323                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7324                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7325                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7326               }
7327             }
7328           }
7329         }
7330         // Merge in delay slot (wont dirty)
7331         for(r=0;r<HOST_REGS;r++) {
7332           if(r!=EXCLUDE_REG) {
7333             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7334             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7335             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7336             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7337             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7338             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7339             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7340             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7341             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7342             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7343           }
7344         }
7345         if(wr) {
7346           #ifndef DESTRUCTIVE_WRITEBACK
7347           branch_regs[i].dirty&=wont_dirty_i;
7348           #endif
7349           branch_regs[i].dirty|=will_dirty_i;
7350         }
7351       }
7352       else
7353       {
7354         // Internal branch
7355         if(ba[i]<=start+i*4) {
7356           // Backward branch
7357           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7358           {
7359             // Unconditional branch
7360             temp_will_dirty=0;
7361             temp_wont_dirty=0;
7362             // Merge in delay slot (will dirty)
7363             for(r=0;r<HOST_REGS;r++) {
7364               if(r!=EXCLUDE_REG) {
7365                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7366                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7367                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7368                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7369                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7370                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7371                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7372                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7373                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7374                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7375                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7376                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7377                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7378                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7379               }
7380             }
7381           } else {
7382             // Conditional branch (not taken case)
7383             temp_will_dirty=will_dirty_next;
7384             temp_wont_dirty=wont_dirty_next;
7385             // Merge in delay slot (will dirty)
7386             for(r=0;r<HOST_REGS;r++) {
7387               if(r!=EXCLUDE_REG) {
7388                 if(!likely[i]) {
7389                   // Will not dirty if likely branch is not taken
7390                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7391                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7392                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7393                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7394                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7395                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7396                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7397                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7398                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7399                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7400                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7401                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7402                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7403                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7404                 }
7405               }
7406             }
7407           }
7408           // Merge in delay slot (wont dirty)
7409           for(r=0;r<HOST_REGS;r++) {
7410             if(r!=EXCLUDE_REG) {
7411               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7412               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7413               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7414               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7415               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7416               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7417               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7418               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7419               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7420               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7421             }
7422           }
7423           // Deal with changed mappings
7424           if(i<iend) {
7425             for(r=0;r<HOST_REGS;r++) {
7426               if(r!=EXCLUDE_REG) {
7427                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7428                   temp_will_dirty&=~(1<<r);
7429                   temp_wont_dirty&=~(1<<r);
7430                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7431                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7432                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7433                   } else {
7434                     temp_will_dirty|=1<<r;
7435                     temp_wont_dirty|=1<<r;
7436                   }
7437                 }
7438               }
7439             }
7440           }
7441           if(wr) {
7442             will_dirty[i]=temp_will_dirty;
7443             wont_dirty[i]=temp_wont_dirty;
7444             clean_registers((ba[i]-start)>>2,i-1,0);
7445           }else{
7446             // Limit recursion.  It can take an excessive amount
7447             // of time if there are a lot of nested loops.
7448             will_dirty[(ba[i]-start)>>2]=0;
7449             wont_dirty[(ba[i]-start)>>2]=-1;
7450           }
7451         }
7452         /*else*/ if(1)
7453         {
7454           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7455           {
7456             // Unconditional branch
7457             will_dirty_i=0;
7458             wont_dirty_i=0;
7459           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7460             for(r=0;r<HOST_REGS;r++) {
7461               if(r!=EXCLUDE_REG) {
7462                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7463                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7464                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7465                 }
7466                 if(branch_regs[i].regmap[r]>=0) {
7467                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7468                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7469                 }
7470               }
7471             }
7472           //}
7473             // Merge in delay slot
7474             for(r=0;r<HOST_REGS;r++) {
7475               if(r!=EXCLUDE_REG) {
7476                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7477                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7478                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7479                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7480                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7481                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7482                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7483                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7484                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7485                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7486                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7487                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7488                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7489                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7490               }
7491             }
7492           } else {
7493             // Conditional branch
7494             will_dirty_i=will_dirty_next;
7495             wont_dirty_i=wont_dirty_next;
7496           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7497             for(r=0;r<HOST_REGS;r++) {
7498               if(r!=EXCLUDE_REG) {
7499                 signed char target_reg=branch_regs[i].regmap[r];
7500                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7501                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7502                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7503                 }
7504                 else if(target_reg>=0) {
7505                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7506                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7507                 }
7508                 // Treat delay slot as part of branch too
7509                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7510                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7511                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7512                 }
7513                 else
7514                 {
7515                   will_dirty[i+1]&=~(1<<r);
7516                 }*/
7517               }
7518             }
7519           //}
7520             // Merge in delay slot
7521             for(r=0;r<HOST_REGS;r++) {
7522               if(r!=EXCLUDE_REG) {
7523                 if(!likely[i]) {
7524                   // Might not dirty if likely branch is not taken
7525                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7526                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7527                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7528                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7529                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7530                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7531                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7532                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7533                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7534                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7535                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7536                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7537                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7538                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7539                 }
7540               }
7541             }
7542           }
7543           // Merge in delay slot (won't dirty)
7544           for(r=0;r<HOST_REGS;r++) {
7545             if(r!=EXCLUDE_REG) {
7546               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7547               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7548               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7549               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7550               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7551               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7552               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7553               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7554               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7555               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7556             }
7557           }
7558           if(wr) {
7559             #ifndef DESTRUCTIVE_WRITEBACK
7560             branch_regs[i].dirty&=wont_dirty_i;
7561             #endif
7562             branch_regs[i].dirty|=will_dirty_i;
7563           }
7564         }
7565       }
7566     }
7567     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7568     {
7569       // SYSCALL instruction (software interrupt)
7570       will_dirty_i=0;
7571       wont_dirty_i=0;
7572     }
7573     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7574     {
7575       // ERET instruction (return from interrupt)
7576       will_dirty_i=0;
7577       wont_dirty_i=0;
7578     }
7579     will_dirty_next=will_dirty_i;
7580     wont_dirty_next=wont_dirty_i;
7581     for(r=0;r<HOST_REGS;r++) {
7582       if(r!=EXCLUDE_REG) {
7583         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7584         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7585         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7586         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7587         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7588         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7589         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7590         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7591         if(i>istart) {
7592           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7593           {
7594             // Don't store a register immediately after writing it,
7595             // may prevent dual-issue.
7596             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7597             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7598           }
7599         }
7600       }
7601     }
7602     // Save it
7603     will_dirty[i]=will_dirty_i;
7604     wont_dirty[i]=wont_dirty_i;
7605     // Mark registers that won't be dirtied as not dirty
7606     if(wr) {
7607       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7608       for(r=0;r<HOST_REGS;r++) {
7609         if((will_dirty_i>>r)&1) {
7610           printf(" r%d",r);
7611         }
7612       }
7613       printf("\n");*/
7614
7615       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7616         regs[i].dirty|=will_dirty_i;
7617         #ifndef DESTRUCTIVE_WRITEBACK
7618         regs[i].dirty&=wont_dirty_i;
7619         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7620         {
7621           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7622             for(r=0;r<HOST_REGS;r++) {
7623               if(r!=EXCLUDE_REG) {
7624                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7625                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7626                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7627               }
7628             }
7629           }
7630         }
7631         else
7632         {
7633           if(i<iend) {
7634             for(r=0;r<HOST_REGS;r++) {
7635               if(r!=EXCLUDE_REG) {
7636                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7637                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7638                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7639               }
7640             }
7641           }
7642         }
7643         #endif
7644       //}
7645     }
7646     // Deal with changed mappings
7647     temp_will_dirty=will_dirty_i;
7648     temp_wont_dirty=wont_dirty_i;
7649     for(r=0;r<HOST_REGS;r++) {
7650       if(r!=EXCLUDE_REG) {
7651         int nr;
7652         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7653           if(wr) {
7654             #ifndef DESTRUCTIVE_WRITEBACK
7655             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7656             #endif
7657             regs[i].wasdirty|=will_dirty_i&(1<<r);
7658           }
7659         }
7660         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7661           // Register moved to a different register
7662           will_dirty_i&=~(1<<r);
7663           wont_dirty_i&=~(1<<r);
7664           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7665           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7666           if(wr) {
7667             #ifndef DESTRUCTIVE_WRITEBACK
7668             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7669             #endif
7670             regs[i].wasdirty|=will_dirty_i&(1<<r);
7671           }
7672         }
7673         else {
7674           will_dirty_i&=~(1<<r);
7675           wont_dirty_i&=~(1<<r);
7676           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7677             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7678             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7679           } else {
7680             wont_dirty_i|=1<<r;
7681             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7682           }
7683         }
7684       }
7685     }
7686   }
7687 }
7688
7689   /* disassembly */
7690 void disassemble_inst(int i)
7691 {
7692     if (bt[i]) printf("*"); else printf(" ");
7693     switch(itype[i]) {
7694       case UJUMP:
7695         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7696       case CJUMP:
7697         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7698       case SJUMP:
7699         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7700       case FJUMP:
7701         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7702       case RJUMP:
7703         if (opcode[i]==0x9&&rt1[i]!=31)
7704           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7705         else
7706           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7707         break;
7708       case SPAN:
7709         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7710       case IMM16:
7711         if(opcode[i]==0xf) //LUI
7712           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7713         else
7714           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7715         break;
7716       case LOAD:
7717       case LOADLR:
7718         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7719         break;
7720       case STORE:
7721       case STORELR:
7722         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7723         break;
7724       case ALU:
7725       case SHIFT:
7726         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7727         break;
7728       case MULTDIV:
7729         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7730         break;
7731       case SHIFTIMM:
7732         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7733         break;
7734       case MOV:
7735         if((opcode2[i]&0x1d)==0x10)
7736           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7737         else if((opcode2[i]&0x1d)==0x11)
7738           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7739         else
7740           printf (" %x: %s\n",start+i*4,insn[i]);
7741         break;
7742       case COP0:
7743         if(opcode2[i]==0)
7744           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7745         else if(opcode2[i]==4)
7746           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7747         else printf (" %x: %s\n",start+i*4,insn[i]);
7748         break;
7749       case COP1:
7750         if(opcode2[i]<3)
7751           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7752         else if(opcode2[i]>3)
7753           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7754         else printf (" %x: %s\n",start+i*4,insn[i]);
7755         break;
7756       case COP2:
7757         if(opcode2[i]<3)
7758           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7759         else if(opcode2[i]>3)
7760           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7761         else printf (" %x: %s\n",start+i*4,insn[i]);
7762         break;
7763       case C1LS:
7764         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7765         break;
7766       case C2LS:
7767         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7768         break;
7769       case INTCALL:
7770         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7771         break;
7772       default:
7773         //printf (" %s %8x\n",insn[i],source[i]);
7774         printf (" %x: %s\n",start+i*4,insn[i]);
7775     }
7776 }
7777
7778 // clear the state completely, instead of just marking
7779 // things invalid like invalidate_all_pages() does
7780 void new_dynarec_clear_full()
7781 {
7782   int n;
7783   out=(u_char *)BASE_ADDR;
7784   memset(invalid_code,1,sizeof(invalid_code));
7785   memset(hash_table,0xff,sizeof(hash_table));
7786   memset(mini_ht,-1,sizeof(mini_ht));
7787   memset(restore_candidate,0,sizeof(restore_candidate));
7788   memset(shadow,0,sizeof(shadow));
7789   copy=shadow;
7790   expirep=16384; // Expiry pointer, +2 blocks
7791   pending_exception=0;
7792   literalcount=0;
7793   stop_after_jal=0;
7794   // TLB
7795 #ifndef DISABLE_TLB
7796   using_tlb=0;
7797 #endif
7798   sp_in_mirror=0;
7799   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7800     memory_map[n]=-1;
7801   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7802     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7803   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7804     memory_map[n]=-1;
7805   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7806   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7807   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7808 }
7809
7810 void new_dynarec_init()
7811 {
7812   printf("Init new dynarec\n");
7813   out=(u_char *)BASE_ADDR;
7814   if (mmap (out, 1<<TARGET_SIZE_2,
7815             PROT_READ | PROT_WRITE | PROT_EXEC,
7816             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7817             -1, 0) <= 0) {printf("mmap() failed\n");}
7818 #ifdef MUPEN64
7819   rdword=&readmem_dword;
7820   fake_pc.f.r.rs=&readmem_dword;
7821   fake_pc.f.r.rt=&readmem_dword;
7822   fake_pc.f.r.rd=&readmem_dword;
7823 #endif
7824   int n;
7825   new_dynarec_clear_full();
7826 #ifdef HOST_IMM8
7827   // Copy this into local area so we don't have to put it in every literal pool
7828   invc_ptr=invalid_code;
7829 #endif
7830 #ifdef MUPEN64
7831   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7832     writemem[n] = write_nomem_new;
7833     writememb[n] = write_nomemb_new;
7834     writememh[n] = write_nomemh_new;
7835 #ifndef FORCE32
7836     writememd[n] = write_nomemd_new;
7837 #endif
7838     readmem[n] = read_nomem_new;
7839     readmemb[n] = read_nomemb_new;
7840     readmemh[n] = read_nomemh_new;
7841 #ifndef FORCE32
7842     readmemd[n] = read_nomemd_new;
7843 #endif
7844   }
7845   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7846     writemem[n] = write_rdram_new;
7847     writememb[n] = write_rdramb_new;
7848     writememh[n] = write_rdramh_new;
7849 #ifndef FORCE32
7850     writememd[n] = write_rdramd_new;
7851 #endif
7852   }
7853   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7854     writemem[n] = write_nomem_new;
7855     writememb[n] = write_nomemb_new;
7856     writememh[n] = write_nomemh_new;
7857 #ifndef FORCE32
7858     writememd[n] = write_nomemd_new;
7859 #endif
7860     readmem[n] = read_nomem_new;
7861     readmemb[n] = read_nomemb_new;
7862     readmemh[n] = read_nomemh_new;
7863 #ifndef FORCE32
7864     readmemd[n] = read_nomemd_new;
7865 #endif
7866   }
7867 #endif
7868   tlb_hacks();
7869   arch_init();
7870 }
7871
7872 void new_dynarec_cleanup()
7873 {
7874   int n;
7875   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7876   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7877   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7878   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7879   #ifdef ROM_COPY
7880   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7881   #endif
7882 }
7883
7884 int new_recompile_block(int addr)
7885 {
7886 /*
7887   if(addr==0x800cd050) {
7888     int block;
7889     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7890     int n;
7891     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7892   }
7893 */
7894   //if(Count==365117028) tracedebug=1;
7895   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7896   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7897   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7898   //if(debug)
7899   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7900   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7901   /*if(Count>=312978186) {
7902     rlist();
7903   }*/
7904   //rlist();
7905   start = (u_int)addr&~3;
7906   //assert(((u_int)addr&1)==0);
7907 #ifdef PCSX
7908   if(!sp_in_mirror&&(signed int)(psxRegs.GPR.n.sp&0xffe00000)>0x80200000&&
7909      0x10000<=psxRegs.GPR.n.sp&&(psxRegs.GPR.n.sp&~0xe0e00000)<RAM_SIZE) {
7910     printf("SP hack enabled (%08x), @%08x\n", psxRegs.GPR.n.sp, psxRegs.pc);
7911     sp_in_mirror=1;
7912   }
7913   if (Config.HLE && start == 0x80001000) // hlecall
7914   {
7915     // XXX: is this enough? Maybe check hleSoftCall?
7916     u_int beginning=(u_int)out;
7917     u_int page=get_page(start);
7918     invalid_code[start>>12]=0;
7919     emit_movimm(start,0);
7920     emit_writeword(0,(int)&pcaddr);
7921     emit_jmp((int)new_dyna_leave);
7922 #ifdef __arm__
7923     __clear_cache((void *)beginning,out);
7924 #endif
7925     ll_add(jump_in+page,start,(void *)beginning);
7926     return 0;
7927   }
7928   else if ((u_int)addr < 0x00200000 ||
7929     (0xa0000000 <= addr && addr < 0xa0200000)) {
7930     // used for BIOS calls mostly?
7931     source = (u_int *)((u_int)rdram+(start&0x1fffff));
7932     pagelimit = (addr&0xa0000000)|0x00200000;
7933   }
7934   else if (!Config.HLE && (
7935 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7936     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7937     // BIOS
7938     source = (u_int *)((u_int)psxR+(start&0x7ffff));
7939     pagelimit = (addr&0xfff00000)|0x80000;
7940   }
7941   else
7942 #endif
7943 #ifdef MUPEN64
7944   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7945     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7946     pagelimit = 0xa4001000;
7947   }
7948   else
7949 #endif
7950   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7951     source = (u_int *)((u_int)rdram+start-0x80000000);
7952     pagelimit = 0x80000000+RAM_SIZE;
7953   }
7954 #ifndef DISABLE_TLB
7955   else if ((signed int)addr >= (signed int)0xC0000000) {
7956     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7957     //if(tlb_LUT_r[start>>12])
7958       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7959     if((signed int)memory_map[start>>12]>=0) {
7960       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7961       pagelimit=(start+4096)&0xFFFFF000;
7962       int map=memory_map[start>>12];
7963       int i;
7964       for(i=0;i<5;i++) {
7965         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7966         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7967       }
7968       assem_debug("pagelimit=%x\n",pagelimit);
7969       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7970     }
7971     else {
7972       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7973       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7974       return -1; // Caller will invoke exception handler
7975     }
7976     //printf("source= %x\n",(int)source);
7977   }
7978 #endif
7979   else {
7980     printf("Compile at bogus memory address: %x \n", (int)addr);
7981     exit(1);
7982   }
7983
7984   /* Pass 1: disassemble */
7985   /* Pass 2: register dependencies, branch targets */
7986   /* Pass 3: register allocation */
7987   /* Pass 4: branch dependencies */
7988   /* Pass 5: pre-alloc */
7989   /* Pass 6: optimize clean/dirty state */
7990   /* Pass 7: flag 32-bit registers */
7991   /* Pass 8: assembly */
7992   /* Pass 9: linker */
7993   /* Pass 10: garbage collection / free memory */
7994
7995   int i,j;
7996   int done=0;
7997   unsigned int type,op,op2;
7998
7999   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8000
8001   /* Pass 1 disassembly */
8002
8003   for(i=0;!done;i++) {
8004     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8005     minimum_free_regs[i]=0;
8006     opcode[i]=op=source[i]>>26;
8007     switch(op)
8008     {
8009       case 0x00: strcpy(insn[i],"special"); type=NI;
8010         op2=source[i]&0x3f;
8011         switch(op2)
8012         {
8013           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8014           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8015           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8016           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8017           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8018           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8019           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8020           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8021           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8022           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8023           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8024           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8025           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8026           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8027           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8028           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8029           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8030           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8031           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8032           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8033           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8034           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8035           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8036           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8037           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8038           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8039           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8040           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8041           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8042           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8043           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8044           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8045           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8046           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8047           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8048 #ifndef FORCE32
8049           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8050           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8051           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8052           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8053           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8054           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8055           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8056           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8057           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8058           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8059           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8060           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8061           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8062           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8063           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8064           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8065           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8066 #endif
8067         }
8068         break;
8069       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8070         op2=(source[i]>>16)&0x1f;
8071         switch(op2)
8072         {
8073           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8074           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8075           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8076           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8077           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8078           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8079           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8080           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8081           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8082           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8083           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8084           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8085           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8086           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8087         }
8088         break;
8089       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8090       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8091       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8092       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8093       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8094       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8095       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8096       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8097       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8098       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8099       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8100       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8101       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8102       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8103       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8104         op2=(source[i]>>21)&0x1f;
8105         switch(op2)
8106         {
8107           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8108           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8109           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8110           switch(source[i]&0x3f)
8111           {
8112             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8113             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8114             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8115             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8116 #ifdef PCSX
8117             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8118 #else
8119             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8120 #endif
8121           }
8122         }
8123         break;
8124       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8125         op2=(source[i]>>21)&0x1f;
8126         switch(op2)
8127         {
8128           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8129           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8130           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8131           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8132           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8133           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8134           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8135           switch((source[i]>>16)&0x3)
8136           {
8137             case 0x00: strcpy(insn[i],"BC1F"); break;
8138             case 0x01: strcpy(insn[i],"BC1T"); break;
8139             case 0x02: strcpy(insn[i],"BC1FL"); break;
8140             case 0x03: strcpy(insn[i],"BC1TL"); break;
8141           }
8142           break;
8143           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8144           switch(source[i]&0x3f)
8145           {
8146             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8147             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8148             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8149             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8150             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8151             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8152             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8153             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8154             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8155             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8156             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8157             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8158             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8159             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8160             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8161             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8162             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8163             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8164             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8165             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8166             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8167             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8168             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8169             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8170             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8171             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8172             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8173             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8174             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8175             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8176             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8177             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8178             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8179             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8180             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8181           }
8182           break;
8183           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8184           switch(source[i]&0x3f)
8185           {
8186             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8187             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8188             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8189             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8190             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8191             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8192             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8193             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8194             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8195             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8196             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8197             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8198             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8199             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8200             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8201             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8202             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8203             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8204             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8205             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8206             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8207             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8208             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8209             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8210             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8211             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8212             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8213             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8214             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8215             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8216             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8217             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8218             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8219             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8220             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8221           }
8222           break;
8223           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8224           switch(source[i]&0x3f)
8225           {
8226             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8227             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8228           }
8229           break;
8230           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8231           switch(source[i]&0x3f)
8232           {
8233             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8234             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8235           }
8236           break;
8237         }
8238         break;
8239 #ifndef FORCE32
8240       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8241       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8242       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8243       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8244       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8245       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8246       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8247       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8248 #endif
8249       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8250       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8251       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8252       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8253       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8254       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8255       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8256 #ifndef FORCE32
8257       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8258 #endif
8259       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8260       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8261       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8262       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8263 #ifndef FORCE32
8264       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8265       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8266 #endif
8267       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8268       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8269       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8270       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8271 #ifndef FORCE32
8272       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8273       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8274       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8275 #endif
8276       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8277       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8278 #ifndef FORCE32
8279       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8280       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8281       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8282 #endif
8283 #ifdef PCSX
8284       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8285         // note: COP MIPS-1 encoding differs from MIPS32
8286         op2=(source[i]>>21)&0x1f;
8287         if (source[i]&0x3f) {
8288           if (gte_handlers[source[i]&0x3f]!=NULL) {
8289             snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8290             type=C2OP;
8291           }
8292         }
8293         else switch(op2)
8294         {
8295           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8296           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8297           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8298           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8299         }
8300         break;
8301       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8302       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8303       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8304 #endif
8305       default: strcpy(insn[i],"???"); type=NI;
8306         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8307         break;
8308     }
8309     itype[i]=type;
8310     opcode2[i]=op2;
8311     /* Get registers/immediates */
8312     lt1[i]=0;
8313     us1[i]=0;
8314     us2[i]=0;
8315     dep1[i]=0;
8316     dep2[i]=0;
8317     switch(type) {
8318       case LOAD:
8319         rs1[i]=(source[i]>>21)&0x1f;
8320         rs2[i]=0;
8321         rt1[i]=(source[i]>>16)&0x1f;
8322         rt2[i]=0;
8323         imm[i]=(short)source[i];
8324         break;
8325       case STORE:
8326       case STORELR:
8327         rs1[i]=(source[i]>>21)&0x1f;
8328         rs2[i]=(source[i]>>16)&0x1f;
8329         rt1[i]=0;
8330         rt2[i]=0;
8331         imm[i]=(short)source[i];
8332         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8333         break;
8334       case LOADLR:
8335         // LWL/LWR only load part of the register,
8336         // therefore the target register must be treated as a source too
8337         rs1[i]=(source[i]>>21)&0x1f;
8338         rs2[i]=(source[i]>>16)&0x1f;
8339         rt1[i]=(source[i]>>16)&0x1f;
8340         rt2[i]=0;
8341         imm[i]=(short)source[i];
8342         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8343         if(op==0x26) dep1[i]=rt1[i]; // LWR
8344         break;
8345       case IMM16:
8346         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8347         else rs1[i]=(source[i]>>21)&0x1f;
8348         rs2[i]=0;
8349         rt1[i]=(source[i]>>16)&0x1f;
8350         rt2[i]=0;
8351         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8352           imm[i]=(unsigned short)source[i];
8353         }else{
8354           imm[i]=(short)source[i];
8355         }
8356         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8357         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8358         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8359         break;
8360       case UJUMP:
8361         rs1[i]=0;
8362         rs2[i]=0;
8363         rt1[i]=0;
8364         rt2[i]=0;
8365         // The JAL instruction writes to r31.
8366         if (op&1) {
8367           rt1[i]=31;
8368         }
8369         rs2[i]=CCREG;
8370         break;
8371       case RJUMP:
8372         rs1[i]=(source[i]>>21)&0x1f;
8373         rs2[i]=0;
8374         rt1[i]=0;
8375         rt2[i]=0;
8376         // The JALR instruction writes to rd.
8377         if (op2&1) {
8378           rt1[i]=(source[i]>>11)&0x1f;
8379         }
8380         rs2[i]=CCREG;
8381         break;
8382       case CJUMP:
8383         rs1[i]=(source[i]>>21)&0x1f;
8384         rs2[i]=(source[i]>>16)&0x1f;
8385         rt1[i]=0;
8386         rt2[i]=0;
8387         if(op&2) { // BGTZ/BLEZ
8388           rs2[i]=0;
8389         }
8390         us1[i]=rs1[i];
8391         us2[i]=rs2[i];
8392         likely[i]=op>>4;
8393         break;
8394       case SJUMP:
8395         rs1[i]=(source[i]>>21)&0x1f;
8396         rs2[i]=CCREG;
8397         rt1[i]=0;
8398         rt2[i]=0;
8399         us1[i]=rs1[i];
8400         if(op2&0x10) { // BxxAL
8401           rt1[i]=31;
8402           // NOTE: If the branch is not taken, r31 is still overwritten
8403         }
8404         likely[i]=(op2&2)>>1;
8405         break;
8406       case FJUMP:
8407         rs1[i]=FSREG;
8408         rs2[i]=CSREG;
8409         rt1[i]=0;
8410         rt2[i]=0;
8411         likely[i]=((source[i])>>17)&1;
8412         break;
8413       case ALU:
8414         rs1[i]=(source[i]>>21)&0x1f; // source
8415         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8416         rt1[i]=(source[i]>>11)&0x1f; // destination
8417         rt2[i]=0;
8418         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8419           us1[i]=rs1[i];us2[i]=rs2[i];
8420         }
8421         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8422           dep1[i]=rs1[i];dep2[i]=rs2[i];
8423         }
8424         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8425           dep1[i]=rs1[i];dep2[i]=rs2[i];
8426         }
8427         break;
8428       case MULTDIV:
8429         rs1[i]=(source[i]>>21)&0x1f; // source
8430         rs2[i]=(source[i]>>16)&0x1f; // divisor
8431         rt1[i]=HIREG;
8432         rt2[i]=LOREG;
8433         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8434           us1[i]=rs1[i];us2[i]=rs2[i];
8435         }
8436         break;
8437       case MOV:
8438         rs1[i]=0;
8439         rs2[i]=0;
8440         rt1[i]=0;
8441         rt2[i]=0;
8442         if(op2==0x10) rs1[i]=HIREG; // MFHI
8443         if(op2==0x11) rt1[i]=HIREG; // MTHI
8444         if(op2==0x12) rs1[i]=LOREG; // MFLO
8445         if(op2==0x13) rt1[i]=LOREG; // MTLO
8446         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8447         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8448         dep1[i]=rs1[i];
8449         break;
8450       case SHIFT:
8451         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8452         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8453         rt1[i]=(source[i]>>11)&0x1f; // destination
8454         rt2[i]=0;
8455         // DSLLV/DSRLV/DSRAV are 64-bit
8456         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8457         break;
8458       case SHIFTIMM:
8459         rs1[i]=(source[i]>>16)&0x1f;
8460         rs2[i]=0;
8461         rt1[i]=(source[i]>>11)&0x1f;
8462         rt2[i]=0;
8463         imm[i]=(source[i]>>6)&0x1f;
8464         // DSxx32 instructions
8465         if(op2>=0x3c) imm[i]|=0x20;
8466         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8467         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8468         break;
8469       case COP0:
8470         rs1[i]=0;
8471         rs2[i]=0;
8472         rt1[i]=0;
8473         rt2[i]=0;
8474         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8475         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8476         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8477         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8478         break;
8479       case COP1:
8480       case COP2:
8481         rs1[i]=0;
8482         rs2[i]=0;
8483         rt1[i]=0;
8484         rt2[i]=0;
8485         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8486         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8487         if(op2==5) us1[i]=rs1[i]; // DMTC1
8488         rs2[i]=CSREG;
8489         break;
8490       case C1LS:
8491         rs1[i]=(source[i]>>21)&0x1F;
8492         rs2[i]=CSREG;
8493         rt1[i]=0;
8494         rt2[i]=0;
8495         imm[i]=(short)source[i];
8496         break;
8497       case C2LS:
8498         rs1[i]=(source[i]>>21)&0x1F;
8499         rs2[i]=0;
8500         rt1[i]=0;
8501         rt2[i]=0;
8502         imm[i]=(short)source[i];
8503         break;
8504       case FLOAT:
8505       case FCONV:
8506         rs1[i]=0;
8507         rs2[i]=CSREG;
8508         rt1[i]=0;
8509         rt2[i]=0;
8510         break;
8511       case FCOMP:
8512         rs1[i]=FSREG;
8513         rs2[i]=CSREG;
8514         rt1[i]=FSREG;
8515         rt2[i]=0;
8516         break;
8517       case SYSCALL:
8518       case HLECALL:
8519       case INTCALL:
8520         rs1[i]=CCREG;
8521         rs2[i]=0;
8522         rt1[i]=0;
8523         rt2[i]=0;
8524         break;
8525       default:
8526         rs1[i]=0;
8527         rs2[i]=0;
8528         rt1[i]=0;
8529         rt2[i]=0;
8530     }
8531     /* Calculate branch target addresses */
8532     if(type==UJUMP)
8533       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8534     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8535       ba[i]=start+i*4+8; // Ignore never taken branch
8536     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8537       ba[i]=start+i*4+8; // Ignore never taken branch
8538     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8539       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8540     else ba[i]=-1;
8541 #ifdef PCSX
8542     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8543       int do_in_intrp=0;
8544       // branch in delay slot?
8545       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8546         // don't handle first branch and call interpreter if it's hit
8547         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8548         do_in_intrp=1;
8549       }
8550       // basic load delay detection
8551       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8552         int t=(ba[i-1]-start)/4;
8553         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8554           // jump target wants DS result - potential load delay effect
8555           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8556           do_in_intrp=1;
8557           bt[t+1]=1; // expected return from interpreter
8558         }
8559         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8560               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8561           // v0 overwrite like this is a sign of trouble, bail out
8562           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8563           do_in_intrp=1;
8564         }
8565       }
8566       if(do_in_intrp) {
8567         rs1[i-1]=CCREG;
8568         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8569         ba[i-1]=-1;
8570         itype[i-1]=INTCALL;
8571         done=2;
8572         i--; // don't compile the DS
8573       }
8574     }
8575 #endif
8576     /* Is this the end of the block? */
8577     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8578       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8579         done=2;
8580       }
8581       else {
8582         if(stop_after_jal) done=1;
8583         // Stop on BREAK
8584         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8585       }
8586       // Don't recompile stuff that's already compiled
8587       if(check_addr(start+i*4+4)) done=1;
8588       // Don't get too close to the limit
8589       if(i>MAXBLOCK/2) done=1;
8590     }
8591     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8592     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8593     if(done==2) {
8594       // Does the block continue due to a branch?
8595       for(j=i-1;j>=0;j--)
8596       {
8597         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8598         if(ba[j]==start+i*4+4) done=j=0;
8599         if(ba[j]==start+i*4+8) done=j=0;
8600       }
8601     }
8602     //assert(i<MAXBLOCK-1);
8603     if(start+i*4==pagelimit-4) done=1;
8604     assert(start+i*4<pagelimit);
8605     if (i==MAXBLOCK-1) done=1;
8606     // Stop if we're compiling junk
8607     if(itype[i]==NI&&opcode[i]==0x11) {
8608       done=stop_after_jal=1;
8609       printf("Disabled speculative precompilation\n");
8610     }
8611   }
8612   slen=i;
8613   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8614     if(start+i*4==pagelimit) {
8615       itype[i-1]=SPAN;
8616     }
8617   }
8618   assert(slen>0);
8619
8620   /* Pass 2 - Register dependencies and branch targets */
8621
8622   unneeded_registers(0,slen-1,0);
8623
8624   /* Pass 3 - Register allocation */
8625
8626   struct regstat current; // Current register allocations/status
8627   current.is32=1;
8628   current.dirty=0;
8629   current.u=unneeded_reg[0];
8630   current.uu=unneeded_reg_upper[0];
8631   clear_all_regs(current.regmap);
8632   alloc_reg(&current,0,CCREG);
8633   dirty_reg(&current,CCREG);
8634   current.isconst=0;
8635   current.wasconst=0;
8636   int ds=0;
8637   int cc=0;
8638   int hr=-1;
8639
8640 #ifndef FORCE32
8641   provisional_32bit();
8642 #endif
8643   if((u_int)addr&1) {
8644     // First instruction is delay slot
8645     cc=-1;
8646     bt[1]=1;
8647     ds=1;
8648     unneeded_reg[0]=1;
8649     unneeded_reg_upper[0]=1;
8650     current.regmap[HOST_BTREG]=BTREG;
8651   }
8652
8653   for(i=0;i<slen;i++)
8654   {
8655     if(bt[i])
8656     {
8657       int hr;
8658       for(hr=0;hr<HOST_REGS;hr++)
8659       {
8660         // Is this really necessary?
8661         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8662       }
8663       current.isconst=0;
8664     }
8665     if(i>1)
8666     {
8667       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8668       {
8669         if(rs1[i-2]==0||rs2[i-2]==0)
8670         {
8671           if(rs1[i-2]) {
8672             current.is32|=1LL<<rs1[i-2];
8673             int hr=get_reg(current.regmap,rs1[i-2]|64);
8674             if(hr>=0) current.regmap[hr]=-1;
8675           }
8676           if(rs2[i-2]) {
8677             current.is32|=1LL<<rs2[i-2];
8678             int hr=get_reg(current.regmap,rs2[i-2]|64);
8679             if(hr>=0) current.regmap[hr]=-1;
8680           }
8681         }
8682       }
8683     }
8684 #ifndef FORCE32
8685     // If something jumps here with 64-bit values
8686     // then promote those registers to 64 bits
8687     if(bt[i])
8688     {
8689       uint64_t temp_is32=current.is32;
8690       for(j=i-1;j>=0;j--)
8691       {
8692         if(ba[j]==start+i*4)
8693           temp_is32&=branch_regs[j].is32;
8694       }
8695       for(j=i;j<slen;j++)
8696       {
8697         if(ba[j]==start+i*4)
8698           //temp_is32=1;
8699           temp_is32&=p32[j];
8700       }
8701       if(temp_is32!=current.is32) {
8702         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8703         #ifndef DESTRUCTIVE_WRITEBACK
8704         if(ds)
8705         #endif
8706         for(hr=0;hr<HOST_REGS;hr++)
8707         {
8708           int r=current.regmap[hr];
8709           if(r>0&&r<64)
8710           {
8711             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8712               temp_is32|=1LL<<r;
8713               //printf("restore %d\n",r);
8714             }
8715           }
8716         }
8717         current.is32=temp_is32;
8718       }
8719     }
8720 #else
8721     current.is32=-1LL;
8722 #endif
8723
8724     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8725     regs[i].wasconst=current.isconst;
8726     regs[i].was32=current.is32;
8727     regs[i].wasdirty=current.dirty;
8728     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8729     // To change a dirty register from 32 to 64 bits, we must write
8730     // it out during the previous cycle (for branches, 2 cycles)
8731     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8732     {
8733       uint64_t temp_is32=current.is32;
8734       for(j=i-1;j>=0;j--)
8735       {
8736         if(ba[j]==start+i*4+4)
8737           temp_is32&=branch_regs[j].is32;
8738       }
8739       for(j=i;j<slen;j++)
8740       {
8741         if(ba[j]==start+i*4+4)
8742           //temp_is32=1;
8743           temp_is32&=p32[j];
8744       }
8745       if(temp_is32!=current.is32) {
8746         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8747         for(hr=0;hr<HOST_REGS;hr++)
8748         {
8749           int r=current.regmap[hr];
8750           if(r>0)
8751           {
8752             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8753               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8754               {
8755                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8756                 {
8757                   //printf("dump %d/r%d\n",hr,r);
8758                   current.regmap[hr]=-1;
8759                   if(get_reg(current.regmap,r|64)>=0)
8760                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8761                 }
8762               }
8763             }
8764           }
8765         }
8766       }
8767     }
8768     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8769     {
8770       uint64_t temp_is32=current.is32;
8771       for(j=i-1;j>=0;j--)
8772       {
8773         if(ba[j]==start+i*4+8)
8774           temp_is32&=branch_regs[j].is32;
8775       }
8776       for(j=i;j<slen;j++)
8777       {
8778         if(ba[j]==start+i*4+8)
8779           //temp_is32=1;
8780           temp_is32&=p32[j];
8781       }
8782       if(temp_is32!=current.is32) {
8783         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8784         for(hr=0;hr<HOST_REGS;hr++)
8785         {
8786           int r=current.regmap[hr];
8787           if(r>0)
8788           {
8789             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8790               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8791               {
8792                 //printf("dump %d/r%d\n",hr,r);
8793                 current.regmap[hr]=-1;
8794                 if(get_reg(current.regmap,r|64)>=0)
8795                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8796               }
8797             }
8798           }
8799         }
8800       }
8801     }
8802     #endif
8803     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8804       if(i+1<slen) {
8805         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8806         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8807         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8808         current.u|=1;
8809         current.uu|=1;
8810       } else {
8811         current.u=1;
8812         current.uu=1;
8813       }
8814     } else {
8815       if(i+1<slen) {
8816         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8817         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8818         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8819         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8820         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8821         current.u|=1;
8822         current.uu|=1;
8823       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8824     }
8825     is_ds[i]=ds;
8826     if(ds) {
8827       ds=0; // Skip delay slot, already allocated as part of branch
8828       // ...but we need to alloc it in case something jumps here
8829       if(i+1<slen) {
8830         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8831         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8832       }else{
8833         current.u=branch_unneeded_reg[i-1];
8834         current.uu=branch_unneeded_reg_upper[i-1];
8835       }
8836       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8837       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8838       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8839       current.u|=1;
8840       current.uu|=1;
8841       struct regstat temp;
8842       memcpy(&temp,&current,sizeof(current));
8843       temp.wasdirty=temp.dirty;
8844       temp.was32=temp.is32;
8845       // TODO: Take into account unconditional branches, as below
8846       delayslot_alloc(&temp,i);
8847       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8848       regs[i].wasdirty=temp.wasdirty;
8849       regs[i].was32=temp.was32;
8850       regs[i].dirty=temp.dirty;
8851       regs[i].is32=temp.is32;
8852       regs[i].isconst=0;
8853       regs[i].wasconst=0;
8854       current.isconst=0;
8855       // Create entry (branch target) regmap
8856       for(hr=0;hr<HOST_REGS;hr++)
8857       {
8858         int r=temp.regmap[hr];
8859         if(r>=0) {
8860           if(r!=regmap_pre[i][hr]) {
8861             regs[i].regmap_entry[hr]=-1;
8862           }
8863           else
8864           {
8865             if(r<64){
8866               if((current.u>>r)&1) {
8867                 regs[i].regmap_entry[hr]=-1;
8868                 regs[i].regmap[hr]=-1;
8869                 //Don't clear regs in the delay slot as the branch might need them
8870                 //current.regmap[hr]=-1;
8871               }else
8872                 regs[i].regmap_entry[hr]=r;
8873             }
8874             else {
8875               if((current.uu>>(r&63))&1) {
8876                 regs[i].regmap_entry[hr]=-1;
8877                 regs[i].regmap[hr]=-1;
8878                 //Don't clear regs in the delay slot as the branch might need them
8879                 //current.regmap[hr]=-1;
8880               }else
8881                 regs[i].regmap_entry[hr]=r;
8882             }
8883           }
8884         } else {
8885           // First instruction expects CCREG to be allocated
8886           if(i==0&&hr==HOST_CCREG)
8887             regs[i].regmap_entry[hr]=CCREG;
8888           else
8889             regs[i].regmap_entry[hr]=-1;
8890         }
8891       }
8892     }
8893     else { // Not delay slot
8894       switch(itype[i]) {
8895         case UJUMP:
8896           //current.isconst=0; // DEBUG
8897           //current.wasconst=0; // DEBUG
8898           //regs[i].wasconst=0; // DEBUG
8899           clear_const(&current,rt1[i]);
8900           alloc_cc(&current,i);
8901           dirty_reg(&current,CCREG);
8902           if (rt1[i]==31) {
8903             alloc_reg(&current,i,31);
8904             dirty_reg(&current,31);
8905             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8906             //assert(rt1[i+1]!=rt1[i]);
8907             #ifdef REG_PREFETCH
8908             alloc_reg(&current,i,PTEMP);
8909             #endif
8910             //current.is32|=1LL<<rt1[i];
8911           }
8912           ooo[i]=1;
8913           delayslot_alloc(&current,i+1);
8914           //current.isconst=0; // DEBUG
8915           ds=1;
8916           //printf("i=%d, isconst=%x\n",i,current.isconst);
8917           break;
8918         case RJUMP:
8919           //current.isconst=0;
8920           //current.wasconst=0;
8921           //regs[i].wasconst=0;
8922           clear_const(&current,rs1[i]);
8923           clear_const(&current,rt1[i]);
8924           alloc_cc(&current,i);
8925           dirty_reg(&current,CCREG);
8926           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8927             alloc_reg(&current,i,rs1[i]);
8928             if (rt1[i]!=0) {
8929               alloc_reg(&current,i,rt1[i]);
8930               dirty_reg(&current,rt1[i]);
8931               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8932               assert(rt1[i+1]!=rt1[i]);
8933               #ifdef REG_PREFETCH
8934               alloc_reg(&current,i,PTEMP);
8935               #endif
8936             }
8937             #ifdef USE_MINI_HT
8938             if(rs1[i]==31) { // JALR
8939               alloc_reg(&current,i,RHASH);
8940               #ifndef HOST_IMM_ADDR32
8941               alloc_reg(&current,i,RHTBL);
8942               #endif
8943             }
8944             #endif
8945             delayslot_alloc(&current,i+1);
8946           } else {
8947             // The delay slot overwrites our source register,
8948             // allocate a temporary register to hold the old value.
8949             current.isconst=0;
8950             current.wasconst=0;
8951             regs[i].wasconst=0;
8952             delayslot_alloc(&current,i+1);
8953             current.isconst=0;
8954             alloc_reg(&current,i,RTEMP);
8955           }
8956           //current.isconst=0; // DEBUG
8957           ooo[i]=1;
8958           ds=1;
8959           break;
8960         case CJUMP:
8961           //current.isconst=0;
8962           //current.wasconst=0;
8963           //regs[i].wasconst=0;
8964           clear_const(&current,rs1[i]);
8965           clear_const(&current,rs2[i]);
8966           if((opcode[i]&0x3E)==4) // BEQ/BNE
8967           {
8968             alloc_cc(&current,i);
8969             dirty_reg(&current,CCREG);
8970             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8971             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8972             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8973             {
8974               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8975               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8976             }
8977             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8978                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8979               // The delay slot overwrites one of our conditions.
8980               // Allocate the branch condition registers instead.
8981               current.isconst=0;
8982               current.wasconst=0;
8983               regs[i].wasconst=0;
8984               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8985               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8986               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8987               {
8988                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8989                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8990               }
8991             }
8992             else
8993             {
8994               ooo[i]=1;
8995               delayslot_alloc(&current,i+1);
8996             }
8997           }
8998           else
8999           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9000           {
9001             alloc_cc(&current,i);
9002             dirty_reg(&current,CCREG);
9003             alloc_reg(&current,i,rs1[i]);
9004             if(!(current.is32>>rs1[i]&1))
9005             {
9006               alloc_reg64(&current,i,rs1[i]);
9007             }
9008             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9009               // The delay slot overwrites one of our conditions.
9010               // Allocate the branch condition registers instead.
9011               current.isconst=0;
9012               current.wasconst=0;
9013               regs[i].wasconst=0;
9014               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9015               if(!((current.is32>>rs1[i])&1))
9016               {
9017                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9018               }
9019             }
9020             else
9021             {
9022               ooo[i]=1;
9023               delayslot_alloc(&current,i+1);
9024             }
9025           }
9026           else
9027           // Don't alloc the delay slot yet because we might not execute it
9028           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9029           {
9030             current.isconst=0;
9031             current.wasconst=0;
9032             regs[i].wasconst=0;
9033             alloc_cc(&current,i);
9034             dirty_reg(&current,CCREG);
9035             alloc_reg(&current,i,rs1[i]);
9036             alloc_reg(&current,i,rs2[i]);
9037             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9038             {
9039               alloc_reg64(&current,i,rs1[i]);
9040               alloc_reg64(&current,i,rs2[i]);
9041             }
9042           }
9043           else
9044           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9045           {
9046             current.isconst=0;
9047             current.wasconst=0;
9048             regs[i].wasconst=0;
9049             alloc_cc(&current,i);
9050             dirty_reg(&current,CCREG);
9051             alloc_reg(&current,i,rs1[i]);
9052             if(!(current.is32>>rs1[i]&1))
9053             {
9054               alloc_reg64(&current,i,rs1[i]);
9055             }
9056           }
9057           ds=1;
9058           //current.isconst=0;
9059           break;
9060         case SJUMP:
9061           //current.isconst=0;
9062           //current.wasconst=0;
9063           //regs[i].wasconst=0;
9064           clear_const(&current,rs1[i]);
9065           clear_const(&current,rt1[i]);
9066           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9067           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9068           {
9069             alloc_cc(&current,i);
9070             dirty_reg(&current,CCREG);
9071             alloc_reg(&current,i,rs1[i]);
9072             if(!(current.is32>>rs1[i]&1))
9073             {
9074               alloc_reg64(&current,i,rs1[i]);
9075             }
9076             if (rt1[i]==31) { // BLTZAL/BGEZAL
9077               alloc_reg(&current,i,31);
9078               dirty_reg(&current,31);
9079               //#ifdef REG_PREFETCH
9080               //alloc_reg(&current,i,PTEMP);
9081               //#endif
9082               //current.is32|=1LL<<rt1[i];
9083             }
9084             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9085                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9086               // Allocate the branch condition registers instead.
9087               current.isconst=0;
9088               current.wasconst=0;
9089               regs[i].wasconst=0;
9090               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9091               if(!((current.is32>>rs1[i])&1))
9092               {
9093                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9094               }
9095             }
9096             else
9097             {
9098               ooo[i]=1;
9099               delayslot_alloc(&current,i+1);
9100             }
9101           }
9102           else
9103           // Don't alloc the delay slot yet because we might not execute it
9104           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9105           {
9106             current.isconst=0;
9107             current.wasconst=0;
9108             regs[i].wasconst=0;
9109             alloc_cc(&current,i);
9110             dirty_reg(&current,CCREG);
9111             alloc_reg(&current,i,rs1[i]);
9112             if(!(current.is32>>rs1[i]&1))
9113             {
9114               alloc_reg64(&current,i,rs1[i]);
9115             }
9116           }
9117           ds=1;
9118           //current.isconst=0;
9119           break;
9120         case FJUMP:
9121           current.isconst=0;
9122           current.wasconst=0;
9123           regs[i].wasconst=0;
9124           if(likely[i]==0) // BC1F/BC1T
9125           {
9126             // TODO: Theoretically we can run out of registers here on x86.
9127             // The delay slot can allocate up to six, and we need to check
9128             // CSREG before executing the delay slot.  Possibly we can drop
9129             // the cycle count and then reload it after checking that the
9130             // FPU is in a usable state, or don't do out-of-order execution.
9131             alloc_cc(&current,i);
9132             dirty_reg(&current,CCREG);
9133             alloc_reg(&current,i,FSREG);
9134             alloc_reg(&current,i,CSREG);
9135             if(itype[i+1]==FCOMP) {
9136               // The delay slot overwrites the branch condition.
9137               // Allocate the branch condition registers instead.
9138               alloc_cc(&current,i);
9139               dirty_reg(&current,CCREG);
9140               alloc_reg(&current,i,CSREG);
9141               alloc_reg(&current,i,FSREG);
9142             }
9143             else {
9144               ooo[i]=1;
9145               delayslot_alloc(&current,i+1);
9146               alloc_reg(&current,i+1,CSREG);
9147             }
9148           }
9149           else
9150           // Don't alloc the delay slot yet because we might not execute it
9151           if(likely[i]) // BC1FL/BC1TL
9152           {
9153             alloc_cc(&current,i);
9154             dirty_reg(&current,CCREG);
9155             alloc_reg(&current,i,CSREG);
9156             alloc_reg(&current,i,FSREG);
9157           }
9158           ds=1;
9159           current.isconst=0;
9160           break;
9161         case IMM16:
9162           imm16_alloc(&current,i);
9163           break;
9164         case LOAD:
9165         case LOADLR:
9166           load_alloc(&current,i);
9167           break;
9168         case STORE:
9169         case STORELR:
9170           store_alloc(&current,i);
9171           break;
9172         case ALU:
9173           alu_alloc(&current,i);
9174           break;
9175         case SHIFT:
9176           shift_alloc(&current,i);
9177           break;
9178         case MULTDIV:
9179           multdiv_alloc(&current,i);
9180           break;
9181         case SHIFTIMM:
9182           shiftimm_alloc(&current,i);
9183           break;
9184         case MOV:
9185           mov_alloc(&current,i);
9186           break;
9187         case COP0:
9188           cop0_alloc(&current,i);
9189           break;
9190         case COP1:
9191         case COP2:
9192           cop1_alloc(&current,i);
9193           break;
9194         case C1LS:
9195           c1ls_alloc(&current,i);
9196           break;
9197         case C2LS:
9198           c2ls_alloc(&current,i);
9199           break;
9200         case C2OP:
9201           c2op_alloc(&current,i);
9202           break;
9203         case FCONV:
9204           fconv_alloc(&current,i);
9205           break;
9206         case FLOAT:
9207           float_alloc(&current,i);
9208           break;
9209         case FCOMP:
9210           fcomp_alloc(&current,i);
9211           break;
9212         case SYSCALL:
9213         case HLECALL:
9214         case INTCALL:
9215           syscall_alloc(&current,i);
9216           break;
9217         case SPAN:
9218           pagespan_alloc(&current,i);
9219           break;
9220       }
9221
9222       // Drop the upper half of registers that have become 32-bit
9223       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9224       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9225         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9226         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9227         current.uu|=1;
9228       } else {
9229         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9230         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9231         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9232         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9233         current.uu|=1;
9234       }
9235
9236       // Create entry (branch target) regmap
9237       for(hr=0;hr<HOST_REGS;hr++)
9238       {
9239         int r,or,er;
9240         r=current.regmap[hr];
9241         if(r>=0) {
9242           if(r!=regmap_pre[i][hr]) {
9243             // TODO: delay slot (?)
9244             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9245             if(or<0||(r&63)>=TEMPREG){
9246               regs[i].regmap_entry[hr]=-1;
9247             }
9248             else
9249             {
9250               // Just move it to a different register
9251               regs[i].regmap_entry[hr]=r;
9252               // If it was dirty before, it's still dirty
9253               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9254             }
9255           }
9256           else
9257           {
9258             // Unneeded
9259             if(r==0){
9260               regs[i].regmap_entry[hr]=0;
9261             }
9262             else
9263             if(r<64){
9264               if((current.u>>r)&1) {
9265                 regs[i].regmap_entry[hr]=-1;
9266                 //regs[i].regmap[hr]=-1;
9267                 current.regmap[hr]=-1;
9268               }else
9269                 regs[i].regmap_entry[hr]=r;
9270             }
9271             else {
9272               if((current.uu>>(r&63))&1) {
9273                 regs[i].regmap_entry[hr]=-1;
9274                 //regs[i].regmap[hr]=-1;
9275                 current.regmap[hr]=-1;
9276               }else
9277                 regs[i].regmap_entry[hr]=r;
9278             }
9279           }
9280         } else {
9281           // Branches expect CCREG to be allocated at the target
9282           if(regmap_pre[i][hr]==CCREG)
9283             regs[i].regmap_entry[hr]=CCREG;
9284           else
9285             regs[i].regmap_entry[hr]=-1;
9286         }
9287       }
9288       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9289     }
9290     /* Branch post-alloc */
9291     if(i>0)
9292     {
9293       current.was32=current.is32;
9294       current.wasdirty=current.dirty;
9295       switch(itype[i-1]) {
9296         case UJUMP:
9297           memcpy(&branch_regs[i-1],&current,sizeof(current));
9298           branch_regs[i-1].isconst=0;
9299           branch_regs[i-1].wasconst=0;
9300           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9301           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9302           alloc_cc(&branch_regs[i-1],i-1);
9303           dirty_reg(&branch_regs[i-1],CCREG);
9304           if(rt1[i-1]==31) { // JAL
9305             alloc_reg(&branch_regs[i-1],i-1,31);
9306             dirty_reg(&branch_regs[i-1],31);
9307             branch_regs[i-1].is32|=1LL<<31;
9308           }
9309           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9310           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9311           break;
9312         case RJUMP:
9313           memcpy(&branch_regs[i-1],&current,sizeof(current));
9314           branch_regs[i-1].isconst=0;
9315           branch_regs[i-1].wasconst=0;
9316           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9317           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9318           alloc_cc(&branch_regs[i-1],i-1);
9319           dirty_reg(&branch_regs[i-1],CCREG);
9320           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9321           if(rt1[i-1]!=0) { // JALR
9322             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9323             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9324             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9325           }
9326           #ifdef USE_MINI_HT
9327           if(rs1[i-1]==31) { // JALR
9328             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9329             #ifndef HOST_IMM_ADDR32
9330             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9331             #endif
9332           }
9333           #endif
9334           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9335           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9336           break;
9337         case CJUMP:
9338           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9339           {
9340             alloc_cc(&current,i-1);
9341             dirty_reg(&current,CCREG);
9342             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9343                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9344               // The delay slot overwrote one of our conditions
9345               // Delay slot goes after the test (in order)
9346               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9347               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9348               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9349               current.u|=1;
9350               current.uu|=1;
9351               delayslot_alloc(&current,i);
9352               current.isconst=0;
9353             }
9354             else
9355             {
9356               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9357               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9358               // Alloc the branch condition registers
9359               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9360               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9361               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9362               {
9363                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9364                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9365               }
9366             }
9367             memcpy(&branch_regs[i-1],&current,sizeof(current));
9368             branch_regs[i-1].isconst=0;
9369             branch_regs[i-1].wasconst=0;
9370             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9371             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9372           }
9373           else
9374           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9375           {
9376             alloc_cc(&current,i-1);
9377             dirty_reg(&current,CCREG);
9378             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9379               // The delay slot overwrote the branch condition
9380               // Delay slot goes after the test (in order)
9381               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9382               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9383               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9384               current.u|=1;
9385               current.uu|=1;
9386               delayslot_alloc(&current,i);
9387               current.isconst=0;
9388             }
9389             else
9390             {
9391               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9392               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9393               // Alloc the branch condition register
9394               alloc_reg(&current,i-1,rs1[i-1]);
9395               if(!(current.is32>>rs1[i-1]&1))
9396               {
9397                 alloc_reg64(&current,i-1,rs1[i-1]);
9398               }
9399             }
9400             memcpy(&branch_regs[i-1],&current,sizeof(current));
9401             branch_regs[i-1].isconst=0;
9402             branch_regs[i-1].wasconst=0;
9403             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9404             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9405           }
9406           else
9407           // Alloc the delay slot in case the branch is taken
9408           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9409           {
9410             memcpy(&branch_regs[i-1],&current,sizeof(current));
9411             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9412             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9413             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9414             alloc_cc(&branch_regs[i-1],i);
9415             dirty_reg(&branch_regs[i-1],CCREG);
9416             delayslot_alloc(&branch_regs[i-1],i);
9417             branch_regs[i-1].isconst=0;
9418             alloc_reg(&current,i,CCREG); // Not taken path
9419             dirty_reg(&current,CCREG);
9420             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9421           }
9422           else
9423           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9424           {
9425             memcpy(&branch_regs[i-1],&current,sizeof(current));
9426             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9427             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9428             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9429             alloc_cc(&branch_regs[i-1],i);
9430             dirty_reg(&branch_regs[i-1],CCREG);
9431             delayslot_alloc(&branch_regs[i-1],i);
9432             branch_regs[i-1].isconst=0;
9433             alloc_reg(&current,i,CCREG); // Not taken path
9434             dirty_reg(&current,CCREG);
9435             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9436           }
9437           break;
9438         case SJUMP:
9439           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9440           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9441           {
9442             alloc_cc(&current,i-1);
9443             dirty_reg(&current,CCREG);
9444             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9445               // The delay slot overwrote the branch condition
9446               // Delay slot goes after the test (in order)
9447               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9448               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9449               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9450               current.u|=1;
9451               current.uu|=1;
9452               delayslot_alloc(&current,i);
9453               current.isconst=0;
9454             }
9455             else
9456             {
9457               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9458               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9459               // Alloc the branch condition register
9460               alloc_reg(&current,i-1,rs1[i-1]);
9461               if(!(current.is32>>rs1[i-1]&1))
9462               {
9463                 alloc_reg64(&current,i-1,rs1[i-1]);
9464               }
9465             }
9466             memcpy(&branch_regs[i-1],&current,sizeof(current));
9467             branch_regs[i-1].isconst=0;
9468             branch_regs[i-1].wasconst=0;
9469             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9470             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9471           }
9472           else
9473           // Alloc the delay slot in case the branch is taken
9474           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9475           {
9476             memcpy(&branch_regs[i-1],&current,sizeof(current));
9477             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9478             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9479             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9480             alloc_cc(&branch_regs[i-1],i);
9481             dirty_reg(&branch_regs[i-1],CCREG);
9482             delayslot_alloc(&branch_regs[i-1],i);
9483             branch_regs[i-1].isconst=0;
9484             alloc_reg(&current,i,CCREG); // Not taken path
9485             dirty_reg(&current,CCREG);
9486             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9487           }
9488           // FIXME: BLTZAL/BGEZAL
9489           if(opcode2[i-1]&0x10) { // BxxZAL
9490             alloc_reg(&branch_regs[i-1],i-1,31);
9491             dirty_reg(&branch_regs[i-1],31);
9492             branch_regs[i-1].is32|=1LL<<31;
9493           }
9494           break;
9495         case FJUMP:
9496           if(likely[i-1]==0) // BC1F/BC1T
9497           {
9498             alloc_cc(&current,i-1);
9499             dirty_reg(&current,CCREG);
9500             if(itype[i]==FCOMP) {
9501               // The delay slot overwrote the branch condition
9502               // Delay slot goes after the test (in order)
9503               delayslot_alloc(&current,i);
9504               current.isconst=0;
9505             }
9506             else
9507             {
9508               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9509               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9510               // Alloc the branch condition register
9511               alloc_reg(&current,i-1,FSREG);
9512             }
9513             memcpy(&branch_regs[i-1],&current,sizeof(current));
9514             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9515           }
9516           else // BC1FL/BC1TL
9517           {
9518             // Alloc the delay slot in case the branch is taken
9519             memcpy(&branch_regs[i-1],&current,sizeof(current));
9520             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9521             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9522             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9523             alloc_cc(&branch_regs[i-1],i);
9524             dirty_reg(&branch_regs[i-1],CCREG);
9525             delayslot_alloc(&branch_regs[i-1],i);
9526             branch_regs[i-1].isconst=0;
9527             alloc_reg(&current,i,CCREG); // Not taken path
9528             dirty_reg(&current,CCREG);
9529             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9530           }
9531           break;
9532       }
9533
9534       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9535       {
9536         if(rt1[i-1]==31) // JAL/JALR
9537         {
9538           // Subroutine call will return here, don't alloc any registers
9539           current.is32=1;
9540           current.dirty=0;
9541           clear_all_regs(current.regmap);
9542           alloc_reg(&current,i,CCREG);
9543           dirty_reg(&current,CCREG);
9544         }
9545         else if(i+1<slen)
9546         {
9547           // Internal branch will jump here, match registers to caller
9548           current.is32=0x3FFFFFFFFLL;
9549           current.dirty=0;
9550           clear_all_regs(current.regmap);
9551           alloc_reg(&current,i,CCREG);
9552           dirty_reg(&current,CCREG);
9553           for(j=i-1;j>=0;j--)
9554           {
9555             if(ba[j]==start+i*4+4) {
9556               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9557               current.is32=branch_regs[j].is32;
9558               current.dirty=branch_regs[j].dirty;
9559               break;
9560             }
9561           }
9562           while(j>=0) {
9563             if(ba[j]==start+i*4+4) {
9564               for(hr=0;hr<HOST_REGS;hr++) {
9565                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9566                   current.regmap[hr]=-1;
9567                 }
9568                 current.is32&=branch_regs[j].is32;
9569                 current.dirty&=branch_regs[j].dirty;
9570               }
9571             }
9572             j--;
9573           }
9574         }
9575       }
9576     }
9577
9578     // Count cycles in between branches
9579     ccadj[i]=cc;
9580     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9581     {
9582       cc=0;
9583     }
9584 #ifdef PCSX
9585     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9586     {
9587       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9588     }
9589     else if(itype[i]==C2LS)
9590     {
9591       cc+=4;
9592     }
9593 #endif
9594     else
9595     {
9596       cc++;
9597     }
9598
9599     flush_dirty_uppers(&current);
9600     if(!is_ds[i]) {
9601       regs[i].is32=current.is32;
9602       regs[i].dirty=current.dirty;
9603       regs[i].isconst=current.isconst;
9604       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9605     }
9606     for(hr=0;hr<HOST_REGS;hr++) {
9607       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9608         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9609           regs[i].wasconst&=~(1<<hr);
9610         }
9611       }
9612     }
9613     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9614   }
9615
9616   /* Pass 4 - Cull unused host registers */
9617
9618   uint64_t nr=0;
9619
9620   for (i=slen-1;i>=0;i--)
9621   {
9622     int hr;
9623     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9624     {
9625       if(ba[i]<start || ba[i]>=(start+slen*4))
9626       {
9627         // Branch out of this block, don't need anything
9628         nr=0;
9629       }
9630       else
9631       {
9632         // Internal branch
9633         // Need whatever matches the target
9634         nr=0;
9635         int t=(ba[i]-start)>>2;
9636         for(hr=0;hr<HOST_REGS;hr++)
9637         {
9638           if(regs[i].regmap_entry[hr]>=0) {
9639             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9640           }
9641         }
9642       }
9643       // Conditional branch may need registers for following instructions
9644       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9645       {
9646         if(i<slen-2) {
9647           nr|=needed_reg[i+2];
9648           for(hr=0;hr<HOST_REGS;hr++)
9649           {
9650             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9651             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9652           }
9653         }
9654       }
9655       // Don't need stuff which is overwritten
9656       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9657       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9658       // Merge in delay slot
9659       for(hr=0;hr<HOST_REGS;hr++)
9660       {
9661         if(!likely[i]) {
9662           // These are overwritten unless the branch is "likely"
9663           // and the delay slot is nullified if not taken
9664           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9665           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9666         }
9667         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9668         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9669         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9670         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9671         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9672         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9673         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9674         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9675         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9676           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9677           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9678         }
9679         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9680           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9681           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9682         }
9683         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9684           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9685           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9686         }
9687       }
9688     }
9689     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9690     {
9691       // SYSCALL instruction (software interrupt)
9692       nr=0;
9693     }
9694     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9695     {
9696       // ERET instruction (return from interrupt)
9697       nr=0;
9698     }
9699     else // Non-branch
9700     {
9701       if(i<slen-1) {
9702         for(hr=0;hr<HOST_REGS;hr++) {
9703           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9704           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9705           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9706           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9707         }
9708       }
9709     }
9710     for(hr=0;hr<HOST_REGS;hr++)
9711     {
9712       // Overwritten registers are not needed
9713       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9714       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9715       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9716       // Source registers are needed
9717       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9718       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9719       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9720       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9721       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9722       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9723       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9724       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9725       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9726         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9727         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9728       }
9729       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9730         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9731         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9732       }
9733       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9734         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9735         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9736       }
9737       // Don't store a register immediately after writing it,
9738       // may prevent dual-issue.
9739       // But do so if this is a branch target, otherwise we
9740       // might have to load the register before the branch.
9741       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9742         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9743            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9744           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9745           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9746         }
9747         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9748            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9749           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9750           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9751         }
9752       }
9753     }
9754     // Cycle count is needed at branches.  Assume it is needed at the target too.
9755     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9756       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9757       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9758     }
9759     // Save it
9760     needed_reg[i]=nr;
9761
9762     // Deallocate unneeded registers
9763     for(hr=0;hr<HOST_REGS;hr++)
9764     {
9765       if(!((nr>>hr)&1)) {
9766         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9767         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9768            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9769            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9770         {
9771           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9772           {
9773             if(likely[i]) {
9774               regs[i].regmap[hr]=-1;
9775               regs[i].isconst&=~(1<<hr);
9776               if(i<slen-2) {
9777                 regmap_pre[i+2][hr]=-1;
9778                 regs[i+2].wasconst&=~(1<<hr);
9779               }
9780             }
9781           }
9782         }
9783         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9784         {
9785           int d1=0,d2=0,map=0,temp=0;
9786           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9787           {
9788             d1=dep1[i+1];
9789             d2=dep2[i+1];
9790           }
9791           if(using_tlb) {
9792             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9793                itype[i+1]==STORE || itype[i+1]==STORELR ||
9794                itype[i+1]==C1LS || itype[i+1]==C2LS)
9795             map=TLREG;
9796           } else
9797           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9798              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9799             map=INVCP;
9800           }
9801           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9802              itype[i+1]==C1LS || itype[i+1]==C2LS)
9803             temp=FTEMP;
9804           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9805              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9806              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9807              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9808              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9809              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9810              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9811              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9812              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9813              regs[i].regmap[hr]!=map )
9814           {
9815             regs[i].regmap[hr]=-1;
9816             regs[i].isconst&=~(1<<hr);
9817             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9818                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9819                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9820                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9821                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9822                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9823                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9824                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9825                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9826                branch_regs[i].regmap[hr]!=map)
9827             {
9828               branch_regs[i].regmap[hr]=-1;
9829               branch_regs[i].regmap_entry[hr]=-1;
9830               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9831               {
9832                 if(!likely[i]&&i<slen-2) {
9833                   regmap_pre[i+2][hr]=-1;
9834                   regs[i+2].wasconst&=~(1<<hr);
9835                 }
9836               }
9837             }
9838           }
9839         }
9840         else
9841         {
9842           // Non-branch
9843           if(i>0)
9844           {
9845             int d1=0,d2=0,map=-1,temp=-1;
9846             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9847             {
9848               d1=dep1[i];
9849               d2=dep2[i];
9850             }
9851             if(using_tlb) {
9852               if(itype[i]==LOAD || itype[i]==LOADLR ||
9853                  itype[i]==STORE || itype[i]==STORELR ||
9854                  itype[i]==C1LS || itype[i]==C2LS)
9855               map=TLREG;
9856             } else if(itype[i]==STORE || itype[i]==STORELR ||
9857                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9858               map=INVCP;
9859             }
9860             if(itype[i]==LOADLR || itype[i]==STORELR ||
9861                itype[i]==C1LS || itype[i]==C2LS)
9862               temp=FTEMP;
9863             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9864                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9865                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9866                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9867                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9868                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9869             {
9870               if(i<slen-1&&!is_ds[i]) {
9871                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9872                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9873                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9874                 {
9875                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9876                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9877                 }
9878                 regmap_pre[i+1][hr]=-1;
9879                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9880                 regs[i+1].wasconst&=~(1<<hr);
9881               }
9882               regs[i].regmap[hr]=-1;
9883               regs[i].isconst&=~(1<<hr);
9884             }
9885           }
9886         }
9887       }
9888     }
9889   }
9890
9891   /* Pass 5 - Pre-allocate registers */
9892
9893   // If a register is allocated during a loop, try to allocate it for the
9894   // entire loop, if possible.  This avoids loading/storing registers
9895   // inside of the loop.
9896
9897   signed char f_regmap[HOST_REGS];
9898   clear_all_regs(f_regmap);
9899   for(i=0;i<slen-1;i++)
9900   {
9901     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9902     {
9903       if(ba[i]>=start && ba[i]<(start+i*4))
9904       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9905       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9906       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9907       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9908       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9909       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9910       {
9911         int t=(ba[i]-start)>>2;
9912         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9913         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9914         for(hr=0;hr<HOST_REGS;hr++)
9915         {
9916           if(regs[i].regmap[hr]>64) {
9917             if(!((regs[i].dirty>>hr)&1))
9918               f_regmap[hr]=regs[i].regmap[hr];
9919             else f_regmap[hr]=-1;
9920           }
9921           else if(regs[i].regmap[hr]>=0) {
9922             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9923               // dealloc old register
9924               int n;
9925               for(n=0;n<HOST_REGS;n++)
9926               {
9927                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9928               }
9929               // and alloc new one
9930               f_regmap[hr]=regs[i].regmap[hr];
9931             }
9932           }
9933           if(branch_regs[i].regmap[hr]>64) {
9934             if(!((branch_regs[i].dirty>>hr)&1))
9935               f_regmap[hr]=branch_regs[i].regmap[hr];
9936             else f_regmap[hr]=-1;
9937           }
9938           else if(branch_regs[i].regmap[hr]>=0) {
9939             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9940               // dealloc old register
9941               int n;
9942               for(n=0;n<HOST_REGS;n++)
9943               {
9944                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9945               }
9946               // and alloc new one
9947               f_regmap[hr]=branch_regs[i].regmap[hr];
9948             }
9949           }
9950           if(ooo[i]) {
9951             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9952               f_regmap[hr]=branch_regs[i].regmap[hr];
9953           }else{
9954             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9955               f_regmap[hr]=branch_regs[i].regmap[hr];
9956           }
9957           // Avoid dirty->clean transition
9958           #ifdef DESTRUCTIVE_WRITEBACK
9959           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9960           #endif
9961           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9962           // case above, however it's always a good idea.  We can't hoist the
9963           // load if the register was already allocated, so there's no point
9964           // wasting time analyzing most of these cases.  It only "succeeds"
9965           // when the mapping was different and the load can be replaced with
9966           // a mov, which is of negligible benefit.  So such cases are
9967           // skipped below.
9968           if(f_regmap[hr]>0) {
9969             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
9970               int r=f_regmap[hr];
9971               for(j=t;j<=i;j++)
9972               {
9973                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9974                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9975                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9976                 if(r>63) {
9977                   // NB This can exclude the case where the upper-half
9978                   // register is lower numbered than the lower-half
9979                   // register.  Not sure if it's worth fixing...
9980                   if(get_reg(regs[j].regmap,r&63)<0) break;
9981                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9982                   if(regs[j].is32&(1LL<<(r&63))) break;
9983                 }
9984                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9985                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9986                   int k;
9987                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9988                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9989                     if(r>63) {
9990                       if(get_reg(regs[i].regmap,r&63)<0) break;
9991                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9992                     }
9993                     k=i;
9994                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9995                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9996                         //printf("no free regs for store %x\n",start+(k-1)*4);
9997                         break;
9998                       }
9999                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10000                         //printf("no-match due to different register\n");
10001                         break;
10002                       }
10003                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10004                         //printf("no-match due to branch\n");
10005                         break;
10006                       }
10007                       // call/ret fast path assumes no registers allocated
10008                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10009                         break;
10010                       }
10011                       if(r>63) {
10012                         // NB This can exclude the case where the upper-half
10013                         // register is lower numbered than the lower-half
10014                         // register.  Not sure if it's worth fixing...
10015                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10016                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10017                       }
10018                       k--;
10019                     }
10020                     if(i<slen-1) {
10021                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10022                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10023                         //printf("bad match after branch\n");
10024                         break;
10025                       }
10026                     }
10027                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10028                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10029                       while(k<i) {
10030                         regs[k].regmap_entry[hr]=f_regmap[hr];
10031                         regs[k].regmap[hr]=f_regmap[hr];
10032                         regmap_pre[k+1][hr]=f_regmap[hr];
10033                         regs[k].wasdirty&=~(1<<hr);
10034                         regs[k].dirty&=~(1<<hr);
10035                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10036                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10037                         regs[k].wasconst&=~(1<<hr);
10038                         regs[k].isconst&=~(1<<hr);
10039                         k++;
10040                       }
10041                     }
10042                     else {
10043                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10044                       break;
10045                     }
10046                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10047                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10048                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10049                       regs[i].regmap_entry[hr]=f_regmap[hr];
10050                       regs[i].regmap[hr]=f_regmap[hr];
10051                       regs[i].wasdirty&=~(1<<hr);
10052                       regs[i].dirty&=~(1<<hr);
10053                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10054                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10055                       regs[i].wasconst&=~(1<<hr);
10056                       regs[i].isconst&=~(1<<hr);
10057                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10058                       branch_regs[i].wasdirty&=~(1<<hr);
10059                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10060                       branch_regs[i].regmap[hr]=f_regmap[hr];
10061                       branch_regs[i].dirty&=~(1<<hr);
10062                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10063                       branch_regs[i].wasconst&=~(1<<hr);
10064                       branch_regs[i].isconst&=~(1<<hr);
10065                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10066                         regmap_pre[i+2][hr]=f_regmap[hr];
10067                         regs[i+2].wasdirty&=~(1<<hr);
10068                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10069                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10070                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10071                       }
10072                     }
10073                   }
10074                   for(k=t;k<j;k++) {
10075                     // Alloc register clean at beginning of loop,
10076                     // but may dirty it in pass 6
10077                     regs[k].regmap_entry[hr]=f_regmap[hr];
10078                     regs[k].regmap[hr]=f_regmap[hr];
10079                     regs[k].dirty&=~(1<<hr);
10080                     regs[k].wasconst&=~(1<<hr);
10081                     regs[k].isconst&=~(1<<hr);
10082                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10083                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10084                       branch_regs[k].regmap[hr]=f_regmap[hr];
10085                       branch_regs[k].dirty&=~(1<<hr);
10086                       branch_regs[k].wasconst&=~(1<<hr);
10087                       branch_regs[k].isconst&=~(1<<hr);
10088                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10089                         regmap_pre[k+2][hr]=f_regmap[hr];
10090                         regs[k+2].wasdirty&=~(1<<hr);
10091                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10092                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10093                       }
10094                     }
10095                     else
10096                     {
10097                       regmap_pre[k+1][hr]=f_regmap[hr];
10098                       regs[k+1].wasdirty&=~(1<<hr);
10099                     }
10100                   }
10101                   if(regs[j].regmap[hr]==f_regmap[hr])
10102                     regs[j].regmap_entry[hr]=f_regmap[hr];
10103                   break;
10104                 }
10105                 if(j==i) break;
10106                 if(regs[j].regmap[hr]>=0)
10107                   break;
10108                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10109                   //printf("no-match due to different register\n");
10110                   break;
10111                 }
10112                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10113                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10114                   break;
10115                 }
10116                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10117                 {
10118                   // Stop on unconditional branch
10119                   break;
10120                 }
10121                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10122                 {
10123                   if(ooo[j]) {
10124                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10125                       break;
10126                   }else{
10127                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10128                       break;
10129                   }
10130                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10131                     //printf("no-match due to different register (branch)\n");
10132                     break;
10133                   }
10134                 }
10135                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10136                   //printf("No free regs for store %x\n",start+j*4);
10137                   break;
10138                 }
10139                 if(f_regmap[hr]>=64) {
10140                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10141                     break;
10142                   }
10143                   else
10144                   {
10145                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10146                       break;
10147                     }
10148                   }
10149                 }
10150               }
10151             }
10152           }
10153         }
10154       }
10155     }else{
10156       // Non branch or undetermined branch target
10157       for(hr=0;hr<HOST_REGS;hr++)
10158       {
10159         if(hr!=EXCLUDE_REG) {
10160           if(regs[i].regmap[hr]>64) {
10161             if(!((regs[i].dirty>>hr)&1))
10162               f_regmap[hr]=regs[i].regmap[hr];
10163           }
10164           else if(regs[i].regmap[hr]>=0) {
10165             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10166               // dealloc old register
10167               int n;
10168               for(n=0;n<HOST_REGS;n++)
10169               {
10170                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10171               }
10172               // and alloc new one
10173               f_regmap[hr]=regs[i].regmap[hr];
10174             }
10175           }
10176         }
10177       }
10178       // Try to restore cycle count at branch targets
10179       if(bt[i]) {
10180         for(j=i;j<slen-1;j++) {
10181           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10182           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10183             //printf("no free regs for store %x\n",start+j*4);
10184             break;
10185           }
10186         }
10187         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10188           int k=i;
10189           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10190           while(k<j) {
10191             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10192             regs[k].regmap[HOST_CCREG]=CCREG;
10193             regmap_pre[k+1][HOST_CCREG]=CCREG;
10194             regs[k+1].wasdirty|=1<<HOST_CCREG;
10195             regs[k].dirty|=1<<HOST_CCREG;
10196             regs[k].wasconst&=~(1<<HOST_CCREG);
10197             regs[k].isconst&=~(1<<HOST_CCREG);
10198             k++;
10199           }
10200           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10201         }
10202         // Work backwards from the branch target
10203         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10204         {
10205           //printf("Extend backwards\n");
10206           int k;
10207           k=i;
10208           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10209             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10210               //printf("no free regs for store %x\n",start+(k-1)*4);
10211               break;
10212             }
10213             k--;
10214           }
10215           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10216             //printf("Extend CC, %x ->\n",start+k*4);
10217             while(k<=i) {
10218               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10219               regs[k].regmap[HOST_CCREG]=CCREG;
10220               regmap_pre[k+1][HOST_CCREG]=CCREG;
10221               regs[k+1].wasdirty|=1<<HOST_CCREG;
10222               regs[k].dirty|=1<<HOST_CCREG;
10223               regs[k].wasconst&=~(1<<HOST_CCREG);
10224               regs[k].isconst&=~(1<<HOST_CCREG);
10225               k++;
10226             }
10227           }
10228           else {
10229             //printf("Fail Extend CC, %x ->\n",start+k*4);
10230           }
10231         }
10232       }
10233       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10234          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10235          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10236          itype[i]!=FCONV&&itype[i]!=FCOMP)
10237       {
10238         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10239       }
10240     }
10241   }
10242
10243   // Cache memory offset or tlb map pointer if a register is available
10244   #ifndef HOST_IMM_ADDR32
10245   #ifndef RAM_OFFSET
10246   if(using_tlb)
10247   #endif
10248   {
10249     int earliest_available[HOST_REGS];
10250     int loop_start[HOST_REGS];
10251     int score[HOST_REGS];
10252     int end[HOST_REGS];
10253     int reg=using_tlb?MMREG:ROREG;
10254
10255     // Init
10256     for(hr=0;hr<HOST_REGS;hr++) {
10257       score[hr]=0;earliest_available[hr]=0;
10258       loop_start[hr]=MAXBLOCK;
10259     }
10260     for(i=0;i<slen-1;i++)
10261     {
10262       // Can't do anything if no registers are available
10263       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10264         for(hr=0;hr<HOST_REGS;hr++) {
10265           score[hr]=0;earliest_available[hr]=i+1;
10266           loop_start[hr]=MAXBLOCK;
10267         }
10268       }
10269       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10270         if(!ooo[i]) {
10271           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10272             for(hr=0;hr<HOST_REGS;hr++) {
10273               score[hr]=0;earliest_available[hr]=i+1;
10274               loop_start[hr]=MAXBLOCK;
10275             }
10276           }
10277         }else{
10278           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10279             for(hr=0;hr<HOST_REGS;hr++) {
10280               score[hr]=0;earliest_available[hr]=i+1;
10281               loop_start[hr]=MAXBLOCK;
10282             }
10283           }
10284         }
10285       }
10286       // Mark unavailable registers
10287       for(hr=0;hr<HOST_REGS;hr++) {
10288         if(regs[i].regmap[hr]>=0) {
10289           score[hr]=0;earliest_available[hr]=i+1;
10290           loop_start[hr]=MAXBLOCK;
10291         }
10292         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10293           if(branch_regs[i].regmap[hr]>=0) {
10294             score[hr]=0;earliest_available[hr]=i+2;
10295             loop_start[hr]=MAXBLOCK;
10296           }
10297         }
10298       }
10299       // No register allocations after unconditional jumps
10300       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10301       {
10302         for(hr=0;hr<HOST_REGS;hr++) {
10303           score[hr]=0;earliest_available[hr]=i+2;
10304           loop_start[hr]=MAXBLOCK;
10305         }
10306         i++; // Skip delay slot too
10307         //printf("skip delay slot: %x\n",start+i*4);
10308       }
10309       else
10310       // Possible match
10311       if(itype[i]==LOAD||itype[i]==LOADLR||
10312          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10313         for(hr=0;hr<HOST_REGS;hr++) {
10314           if(hr!=EXCLUDE_REG) {
10315             end[hr]=i-1;
10316             for(j=i;j<slen-1;j++) {
10317               if(regs[j].regmap[hr]>=0) break;
10318               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10319                 if(branch_regs[j].regmap[hr]>=0) break;
10320                 if(ooo[j]) {
10321                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10322                 }else{
10323                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10324                 }
10325               }
10326               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10327               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10328                 int t=(ba[j]-start)>>2;
10329                 if(t<j&&t>=earliest_available[hr]) {
10330                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10331                     // Score a point for hoisting loop invariant
10332                     if(t<loop_start[hr]) loop_start[hr]=t;
10333                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10334                     score[hr]++;
10335                     end[hr]=j;
10336                   }
10337                 }
10338                 else if(t<j) {
10339                   if(regs[t].regmap[hr]==reg) {
10340                     // Score a point if the branch target matches this register
10341                     score[hr]++;
10342                     end[hr]=j;
10343                   }
10344                 }
10345                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10346                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10347                   score[hr]++;
10348                   end[hr]=j;
10349                 }
10350               }
10351               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10352               {
10353                 // Stop on unconditional branch
10354                 break;
10355               }
10356               else
10357               if(itype[j]==LOAD||itype[j]==LOADLR||
10358                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10359                 score[hr]++;
10360                 end[hr]=j;
10361               }
10362             }
10363           }
10364         }
10365         // Find highest score and allocate that register
10366         int maxscore=0;
10367         for(hr=0;hr<HOST_REGS;hr++) {
10368           if(hr!=EXCLUDE_REG) {
10369             if(score[hr]>score[maxscore]) {
10370               maxscore=hr;
10371               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10372             }
10373           }
10374         }
10375         if(score[maxscore]>1)
10376         {
10377           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10378           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10379             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10380             assert(regs[j].regmap[maxscore]<0);
10381             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10382             regs[j].regmap[maxscore]=reg;
10383             regs[j].dirty&=~(1<<maxscore);
10384             regs[j].wasconst&=~(1<<maxscore);
10385             regs[j].isconst&=~(1<<maxscore);
10386             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10387               branch_regs[j].regmap[maxscore]=reg;
10388               branch_regs[j].wasdirty&=~(1<<maxscore);
10389               branch_regs[j].dirty&=~(1<<maxscore);
10390               branch_regs[j].wasconst&=~(1<<maxscore);
10391               branch_regs[j].isconst&=~(1<<maxscore);
10392               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10393                 regmap_pre[j+2][maxscore]=reg;
10394                 regs[j+2].wasdirty&=~(1<<maxscore);
10395               }
10396               // loop optimization (loop_preload)
10397               int t=(ba[j]-start)>>2;
10398               if(t==loop_start[maxscore]) {
10399                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10400                   regs[t].regmap_entry[maxscore]=reg;
10401               }
10402             }
10403             else
10404             {
10405               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10406                 regmap_pre[j+1][maxscore]=reg;
10407                 regs[j+1].wasdirty&=~(1<<maxscore);
10408               }
10409             }
10410           }
10411           i=j-1;
10412           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10413           for(hr=0;hr<HOST_REGS;hr++) {
10414             score[hr]=0;earliest_available[hr]=i+i;
10415             loop_start[hr]=MAXBLOCK;
10416           }
10417         }
10418       }
10419     }
10420   }
10421   #endif
10422
10423   // This allocates registers (if possible) one instruction prior
10424   // to use, which can avoid a load-use penalty on certain CPUs.
10425   for(i=0;i<slen-1;i++)
10426   {
10427     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10428     {
10429       if(!bt[i+1])
10430       {
10431         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10432            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10433         {
10434           if(rs1[i+1]) {
10435             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10436             {
10437               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10438               {
10439                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10440                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10441                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10442                 regs[i].isconst&=~(1<<hr);
10443                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10444                 constmap[i][hr]=constmap[i+1][hr];
10445                 regs[i+1].wasdirty&=~(1<<hr);
10446                 regs[i].dirty&=~(1<<hr);
10447               }
10448             }
10449           }
10450           if(rs2[i+1]) {
10451             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10452             {
10453               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10454               {
10455                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10456                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10457                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10458                 regs[i].isconst&=~(1<<hr);
10459                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10460                 constmap[i][hr]=constmap[i+1][hr];
10461                 regs[i+1].wasdirty&=~(1<<hr);
10462                 regs[i].dirty&=~(1<<hr);
10463               }
10464             }
10465           }
10466           // Preload target address for load instruction (non-constant)
10467           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10468             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10469             {
10470               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10471               {
10472                 regs[i].regmap[hr]=rs1[i+1];
10473                 regmap_pre[i+1][hr]=rs1[i+1];
10474                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10475                 regs[i].isconst&=~(1<<hr);
10476                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10477                 constmap[i][hr]=constmap[i+1][hr];
10478                 regs[i+1].wasdirty&=~(1<<hr);
10479                 regs[i].dirty&=~(1<<hr);
10480               }
10481             }
10482           }
10483           // Load source into target register
10484           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10485             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10486             {
10487               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10488               {
10489                 regs[i].regmap[hr]=rs1[i+1];
10490                 regmap_pre[i+1][hr]=rs1[i+1];
10491                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10492                 regs[i].isconst&=~(1<<hr);
10493                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10494                 constmap[i][hr]=constmap[i+1][hr];
10495                 regs[i+1].wasdirty&=~(1<<hr);
10496                 regs[i].dirty&=~(1<<hr);
10497               }
10498             }
10499           }
10500           // Preload map address
10501           #ifndef HOST_IMM_ADDR32
10502           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10503             hr=get_reg(regs[i+1].regmap,TLREG);
10504             if(hr>=0) {
10505               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10506               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10507                 int nr;
10508                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10509                 {
10510                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10511                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10512                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10513                   regs[i].isconst&=~(1<<hr);
10514                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10515                   constmap[i][hr]=constmap[i+1][hr];
10516                   regs[i+1].wasdirty&=~(1<<hr);
10517                   regs[i].dirty&=~(1<<hr);
10518                 }
10519                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10520                 {
10521                   // move it to another register
10522                   regs[i+1].regmap[hr]=-1;
10523                   regmap_pre[i+2][hr]=-1;
10524                   regs[i+1].regmap[nr]=TLREG;
10525                   regmap_pre[i+2][nr]=TLREG;
10526                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10527                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10528                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10529                   regs[i].isconst&=~(1<<nr);
10530                   regs[i+1].isconst&=~(1<<nr);
10531                   regs[i].dirty&=~(1<<nr);
10532                   regs[i+1].wasdirty&=~(1<<nr);
10533                   regs[i+1].dirty&=~(1<<nr);
10534                   regs[i+2].wasdirty&=~(1<<nr);
10535                 }
10536               }
10537             }
10538           }
10539           #endif
10540           // Address for store instruction (non-constant)
10541           if(itype[i+1]==STORE||itype[i+1]==STORELR
10542              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10543             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10544               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10545               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10546               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10547               assert(hr>=0);
10548               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10549               {
10550                 regs[i].regmap[hr]=rs1[i+1];
10551                 regmap_pre[i+1][hr]=rs1[i+1];
10552                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10553                 regs[i].isconst&=~(1<<hr);
10554                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10555                 constmap[i][hr]=constmap[i+1][hr];
10556                 regs[i+1].wasdirty&=~(1<<hr);
10557                 regs[i].dirty&=~(1<<hr);
10558               }
10559             }
10560           }
10561           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10562             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10563               int nr;
10564               hr=get_reg(regs[i+1].regmap,FTEMP);
10565               assert(hr>=0);
10566               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10567               {
10568                 regs[i].regmap[hr]=rs1[i+1];
10569                 regmap_pre[i+1][hr]=rs1[i+1];
10570                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10571                 regs[i].isconst&=~(1<<hr);
10572                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10573                 constmap[i][hr]=constmap[i+1][hr];
10574                 regs[i+1].wasdirty&=~(1<<hr);
10575                 regs[i].dirty&=~(1<<hr);
10576               }
10577               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10578               {
10579                 // move it to another register
10580                 regs[i+1].regmap[hr]=-1;
10581                 regmap_pre[i+2][hr]=-1;
10582                 regs[i+1].regmap[nr]=FTEMP;
10583                 regmap_pre[i+2][nr]=FTEMP;
10584                 regs[i].regmap[nr]=rs1[i+1];
10585                 regmap_pre[i+1][nr]=rs1[i+1];
10586                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10587                 regs[i].isconst&=~(1<<nr);
10588                 regs[i+1].isconst&=~(1<<nr);
10589                 regs[i].dirty&=~(1<<nr);
10590                 regs[i+1].wasdirty&=~(1<<nr);
10591                 regs[i+1].dirty&=~(1<<nr);
10592                 regs[i+2].wasdirty&=~(1<<nr);
10593               }
10594             }
10595           }
10596           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10597             if(itype[i+1]==LOAD)
10598               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10599             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10600               hr=get_reg(regs[i+1].regmap,FTEMP);
10601             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10602               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10603               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10604             }
10605             if(hr>=0&&regs[i].regmap[hr]<0) {
10606               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10607               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10608                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10609                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10610                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10611                 regs[i].isconst&=~(1<<hr);
10612                 regs[i+1].wasdirty&=~(1<<hr);
10613                 regs[i].dirty&=~(1<<hr);
10614               }
10615             }
10616           }
10617         }
10618       }
10619     }
10620   }
10621
10622   /* Pass 6 - Optimize clean/dirty state */
10623   clean_registers(0,slen-1,1);
10624
10625   /* Pass 7 - Identify 32-bit registers */
10626 #ifndef FORCE32
10627   provisional_r32();
10628
10629   u_int r32=0;
10630
10631   for (i=slen-1;i>=0;i--)
10632   {
10633     int hr;
10634     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10635     {
10636       if(ba[i]<start || ba[i]>=(start+slen*4))
10637       {
10638         // Branch out of this block, don't need anything
10639         r32=0;
10640       }
10641       else
10642       {
10643         // Internal branch
10644         // Need whatever matches the target
10645         // (and doesn't get overwritten by the delay slot instruction)
10646         r32=0;
10647         int t=(ba[i]-start)>>2;
10648         if(ba[i]>start+i*4) {
10649           // Forward branch
10650           if(!(requires_32bit[t]&~regs[i].was32))
10651             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10652         }else{
10653           // Backward branch
10654           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10655           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10656           if(!(pr32[t]&~regs[i].was32))
10657             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10658         }
10659       }
10660       // Conditional branch may need registers for following instructions
10661       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10662       {
10663         if(i<slen-2) {
10664           r32|=requires_32bit[i+2];
10665           r32&=regs[i].was32;
10666           // Mark this address as a branch target since it may be called
10667           // upon return from interrupt
10668           bt[i+2]=1;
10669         }
10670       }
10671       // Merge in delay slot
10672       if(!likely[i]) {
10673         // These are overwritten unless the branch is "likely"
10674         // and the delay slot is nullified if not taken
10675         r32&=~(1LL<<rt1[i+1]);
10676         r32&=~(1LL<<rt2[i+1]);
10677       }
10678       // Assume these are needed (delay slot)
10679       if(us1[i+1]>0)
10680       {
10681         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10682       }
10683       if(us2[i+1]>0)
10684       {
10685         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10686       }
10687       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10688       {
10689         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10690       }
10691       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10692       {
10693         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10694       }
10695     }
10696     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10697     {
10698       // SYSCALL instruction (software interrupt)
10699       r32=0;
10700     }
10701     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10702     {
10703       // ERET instruction (return from interrupt)
10704       r32=0;
10705     }
10706     // Check 32 bits
10707     r32&=~(1LL<<rt1[i]);
10708     r32&=~(1LL<<rt2[i]);
10709     if(us1[i]>0)
10710     {
10711       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10712     }
10713     if(us2[i]>0)
10714     {
10715       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10716     }
10717     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10718     {
10719       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10720     }
10721     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10722     {
10723       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10724     }
10725     requires_32bit[i]=r32;
10726
10727     // Dirty registers which are 32-bit, require 32-bit input
10728     // as they will be written as 32-bit values
10729     for(hr=0;hr<HOST_REGS;hr++)
10730     {
10731       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10732         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10733           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10734           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10735         }
10736       }
10737     }
10738     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10739   }
10740 #else
10741   for (i=slen-1;i>=0;i--)
10742   {
10743     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10744     {
10745       // Conditional branch
10746       if((source[i]>>16)!=0x1000&&i<slen-2) {
10747         // Mark this address as a branch target since it may be called
10748         // upon return from interrupt
10749         bt[i+2]=1;
10750       }
10751     }
10752   }
10753 #endif
10754
10755   if(itype[slen-1]==SPAN) {
10756     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10757   }
10758
10759   /* Debug/disassembly */
10760   if((void*)assem_debug==(void*)printf)
10761   for(i=0;i<slen;i++)
10762   {
10763     printf("U:");
10764     int r;
10765     for(r=1;r<=CCREG;r++) {
10766       if((unneeded_reg[i]>>r)&1) {
10767         if(r==HIREG) printf(" HI");
10768         else if(r==LOREG) printf(" LO");
10769         else printf(" r%d",r);
10770       }
10771     }
10772 #ifndef FORCE32
10773     printf(" UU:");
10774     for(r=1;r<=CCREG;r++) {
10775       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10776         if(r==HIREG) printf(" HI");
10777         else if(r==LOREG) printf(" LO");
10778         else printf(" r%d",r);
10779       }
10780     }
10781     printf(" 32:");
10782     for(r=0;r<=CCREG;r++) {
10783       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10784       if((regs[i].was32>>r)&1) {
10785         if(r==CCREG) printf(" CC");
10786         else if(r==HIREG) printf(" HI");
10787         else if(r==LOREG) printf(" LO");
10788         else printf(" r%d",r);
10789       }
10790     }
10791 #endif
10792     printf("\n");
10793     #if defined(__i386__) || defined(__x86_64__)
10794     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10795     #endif
10796     #ifdef __arm__
10797     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10798     #endif
10799     printf("needs: ");
10800     if(needed_reg[i]&1) printf("eax ");
10801     if((needed_reg[i]>>1)&1) printf("ecx ");
10802     if((needed_reg[i]>>2)&1) printf("edx ");
10803     if((needed_reg[i]>>3)&1) printf("ebx ");
10804     if((needed_reg[i]>>5)&1) printf("ebp ");
10805     if((needed_reg[i]>>6)&1) printf("esi ");
10806     if((needed_reg[i]>>7)&1) printf("edi ");
10807     printf("r:");
10808     for(r=0;r<=CCREG;r++) {
10809       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10810       if((requires_32bit[i]>>r)&1) {
10811         if(r==CCREG) printf(" CC");
10812         else if(r==HIREG) printf(" HI");
10813         else if(r==LOREG) printf(" LO");
10814         else printf(" r%d",r);
10815       }
10816     }
10817     printf("\n");
10818     /*printf("pr:");
10819     for(r=0;r<=CCREG;r++) {
10820       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10821       if((pr32[i]>>r)&1) {
10822         if(r==CCREG) printf(" CC");
10823         else if(r==HIREG) printf(" HI");
10824         else if(r==LOREG) printf(" LO");
10825         else printf(" r%d",r);
10826       }
10827     }
10828     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10829     printf("\n");*/
10830     #if defined(__i386__) || defined(__x86_64__)
10831     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10832     printf("dirty: ");
10833     if(regs[i].wasdirty&1) printf("eax ");
10834     if((regs[i].wasdirty>>1)&1) printf("ecx ");
10835     if((regs[i].wasdirty>>2)&1) printf("edx ");
10836     if((regs[i].wasdirty>>3)&1) printf("ebx ");
10837     if((regs[i].wasdirty>>5)&1) printf("ebp ");
10838     if((regs[i].wasdirty>>6)&1) printf("esi ");
10839     if((regs[i].wasdirty>>7)&1) printf("edi ");
10840     #endif
10841     #ifdef __arm__
10842     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10843     printf("dirty: ");
10844     if(regs[i].wasdirty&1) printf("r0 ");
10845     if((regs[i].wasdirty>>1)&1) printf("r1 ");
10846     if((regs[i].wasdirty>>2)&1) printf("r2 ");
10847     if((regs[i].wasdirty>>3)&1) printf("r3 ");
10848     if((regs[i].wasdirty>>4)&1) printf("r4 ");
10849     if((regs[i].wasdirty>>5)&1) printf("r5 ");
10850     if((regs[i].wasdirty>>6)&1) printf("r6 ");
10851     if((regs[i].wasdirty>>7)&1) printf("r7 ");
10852     if((regs[i].wasdirty>>8)&1) printf("r8 ");
10853     if((regs[i].wasdirty>>9)&1) printf("r9 ");
10854     if((regs[i].wasdirty>>10)&1) printf("r10 ");
10855     if((regs[i].wasdirty>>12)&1) printf("r12 ");
10856     #endif
10857     printf("\n");
10858     disassemble_inst(i);
10859     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10860     #if defined(__i386__) || defined(__x86_64__)
10861     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10862     if(regs[i].dirty&1) printf("eax ");
10863     if((regs[i].dirty>>1)&1) printf("ecx ");
10864     if((regs[i].dirty>>2)&1) printf("edx ");
10865     if((regs[i].dirty>>3)&1) printf("ebx ");
10866     if((regs[i].dirty>>5)&1) printf("ebp ");
10867     if((regs[i].dirty>>6)&1) printf("esi ");
10868     if((regs[i].dirty>>7)&1) printf("edi ");
10869     #endif
10870     #ifdef __arm__
10871     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10872     if(regs[i].dirty&1) printf("r0 ");
10873     if((regs[i].dirty>>1)&1) printf("r1 ");
10874     if((regs[i].dirty>>2)&1) printf("r2 ");
10875     if((regs[i].dirty>>3)&1) printf("r3 ");
10876     if((regs[i].dirty>>4)&1) printf("r4 ");
10877     if((regs[i].dirty>>5)&1) printf("r5 ");
10878     if((regs[i].dirty>>6)&1) printf("r6 ");
10879     if((regs[i].dirty>>7)&1) printf("r7 ");
10880     if((regs[i].dirty>>8)&1) printf("r8 ");
10881     if((regs[i].dirty>>9)&1) printf("r9 ");
10882     if((regs[i].dirty>>10)&1) printf("r10 ");
10883     if((regs[i].dirty>>12)&1) printf("r12 ");
10884     #endif
10885     printf("\n");
10886     if(regs[i].isconst) {
10887       printf("constants: ");
10888       #if defined(__i386__) || defined(__x86_64__)
10889       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10890       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10891       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10892       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10893       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10894       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10895       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10896       #endif
10897       #ifdef __arm__
10898       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10899       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10900       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10901       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10902       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10903       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10904       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10905       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10906       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10907       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10908       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10909       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10910       #endif
10911       printf("\n");
10912     }
10913 #ifndef FORCE32
10914     printf(" 32:");
10915     for(r=0;r<=CCREG;r++) {
10916       if((regs[i].is32>>r)&1) {
10917         if(r==CCREG) printf(" CC");
10918         else if(r==HIREG) printf(" HI");
10919         else if(r==LOREG) printf(" LO");
10920         else printf(" r%d",r);
10921       }
10922     }
10923     printf("\n");
10924 #endif
10925     /*printf(" p32:");
10926     for(r=0;r<=CCREG;r++) {
10927       if((p32[i]>>r)&1) {
10928         if(r==CCREG) printf(" CC");
10929         else if(r==HIREG) printf(" HI");
10930         else if(r==LOREG) printf(" LO");
10931         else printf(" r%d",r);
10932       }
10933     }
10934     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10935     else printf("\n");*/
10936     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10937       #if defined(__i386__) || defined(__x86_64__)
10938       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10939       if(branch_regs[i].dirty&1) printf("eax ");
10940       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10941       if((branch_regs[i].dirty>>2)&1) printf("edx ");
10942       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10943       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10944       if((branch_regs[i].dirty>>6)&1) printf("esi ");
10945       if((branch_regs[i].dirty>>7)&1) printf("edi ");
10946       #endif
10947       #ifdef __arm__
10948       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10949       if(branch_regs[i].dirty&1) printf("r0 ");
10950       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10951       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10952       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10953       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10954       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10955       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10956       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10957       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10958       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10959       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10960       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10961       #endif
10962 #ifndef FORCE32
10963       printf(" 32:");
10964       for(r=0;r<=CCREG;r++) {
10965         if((branch_regs[i].is32>>r)&1) {
10966           if(r==CCREG) printf(" CC");
10967           else if(r==HIREG) printf(" HI");
10968           else if(r==LOREG) printf(" LO");
10969           else printf(" r%d",r);
10970         }
10971       }
10972       printf("\n");
10973 #endif
10974     }
10975   }
10976
10977   /* Pass 8 - Assembly */
10978   linkcount=0;stubcount=0;
10979   ds=0;is_delayslot=0;
10980   cop1_usable=0;
10981   uint64_t is32_pre=0;
10982   u_int dirty_pre=0;
10983   u_int beginning=(u_int)out;
10984   if((u_int)addr&1) {
10985     ds=1;
10986     pagespan_ds();
10987   }
10988   u_int instr_addr0_override=0;
10989
10990 #ifdef PCSX
10991   if (start == 0x80030000) {
10992     // nasty hack for fastbios thing
10993     // override block entry to this code
10994     instr_addr0_override=(u_int)out;
10995     emit_movimm(start,0);
10996     // abuse io address var as a flag that we
10997     // have already returned here once
10998     emit_readword((int)&address,1);
10999     emit_writeword(0,(int)&pcaddr);
11000     emit_writeword(0,(int)&address);
11001     emit_cmp(0,1);
11002     emit_jne((int)new_dyna_leave);
11003   }
11004 #endif
11005   for(i=0;i<slen;i++)
11006   {
11007     //if(ds) printf("ds: ");
11008     if((void*)assem_debug==(void*)printf) disassemble_inst(i);
11009     if(ds) {
11010       ds=0; // Skip delay slot
11011       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11012       instr_addr[i]=0;
11013     } else {
11014       #ifndef DESTRUCTIVE_WRITEBACK
11015       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11016       {
11017         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11018               unneeded_reg[i],unneeded_reg_upper[i]);
11019         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11020               unneeded_reg[i],unneeded_reg_upper[i]);
11021       }
11022       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11023         is32_pre=branch_regs[i].is32;
11024         dirty_pre=branch_regs[i].dirty;
11025       }else{
11026         is32_pre=regs[i].is32;
11027         dirty_pre=regs[i].dirty;
11028       }
11029       #endif
11030       // write back
11031       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11032       {
11033         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11034                       unneeded_reg[i],unneeded_reg_upper[i]);
11035         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11036       }
11037       // branch target entry point
11038       instr_addr[i]=(u_int)out;
11039       assem_debug("<->\n");
11040       // load regs
11041       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11042         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11043       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11044       address_generation(i,&regs[i],regs[i].regmap_entry);
11045       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11046       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11047       {
11048         // Load the delay slot registers if necessary
11049         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11050           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11051         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11052           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11053         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11054           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11055       }
11056       else if(i+1<slen)
11057       {
11058         // Preload registers for following instruction
11059         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11060           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11061             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11062         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11063           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11064             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11065       }
11066       // TODO: if(is_ooo(i)) address_generation(i+1);
11067       if(itype[i]==CJUMP||itype[i]==FJUMP)
11068         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11069       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11070         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11071       if(bt[i]) cop1_usable=0;
11072       // assemble
11073       switch(itype[i]) {
11074         case ALU:
11075           alu_assemble(i,&regs[i]);break;
11076         case IMM16:
11077           imm16_assemble(i,&regs[i]);break;
11078         case SHIFT:
11079           shift_assemble(i,&regs[i]);break;
11080         case SHIFTIMM:
11081           shiftimm_assemble(i,&regs[i]);break;
11082         case LOAD:
11083           load_assemble(i,&regs[i]);break;
11084         case LOADLR:
11085           loadlr_assemble(i,&regs[i]);break;
11086         case STORE:
11087           store_assemble(i,&regs[i]);break;
11088         case STORELR:
11089           storelr_assemble(i,&regs[i]);break;
11090         case COP0:
11091           cop0_assemble(i,&regs[i]);break;
11092         case COP1:
11093           cop1_assemble(i,&regs[i]);break;
11094         case C1LS:
11095           c1ls_assemble(i,&regs[i]);break;
11096         case COP2:
11097           cop2_assemble(i,&regs[i]);break;
11098         case C2LS:
11099           c2ls_assemble(i,&regs[i]);break;
11100         case C2OP:
11101           c2op_assemble(i,&regs[i]);break;
11102         case FCONV:
11103           fconv_assemble(i,&regs[i]);break;
11104         case FLOAT:
11105           float_assemble(i,&regs[i]);break;
11106         case FCOMP:
11107           fcomp_assemble(i,&regs[i]);break;
11108         case MULTDIV:
11109           multdiv_assemble(i,&regs[i]);break;
11110         case MOV:
11111           mov_assemble(i,&regs[i]);break;
11112         case SYSCALL:
11113           syscall_assemble(i,&regs[i]);break;
11114         case HLECALL:
11115           hlecall_assemble(i,&regs[i]);break;
11116         case INTCALL:
11117           intcall_assemble(i,&regs[i]);break;
11118         case UJUMP:
11119           ujump_assemble(i,&regs[i]);ds=1;break;
11120         case RJUMP:
11121           rjump_assemble(i,&regs[i]);ds=1;break;
11122         case CJUMP:
11123           cjump_assemble(i,&regs[i]);ds=1;break;
11124         case SJUMP:
11125           sjump_assemble(i,&regs[i]);ds=1;break;
11126         case FJUMP:
11127           fjump_assemble(i,&regs[i]);ds=1;break;
11128         case SPAN:
11129           pagespan_assemble(i,&regs[i]);break;
11130       }
11131       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11132         literal_pool(1024);
11133       else
11134         literal_pool_jumpover(256);
11135     }
11136   }
11137   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11138   // If the block did not end with an unconditional branch,
11139   // add a jump to the next instruction.
11140   if(i>1) {
11141     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11142       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11143       assert(i==slen);
11144       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11145         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11146         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11147           emit_loadreg(CCREG,HOST_CCREG);
11148         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11149       }
11150       else if(!likely[i-2])
11151       {
11152         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11153         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11154       }
11155       else
11156       {
11157         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11158         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11159       }
11160       add_to_linker((int)out,start+i*4,0);
11161       emit_jmp(0);
11162     }
11163   }
11164   else
11165   {
11166     assert(i>0);
11167     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11168     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11169     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11170       emit_loadreg(CCREG,HOST_CCREG);
11171     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
11172     add_to_linker((int)out,start+i*4,0);
11173     emit_jmp(0);
11174   }
11175
11176   // TODO: delay slot stubs?
11177   // Stubs
11178   for(i=0;i<stubcount;i++)
11179   {
11180     switch(stubs[i][0])
11181     {
11182       case LOADB_STUB:
11183       case LOADH_STUB:
11184       case LOADW_STUB:
11185       case LOADD_STUB:
11186       case LOADBU_STUB:
11187       case LOADHU_STUB:
11188         do_readstub(i);break;
11189       case STOREB_STUB:
11190       case STOREH_STUB:
11191       case STOREW_STUB:
11192       case STORED_STUB:
11193         do_writestub(i);break;
11194       case CC_STUB:
11195         do_ccstub(i);break;
11196       case INVCODE_STUB:
11197         do_invstub(i);break;
11198       case FP_STUB:
11199         do_cop1stub(i);break;
11200       case STORELR_STUB:
11201         do_unalignedwritestub(i);break;
11202     }
11203   }
11204
11205   if (instr_addr0_override)
11206     instr_addr[0] = instr_addr0_override;
11207
11208   /* Pass 9 - Linker */
11209   for(i=0;i<linkcount;i++)
11210   {
11211     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11212     literal_pool(64);
11213     if(!link_addr[i][2])
11214     {
11215       void *stub=out;
11216       void *addr=check_addr(link_addr[i][1]);
11217       emit_extjump(link_addr[i][0],link_addr[i][1]);
11218       if(addr) {
11219         set_jump_target(link_addr[i][0],(int)addr);
11220         add_link(link_addr[i][1],stub);
11221       }
11222       else set_jump_target(link_addr[i][0],(int)stub);
11223     }
11224     else
11225     {
11226       // Internal branch
11227       int target=(link_addr[i][1]-start)>>2;
11228       assert(target>=0&&target<slen);
11229       assert(instr_addr[target]);
11230       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11231       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11232       //#else
11233       set_jump_target(link_addr[i][0],instr_addr[target]);
11234       //#endif
11235     }
11236   }
11237   // External Branch Targets (jump_in)
11238   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11239   for(i=0;i<slen;i++)
11240   {
11241     if(bt[i]||i==0)
11242     {
11243       if(instr_addr[i]) // TODO - delay slots (=null)
11244       {
11245         u_int vaddr=start+i*4;
11246         u_int page=get_page(vaddr);
11247         u_int vpage=get_vpage(vaddr);
11248         literal_pool(256);
11249         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11250 #ifndef FORCE32
11251         if(!requires_32bit[i])
11252 #else
11253         if(1)
11254 #endif
11255         {
11256           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11257           assem_debug("jump_in: %x\n",start+i*4);
11258           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11259           int entry_point=do_dirty_stub(i);
11260           ll_add(jump_in+page,vaddr,(void *)entry_point);
11261           // If there was an existing entry in the hash table,
11262           // replace it with the new address.
11263           // Don't add new entries.  We'll insert the
11264           // ones that actually get used in check_addr().
11265           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11266           if(ht_bin[0]==vaddr) {
11267             ht_bin[1]=entry_point;
11268           }
11269           if(ht_bin[2]==vaddr) {
11270             ht_bin[3]=entry_point;
11271           }
11272         }
11273         else
11274         {
11275           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11276           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11277           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11278           //int entry_point=(int)out;
11279           ////assem_debug("entry_point: %x\n",entry_point);
11280           //load_regs_entry(i);
11281           //if(entry_point==(int)out)
11282           //  entry_point=instr_addr[i];
11283           //else
11284           //  emit_jmp(instr_addr[i]);
11285           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11286           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11287           int entry_point=do_dirty_stub(i);
11288           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11289         }
11290       }
11291     }
11292   }
11293   // Write out the literal pool if necessary
11294   literal_pool(0);
11295   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11296   // Align code
11297   if(((u_int)out)&7) emit_addnop(13);
11298   #endif
11299   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11300   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11301   memcpy(copy,source,slen*4);
11302   copy+=slen*4;
11303
11304   #ifdef __arm__
11305   __clear_cache((void *)beginning,out);
11306   #endif
11307
11308   // If we're within 256K of the end of the buffer,
11309   // start over from the beginning. (Is 256K enough?)
11310   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11311
11312   // Trap writes to any of the pages we compiled
11313   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11314     invalid_code[i]=0;
11315 #ifndef DISABLE_TLB
11316     memory_map[i]|=0x40000000;
11317     if((signed int)start>=(signed int)0xC0000000) {
11318       assert(using_tlb);
11319       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11320       invalid_code[j]=0;
11321       memory_map[j]|=0x40000000;
11322       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11323     }
11324 #endif
11325   }
11326 #ifdef PCSX
11327   // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
11328   if(get_page(start)<(RAM_SIZE>>12))
11329     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11330       invalid_code[((u_int)0x80000000>>12)|i]=0;
11331 #endif
11332
11333   /* Pass 10 - Free memory by expiring oldest blocks */
11334
11335   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11336   while(expirep!=end)
11337   {
11338     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11339     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11340     inv_debug("EXP: Phase %d\n",expirep);
11341     switch((expirep>>11)&3)
11342     {
11343       case 0:
11344         // Clear jump_in and jump_dirty
11345         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11346         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11347         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11348         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11349         break;
11350       case 1:
11351         // Clear pointers
11352         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11353         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11354         break;
11355       case 2:
11356         // Clear hash table
11357         for(i=0;i<32;i++) {
11358           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11359           if((ht_bin[3]>>shift)==(base>>shift) ||
11360              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11361             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11362             ht_bin[2]=ht_bin[3]=-1;
11363           }
11364           if((ht_bin[1]>>shift)==(base>>shift) ||
11365              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11366             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11367             ht_bin[0]=ht_bin[2];
11368             ht_bin[1]=ht_bin[3];
11369             ht_bin[2]=ht_bin[3]=-1;
11370           }
11371         }
11372         break;
11373       case 3:
11374         // Clear jump_out
11375         #ifdef __arm__
11376         if((expirep&2047)==0)
11377           do_clear_cache();
11378         #endif
11379         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11380         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11381         break;
11382     }
11383     expirep=(expirep+1)&65535;
11384   }
11385   return 0;
11386 }
11387
11388 // vim:shiftwidth=2:expandtab