a736d565cccb1c36fd7bb884d2aa64820fcde440
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2  *   Mupen64plus - new_dynarec.c                                           *
3  *   Copyright (C) 2009-2011 Ari64                                         *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21 #include <stdlib.h>
22 #include <stdint.h> //include for uint64_t
23 #include <assert.h>
24 #include <sys/mman.h>
25
26 #include "emu_if.h" //emulator interface
27
28 //#define DISASM
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
33
34 #ifdef __i386__
35 #include "assem_x86.h"
36 #endif
37 #ifdef __x86_64__
38 #include "assem_x64.h"
39 #endif
40 #ifdef __arm__
41 #include "assem_arm.h"
42 #endif
43
44 #define MAXBLOCK 4096
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
46
47 struct regstat
48 {
49   signed char regmap_entry[HOST_REGS];
50   signed char regmap[HOST_REGS];
51   uint64_t was32;
52   uint64_t is32;
53   uint64_t wasdirty;
54   uint64_t dirty;
55   uint64_t u;
56   uint64_t uu;
57   u_int wasconst;
58   u_int isconst;
59   u_int loadedconst;             // host regs that have constants loaded
60   u_int waswritten;              // MIPS regs that were used as store base before
61 };
62
63 struct ll_entry
64 {
65   u_int vaddr;
66   u_int reg32;
67   void *addr;
68   struct ll_entry *next;
69 };
70
71   u_int start;
72   u_int *source;
73   u_int pagelimit;
74   char insn[MAXBLOCK][10];
75   u_char itype[MAXBLOCK];
76   u_char opcode[MAXBLOCK];
77   u_char opcode2[MAXBLOCK];
78   u_char bt[MAXBLOCK];
79   u_char rs1[MAXBLOCK];
80   u_char rs2[MAXBLOCK];
81   u_char rt1[MAXBLOCK];
82   u_char rt2[MAXBLOCK];
83   u_char us1[MAXBLOCK];
84   u_char us2[MAXBLOCK];
85   u_char dep1[MAXBLOCK];
86   u_char dep2[MAXBLOCK];
87   u_char lt1[MAXBLOCK];
88   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89   static uint64_t gte_rt[MAXBLOCK];
90   static uint64_t gte_unneeded[MAXBLOCK];
91   static u_int smrv[32]; // speculated MIPS register values
92   static u_int smrv_strong; // mask or regs that are likely to have correct values
93   static u_int smrv_weak; // same, but somewhat less likely
94   static u_int smrv_strong_next; // same, but after current insn executes
95   static u_int smrv_weak_next;
96   int imm[MAXBLOCK];
97   u_int ba[MAXBLOCK];
98   char likely[MAXBLOCK];
99   char is_ds[MAXBLOCK];
100   char ooo[MAXBLOCK];
101   uint64_t unneeded_reg[MAXBLOCK];
102   uint64_t unneeded_reg_upper[MAXBLOCK];
103   uint64_t branch_unneeded_reg[MAXBLOCK];
104   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
105   uint64_t p32[MAXBLOCK];
106   uint64_t pr32[MAXBLOCK];
107   signed char regmap_pre[MAXBLOCK][HOST_REGS];
108   static uint64_t current_constmap[HOST_REGS];
109   static uint64_t constmap[MAXBLOCK][HOST_REGS];
110   static struct regstat regs[MAXBLOCK];
111   static struct regstat branch_regs[MAXBLOCK];
112   signed char minimum_free_regs[MAXBLOCK];
113   u_int needed_reg[MAXBLOCK];
114   uint64_t requires_32bit[MAXBLOCK];
115   u_int wont_dirty[MAXBLOCK];
116   u_int will_dirty[MAXBLOCK];
117   int ccadj[MAXBLOCK];
118   int slen;
119   u_int instr_addr[MAXBLOCK];
120   u_int link_addr[MAXBLOCK][3];
121   int linkcount;
122   u_int stubs[MAXBLOCK*3][8];
123   int stubcount;
124   u_int literals[1024][2];
125   int literalcount;
126   int is_delayslot;
127   int cop1_usable;
128   u_char *out;
129   struct ll_entry *jump_in[4096];
130   struct ll_entry *jump_out[4096];
131   struct ll_entry *jump_dirty[4096];
132   u_int hash_table[65536][4]  __attribute__((aligned(16)));
133   char shadow[1048576]  __attribute__((aligned(16)));
134   void *copy;
135   int expirep;
136 #ifndef PCSX
137   u_int using_tlb;
138 #else
139   static const u_int using_tlb=0;
140 #endif
141   int new_dynarec_did_compile;
142   int new_dynarec_hacks;
143   u_int stop_after_jal;
144 #ifndef RAM_FIXED
145   static u_int ram_offset;
146 #else
147   static const u_int ram_offset=0;
148 #endif
149   extern u_char restore_candidate[512];
150   extern int cycle_count;
151
152   /* registers that may be allocated */
153   /* 1-31 gpr */
154 #define HIREG 32 // hi
155 #define LOREG 33 // lo
156 #define FSREG 34 // FPU status (FCSR)
157 #define CSREG 35 // Coprocessor status
158 #define CCREG 36 // Cycle count
159 #define INVCP 37 // Pointer to invalid_code
160 #define MMREG 38 // Pointer to memory_map
161 #define ROREG 39 // ram offset (if rdram!=0x80000000)
162 #define TEMPREG 40
163 #define FTEMP 40 // FPU temporary register
164 #define PTEMP 41 // Prefetch temporary register
165 #define TLREG 42 // TLB mapping offset
166 #define RHASH 43 // Return address hash
167 #define RHTBL 44 // Return address hash table address
168 #define RTEMP 45 // JR/JALR address register
169 #define MAXREG 45
170 #define AGEN1 46 // Address generation temporary register
171 #define AGEN2 47 // Address generation temporary register
172 #define MGEN1 48 // Maptable address generation temporary register
173 #define MGEN2 49 // Maptable address generation temporary register
174 #define BTREG 50 // Branch target temporary register
175
176   /* instruction types */
177 #define NOP 0     // No operation
178 #define LOAD 1    // Load
179 #define STORE 2   // Store
180 #define LOADLR 3  // Unaligned load
181 #define STORELR 4 // Unaligned store
182 #define MOV 5     // Move 
183 #define ALU 6     // Arithmetic/logic
184 #define MULTDIV 7 // Multiply/divide
185 #define SHIFT 8   // Shift by register
186 #define SHIFTIMM 9// Shift by immediate
187 #define IMM16 10  // 16-bit immediate
188 #define RJUMP 11  // Unconditional jump to register
189 #define UJUMP 12  // Unconditional jump
190 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
191 #define SJUMP 14  // Conditional branch (regimm format)
192 #define COP0 15   // Coprocessor 0
193 #define COP1 16   // Coprocessor 1
194 #define C1LS 17   // Coprocessor 1 load/store
195 #define FJUMP 18  // Conditional branch (floating point)
196 #define FLOAT 19  // Floating point unit
197 #define FCONV 20  // Convert integer to float
198 #define FCOMP 21  // Floating point compare (sets FSREG)
199 #define SYSCALL 22// SYSCALL
200 #define OTHER 23  // Other
201 #define SPAN 24   // Branch/delay slot spans 2 pages
202 #define NI 25     // Not implemented
203 #define HLECALL 26// PCSX fake opcodes for HLE
204 #define COP2 27   // Coprocessor 2 move
205 #define C2LS 28   // Coprocessor 2 load/store
206 #define C2OP 29   // Coprocessor 2 operation
207 #define INTCALL 30// Call interpreter to handle rare corner cases
208
209   /* stubs */
210 #define CC_STUB 1
211 #define FP_STUB 2
212 #define LOADB_STUB 3
213 #define LOADH_STUB 4
214 #define LOADW_STUB 5
215 #define LOADD_STUB 6
216 #define LOADBU_STUB 7
217 #define LOADHU_STUB 8
218 #define STOREB_STUB 9
219 #define STOREH_STUB 10
220 #define STOREW_STUB 11
221 #define STORED_STUB 12
222 #define STORELR_STUB 13
223 #define INVCODE_STUB 14
224
225   /* branch codes */
226 #define TAKEN 1
227 #define NOTTAKEN 2
228 #define NULLDS 3
229
230 // asm linkage
231 int new_recompile_block(int addr);
232 void *get_addr_ht(u_int vaddr);
233 void invalidate_block(u_int block);
234 void invalidate_addr(u_int addr);
235 void remove_hash(int vaddr);
236 void jump_vaddr();
237 void dyna_linker();
238 void dyna_linker_ds();
239 void verify_code();
240 void verify_code_vm();
241 void verify_code_ds();
242 void cc_interrupt();
243 void fp_exception();
244 void fp_exception_ds();
245 void jump_syscall();
246 void jump_syscall_hle();
247 void jump_eret();
248 void jump_hlecall();
249 void jump_intcall();
250 void new_dyna_leave();
251
252 // TLB
253 void TLBWI_new();
254 void TLBWR_new();
255 void read_nomem_new();
256 void read_nomemb_new();
257 void read_nomemh_new();
258 void read_nomemd_new();
259 void write_nomem_new();
260 void write_nomemb_new();
261 void write_nomemh_new();
262 void write_nomemd_new();
263 void write_rdram_new();
264 void write_rdramb_new();
265 void write_rdramh_new();
266 void write_rdramd_new();
267 extern u_int memory_map[1048576];
268
269 // Needed by assembler
270 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
271 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
272 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
273 void load_all_regs(signed char i_regmap[]);
274 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
275 void load_regs_entry(int t);
276 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
277
278 int tracedebug=0;
279
280 //#define DEBUG_CYCLE_COUNT 1
281
282 int cycle_multiplier; // 100 for 1.0
283
284 static int CLOCK_ADJUST(int x)
285 {
286   int s=(x>>31)|1;
287   return (x * cycle_multiplier + s * 50) / 100;
288 }
289
290 static void tlb_hacks()
291 {
292 #ifndef DISABLE_TLB
293   // Goldeneye hack
294   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
295   {
296     u_int addr;
297     int n;
298     switch (ROM_HEADER->Country_code&0xFF) 
299     {
300       case 0x45: // U
301         addr=0x34b30;
302         break;                   
303       case 0x4A: // J 
304         addr=0x34b70;    
305         break;    
306       case 0x50: // E 
307         addr=0x329f0;
308         break;                        
309       default: 
310         // Unknown country code
311         addr=0;
312         break;
313     }
314     u_int rom_addr=(u_int)rom;
315     #ifdef ROM_COPY
316     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
317     // in the lower 4G of memory to use this hack.  Copy it if necessary.
318     if((void *)rom>(void *)0xffffffff) {
319       munmap(ROM_COPY, 67108864);
320       if(mmap(ROM_COPY, 12582912,
321               PROT_READ | PROT_WRITE,
322               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
323               -1, 0) <= 0) {printf("mmap() failed\n");}
324       memcpy(ROM_COPY,rom,12582912);
325       rom_addr=(u_int)ROM_COPY;
326     }
327     #endif
328     if(addr) {
329       for(n=0x7F000;n<0x80000;n++) {
330         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
331       }
332     }
333   }
334 #endif
335 }
336
337 static u_int get_page(u_int vaddr)
338 {
339 #ifndef PCSX
340   u_int page=(vaddr^0x80000000)>>12;
341 #else
342   u_int page=vaddr&~0xe0000000;
343   if (page < 0x1000000)
344     page &= ~0x0e00000; // RAM mirrors
345   page>>=12;
346 #endif
347 #ifndef DISABLE_TLB
348   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
349 #endif
350   if(page>2048) page=2048+(page&2047);
351   return page;
352 }
353
354 #ifndef PCSX
355 static u_int get_vpage(u_int vaddr)
356 {
357   u_int vpage=(vaddr^0x80000000)>>12;
358 #ifndef DISABLE_TLB
359   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
360 #endif
361   if(vpage>2048) vpage=2048+(vpage&2047);
362   return vpage;
363 }
364 #else
365 // no virtual mem in PCSX
366 static u_int get_vpage(u_int vaddr)
367 {
368   return get_page(vaddr);
369 }
370 #endif
371
372 // Get address from virtual address
373 // This is called from the recompiled JR/JALR instructions
374 void *get_addr(u_int vaddr)
375 {
376   u_int page=get_page(vaddr);
377   u_int vpage=get_vpage(vaddr);
378   struct ll_entry *head;
379   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
380   head=jump_in[page];
381   while(head!=NULL) {
382     if(head->vaddr==vaddr&&head->reg32==0) {
383   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
384       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
385       ht_bin[3]=ht_bin[1];
386       ht_bin[2]=ht_bin[0];
387       ht_bin[1]=(int)head->addr;
388       ht_bin[0]=vaddr;
389       return head->addr;
390     }
391     head=head->next;
392   }
393   head=jump_dirty[vpage];
394   while(head!=NULL) {
395     if(head->vaddr==vaddr&&head->reg32==0) {
396       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
397       // Don't restore blocks which are about to expire from the cache
398       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
399       if(verify_dirty(head->addr)) {
400         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
401         invalid_code[vaddr>>12]=0;
402         inv_code_start=inv_code_end=~0;
403 #ifndef DISABLE_TLB
404         memory_map[vaddr>>12]|=0x40000000;
405 #endif
406         if(vpage<2048) {
407 #ifndef DISABLE_TLB
408           if(tlb_LUT_r[vaddr>>12]) {
409             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
410             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
411           }
412 #endif
413           restore_candidate[vpage>>3]|=1<<(vpage&7);
414         }
415         else restore_candidate[page>>3]|=1<<(page&7);
416         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
417         if(ht_bin[0]==vaddr) {
418           ht_bin[1]=(int)head->addr; // Replace existing entry
419         }
420         else
421         {
422           ht_bin[3]=ht_bin[1];
423           ht_bin[2]=ht_bin[0];
424           ht_bin[1]=(int)head->addr;
425           ht_bin[0]=vaddr;
426         }
427         return head->addr;
428       }
429     }
430     head=head->next;
431   }
432   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
433   int r=new_recompile_block(vaddr);
434   if(r==0) return get_addr(vaddr);
435   // Execute in unmapped page, generate pagefault execption
436   Status|=2;
437   Cause=(vaddr<<31)|0x8;
438   EPC=(vaddr&1)?vaddr-5:vaddr;
439   BadVAddr=(vaddr&~1);
440   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
441   EntryHi=BadVAddr&0xFFFFE000;
442   return get_addr_ht(0x80000000);
443 }
444 // Look up address in hash table first
445 void *get_addr_ht(u_int vaddr)
446 {
447   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
448   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
449   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
450   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
451   return get_addr(vaddr);
452 }
453
454 void *get_addr_32(u_int vaddr,u_int flags)
455 {
456 #ifdef FORCE32
457   return get_addr(vaddr);
458 #else
459   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
460   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
461   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
462   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
463   u_int page=get_page(vaddr);
464   u_int vpage=get_vpage(vaddr);
465   struct ll_entry *head;
466   head=jump_in[page];
467   while(head!=NULL) {
468     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
469       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
470       if(head->reg32==0) {
471         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
472         if(ht_bin[0]==-1) {
473           ht_bin[1]=(int)head->addr;
474           ht_bin[0]=vaddr;
475         }else if(ht_bin[2]==-1) {
476           ht_bin[3]=(int)head->addr;
477           ht_bin[2]=vaddr;
478         }
479         //ht_bin[3]=ht_bin[1];
480         //ht_bin[2]=ht_bin[0];
481         //ht_bin[1]=(int)head->addr;
482         //ht_bin[0]=vaddr;
483       }
484       return head->addr;
485     }
486     head=head->next;
487   }
488   head=jump_dirty[vpage];
489   while(head!=NULL) {
490     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
491       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
492       // Don't restore blocks which are about to expire from the cache
493       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
494       if(verify_dirty(head->addr)) {
495         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
496         invalid_code[vaddr>>12]=0;
497         inv_code_start=inv_code_end=~0;
498         memory_map[vaddr>>12]|=0x40000000;
499         if(vpage<2048) {
500 #ifndef DISABLE_TLB
501           if(tlb_LUT_r[vaddr>>12]) {
502             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
503             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
504           }
505 #endif
506           restore_candidate[vpage>>3]|=1<<(vpage&7);
507         }
508         else restore_candidate[page>>3]|=1<<(page&7);
509         if(head->reg32==0) {
510           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
511           if(ht_bin[0]==-1) {
512             ht_bin[1]=(int)head->addr;
513             ht_bin[0]=vaddr;
514           }else if(ht_bin[2]==-1) {
515             ht_bin[3]=(int)head->addr;
516             ht_bin[2]=vaddr;
517           }
518           //ht_bin[3]=ht_bin[1];
519           //ht_bin[2]=ht_bin[0];
520           //ht_bin[1]=(int)head->addr;
521           //ht_bin[0]=vaddr;
522         }
523         return head->addr;
524       }
525     }
526     head=head->next;
527   }
528   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
529   int r=new_recompile_block(vaddr);
530   if(r==0) return get_addr(vaddr);
531   // Execute in unmapped page, generate pagefault execption
532   Status|=2;
533   Cause=(vaddr<<31)|0x8;
534   EPC=(vaddr&1)?vaddr-5:vaddr;
535   BadVAddr=(vaddr&~1);
536   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
537   EntryHi=BadVAddr&0xFFFFE000;
538   return get_addr_ht(0x80000000);
539 #endif
540 }
541
542 void clear_all_regs(signed char regmap[])
543 {
544   int hr;
545   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
546 }
547
548 signed char get_reg(signed char regmap[],int r)
549 {
550   int hr;
551   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
552   return -1;
553 }
554
555 // Find a register that is available for two consecutive cycles
556 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
557 {
558   int hr;
559   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
560   return -1;
561 }
562
563 int count_free_regs(signed char regmap[])
564 {
565   int count=0;
566   int hr;
567   for(hr=0;hr<HOST_REGS;hr++)
568   {
569     if(hr!=EXCLUDE_REG) {
570       if(regmap[hr]<0) count++;
571     }
572   }
573   return count;
574 }
575
576 void dirty_reg(struct regstat *cur,signed char reg)
577 {
578   int hr;
579   if(!reg) return;
580   for (hr=0;hr<HOST_REGS;hr++) {
581     if((cur->regmap[hr]&63)==reg) {
582       cur->dirty|=1<<hr;
583     }
584   }
585 }
586
587 // If we dirty the lower half of a 64 bit register which is now being
588 // sign-extended, we need to dump the upper half.
589 // Note: Do this only after completion of the instruction, because
590 // some instructions may need to read the full 64-bit value even if
591 // overwriting it (eg SLTI, DSRA32).
592 static void flush_dirty_uppers(struct regstat *cur)
593 {
594   int hr,reg;
595   for (hr=0;hr<HOST_REGS;hr++) {
596     if((cur->dirty>>hr)&1) {
597       reg=cur->regmap[hr];
598       if(reg>=64) 
599         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
600     }
601   }
602 }
603
604 void set_const(struct regstat *cur,signed char reg,uint64_t value)
605 {
606   int hr;
607   if(!reg) return;
608   for (hr=0;hr<HOST_REGS;hr++) {
609     if(cur->regmap[hr]==reg) {
610       cur->isconst|=1<<hr;
611       current_constmap[hr]=value;
612     }
613     else if((cur->regmap[hr]^64)==reg) {
614       cur->isconst|=1<<hr;
615       current_constmap[hr]=value>>32;
616     }
617   }
618 }
619
620 void clear_const(struct regstat *cur,signed char reg)
621 {
622   int hr;
623   if(!reg) return;
624   for (hr=0;hr<HOST_REGS;hr++) {
625     if((cur->regmap[hr]&63)==reg) {
626       cur->isconst&=~(1<<hr);
627     }
628   }
629 }
630
631 int is_const(struct regstat *cur,signed char reg)
632 {
633   int hr;
634   if(reg<0) return 0;
635   if(!reg) return 1;
636   for (hr=0;hr<HOST_REGS;hr++) {
637     if((cur->regmap[hr]&63)==reg) {
638       return (cur->isconst>>hr)&1;
639     }
640   }
641   return 0;
642 }
643 uint64_t get_const(struct regstat *cur,signed char reg)
644 {
645   int hr;
646   if(!reg) return 0;
647   for (hr=0;hr<HOST_REGS;hr++) {
648     if(cur->regmap[hr]==reg) {
649       return current_constmap[hr];
650     }
651   }
652   printf("Unknown constant in r%d\n",reg);
653   exit(1);
654 }
655
656 // Least soon needed registers
657 // Look at the next ten instructions and see which registers
658 // will be used.  Try not to reallocate these.
659 void lsn(u_char hsn[], int i, int *preferred_reg)
660 {
661   int j;
662   int b=-1;
663   for(j=0;j<9;j++)
664   {
665     if(i+j>=slen) {
666       j=slen-i-1;
667       break;
668     }
669     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
670     {
671       // Don't go past an unconditonal jump
672       j++;
673       break;
674     }
675   }
676   for(;j>=0;j--)
677   {
678     if(rs1[i+j]) hsn[rs1[i+j]]=j;
679     if(rs2[i+j]) hsn[rs2[i+j]]=j;
680     if(rt1[i+j]) hsn[rt1[i+j]]=j;
681     if(rt2[i+j]) hsn[rt2[i+j]]=j;
682     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
683       // Stores can allocate zero
684       hsn[rs1[i+j]]=j;
685       hsn[rs2[i+j]]=j;
686     }
687     // On some architectures stores need invc_ptr
688     #if defined(HOST_IMM8)
689     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
690       hsn[INVCP]=j;
691     }
692     #endif
693     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
694     {
695       hsn[CCREG]=j;
696       b=j;
697     }
698   }
699   if(b>=0)
700   {
701     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
702     {
703       // Follow first branch
704       int t=(ba[i+b]-start)>>2;
705       j=7-b;if(t+j>=slen) j=slen-t-1;
706       for(;j>=0;j--)
707       {
708         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
709         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
710         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
711         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
712       }
713     }
714     // TODO: preferred register based on backward branch
715   }
716   // Delay slot should preferably not overwrite branch conditions or cycle count
717   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
718     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
719     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
720     hsn[CCREG]=1;
721     // ...or hash tables
722     hsn[RHASH]=1;
723     hsn[RHTBL]=1;
724   }
725   // Coprocessor load/store needs FTEMP, even if not declared
726   if(itype[i]==C1LS||itype[i]==C2LS) {
727     hsn[FTEMP]=0;
728   }
729   // Load L/R also uses FTEMP as a temporary register
730   if(itype[i]==LOADLR) {
731     hsn[FTEMP]=0;
732   }
733   // Also SWL/SWR/SDL/SDR
734   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
735     hsn[FTEMP]=0;
736   }
737   // Don't remove the TLB registers either
738   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
739     hsn[TLREG]=0;
740   }
741   // Don't remove the miniht registers
742   if(itype[i]==UJUMP||itype[i]==RJUMP)
743   {
744     hsn[RHASH]=0;
745     hsn[RHTBL]=0;
746   }
747 }
748
749 // We only want to allocate registers if we're going to use them again soon
750 int needed_again(int r, int i)
751 {
752   int j;
753   int b=-1;
754   int rn=10;
755   
756   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
757   {
758     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
759       return 0; // Don't need any registers if exiting the block
760   }
761   for(j=0;j<9;j++)
762   {
763     if(i+j>=slen) {
764       j=slen-i-1;
765       break;
766     }
767     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
768     {
769       // Don't go past an unconditonal jump
770       j++;
771       break;
772     }
773     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
774     {
775       break;
776     }
777   }
778   for(;j>=1;j--)
779   {
780     if(rs1[i+j]==r) rn=j;
781     if(rs2[i+j]==r) rn=j;
782     if((unneeded_reg[i+j]>>r)&1) rn=10;
783     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
784     {
785       b=j;
786     }
787   }
788   /*
789   if(b>=0)
790   {
791     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
792     {
793       // Follow first branch
794       int o=rn;
795       int t=(ba[i+b]-start)>>2;
796       j=7-b;if(t+j>=slen) j=slen-t-1;
797       for(;j>=0;j--)
798       {
799         if(!((unneeded_reg[t+j]>>r)&1)) {
800           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
801           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
802         }
803         else rn=o;
804       }
805     }
806   }*/
807   if(rn<10) return 1;
808   return 0;
809 }
810
811 // Try to match register allocations at the end of a loop with those
812 // at the beginning
813 int loop_reg(int i, int r, int hr)
814 {
815   int j,k;
816   for(j=0;j<9;j++)
817   {
818     if(i+j>=slen) {
819       j=slen-i-1;
820       break;
821     }
822     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
823     {
824       // Don't go past an unconditonal jump
825       j++;
826       break;
827     }
828   }
829   k=0;
830   if(i>0){
831     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
832       k--;
833   }
834   for(;k<j;k++)
835   {
836     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
837     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
838     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
839     {
840       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
841       {
842         int t=(ba[i+k]-start)>>2;
843         int reg=get_reg(regs[t].regmap_entry,r);
844         if(reg>=0) return reg;
845         //reg=get_reg(regs[t+1].regmap_entry,r);
846         //if(reg>=0) return reg;
847       }
848     }
849   }
850   return hr;
851 }
852
853
854 // Allocate every register, preserving source/target regs
855 void alloc_all(struct regstat *cur,int i)
856 {
857   int hr;
858   
859   for(hr=0;hr<HOST_REGS;hr++) {
860     if(hr!=EXCLUDE_REG) {
861       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
862          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
863       {
864         cur->regmap[hr]=-1;
865         cur->dirty&=~(1<<hr);
866       }
867       // Don't need zeros
868       if((cur->regmap[hr]&63)==0)
869       {
870         cur->regmap[hr]=-1;
871         cur->dirty&=~(1<<hr);
872       }
873     }
874   }
875 }
876
877 #ifndef FORCE32
878 void div64(int64_t dividend,int64_t divisor)
879 {
880   lo=dividend/divisor;
881   hi=dividend%divisor;
882   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
883   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
884 }
885 void divu64(uint64_t dividend,uint64_t divisor)
886 {
887   lo=dividend/divisor;
888   hi=dividend%divisor;
889   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
890   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
891 }
892
893 void mult64(uint64_t m1,uint64_t m2)
894 {
895    unsigned long long int op1, op2, op3, op4;
896    unsigned long long int result1, result2, result3, result4;
897    unsigned long long int temp1, temp2, temp3, temp4;
898    int sign = 0;
899    
900    if (m1 < 0)
901      {
902     op2 = -m1;
903     sign = 1 - sign;
904      }
905    else op2 = m1;
906    if (m2 < 0)
907      {
908     op4 = -m2;
909     sign = 1 - sign;
910      }
911    else op4 = m2;
912    
913    op1 = op2 & 0xFFFFFFFF;
914    op2 = (op2 >> 32) & 0xFFFFFFFF;
915    op3 = op4 & 0xFFFFFFFF;
916    op4 = (op4 >> 32) & 0xFFFFFFFF;
917    
918    temp1 = op1 * op3;
919    temp2 = (temp1 >> 32) + op1 * op4;
920    temp3 = op2 * op3;
921    temp4 = (temp3 >> 32) + op2 * op4;
922    
923    result1 = temp1 & 0xFFFFFFFF;
924    result2 = temp2 + (temp3 & 0xFFFFFFFF);
925    result3 = (result2 >> 32) + temp4;
926    result4 = (result3 >> 32);
927    
928    lo = result1 | (result2 << 32);
929    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
930    if (sign)
931      {
932     hi = ~hi;
933     if (!lo) hi++;
934     else lo = ~lo + 1;
935      }
936 }
937
938 void multu64(uint64_t m1,uint64_t m2)
939 {
940    unsigned long long int op1, op2, op3, op4;
941    unsigned long long int result1, result2, result3, result4;
942    unsigned long long int temp1, temp2, temp3, temp4;
943    
944    op1 = m1 & 0xFFFFFFFF;
945    op2 = (m1 >> 32) & 0xFFFFFFFF;
946    op3 = m2 & 0xFFFFFFFF;
947    op4 = (m2 >> 32) & 0xFFFFFFFF;
948    
949    temp1 = op1 * op3;
950    temp2 = (temp1 >> 32) + op1 * op4;
951    temp3 = op2 * op3;
952    temp4 = (temp3 >> 32) + op2 * op4;
953    
954    result1 = temp1 & 0xFFFFFFFF;
955    result2 = temp2 + (temp3 & 0xFFFFFFFF);
956    result3 = (result2 >> 32) + temp4;
957    result4 = (result3 >> 32);
958    
959    lo = result1 | (result2 << 32);
960    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
961    
962   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
963   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
964 }
965
966 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
967 {
968   if(bits) {
969     original<<=64-bits;
970     original>>=64-bits;
971     loaded<<=bits;
972     original|=loaded;
973   }
974   else original=loaded;
975   return original;
976 }
977 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
978 {
979   if(bits^56) {
980     original>>=64-(bits^56);
981     original<<=64-(bits^56);
982     loaded>>=bits^56;
983     original|=loaded;
984   }
985   else original=loaded;
986   return original;
987 }
988 #endif
989
990 #ifdef __i386__
991 #include "assem_x86.c"
992 #endif
993 #ifdef __x86_64__
994 #include "assem_x64.c"
995 #endif
996 #ifdef __arm__
997 #include "assem_arm.c"
998 #endif
999
1000 // Add virtual address mapping to linked list
1001 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1002 {
1003   struct ll_entry *new_entry;
1004   new_entry=malloc(sizeof(struct ll_entry));
1005   assert(new_entry!=NULL);
1006   new_entry->vaddr=vaddr;
1007   new_entry->reg32=0;
1008   new_entry->addr=addr;
1009   new_entry->next=*head;
1010   *head=new_entry;
1011 }
1012
1013 // Add virtual address mapping for 32-bit compiled block
1014 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1015 {
1016   ll_add(head,vaddr,addr);
1017 #ifndef FORCE32
1018   (*head)->reg32=reg32;
1019 #endif
1020 }
1021
1022 // Check if an address is already compiled
1023 // but don't return addresses which are about to expire from the cache
1024 void *check_addr(u_int vaddr)
1025 {
1026   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1027   if(ht_bin[0]==vaddr) {
1028     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1029       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1030   }
1031   if(ht_bin[2]==vaddr) {
1032     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1033       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1034   }
1035   u_int page=get_page(vaddr);
1036   struct ll_entry *head;
1037   head=jump_in[page];
1038   while(head!=NULL) {
1039     if(head->vaddr==vaddr&&head->reg32==0) {
1040       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1041         // Update existing entry with current address
1042         if(ht_bin[0]==vaddr) {
1043           ht_bin[1]=(int)head->addr;
1044           return head->addr;
1045         }
1046         if(ht_bin[2]==vaddr) {
1047           ht_bin[3]=(int)head->addr;
1048           return head->addr;
1049         }
1050         // Insert into hash table with low priority.
1051         // Don't evict existing entries, as they are probably
1052         // addresses that are being accessed frequently.
1053         if(ht_bin[0]==-1) {
1054           ht_bin[1]=(int)head->addr;
1055           ht_bin[0]=vaddr;
1056         }else if(ht_bin[2]==-1) {
1057           ht_bin[3]=(int)head->addr;
1058           ht_bin[2]=vaddr;
1059         }
1060         return head->addr;
1061       }
1062     }
1063     head=head->next;
1064   }
1065   return 0;
1066 }
1067
1068 void remove_hash(int vaddr)
1069 {
1070   //printf("remove hash: %x\n",vaddr);
1071   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1072   if(ht_bin[2]==vaddr) {
1073     ht_bin[2]=ht_bin[3]=-1;
1074   }
1075   if(ht_bin[0]==vaddr) {
1076     ht_bin[0]=ht_bin[2];
1077     ht_bin[1]=ht_bin[3];
1078     ht_bin[2]=ht_bin[3]=-1;
1079   }
1080 }
1081
1082 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1083 {
1084   struct ll_entry *next;
1085   while(*head) {
1086     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) || 
1087        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1088     {
1089       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1090       remove_hash((*head)->vaddr);
1091       next=(*head)->next;
1092       free(*head);
1093       *head=next;
1094     }
1095     else
1096     {
1097       head=&((*head)->next);
1098     }
1099   }
1100 }
1101
1102 // Remove all entries from linked list
1103 void ll_clear(struct ll_entry **head)
1104 {
1105   struct ll_entry *cur;
1106   struct ll_entry *next;
1107   if(cur=*head) {
1108     *head=0;
1109     while(cur) {
1110       next=cur->next;
1111       free(cur);
1112       cur=next;
1113     }
1114   }
1115 }
1116
1117 // Dereference the pointers and remove if it matches
1118 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1119 {
1120   while(head) {
1121     int ptr=get_pointer(head->addr);
1122     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1123     if(((ptr>>shift)==(addr>>shift)) ||
1124        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1125     {
1126       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1127       u_int host_addr=(u_int)kill_pointer(head->addr);
1128       #ifdef __arm__
1129         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1130       #endif
1131     }
1132     head=head->next;
1133   }
1134 }
1135
1136 // This is called when we write to a compiled block (see do_invstub)
1137 void invalidate_page(u_int page)
1138 {
1139   struct ll_entry *head;
1140   struct ll_entry *next;
1141   head=jump_in[page];
1142   jump_in[page]=0;
1143   while(head!=NULL) {
1144     inv_debug("INVALIDATE: %x\n",head->vaddr);
1145     remove_hash(head->vaddr);
1146     next=head->next;
1147     free(head);
1148     head=next;
1149   }
1150   head=jump_out[page];
1151   jump_out[page]=0;
1152   while(head!=NULL) {
1153     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1154     u_int host_addr=(u_int)kill_pointer(head->addr);
1155     #ifdef __arm__
1156       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1157     #endif
1158     next=head->next;
1159     free(head);
1160     head=next;
1161   }
1162 }
1163
1164 static void invalidate_block_range(u_int block, u_int first, u_int last)
1165 {
1166   u_int page=get_page(block<<12);
1167   //printf("first=%d last=%d\n",first,last);
1168   invalidate_page(page);
1169   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1170   assert(last<page+5);
1171   // Invalidate the adjacent pages if a block crosses a 4K boundary
1172   while(first<page) {
1173     invalidate_page(first);
1174     first++;
1175   }
1176   for(first=page+1;first<last;first++) {
1177     invalidate_page(first);
1178   }
1179   #ifdef __arm__
1180     do_clear_cache();
1181   #endif
1182   
1183   // Don't trap writes
1184   invalid_code[block]=1;
1185 #ifndef DISABLE_TLB
1186   // If there is a valid TLB entry for this page, remove write protect
1187   if(tlb_LUT_w[block]) {
1188     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1189     // CHECK: Is this right?
1190     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1191     u_int real_block=tlb_LUT_w[block]>>12;
1192     invalid_code[real_block]=1;
1193     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1194   }
1195   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1196 #endif
1197
1198   #ifdef USE_MINI_HT
1199   memset(mini_ht,-1,sizeof(mini_ht));
1200   #endif
1201 }
1202
1203 void invalidate_block(u_int block)
1204 {
1205   u_int page=get_page(block<<12);
1206   u_int vpage=get_vpage(block<<12);
1207   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1208   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1209   u_int first,last;
1210   first=last=page;
1211   struct ll_entry *head;
1212   head=jump_dirty[vpage];
1213   //printf("page=%d vpage=%d\n",page,vpage);
1214   while(head!=NULL) {
1215     u_int start,end;
1216     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1217       get_bounds((int)head->addr,&start,&end);
1218       //printf("start: %x end: %x\n",start,end);
1219       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1220         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1221           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1222           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1223         }
1224       }
1225 #ifndef DISABLE_TLB
1226       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1227         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1228           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1229           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1230         }
1231       }
1232 #endif
1233     }
1234     head=head->next;
1235   }
1236   invalidate_block_range(block,first,last);
1237 }
1238
1239 void invalidate_addr(u_int addr)
1240 {
1241 #ifdef PCSX
1242   //static int rhits;
1243   // this check is done by the caller
1244   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1245   u_int page=get_vpage(addr);
1246   if(page<2048) { // RAM
1247     struct ll_entry *head;
1248     u_int addr_min=~0, addr_max=0;
1249     int mask=RAM_SIZE-1;
1250     int pg1;
1251     inv_code_start=addr&~0xfff;
1252     inv_code_end=addr|0xfff;
1253     pg1=page;
1254     if (pg1>0) {
1255       // must check previous page too because of spans..
1256       pg1--;
1257       inv_code_start-=0x1000;
1258     }
1259     for(;pg1<=page;pg1++) {
1260       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1261         u_int start,end;
1262         get_bounds((int)head->addr,&start,&end);
1263         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1264           if(start<addr_min) addr_min=start;
1265           if(end>addr_max) addr_max=end;
1266         }
1267         else if(addr<start) {
1268           if(start<inv_code_end)
1269             inv_code_end=start-1;
1270         }
1271         else {
1272           if(end>inv_code_start)
1273             inv_code_start=end;
1274         }
1275       }
1276     }
1277     if (addr_min!=~0) {
1278       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1279       inv_code_start=inv_code_end=~0;
1280       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1281       return;
1282     }
1283     else {
1284       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1285       return;
1286     }
1287   }
1288 #endif
1289   invalidate_block(addr>>12);
1290 }
1291
1292 // This is called when loading a save state.
1293 // Anything could have changed, so invalidate everything.
1294 void invalidate_all_pages()
1295 {
1296   u_int page,n;
1297   for(page=0;page<4096;page++)
1298     invalidate_page(page);
1299   for(page=0;page<1048576;page++)
1300     if(!invalid_code[page]) {
1301       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1302       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1303     }
1304   #ifdef __arm__
1305   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1306   #endif
1307   #ifdef USE_MINI_HT
1308   memset(mini_ht,-1,sizeof(mini_ht));
1309   #endif
1310   #ifndef DISABLE_TLB
1311   // TLB
1312   for(page=0;page<0x100000;page++) {
1313     if(tlb_LUT_r[page]) {
1314       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1315       if(!tlb_LUT_w[page]||!invalid_code[page])
1316         memory_map[page]|=0x40000000; // Write protect
1317     }
1318     else memory_map[page]=-1;
1319     if(page==0x80000) page=0xC0000;
1320   }
1321   tlb_hacks();
1322   #endif
1323 }
1324
1325 // Add an entry to jump_out after making a link
1326 void add_link(u_int vaddr,void *src)
1327 {
1328   u_int page=get_page(vaddr);
1329   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1330   int *ptr=(int *)(src+4);
1331   assert((*ptr&0x0fff0000)==0x059f0000);
1332   ll_add(jump_out+page,vaddr,src);
1333   //int ptr=get_pointer(src);
1334   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1335 }
1336
1337 // If a code block was found to be unmodified (bit was set in
1338 // restore_candidate) and it remains unmodified (bit is clear
1339 // in invalid_code) then move the entries for that 4K page from
1340 // the dirty list to the clean list.
1341 void clean_blocks(u_int page)
1342 {
1343   struct ll_entry *head;
1344   inv_debug("INV: clean_blocks page=%d\n",page);
1345   head=jump_dirty[page];
1346   while(head!=NULL) {
1347     if(!invalid_code[head->vaddr>>12]) {
1348       // Don't restore blocks which are about to expire from the cache
1349       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1350         u_int start,end;
1351         if(verify_dirty((int)head->addr)) {
1352           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1353           u_int i;
1354           u_int inv=0;
1355           get_bounds((int)head->addr,&start,&end);
1356           if(start-(u_int)rdram<RAM_SIZE) {
1357             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1358               inv|=invalid_code[i];
1359             }
1360           }
1361 #ifndef DISABLE_TLB
1362           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1363             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1364             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1365             if(addr<start||addr>=end) inv=1;
1366           }
1367 #endif
1368           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1369             inv=1;
1370           }
1371           if(!inv) {
1372             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1373             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1374               u_int ppage=page;
1375 #ifndef DISABLE_TLB
1376               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1377 #endif
1378               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1379               //printf("page=%x, addr=%x\n",page,head->vaddr);
1380               //assert(head->vaddr>>12==(page|0x80000));
1381               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1382               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1383               if(!head->reg32) {
1384                 if(ht_bin[0]==head->vaddr) {
1385                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1386                 }
1387                 if(ht_bin[2]==head->vaddr) {
1388                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1389                 }
1390               }
1391             }
1392           }
1393         }
1394       }
1395     }
1396     head=head->next;
1397   }
1398 }
1399
1400
1401 void mov_alloc(struct regstat *current,int i)
1402 {
1403   // Note: Don't need to actually alloc the source registers
1404   if((~current->is32>>rs1[i])&1) {
1405     //alloc_reg64(current,i,rs1[i]);
1406     alloc_reg64(current,i,rt1[i]);
1407     current->is32&=~(1LL<<rt1[i]);
1408   } else {
1409     //alloc_reg(current,i,rs1[i]);
1410     alloc_reg(current,i,rt1[i]);
1411     current->is32|=(1LL<<rt1[i]);
1412   }
1413   clear_const(current,rs1[i]);
1414   clear_const(current,rt1[i]);
1415   dirty_reg(current,rt1[i]);
1416 }
1417
1418 void shiftimm_alloc(struct regstat *current,int i)
1419 {
1420   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1421   {
1422     if(rt1[i]) {
1423       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424       else lt1[i]=rs1[i];
1425       alloc_reg(current,i,rt1[i]);
1426       current->is32|=1LL<<rt1[i];
1427       dirty_reg(current,rt1[i]);
1428       if(is_const(current,rs1[i])) {
1429         int v=get_const(current,rs1[i]);
1430         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1431         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1432         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1433       }
1434       else clear_const(current,rt1[i]);
1435     }
1436   }
1437   else
1438   {
1439     clear_const(current,rs1[i]);
1440     clear_const(current,rt1[i]);
1441   }
1442
1443   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1444   {
1445     if(rt1[i]) {
1446       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1447       alloc_reg64(current,i,rt1[i]);
1448       current->is32&=~(1LL<<rt1[i]);
1449       dirty_reg(current,rt1[i]);
1450     }
1451   }
1452   if(opcode2[i]==0x3c) // DSLL32
1453   {
1454     if(rt1[i]) {
1455       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1456       alloc_reg64(current,i,rt1[i]);
1457       current->is32&=~(1LL<<rt1[i]);
1458       dirty_reg(current,rt1[i]);
1459     }
1460   }
1461   if(opcode2[i]==0x3e) // DSRL32
1462   {
1463     if(rt1[i]) {
1464       alloc_reg64(current,i,rs1[i]);
1465       if(imm[i]==32) {
1466         alloc_reg64(current,i,rt1[i]);
1467         current->is32&=~(1LL<<rt1[i]);
1468       } else {
1469         alloc_reg(current,i,rt1[i]);
1470         current->is32|=1LL<<rt1[i];
1471       }
1472       dirty_reg(current,rt1[i]);
1473     }
1474   }
1475   if(opcode2[i]==0x3f) // DSRA32
1476   {
1477     if(rt1[i]) {
1478       alloc_reg64(current,i,rs1[i]);
1479       alloc_reg(current,i,rt1[i]);
1480       current->is32|=1LL<<rt1[i];
1481       dirty_reg(current,rt1[i]);
1482     }
1483   }
1484 }
1485
1486 void shift_alloc(struct regstat *current,int i)
1487 {
1488   if(rt1[i]) {
1489     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1490     {
1491       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1492       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1493       alloc_reg(current,i,rt1[i]);
1494       if(rt1[i]==rs2[i]) {
1495         alloc_reg_temp(current,i,-1);
1496         minimum_free_regs[i]=1;
1497       }
1498       current->is32|=1LL<<rt1[i];
1499     } else { // DSLLV/DSRLV/DSRAV
1500       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1501       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1502       alloc_reg64(current,i,rt1[i]);
1503       current->is32&=~(1LL<<rt1[i]);
1504       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1505       {
1506         alloc_reg_temp(current,i,-1);
1507         minimum_free_regs[i]=1;
1508       }
1509     }
1510     clear_const(current,rs1[i]);
1511     clear_const(current,rs2[i]);
1512     clear_const(current,rt1[i]);
1513     dirty_reg(current,rt1[i]);
1514   }
1515 }
1516
1517 void alu_alloc(struct regstat *current,int i)
1518 {
1519   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1520     if(rt1[i]) {
1521       if(rs1[i]&&rs2[i]) {
1522         alloc_reg(current,i,rs1[i]);
1523         alloc_reg(current,i,rs2[i]);
1524       }
1525       else {
1526         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1527         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1528       }
1529       alloc_reg(current,i,rt1[i]);
1530     }
1531     current->is32|=1LL<<rt1[i];
1532   }
1533   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1534     if(rt1[i]) {
1535       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1536       {
1537         alloc_reg64(current,i,rs1[i]);
1538         alloc_reg64(current,i,rs2[i]);
1539         alloc_reg(current,i,rt1[i]);
1540       } else {
1541         alloc_reg(current,i,rs1[i]);
1542         alloc_reg(current,i,rs2[i]);
1543         alloc_reg(current,i,rt1[i]);
1544       }
1545     }
1546     current->is32|=1LL<<rt1[i];
1547   }
1548   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1549     if(rt1[i]) {
1550       if(rs1[i]&&rs2[i]) {
1551         alloc_reg(current,i,rs1[i]);
1552         alloc_reg(current,i,rs2[i]);
1553       }
1554       else
1555       {
1556         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1557         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1558       }
1559       alloc_reg(current,i,rt1[i]);
1560       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1561       {
1562         if(!((current->uu>>rt1[i])&1)) {
1563           alloc_reg64(current,i,rt1[i]);
1564         }
1565         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1566           if(rs1[i]&&rs2[i]) {
1567             alloc_reg64(current,i,rs1[i]);
1568             alloc_reg64(current,i,rs2[i]);
1569           }
1570           else
1571           {
1572             // Is is really worth it to keep 64-bit values in registers?
1573             #ifdef NATIVE_64BIT
1574             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1575             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1576             #endif
1577           }
1578         }
1579         current->is32&=~(1LL<<rt1[i]);
1580       } else {
1581         current->is32|=1LL<<rt1[i];
1582       }
1583     }
1584   }
1585   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1586     if(rt1[i]) {
1587       if(rs1[i]&&rs2[i]) {
1588         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1589           alloc_reg64(current,i,rs1[i]);
1590           alloc_reg64(current,i,rs2[i]);
1591           alloc_reg64(current,i,rt1[i]);
1592         } else {
1593           alloc_reg(current,i,rs1[i]);
1594           alloc_reg(current,i,rs2[i]);
1595           alloc_reg(current,i,rt1[i]);
1596         }
1597       }
1598       else {
1599         alloc_reg(current,i,rt1[i]);
1600         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1601           // DADD used as move, or zeroing
1602           // If we have a 64-bit source, then make the target 64 bits too
1603           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1604             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1605             alloc_reg64(current,i,rt1[i]);
1606           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1607             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1608             alloc_reg64(current,i,rt1[i]);
1609           }
1610           if(opcode2[i]>=0x2e&&rs2[i]) {
1611             // DSUB used as negation - 64-bit result
1612             // If we have a 32-bit register, extend it to 64 bits
1613             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1614             alloc_reg64(current,i,rt1[i]);
1615           }
1616         }
1617       }
1618       if(rs1[i]&&rs2[i]) {
1619         current->is32&=~(1LL<<rt1[i]);
1620       } else if(rs1[i]) {
1621         current->is32&=~(1LL<<rt1[i]);
1622         if((current->is32>>rs1[i])&1)
1623           current->is32|=1LL<<rt1[i];
1624       } else if(rs2[i]) {
1625         current->is32&=~(1LL<<rt1[i]);
1626         if((current->is32>>rs2[i])&1)
1627           current->is32|=1LL<<rt1[i];
1628       } else {
1629         current->is32|=1LL<<rt1[i];
1630       }
1631     }
1632   }
1633   clear_const(current,rs1[i]);
1634   clear_const(current,rs2[i]);
1635   clear_const(current,rt1[i]);
1636   dirty_reg(current,rt1[i]);
1637 }
1638
1639 void imm16_alloc(struct regstat *current,int i)
1640 {
1641   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1642   else lt1[i]=rs1[i];
1643   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1644   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1645     current->is32&=~(1LL<<rt1[i]);
1646     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1647       // TODO: Could preserve the 32-bit flag if the immediate is zero
1648       alloc_reg64(current,i,rt1[i]);
1649       alloc_reg64(current,i,rs1[i]);
1650     }
1651     clear_const(current,rs1[i]);
1652     clear_const(current,rt1[i]);
1653   }
1654   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1655     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1656     current->is32|=1LL<<rt1[i];
1657     clear_const(current,rs1[i]);
1658     clear_const(current,rt1[i]);
1659   }
1660   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1661     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1662       if(rs1[i]!=rt1[i]) {
1663         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1664         alloc_reg64(current,i,rt1[i]);
1665         current->is32&=~(1LL<<rt1[i]);
1666       }
1667     }
1668     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1669     if(is_const(current,rs1[i])) {
1670       int v=get_const(current,rs1[i]);
1671       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1672       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1673       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1674     }
1675     else clear_const(current,rt1[i]);
1676   }
1677   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1678     if(is_const(current,rs1[i])) {
1679       int v=get_const(current,rs1[i]);
1680       set_const(current,rt1[i],v+imm[i]);
1681     }
1682     else clear_const(current,rt1[i]);
1683     current->is32|=1LL<<rt1[i];
1684   }
1685   else {
1686     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1687     current->is32|=1LL<<rt1[i];
1688   }
1689   dirty_reg(current,rt1[i]);
1690 }
1691
1692 void load_alloc(struct regstat *current,int i)
1693 {
1694   clear_const(current,rt1[i]);
1695   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1696   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1697   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1698   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1699     alloc_reg(current,i,rt1[i]);
1700     assert(get_reg(current->regmap,rt1[i])>=0);
1701     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1702     {
1703       current->is32&=~(1LL<<rt1[i]);
1704       alloc_reg64(current,i,rt1[i]);
1705     }
1706     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1707     {
1708       current->is32&=~(1LL<<rt1[i]);
1709       alloc_reg64(current,i,rt1[i]);
1710       alloc_all(current,i);
1711       alloc_reg64(current,i,FTEMP);
1712       minimum_free_regs[i]=HOST_REGS;
1713     }
1714     else current->is32|=1LL<<rt1[i];
1715     dirty_reg(current,rt1[i]);
1716     // If using TLB, need a register for pointer to the mapping table
1717     if(using_tlb) alloc_reg(current,i,TLREG);
1718     // LWL/LWR need a temporary register for the old value
1719     if(opcode[i]==0x22||opcode[i]==0x26)
1720     {
1721       alloc_reg(current,i,FTEMP);
1722       alloc_reg_temp(current,i,-1);
1723       minimum_free_regs[i]=1;
1724     }
1725   }
1726   else
1727   {
1728     // Load to r0 or unneeded register (dummy load)
1729     // but we still need a register to calculate the address
1730     if(opcode[i]==0x22||opcode[i]==0x26)
1731     {
1732       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1733     }
1734     // If using TLB, need a register for pointer to the mapping table
1735     if(using_tlb) alloc_reg(current,i,TLREG);
1736     alloc_reg_temp(current,i,-1);
1737     minimum_free_regs[i]=1;
1738     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1739     {
1740       alloc_all(current,i);
1741       alloc_reg64(current,i,FTEMP);
1742       minimum_free_regs[i]=HOST_REGS;
1743     }
1744   }
1745 }
1746
1747 void store_alloc(struct regstat *current,int i)
1748 {
1749   clear_const(current,rs2[i]);
1750   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1751   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1752   alloc_reg(current,i,rs2[i]);
1753   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1754     alloc_reg64(current,i,rs2[i]);
1755     if(rs2[i]) alloc_reg(current,i,FTEMP);
1756   }
1757   // If using TLB, need a register for pointer to the mapping table
1758   if(using_tlb) alloc_reg(current,i,TLREG);
1759   #if defined(HOST_IMM8)
1760   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1761   else alloc_reg(current,i,INVCP);
1762   #endif
1763   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1764     alloc_reg(current,i,FTEMP);
1765   }
1766   // We need a temporary register for address generation
1767   alloc_reg_temp(current,i,-1);
1768   minimum_free_regs[i]=1;
1769 }
1770
1771 void c1ls_alloc(struct regstat *current,int i)
1772 {
1773   //clear_const(current,rs1[i]); // FIXME
1774   clear_const(current,rt1[i]);
1775   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1776   alloc_reg(current,i,CSREG); // Status
1777   alloc_reg(current,i,FTEMP);
1778   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1779     alloc_reg64(current,i,FTEMP);
1780   }
1781   // If using TLB, need a register for pointer to the mapping table
1782   if(using_tlb) alloc_reg(current,i,TLREG);
1783   #if defined(HOST_IMM8)
1784   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1785   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1786     alloc_reg(current,i,INVCP);
1787   #endif
1788   // We need a temporary register for address generation
1789   alloc_reg_temp(current,i,-1);
1790 }
1791
1792 void c2ls_alloc(struct regstat *current,int i)
1793 {
1794   clear_const(current,rt1[i]);
1795   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1796   alloc_reg(current,i,FTEMP);
1797   // If using TLB, need a register for pointer to the mapping table
1798   if(using_tlb) alloc_reg(current,i,TLREG);
1799   #if defined(HOST_IMM8)
1800   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1801   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1802     alloc_reg(current,i,INVCP);
1803   #endif
1804   // We need a temporary register for address generation
1805   alloc_reg_temp(current,i,-1);
1806   minimum_free_regs[i]=1;
1807 }
1808
1809 #ifndef multdiv_alloc
1810 void multdiv_alloc(struct regstat *current,int i)
1811 {
1812   //  case 0x18: MULT
1813   //  case 0x19: MULTU
1814   //  case 0x1A: DIV
1815   //  case 0x1B: DIVU
1816   //  case 0x1C: DMULT
1817   //  case 0x1D: DMULTU
1818   //  case 0x1E: DDIV
1819   //  case 0x1F: DDIVU
1820   clear_const(current,rs1[i]);
1821   clear_const(current,rs2[i]);
1822   if(rs1[i]&&rs2[i])
1823   {
1824     if((opcode2[i]&4)==0) // 32-bit
1825     {
1826       current->u&=~(1LL<<HIREG);
1827       current->u&=~(1LL<<LOREG);
1828       alloc_reg(current,i,HIREG);
1829       alloc_reg(current,i,LOREG);
1830       alloc_reg(current,i,rs1[i]);
1831       alloc_reg(current,i,rs2[i]);
1832       current->is32|=1LL<<HIREG;
1833       current->is32|=1LL<<LOREG;
1834       dirty_reg(current,HIREG);
1835       dirty_reg(current,LOREG);
1836     }
1837     else // 64-bit
1838     {
1839       current->u&=~(1LL<<HIREG);
1840       current->u&=~(1LL<<LOREG);
1841       current->uu&=~(1LL<<HIREG);
1842       current->uu&=~(1LL<<LOREG);
1843       alloc_reg64(current,i,HIREG);
1844       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1845       alloc_reg64(current,i,rs1[i]);
1846       alloc_reg64(current,i,rs2[i]);
1847       alloc_all(current,i);
1848       current->is32&=~(1LL<<HIREG);
1849       current->is32&=~(1LL<<LOREG);
1850       dirty_reg(current,HIREG);
1851       dirty_reg(current,LOREG);
1852       minimum_free_regs[i]=HOST_REGS;
1853     }
1854   }
1855   else
1856   {
1857     // Multiply by zero is zero.
1858     // MIPS does not have a divide by zero exception.
1859     // The result is undefined, we return zero.
1860     alloc_reg(current,i,HIREG);
1861     alloc_reg(current,i,LOREG);
1862     current->is32|=1LL<<HIREG;
1863     current->is32|=1LL<<LOREG;
1864     dirty_reg(current,HIREG);
1865     dirty_reg(current,LOREG);
1866   }
1867 }
1868 #endif
1869
1870 void cop0_alloc(struct regstat *current,int i)
1871 {
1872   if(opcode2[i]==0) // MFC0
1873   {
1874     if(rt1[i]) {
1875       clear_const(current,rt1[i]);
1876       alloc_all(current,i);
1877       alloc_reg(current,i,rt1[i]);
1878       current->is32|=1LL<<rt1[i];
1879       dirty_reg(current,rt1[i]);
1880     }
1881   }
1882   else if(opcode2[i]==4) // MTC0
1883   {
1884     if(rs1[i]){
1885       clear_const(current,rs1[i]);
1886       alloc_reg(current,i,rs1[i]);
1887       alloc_all(current,i);
1888     }
1889     else {
1890       alloc_all(current,i); // FIXME: Keep r0
1891       current->u&=~1LL;
1892       alloc_reg(current,i,0);
1893     }
1894   }
1895   else
1896   {
1897     // TLBR/TLBWI/TLBWR/TLBP/ERET
1898     assert(opcode2[i]==0x10);
1899     alloc_all(current,i);
1900   }
1901   minimum_free_regs[i]=HOST_REGS;
1902 }
1903
1904 void cop1_alloc(struct regstat *current,int i)
1905 {
1906   alloc_reg(current,i,CSREG); // Load status
1907   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1908   {
1909     if(rt1[i]){
1910       clear_const(current,rt1[i]);
1911       if(opcode2[i]==1) {
1912         alloc_reg64(current,i,rt1[i]); // DMFC1
1913         current->is32&=~(1LL<<rt1[i]);
1914       }else{
1915         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1916         current->is32|=1LL<<rt1[i];
1917       }
1918       dirty_reg(current,rt1[i]);
1919     }
1920     alloc_reg_temp(current,i,-1);
1921   }
1922   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1923   {
1924     if(rs1[i]){
1925       clear_const(current,rs1[i]);
1926       if(opcode2[i]==5)
1927         alloc_reg64(current,i,rs1[i]); // DMTC1
1928       else
1929         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1930       alloc_reg_temp(current,i,-1);
1931     }
1932     else {
1933       current->u&=~1LL;
1934       alloc_reg(current,i,0);
1935       alloc_reg_temp(current,i,-1);
1936     }
1937   }
1938   minimum_free_regs[i]=1;
1939 }
1940 void fconv_alloc(struct regstat *current,int i)
1941 {
1942   alloc_reg(current,i,CSREG); // Load status
1943   alloc_reg_temp(current,i,-1);
1944   minimum_free_regs[i]=1;
1945 }
1946 void float_alloc(struct regstat *current,int i)
1947 {
1948   alloc_reg(current,i,CSREG); // Load status
1949   alloc_reg_temp(current,i,-1);
1950   minimum_free_regs[i]=1;
1951 }
1952 void c2op_alloc(struct regstat *current,int i)
1953 {
1954   alloc_reg_temp(current,i,-1);
1955 }
1956 void fcomp_alloc(struct regstat *current,int i)
1957 {
1958   alloc_reg(current,i,CSREG); // Load status
1959   alloc_reg(current,i,FSREG); // Load flags
1960   dirty_reg(current,FSREG); // Flag will be modified
1961   alloc_reg_temp(current,i,-1);
1962   minimum_free_regs[i]=1;
1963 }
1964
1965 void syscall_alloc(struct regstat *current,int i)
1966 {
1967   alloc_cc(current,i);
1968   dirty_reg(current,CCREG);
1969   alloc_all(current,i);
1970   minimum_free_regs[i]=HOST_REGS;
1971   current->isconst=0;
1972 }
1973
1974 void delayslot_alloc(struct regstat *current,int i)
1975 {
1976   switch(itype[i]) {
1977     case UJUMP:
1978     case CJUMP:
1979     case SJUMP:
1980     case RJUMP:
1981     case FJUMP:
1982     case SYSCALL:
1983     case HLECALL:
1984     case SPAN:
1985       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1986       printf("Disabled speculative precompilation\n");
1987       stop_after_jal=1;
1988       break;
1989     case IMM16:
1990       imm16_alloc(current,i);
1991       break;
1992     case LOAD:
1993     case LOADLR:
1994       load_alloc(current,i);
1995       break;
1996     case STORE:
1997     case STORELR:
1998       store_alloc(current,i);
1999       break;
2000     case ALU:
2001       alu_alloc(current,i);
2002       break;
2003     case SHIFT:
2004       shift_alloc(current,i);
2005       break;
2006     case MULTDIV:
2007       multdiv_alloc(current,i);
2008       break;
2009     case SHIFTIMM:
2010       shiftimm_alloc(current,i);
2011       break;
2012     case MOV:
2013       mov_alloc(current,i);
2014       break;
2015     case COP0:
2016       cop0_alloc(current,i);
2017       break;
2018     case COP1:
2019     case COP2:
2020       cop1_alloc(current,i);
2021       break;
2022     case C1LS:
2023       c1ls_alloc(current,i);
2024       break;
2025     case C2LS:
2026       c2ls_alloc(current,i);
2027       break;
2028     case FCONV:
2029       fconv_alloc(current,i);
2030       break;
2031     case FLOAT:
2032       float_alloc(current,i);
2033       break;
2034     case FCOMP:
2035       fcomp_alloc(current,i);
2036       break;
2037     case C2OP:
2038       c2op_alloc(current,i);
2039       break;
2040   }
2041 }
2042
2043 // Special case where a branch and delay slot span two pages in virtual memory
2044 static void pagespan_alloc(struct regstat *current,int i)
2045 {
2046   current->isconst=0;
2047   current->wasconst=0;
2048   regs[i].wasconst=0;
2049   minimum_free_regs[i]=HOST_REGS;
2050   alloc_all(current,i);
2051   alloc_cc(current,i);
2052   dirty_reg(current,CCREG);
2053   if(opcode[i]==3) // JAL
2054   {
2055     alloc_reg(current,i,31);
2056     dirty_reg(current,31);
2057   }
2058   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2059   {
2060     alloc_reg(current,i,rs1[i]);
2061     if (rt1[i]!=0) {
2062       alloc_reg(current,i,rt1[i]);
2063       dirty_reg(current,rt1[i]);
2064     }
2065   }
2066   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2067   {
2068     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2069     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2070     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2071     {
2072       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2073       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2074     }
2075   }
2076   else
2077   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2078   {
2079     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2080     if(!((current->is32>>rs1[i])&1))
2081     {
2082       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2083     }
2084   }
2085   else
2086   if(opcode[i]==0x11) // BC1
2087   {
2088     alloc_reg(current,i,FSREG);
2089     alloc_reg(current,i,CSREG);
2090   }
2091   //else ...
2092 }
2093
2094 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2095 {
2096   stubs[stubcount][0]=type;
2097   stubs[stubcount][1]=addr;
2098   stubs[stubcount][2]=retaddr;
2099   stubs[stubcount][3]=a;
2100   stubs[stubcount][4]=b;
2101   stubs[stubcount][5]=c;
2102   stubs[stubcount][6]=d;
2103   stubs[stubcount][7]=e;
2104   stubcount++;
2105 }
2106
2107 // Write out a single register
2108 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2109 {
2110   int hr;
2111   for(hr=0;hr<HOST_REGS;hr++) {
2112     if(hr!=EXCLUDE_REG) {
2113       if((regmap[hr]&63)==r) {
2114         if((dirty>>hr)&1) {
2115           if(regmap[hr]<64) {
2116             emit_storereg(r,hr);
2117 #ifndef FORCE32
2118             if((is32>>regmap[hr])&1) {
2119               emit_sarimm(hr,31,hr);
2120               emit_storereg(r|64,hr);
2121             }
2122 #endif
2123           }else{
2124             emit_storereg(r|64,hr);
2125           }
2126         }
2127       }
2128     }
2129   }
2130 }
2131
2132 int mchecksum()
2133 {
2134   //if(!tracedebug) return 0;
2135   int i;
2136   int sum=0;
2137   for(i=0;i<2097152;i++) {
2138     unsigned int temp=sum;
2139     sum<<=1;
2140     sum|=(~temp)>>31;
2141     sum^=((u_int *)rdram)[i];
2142   }
2143   return sum;
2144 }
2145 int rchecksum()
2146 {
2147   int i;
2148   int sum=0;
2149   for(i=0;i<64;i++)
2150     sum^=((u_int *)reg)[i];
2151   return sum;
2152 }
2153 void rlist()
2154 {
2155   int i;
2156   printf("TRACE: ");
2157   for(i=0;i<32;i++)
2158     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2159   printf("\n");
2160 #ifndef DISABLE_COP1
2161   printf("TRACE: ");
2162   for(i=0;i<32;i++)
2163     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2164   printf("\n");
2165 #endif
2166 }
2167
2168 void enabletrace()
2169 {
2170   tracedebug=1;
2171 }
2172
2173 void memdebug(int i)
2174 {
2175   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2176   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2177   //rlist();
2178   //if(tracedebug) {
2179   //if(Count>=-2084597794) {
2180   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2181   //if(0) {
2182     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2183     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2184     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2185     rlist();
2186     #ifdef __i386__
2187     printf("TRACE: %x\n",(&i)[-1]);
2188     #endif
2189     #ifdef __arm__
2190     int j;
2191     printf("TRACE: %x \n",(&j)[10]);
2192     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2193     #endif
2194     //fflush(stdout);
2195   }
2196   //printf("TRACE: %x\n",(&i)[-1]);
2197 }
2198
2199 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2200 {
2201   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2202 }
2203
2204 void alu_assemble(int i,struct regstat *i_regs)
2205 {
2206   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2207     if(rt1[i]) {
2208       signed char s1,s2,t;
2209       t=get_reg(i_regs->regmap,rt1[i]);
2210       if(t>=0) {
2211         s1=get_reg(i_regs->regmap,rs1[i]);
2212         s2=get_reg(i_regs->regmap,rs2[i]);
2213         if(rs1[i]&&rs2[i]) {
2214           assert(s1>=0);
2215           assert(s2>=0);
2216           if(opcode2[i]&2) emit_sub(s1,s2,t);
2217           else emit_add(s1,s2,t);
2218         }
2219         else if(rs1[i]) {
2220           if(s1>=0) emit_mov(s1,t);
2221           else emit_loadreg(rs1[i],t);
2222         }
2223         else if(rs2[i]) {
2224           if(s2>=0) {
2225             if(opcode2[i]&2) emit_neg(s2,t);
2226             else emit_mov(s2,t);
2227           }
2228           else {
2229             emit_loadreg(rs2[i],t);
2230             if(opcode2[i]&2) emit_neg(t,t);
2231           }
2232         }
2233         else emit_zeroreg(t);
2234       }
2235     }
2236   }
2237   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2238     if(rt1[i]) {
2239       signed char s1l,s2l,s1h,s2h,tl,th;
2240       tl=get_reg(i_regs->regmap,rt1[i]);
2241       th=get_reg(i_regs->regmap,rt1[i]|64);
2242       if(tl>=0) {
2243         s1l=get_reg(i_regs->regmap,rs1[i]);
2244         s2l=get_reg(i_regs->regmap,rs2[i]);
2245         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2246         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2247         if(rs1[i]&&rs2[i]) {
2248           assert(s1l>=0);
2249           assert(s2l>=0);
2250           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2251           else emit_adds(s1l,s2l,tl);
2252           if(th>=0) {
2253             #ifdef INVERTED_CARRY
2254             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2255             #else
2256             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2257             #endif
2258             else emit_add(s1h,s2h,th);
2259           }
2260         }
2261         else if(rs1[i]) {
2262           if(s1l>=0) emit_mov(s1l,tl);
2263           else emit_loadreg(rs1[i],tl);
2264           if(th>=0) {
2265             if(s1h>=0) emit_mov(s1h,th);
2266             else emit_loadreg(rs1[i]|64,th);
2267           }
2268         }
2269         else if(rs2[i]) {
2270           if(s2l>=0) {
2271             if(opcode2[i]&2) emit_negs(s2l,tl);
2272             else emit_mov(s2l,tl);
2273           }
2274           else {
2275             emit_loadreg(rs2[i],tl);
2276             if(opcode2[i]&2) emit_negs(tl,tl);
2277           }
2278           if(th>=0) {
2279             #ifdef INVERTED_CARRY
2280             if(s2h>=0) emit_mov(s2h,th);
2281             else emit_loadreg(rs2[i]|64,th);
2282             if(opcode2[i]&2) {
2283               emit_adcimm(-1,th); // x86 has inverted carry flag
2284               emit_not(th,th);
2285             }
2286             #else
2287             if(opcode2[i]&2) {
2288               if(s2h>=0) emit_rscimm(s2h,0,th);
2289               else {
2290                 emit_loadreg(rs2[i]|64,th);
2291                 emit_rscimm(th,0,th);
2292               }
2293             }else{
2294               if(s2h>=0) emit_mov(s2h,th);
2295               else emit_loadreg(rs2[i]|64,th);
2296             }
2297             #endif
2298           }
2299         }
2300         else {
2301           emit_zeroreg(tl);
2302           if(th>=0) emit_zeroreg(th);
2303         }
2304       }
2305     }
2306   }
2307   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2308     if(rt1[i]) {
2309       signed char s1l,s1h,s2l,s2h,t;
2310       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2311       {
2312         t=get_reg(i_regs->regmap,rt1[i]);
2313         //assert(t>=0);
2314         if(t>=0) {
2315           s1l=get_reg(i_regs->regmap,rs1[i]);
2316           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2317           s2l=get_reg(i_regs->regmap,rs2[i]);
2318           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2319           if(rs2[i]==0) // rx<r0
2320           {
2321             assert(s1h>=0);
2322             if(opcode2[i]==0x2a) // SLT
2323               emit_shrimm(s1h,31,t);
2324             else // SLTU (unsigned can not be less than zero)
2325               emit_zeroreg(t);
2326           }
2327           else if(rs1[i]==0) // r0<rx
2328           {
2329             assert(s2h>=0);
2330             if(opcode2[i]==0x2a) // SLT
2331               emit_set_gz64_32(s2h,s2l,t);
2332             else // SLTU (set if not zero)
2333               emit_set_nz64_32(s2h,s2l,t);
2334           }
2335           else {
2336             assert(s1l>=0);assert(s1h>=0);
2337             assert(s2l>=0);assert(s2h>=0);
2338             if(opcode2[i]==0x2a) // SLT
2339               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2340             else // SLTU
2341               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2342           }
2343         }
2344       } else {
2345         t=get_reg(i_regs->regmap,rt1[i]);
2346         //assert(t>=0);
2347         if(t>=0) {
2348           s1l=get_reg(i_regs->regmap,rs1[i]);
2349           s2l=get_reg(i_regs->regmap,rs2[i]);
2350           if(rs2[i]==0) // rx<r0
2351           {
2352             assert(s1l>=0);
2353             if(opcode2[i]==0x2a) // SLT
2354               emit_shrimm(s1l,31,t);
2355             else // SLTU (unsigned can not be less than zero)
2356               emit_zeroreg(t);
2357           }
2358           else if(rs1[i]==0) // r0<rx
2359           {
2360             assert(s2l>=0);
2361             if(opcode2[i]==0x2a) // SLT
2362               emit_set_gz32(s2l,t);
2363             else // SLTU (set if not zero)
2364               emit_set_nz32(s2l,t);
2365           }
2366           else{
2367             assert(s1l>=0);assert(s2l>=0);
2368             if(opcode2[i]==0x2a) // SLT
2369               emit_set_if_less32(s1l,s2l,t);
2370             else // SLTU
2371               emit_set_if_carry32(s1l,s2l,t);
2372           }
2373         }
2374       }
2375     }
2376   }
2377   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2378     if(rt1[i]) {
2379       signed char s1l,s1h,s2l,s2h,th,tl;
2380       tl=get_reg(i_regs->regmap,rt1[i]);
2381       th=get_reg(i_regs->regmap,rt1[i]|64);
2382       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2383       {
2384         assert(tl>=0);
2385         if(tl>=0) {
2386           s1l=get_reg(i_regs->regmap,rs1[i]);
2387           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2388           s2l=get_reg(i_regs->regmap,rs2[i]);
2389           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2390           if(rs1[i]&&rs2[i]) {
2391             assert(s1l>=0);assert(s1h>=0);
2392             assert(s2l>=0);assert(s2h>=0);
2393             if(opcode2[i]==0x24) { // AND
2394               emit_and(s1l,s2l,tl);
2395               emit_and(s1h,s2h,th);
2396             } else
2397             if(opcode2[i]==0x25) { // OR
2398               emit_or(s1l,s2l,tl);
2399               emit_or(s1h,s2h,th);
2400             } else
2401             if(opcode2[i]==0x26) { // XOR
2402               emit_xor(s1l,s2l,tl);
2403               emit_xor(s1h,s2h,th);
2404             } else
2405             if(opcode2[i]==0x27) { // NOR
2406               emit_or(s1l,s2l,tl);
2407               emit_or(s1h,s2h,th);
2408               emit_not(tl,tl);
2409               emit_not(th,th);
2410             }
2411           }
2412           else
2413           {
2414             if(opcode2[i]==0x24) { // AND
2415               emit_zeroreg(tl);
2416               emit_zeroreg(th);
2417             } else
2418             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2419               if(rs1[i]){
2420                 if(s1l>=0) emit_mov(s1l,tl);
2421                 else emit_loadreg(rs1[i],tl);
2422                 if(s1h>=0) emit_mov(s1h,th);
2423                 else emit_loadreg(rs1[i]|64,th);
2424               }
2425               else
2426               if(rs2[i]){
2427                 if(s2l>=0) emit_mov(s2l,tl);
2428                 else emit_loadreg(rs2[i],tl);
2429                 if(s2h>=0) emit_mov(s2h,th);
2430                 else emit_loadreg(rs2[i]|64,th);
2431               }
2432               else{
2433                 emit_zeroreg(tl);
2434                 emit_zeroreg(th);
2435               }
2436             } else
2437             if(opcode2[i]==0x27) { // NOR
2438               if(rs1[i]){
2439                 if(s1l>=0) emit_not(s1l,tl);
2440                 else{
2441                   emit_loadreg(rs1[i],tl);
2442                   emit_not(tl,tl);
2443                 }
2444                 if(s1h>=0) emit_not(s1h,th);
2445                 else{
2446                   emit_loadreg(rs1[i]|64,th);
2447                   emit_not(th,th);
2448                 }
2449               }
2450               else
2451               if(rs2[i]){
2452                 if(s2l>=0) emit_not(s2l,tl);
2453                 else{
2454                   emit_loadreg(rs2[i],tl);
2455                   emit_not(tl,tl);
2456                 }
2457                 if(s2h>=0) emit_not(s2h,th);
2458                 else{
2459                   emit_loadreg(rs2[i]|64,th);
2460                   emit_not(th,th);
2461                 }
2462               }
2463               else {
2464                 emit_movimm(-1,tl);
2465                 emit_movimm(-1,th);
2466               }
2467             }
2468           }
2469         }
2470       }
2471       else
2472       {
2473         // 32 bit
2474         if(tl>=0) {
2475           s1l=get_reg(i_regs->regmap,rs1[i]);
2476           s2l=get_reg(i_regs->regmap,rs2[i]);
2477           if(rs1[i]&&rs2[i]) {
2478             assert(s1l>=0);
2479             assert(s2l>=0);
2480             if(opcode2[i]==0x24) { // AND
2481               emit_and(s1l,s2l,tl);
2482             } else
2483             if(opcode2[i]==0x25) { // OR
2484               emit_or(s1l,s2l,tl);
2485             } else
2486             if(opcode2[i]==0x26) { // XOR
2487               emit_xor(s1l,s2l,tl);
2488             } else
2489             if(opcode2[i]==0x27) { // NOR
2490               emit_or(s1l,s2l,tl);
2491               emit_not(tl,tl);
2492             }
2493           }
2494           else
2495           {
2496             if(opcode2[i]==0x24) { // AND
2497               emit_zeroreg(tl);
2498             } else
2499             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2500               if(rs1[i]){
2501                 if(s1l>=0) emit_mov(s1l,tl);
2502                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2503               }
2504               else
2505               if(rs2[i]){
2506                 if(s2l>=0) emit_mov(s2l,tl);
2507                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2508               }
2509               else emit_zeroreg(tl);
2510             } else
2511             if(opcode2[i]==0x27) { // NOR
2512               if(rs1[i]){
2513                 if(s1l>=0) emit_not(s1l,tl);
2514                 else {
2515                   emit_loadreg(rs1[i],tl);
2516                   emit_not(tl,tl);
2517                 }
2518               }
2519               else
2520               if(rs2[i]){
2521                 if(s2l>=0) emit_not(s2l,tl);
2522                 else {
2523                   emit_loadreg(rs2[i],tl);
2524                   emit_not(tl,tl);
2525                 }
2526               }
2527               else emit_movimm(-1,tl);
2528             }
2529           }
2530         }
2531       }
2532     }
2533   }
2534 }
2535
2536 void imm16_assemble(int i,struct regstat *i_regs)
2537 {
2538   if (opcode[i]==0x0f) { // LUI
2539     if(rt1[i]) {
2540       signed char t;
2541       t=get_reg(i_regs->regmap,rt1[i]);
2542       //assert(t>=0);
2543       if(t>=0) {
2544         if(!((i_regs->isconst>>t)&1))
2545           emit_movimm(imm[i]<<16,t);
2546       }
2547     }
2548   }
2549   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2550     if(rt1[i]) {
2551       signed char s,t;
2552       t=get_reg(i_regs->regmap,rt1[i]);
2553       s=get_reg(i_regs->regmap,rs1[i]);
2554       if(rs1[i]) {
2555         //assert(t>=0);
2556         //assert(s>=0);
2557         if(t>=0) {
2558           if(!((i_regs->isconst>>t)&1)) {
2559             if(s<0) {
2560               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2561               emit_addimm(t,imm[i],t);
2562             }else{
2563               if(!((i_regs->wasconst>>s)&1))
2564                 emit_addimm(s,imm[i],t);
2565               else
2566                 emit_movimm(constmap[i][s]+imm[i],t);
2567             }
2568           }
2569         }
2570       } else {
2571         if(t>=0) {
2572           if(!((i_regs->isconst>>t)&1))
2573             emit_movimm(imm[i],t);
2574         }
2575       }
2576     }
2577   }
2578   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2579     if(rt1[i]) {
2580       signed char sh,sl,th,tl;
2581       th=get_reg(i_regs->regmap,rt1[i]|64);
2582       tl=get_reg(i_regs->regmap,rt1[i]);
2583       sh=get_reg(i_regs->regmap,rs1[i]|64);
2584       sl=get_reg(i_regs->regmap,rs1[i]);
2585       if(tl>=0) {
2586         if(rs1[i]) {
2587           assert(sh>=0);
2588           assert(sl>=0);
2589           if(th>=0) {
2590             emit_addimm64_32(sh,sl,imm[i],th,tl);
2591           }
2592           else {
2593             emit_addimm(sl,imm[i],tl);
2594           }
2595         } else {
2596           emit_movimm(imm[i],tl);
2597           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2598         }
2599       }
2600     }
2601   }
2602   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2603     if(rt1[i]) {
2604       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2605       signed char sh,sl,t;
2606       t=get_reg(i_regs->regmap,rt1[i]);
2607       sh=get_reg(i_regs->regmap,rs1[i]|64);
2608       sl=get_reg(i_regs->regmap,rs1[i]);
2609       //assert(t>=0);
2610       if(t>=0) {
2611         if(rs1[i]>0) {
2612           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2613           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2614             if(opcode[i]==0x0a) { // SLTI
2615               if(sl<0) {
2616                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2617                 emit_slti32(t,imm[i],t);
2618               }else{
2619                 emit_slti32(sl,imm[i],t);
2620               }
2621             }
2622             else { // SLTIU
2623               if(sl<0) {
2624                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2625                 emit_sltiu32(t,imm[i],t);
2626               }else{
2627                 emit_sltiu32(sl,imm[i],t);
2628               }
2629             }
2630           }else{ // 64-bit
2631             assert(sl>=0);
2632             if(opcode[i]==0x0a) // SLTI
2633               emit_slti64_32(sh,sl,imm[i],t);
2634             else // SLTIU
2635               emit_sltiu64_32(sh,sl,imm[i],t);
2636           }
2637         }else{
2638           // SLTI(U) with r0 is just stupid,
2639           // nonetheless examples can be found
2640           if(opcode[i]==0x0a) // SLTI
2641             if(0<imm[i]) emit_movimm(1,t);
2642             else emit_zeroreg(t);
2643           else // SLTIU
2644           {
2645             if(imm[i]) emit_movimm(1,t);
2646             else emit_zeroreg(t);
2647           }
2648         }
2649       }
2650     }
2651   }
2652   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2653     if(rt1[i]) {
2654       signed char sh,sl,th,tl;
2655       th=get_reg(i_regs->regmap,rt1[i]|64);
2656       tl=get_reg(i_regs->regmap,rt1[i]);
2657       sh=get_reg(i_regs->regmap,rs1[i]|64);
2658       sl=get_reg(i_regs->regmap,rs1[i]);
2659       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2660         if(opcode[i]==0x0c) //ANDI
2661         {
2662           if(rs1[i]) {
2663             if(sl<0) {
2664               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2665               emit_andimm(tl,imm[i],tl);
2666             }else{
2667               if(!((i_regs->wasconst>>sl)&1))
2668                 emit_andimm(sl,imm[i],tl);
2669               else
2670                 emit_movimm(constmap[i][sl]&imm[i],tl);
2671             }
2672           }
2673           else
2674             emit_zeroreg(tl);
2675           if(th>=0) emit_zeroreg(th);
2676         }
2677         else
2678         {
2679           if(rs1[i]) {
2680             if(sl<0) {
2681               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2682             }
2683             if(th>=0) {
2684               if(sh<0) {
2685                 emit_loadreg(rs1[i]|64,th);
2686               }else{
2687                 emit_mov(sh,th);
2688               }
2689             }
2690             if(opcode[i]==0x0d) //ORI
2691             if(sl<0) {
2692               emit_orimm(tl,imm[i],tl);
2693             }else{
2694               if(!((i_regs->wasconst>>sl)&1))
2695                 emit_orimm(sl,imm[i],tl);
2696               else
2697                 emit_movimm(constmap[i][sl]|imm[i],tl);
2698             }
2699             if(opcode[i]==0x0e) //XORI
2700             if(sl<0) {
2701               emit_xorimm(tl,imm[i],tl);
2702             }else{
2703               if(!((i_regs->wasconst>>sl)&1))
2704                 emit_xorimm(sl,imm[i],tl);
2705               else
2706                 emit_movimm(constmap[i][sl]^imm[i],tl);
2707             }
2708           }
2709           else {
2710             emit_movimm(imm[i],tl);
2711             if(th>=0) emit_zeroreg(th);
2712           }
2713         }
2714       }
2715     }
2716   }
2717 }
2718
2719 void shiftimm_assemble(int i,struct regstat *i_regs)
2720 {
2721   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2722   {
2723     if(rt1[i]) {
2724       signed char s,t;
2725       t=get_reg(i_regs->regmap,rt1[i]);
2726       s=get_reg(i_regs->regmap,rs1[i]);
2727       //assert(t>=0);
2728       if(t>=0&&!((i_regs->isconst>>t)&1)){
2729         if(rs1[i]==0)
2730         {
2731           emit_zeroreg(t);
2732         }
2733         else
2734         {
2735           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2736           if(imm[i]) {
2737             if(opcode2[i]==0) // SLL
2738             {
2739               emit_shlimm(s<0?t:s,imm[i],t);
2740             }
2741             if(opcode2[i]==2) // SRL
2742             {
2743               emit_shrimm(s<0?t:s,imm[i],t);
2744             }
2745             if(opcode2[i]==3) // SRA
2746             {
2747               emit_sarimm(s<0?t:s,imm[i],t);
2748             }
2749           }else{
2750             // Shift by zero
2751             if(s>=0 && s!=t) emit_mov(s,t);
2752           }
2753         }
2754       }
2755       //emit_storereg(rt1[i],t); //DEBUG
2756     }
2757   }
2758   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2759   {
2760     if(rt1[i]) {
2761       signed char sh,sl,th,tl;
2762       th=get_reg(i_regs->regmap,rt1[i]|64);
2763       tl=get_reg(i_regs->regmap,rt1[i]);
2764       sh=get_reg(i_regs->regmap,rs1[i]|64);
2765       sl=get_reg(i_regs->regmap,rs1[i]);
2766       if(tl>=0) {
2767         if(rs1[i]==0)
2768         {
2769           emit_zeroreg(tl);
2770           if(th>=0) emit_zeroreg(th);
2771         }
2772         else
2773         {
2774           assert(sl>=0);
2775           assert(sh>=0);
2776           if(imm[i]) {
2777             if(opcode2[i]==0x38) // DSLL
2778             {
2779               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2780               emit_shlimm(sl,imm[i],tl);
2781             }
2782             if(opcode2[i]==0x3a) // DSRL
2783             {
2784               emit_shrdimm(sl,sh,imm[i],tl);
2785               if(th>=0) emit_shrimm(sh,imm[i],th);
2786             }
2787             if(opcode2[i]==0x3b) // DSRA
2788             {
2789               emit_shrdimm(sl,sh,imm[i],tl);
2790               if(th>=0) emit_sarimm(sh,imm[i],th);
2791             }
2792           }else{
2793             // Shift by zero
2794             if(sl!=tl) emit_mov(sl,tl);
2795             if(th>=0&&sh!=th) emit_mov(sh,th);
2796           }
2797         }
2798       }
2799     }
2800   }
2801   if(opcode2[i]==0x3c) // DSLL32
2802   {
2803     if(rt1[i]) {
2804       signed char sl,tl,th;
2805       tl=get_reg(i_regs->regmap,rt1[i]);
2806       th=get_reg(i_regs->regmap,rt1[i]|64);
2807       sl=get_reg(i_regs->regmap,rs1[i]);
2808       if(th>=0||tl>=0){
2809         assert(tl>=0);
2810         assert(th>=0);
2811         assert(sl>=0);
2812         emit_mov(sl,th);
2813         emit_zeroreg(tl);
2814         if(imm[i]>32)
2815         {
2816           emit_shlimm(th,imm[i]&31,th);
2817         }
2818       }
2819     }
2820   }
2821   if(opcode2[i]==0x3e) // DSRL32
2822   {
2823     if(rt1[i]) {
2824       signed char sh,tl,th;
2825       tl=get_reg(i_regs->regmap,rt1[i]);
2826       th=get_reg(i_regs->regmap,rt1[i]|64);
2827       sh=get_reg(i_regs->regmap,rs1[i]|64);
2828       if(tl>=0){
2829         assert(sh>=0);
2830         emit_mov(sh,tl);
2831         if(th>=0) emit_zeroreg(th);
2832         if(imm[i]>32)
2833         {
2834           emit_shrimm(tl,imm[i]&31,tl);
2835         }
2836       }
2837     }
2838   }
2839   if(opcode2[i]==0x3f) // DSRA32
2840   {
2841     if(rt1[i]) {
2842       signed char sh,tl;
2843       tl=get_reg(i_regs->regmap,rt1[i]);
2844       sh=get_reg(i_regs->regmap,rs1[i]|64);
2845       if(tl>=0){
2846         assert(sh>=0);
2847         emit_mov(sh,tl);
2848         if(imm[i]>32)
2849         {
2850           emit_sarimm(tl,imm[i]&31,tl);
2851         }
2852       }
2853     }
2854   }
2855 }
2856
2857 #ifndef shift_assemble
2858 void shift_assemble(int i,struct regstat *i_regs)
2859 {
2860   printf("Need shift_assemble for this architecture.\n");
2861   exit(1);
2862 }
2863 #endif
2864
2865 void load_assemble(int i,struct regstat *i_regs)
2866 {
2867   int s,th,tl,addr,map=-1;
2868   int offset;
2869   int jaddr=0;
2870   int memtarget=0,c=0;
2871   int fastload_reg_override=0;
2872   u_int hr,reglist=0;
2873   th=get_reg(i_regs->regmap,rt1[i]|64);
2874   tl=get_reg(i_regs->regmap,rt1[i]);
2875   s=get_reg(i_regs->regmap,rs1[i]);
2876   offset=imm[i];
2877   for(hr=0;hr<HOST_REGS;hr++) {
2878     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2879   }
2880   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2881   if(s>=0) {
2882     c=(i_regs->wasconst>>s)&1;
2883     if (c) {
2884       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2885       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2886     }
2887   }
2888   //printf("load_assemble: c=%d\n",c);
2889   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2890   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2891 #ifdef PCSX
2892   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2893     ||rt1[i]==0) {
2894       // could be FIFO, must perform the read
2895       // ||dummy read
2896       assem_debug("(forced read)\n");
2897       tl=get_reg(i_regs->regmap,-1);
2898       assert(tl>=0);
2899   }
2900 #endif
2901   if(offset||s<0||c) addr=tl;
2902   else addr=s;
2903   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2904  if(tl>=0) {
2905   //printf("load_assemble: c=%d\n",c);
2906   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2907   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2908   reglist&=~(1<<tl);
2909   if(th>=0) reglist&=~(1<<th);
2910   if(!using_tlb) {
2911     if(!c) {
2912       #ifdef RAM_OFFSET
2913       map=get_reg(i_regs->regmap,ROREG);
2914       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2915       #endif
2916 //#define R29_HACK 1
2917       #ifdef R29_HACK
2918       // Strmnnrmn's speed hack
2919       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2920       #endif
2921       {
2922         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2923       }
2924     }
2925     else if(ram_offset&&memtarget) {
2926       emit_addimm(addr,ram_offset,HOST_TEMPREG);
2927       fastload_reg_override=HOST_TEMPREG;
2928     }
2929   }else{ // using tlb
2930     int x=0;
2931     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2932     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2933     map=get_reg(i_regs->regmap,TLREG);
2934     assert(map>=0);
2935     reglist&=~(1<<map);
2936     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2937     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2938   }
2939   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2940   if (opcode[i]==0x20) { // LB
2941     if(!c||memtarget) {
2942       if(!dummy) {
2943         #ifdef HOST_IMM_ADDR32
2944         if(c)
2945           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2946         else
2947         #endif
2948         {
2949           //emit_xorimm(addr,3,tl);
2950           //gen_tlb_addr_r(tl,map);
2951           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2952           int x=0,a=tl;
2953 #ifdef BIG_ENDIAN_MIPS
2954           if(!c) emit_xorimm(addr,3,tl);
2955           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2956 #else
2957           if(!c) a=addr;
2958 #endif
2959           if(fastload_reg_override) a=fastload_reg_override;
2960
2961           emit_movsbl_indexed_tlb(x,a,map,tl);
2962         }
2963       }
2964       if(jaddr)
2965         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2966     }
2967     else
2968       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2969   }
2970   if (opcode[i]==0x21) { // LH
2971     if(!c||memtarget) {
2972       if(!dummy) {
2973         #ifdef HOST_IMM_ADDR32
2974         if(c)
2975           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2976         else
2977         #endif
2978         {
2979           int x=0,a=tl;
2980 #ifdef BIG_ENDIAN_MIPS
2981           if(!c) emit_xorimm(addr,2,tl);
2982           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2983 #else
2984           if(!c) a=addr;
2985 #endif
2986           if(fastload_reg_override) a=fastload_reg_override;
2987           //#ifdef
2988           //emit_movswl_indexed_tlb(x,tl,map,tl);
2989           //else
2990           if(map>=0) {
2991             gen_tlb_addr_r(a,map);
2992             emit_movswl_indexed(x,a,tl);
2993           }else{
2994             #if 1 //def RAM_OFFSET
2995             emit_movswl_indexed(x,a,tl);
2996             #else
2997             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2998             #endif
2999           }
3000         }
3001       }
3002       if(jaddr)
3003         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3004     }
3005     else
3006       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3007   }
3008   if (opcode[i]==0x23) { // LW
3009     if(!c||memtarget) {
3010       if(!dummy) {
3011         int a=addr;
3012         if(fastload_reg_override) a=fastload_reg_override;
3013         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3014         #ifdef HOST_IMM_ADDR32
3015         if(c)
3016           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3017         else
3018         #endif
3019         emit_readword_indexed_tlb(0,a,map,tl);
3020       }
3021       if(jaddr)
3022         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3023     }
3024     else
3025       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3026   }
3027   if (opcode[i]==0x24) { // LBU
3028     if(!c||memtarget) {
3029       if(!dummy) {
3030         #ifdef HOST_IMM_ADDR32
3031         if(c)
3032           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3033         else
3034         #endif
3035         {
3036           //emit_xorimm(addr,3,tl);
3037           //gen_tlb_addr_r(tl,map);
3038           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3039           int x=0,a=tl;
3040 #ifdef BIG_ENDIAN_MIPS
3041           if(!c) emit_xorimm(addr,3,tl);
3042           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3043 #else
3044           if(!c) a=addr;
3045 #endif
3046           if(fastload_reg_override) a=fastload_reg_override;
3047
3048           emit_movzbl_indexed_tlb(x,a,map,tl);
3049         }
3050       }
3051       if(jaddr)
3052         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3053     }
3054     else
3055       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3056   }
3057   if (opcode[i]==0x25) { // LHU
3058     if(!c||memtarget) {
3059       if(!dummy) {
3060         #ifdef HOST_IMM_ADDR32
3061         if(c)
3062           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3063         else
3064         #endif
3065         {
3066           int x=0,a=tl;
3067 #ifdef BIG_ENDIAN_MIPS
3068           if(!c) emit_xorimm(addr,2,tl);
3069           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3070 #else
3071           if(!c) a=addr;
3072 #endif
3073           if(fastload_reg_override) a=fastload_reg_override;
3074           //#ifdef
3075           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3076           //#else
3077           if(map>=0) {
3078             gen_tlb_addr_r(a,map);
3079             emit_movzwl_indexed(x,a,tl);
3080           }else{
3081             #if 1 //def RAM_OFFSET
3082             emit_movzwl_indexed(x,a,tl);
3083             #else
3084             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3085             #endif
3086           }
3087         }
3088       }
3089       if(jaddr)
3090         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3091     }
3092     else
3093       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3094   }
3095   if (opcode[i]==0x27) { // LWU
3096     assert(th>=0);
3097     if(!c||memtarget) {
3098       if(!dummy) {
3099         int a=addr;
3100         if(fastload_reg_override) a=fastload_reg_override;
3101         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3102         #ifdef HOST_IMM_ADDR32
3103         if(c)
3104           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3105         else
3106         #endif
3107         emit_readword_indexed_tlb(0,a,map,tl);
3108       }
3109       if(jaddr)
3110         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3111     }
3112     else {
3113       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3114     }
3115     emit_zeroreg(th);
3116   }
3117   if (opcode[i]==0x37) { // LD
3118     if(!c||memtarget) {
3119       if(!dummy) {
3120         int a=addr;
3121         if(fastload_reg_override) a=fastload_reg_override;
3122         //gen_tlb_addr_r(tl,map);
3123         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3124         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3125         #ifdef HOST_IMM_ADDR32
3126         if(c)
3127           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3128         else
3129         #endif
3130         emit_readdword_indexed_tlb(0,a,map,th,tl);
3131       }
3132       if(jaddr)
3133         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3134     }
3135     else
3136       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3137   }
3138  }
3139   //emit_storereg(rt1[i],tl); // DEBUG
3140   //if(opcode[i]==0x23)
3141   //if(opcode[i]==0x24)
3142   //if(opcode[i]==0x23||opcode[i]==0x24)
3143   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3144   {
3145     //emit_pusha();
3146     save_regs(0x100f);
3147         emit_readword((int)&last_count,ECX);
3148         #ifdef __i386__
3149         if(get_reg(i_regs->regmap,CCREG)<0)
3150           emit_loadreg(CCREG,HOST_CCREG);
3151         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3152         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3153         emit_writeword(HOST_CCREG,(int)&Count);
3154         #endif
3155         #ifdef __arm__
3156         if(get_reg(i_regs->regmap,CCREG)<0)
3157           emit_loadreg(CCREG,0);
3158         else
3159           emit_mov(HOST_CCREG,0);
3160         emit_add(0,ECX,0);
3161         emit_addimm(0,2*ccadj[i],0);
3162         emit_writeword(0,(int)&Count);
3163         #endif
3164     emit_call((int)memdebug);
3165     //emit_popa();
3166     restore_regs(0x100f);
3167   }/**/
3168 }
3169
3170 #ifndef loadlr_assemble
3171 void loadlr_assemble(int i,struct regstat *i_regs)
3172 {
3173   printf("Need loadlr_assemble for this architecture.\n");
3174   exit(1);
3175 }
3176 #endif
3177
3178 void store_assemble(int i,struct regstat *i_regs)
3179 {
3180   int s,th,tl,map=-1;
3181   int addr,temp;
3182   int offset;
3183   int jaddr=0,jaddr2,type;
3184   int memtarget=0,c=0;
3185   int agr=AGEN1+(i&1);
3186   int faststore_reg_override=0;
3187   u_int hr,reglist=0;
3188   th=get_reg(i_regs->regmap,rs2[i]|64);
3189   tl=get_reg(i_regs->regmap,rs2[i]);
3190   s=get_reg(i_regs->regmap,rs1[i]);
3191   temp=get_reg(i_regs->regmap,agr);
3192   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3193   offset=imm[i];
3194   if(s>=0) {
3195     c=(i_regs->wasconst>>s)&1;
3196     if(c) {
3197       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3198       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3199     }
3200   }
3201   assert(tl>=0);
3202   assert(temp>=0);
3203   for(hr=0;hr<HOST_REGS;hr++) {
3204     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3205   }
3206   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3207   if(offset||s<0||c) addr=temp;
3208   else addr=s;
3209   if(!using_tlb) {
3210     if(!c) {
3211       #ifndef PCSX
3212       #ifdef R29_HACK
3213       // Strmnnrmn's speed hack
3214       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3215       #endif
3216       emit_cmpimm(addr,RAM_SIZE);
3217       #ifdef DESTRUCTIVE_SHIFT
3218       if(s==addr) emit_mov(s,temp);
3219       #endif
3220       #ifdef R29_HACK
3221       memtarget=1;
3222       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3223       #endif
3224       {
3225         jaddr=(int)out;
3226         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3227         // Hint to branch predictor that the branch is unlikely to be taken
3228         if(rs1[i]>=28)
3229           emit_jno_unlikely(0);
3230         else
3231         #endif
3232         emit_jno(0);
3233       }
3234       #else
3235         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3236       #endif
3237     }
3238     else if(ram_offset&&memtarget) {
3239       emit_addimm(addr,ram_offset,HOST_TEMPREG);
3240       faststore_reg_override=HOST_TEMPREG;
3241     }
3242   }else{ // using tlb
3243     int x=0;
3244     if (opcode[i]==0x28) x=3; // SB
3245     if (opcode[i]==0x29) x=2; // SH
3246     map=get_reg(i_regs->regmap,TLREG);
3247     assert(map>=0);
3248     reglist&=~(1<<map);
3249     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3250     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3251   }
3252
3253   if (opcode[i]==0x28) { // SB
3254     if(!c||memtarget) {
3255       int x=0,a=temp;
3256 #ifdef BIG_ENDIAN_MIPS
3257       if(!c) emit_xorimm(addr,3,temp);
3258       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3259 #else
3260       if(!c) a=addr;
3261 #endif
3262       if(faststore_reg_override) a=faststore_reg_override;
3263       //gen_tlb_addr_w(temp,map);
3264       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3265       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3266     }
3267     type=STOREB_STUB;
3268   }
3269   if (opcode[i]==0x29) { // SH
3270     if(!c||memtarget) {
3271       int x=0,a=temp;
3272 #ifdef BIG_ENDIAN_MIPS
3273       if(!c) emit_xorimm(addr,2,temp);
3274       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3275 #else
3276       if(!c) a=addr;
3277 #endif
3278       if(faststore_reg_override) a=faststore_reg_override;
3279       //#ifdef
3280       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3281       //#else
3282       if(map>=0) {
3283         gen_tlb_addr_w(a,map);
3284         emit_writehword_indexed(tl,x,a);
3285       }else
3286         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3287         emit_writehword_indexed(tl,x,a);
3288     }
3289     type=STOREH_STUB;
3290   }
3291   if (opcode[i]==0x2B) { // SW
3292     if(!c||memtarget) {
3293       int a=addr;
3294       if(faststore_reg_override) a=faststore_reg_override;
3295       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3296       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3297     }
3298     type=STOREW_STUB;
3299   }
3300   if (opcode[i]==0x3F) { // SD
3301     if(!c||memtarget) {
3302       int a=addr;
3303       if(faststore_reg_override) a=faststore_reg_override;
3304       if(rs2[i]) {
3305         assert(th>=0);
3306         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3307         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3308         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3309       }else{
3310         // Store zero
3311         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3312         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3313         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3314       }
3315     }
3316     type=STORED_STUB;
3317   }
3318 #ifdef PCSX
3319   if(jaddr) {
3320     // PCSX store handlers don't check invcode again
3321     reglist|=1<<addr;
3322     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3323     jaddr=0;
3324   }
3325 #endif
3326   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3327     if(!c||memtarget) {
3328       #ifdef DESTRUCTIVE_SHIFT
3329       // The x86 shift operation is 'destructive'; it overwrites the
3330       // source register, so we need to make a copy first and use that.
3331       addr=temp;
3332       #endif
3333       #if defined(HOST_IMM8)
3334       int ir=get_reg(i_regs->regmap,INVCP);
3335       assert(ir>=0);
3336       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3337       #else
3338       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3339       #endif
3340       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3341       emit_callne(invalidate_addr_reg[addr]);
3342       #else
3343       jaddr2=(int)out;
3344       emit_jne(0);
3345       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3346       #endif
3347     }
3348   }
3349   u_int addr_val=constmap[i][s]+offset;
3350   if(jaddr) {
3351     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3352   } else if(c&&!memtarget) {
3353     inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3354   }
3355   // basic current block modification detection..
3356   // not looking back as that should be in mips cache already
3357   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3358     printf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3359     assert(i_regs->regmap==regs[i].regmap); // not delay slot
3360     if(i_regs->regmap==regs[i].regmap) {
3361       load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3362       wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3363       emit_movimm(start+i*4+4,0);
3364       emit_writeword(0,(int)&pcaddr);
3365       emit_jmp((int)do_interrupt);
3366     }
3367   }
3368   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3369   //if(opcode[i]==0x2B || opcode[i]==0x28)
3370   //if(opcode[i]==0x2B || opcode[i]==0x29)
3371   //if(opcode[i]==0x2B)
3372   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3373   {
3374     #ifdef __i386__
3375     emit_pusha();
3376     #endif
3377     #ifdef __arm__
3378     save_regs(0x100f);
3379     #endif
3380         emit_readword((int)&last_count,ECX);
3381         #ifdef __i386__
3382         if(get_reg(i_regs->regmap,CCREG)<0)
3383           emit_loadreg(CCREG,HOST_CCREG);
3384         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3385         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3386         emit_writeword(HOST_CCREG,(int)&Count);
3387         #endif
3388         #ifdef __arm__
3389         if(get_reg(i_regs->regmap,CCREG)<0)
3390           emit_loadreg(CCREG,0);
3391         else
3392           emit_mov(HOST_CCREG,0);
3393         emit_add(0,ECX,0);
3394         emit_addimm(0,2*ccadj[i],0);
3395         emit_writeword(0,(int)&Count);
3396         #endif
3397     emit_call((int)memdebug);
3398     #ifdef __i386__
3399     emit_popa();
3400     #endif
3401     #ifdef __arm__
3402     restore_regs(0x100f);
3403     #endif
3404   }/**/
3405 }
3406
3407 void storelr_assemble(int i,struct regstat *i_regs)
3408 {
3409   int s,th,tl;
3410   int temp;
3411   int temp2;
3412   int offset;
3413   int jaddr=0,jaddr2;
3414   int case1,case2,case3;
3415   int done0,done1,done2;
3416   int memtarget=0,c=0;
3417   int agr=AGEN1+(i&1);
3418   u_int hr,reglist=0;
3419   th=get_reg(i_regs->regmap,rs2[i]|64);
3420   tl=get_reg(i_regs->regmap,rs2[i]);
3421   s=get_reg(i_regs->regmap,rs1[i]);
3422   temp=get_reg(i_regs->regmap,agr);
3423   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3424   offset=imm[i];
3425   if(s>=0) {
3426     c=(i_regs->isconst>>s)&1;
3427     if(c) {
3428       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3429       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3430     }
3431   }
3432   assert(tl>=0);
3433   for(hr=0;hr<HOST_REGS;hr++) {
3434     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3435   }
3436   assert(temp>=0);
3437   if(!using_tlb) {
3438     if(!c) {
3439       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3440       if(!offset&&s!=temp) emit_mov(s,temp);
3441       jaddr=(int)out;
3442       emit_jno(0);
3443     }
3444     else
3445     {
3446       if(!memtarget||!rs1[i]) {
3447         jaddr=(int)out;
3448         emit_jmp(0);
3449       }
3450     }
3451     #ifdef RAM_OFFSET
3452     int map=get_reg(i_regs->regmap,ROREG);
3453     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3454     gen_tlb_addr_w(temp,map);
3455     #else
3456     if((u_int)rdram!=0x80000000) 
3457       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3458     #endif
3459   }else{ // using tlb
3460     int map=get_reg(i_regs->regmap,TLREG);
3461     assert(map>=0);
3462     reglist&=~(1<<map);
3463     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3464     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3465     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3466     if(!jaddr&&!memtarget) {
3467       jaddr=(int)out;
3468       emit_jmp(0);
3469     }
3470     gen_tlb_addr_w(temp,map);
3471   }
3472
3473   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3474     temp2=get_reg(i_regs->regmap,FTEMP);
3475     if(!rs2[i]) temp2=th=tl;
3476   }
3477
3478 #ifndef BIG_ENDIAN_MIPS
3479     emit_xorimm(temp,3,temp);
3480 #endif
3481   emit_testimm(temp,2);
3482   case2=(int)out;
3483   emit_jne(0);
3484   emit_testimm(temp,1);
3485   case1=(int)out;
3486   emit_jne(0);
3487   // 0
3488   if (opcode[i]==0x2A) { // SWL
3489     emit_writeword_indexed(tl,0,temp);
3490   }
3491   if (opcode[i]==0x2E) { // SWR
3492     emit_writebyte_indexed(tl,3,temp);
3493   }
3494   if (opcode[i]==0x2C) { // SDL
3495     emit_writeword_indexed(th,0,temp);
3496     if(rs2[i]) emit_mov(tl,temp2);
3497   }
3498   if (opcode[i]==0x2D) { // SDR
3499     emit_writebyte_indexed(tl,3,temp);
3500     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3501   }
3502   done0=(int)out;
3503   emit_jmp(0);
3504   // 1
3505   set_jump_target(case1,(int)out);
3506   if (opcode[i]==0x2A) { // SWL
3507     // Write 3 msb into three least significant bytes
3508     if(rs2[i]) emit_rorimm(tl,8,tl);
3509     emit_writehword_indexed(tl,-1,temp);
3510     if(rs2[i]) emit_rorimm(tl,16,tl);
3511     emit_writebyte_indexed(tl,1,temp);
3512     if(rs2[i]) emit_rorimm(tl,8,tl);
3513   }
3514   if (opcode[i]==0x2E) { // SWR
3515     // Write two lsb into two most significant bytes
3516     emit_writehword_indexed(tl,1,temp);
3517   }
3518   if (opcode[i]==0x2C) { // SDL
3519     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3520     // Write 3 msb into three least significant bytes
3521     if(rs2[i]) emit_rorimm(th,8,th);
3522     emit_writehword_indexed(th,-1,temp);
3523     if(rs2[i]) emit_rorimm(th,16,th);
3524     emit_writebyte_indexed(th,1,temp);
3525     if(rs2[i]) emit_rorimm(th,8,th);
3526   }
3527   if (opcode[i]==0x2D) { // SDR
3528     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3529     // Write two lsb into two most significant bytes
3530     emit_writehword_indexed(tl,1,temp);
3531   }
3532   done1=(int)out;
3533   emit_jmp(0);
3534   // 2
3535   set_jump_target(case2,(int)out);
3536   emit_testimm(temp,1);
3537   case3=(int)out;
3538   emit_jne(0);
3539   if (opcode[i]==0x2A) { // SWL
3540     // Write two msb into two least significant bytes
3541     if(rs2[i]) emit_rorimm(tl,16,tl);
3542     emit_writehword_indexed(tl,-2,temp);
3543     if(rs2[i]) emit_rorimm(tl,16,tl);
3544   }
3545   if (opcode[i]==0x2E) { // SWR
3546     // Write 3 lsb into three most significant bytes
3547     emit_writebyte_indexed(tl,-1,temp);
3548     if(rs2[i]) emit_rorimm(tl,8,tl);
3549     emit_writehword_indexed(tl,0,temp);
3550     if(rs2[i]) emit_rorimm(tl,24,tl);
3551   }
3552   if (opcode[i]==0x2C) { // SDL
3553     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3554     // Write two msb into two least significant bytes
3555     if(rs2[i]) emit_rorimm(th,16,th);
3556     emit_writehword_indexed(th,-2,temp);
3557     if(rs2[i]) emit_rorimm(th,16,th);
3558   }
3559   if (opcode[i]==0x2D) { // SDR
3560     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3561     // Write 3 lsb into three most significant bytes
3562     emit_writebyte_indexed(tl,-1,temp);
3563     if(rs2[i]) emit_rorimm(tl,8,tl);
3564     emit_writehword_indexed(tl,0,temp);
3565     if(rs2[i]) emit_rorimm(tl,24,tl);
3566   }
3567   done2=(int)out;
3568   emit_jmp(0);
3569   // 3
3570   set_jump_target(case3,(int)out);
3571   if (opcode[i]==0x2A) { // SWL
3572     // Write msb into least significant byte
3573     if(rs2[i]) emit_rorimm(tl,24,tl);
3574     emit_writebyte_indexed(tl,-3,temp);
3575     if(rs2[i]) emit_rorimm(tl,8,tl);
3576   }
3577   if (opcode[i]==0x2E) { // SWR
3578     // Write entire word
3579     emit_writeword_indexed(tl,-3,temp);
3580   }
3581   if (opcode[i]==0x2C) { // SDL
3582     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3583     // Write msb into least significant byte
3584     if(rs2[i]) emit_rorimm(th,24,th);
3585     emit_writebyte_indexed(th,-3,temp);
3586     if(rs2[i]) emit_rorimm(th,8,th);
3587   }
3588   if (opcode[i]==0x2D) { // SDR
3589     if(rs2[i]) emit_mov(th,temp2);
3590     // Write entire word
3591     emit_writeword_indexed(tl,-3,temp);
3592   }
3593   set_jump_target(done0,(int)out);
3594   set_jump_target(done1,(int)out);
3595   set_jump_target(done2,(int)out);
3596   if (opcode[i]==0x2C) { // SDL
3597     emit_testimm(temp,4);
3598     done0=(int)out;
3599     emit_jne(0);
3600     emit_andimm(temp,~3,temp);
3601     emit_writeword_indexed(temp2,4,temp);
3602     set_jump_target(done0,(int)out);
3603   }
3604   if (opcode[i]==0x2D) { // SDR
3605     emit_testimm(temp,4);
3606     done0=(int)out;
3607     emit_jeq(0);
3608     emit_andimm(temp,~3,temp);
3609     emit_writeword_indexed(temp2,-4,temp);
3610     set_jump_target(done0,(int)out);
3611   }
3612   if(!c||!memtarget)
3613     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3614   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3615     #ifdef RAM_OFFSET
3616     int map=get_reg(i_regs->regmap,ROREG);
3617     if(map<0) map=HOST_TEMPREG;
3618     gen_orig_addr_w(temp,map);
3619     #else
3620     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3621     #endif
3622     #if defined(HOST_IMM8)
3623     int ir=get_reg(i_regs->regmap,INVCP);
3624     assert(ir>=0);
3625     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3626     #else
3627     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3628     #endif
3629     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3630     emit_callne(invalidate_addr_reg[temp]);
3631     #else
3632     jaddr2=(int)out;
3633     emit_jne(0);
3634     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3635     #endif
3636   }
3637   /*
3638     emit_pusha();
3639     //save_regs(0x100f);
3640         emit_readword((int)&last_count,ECX);
3641         if(get_reg(i_regs->regmap,CCREG)<0)
3642           emit_loadreg(CCREG,HOST_CCREG);
3643         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3644         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3645         emit_writeword(HOST_CCREG,(int)&Count);
3646     emit_call((int)memdebug);
3647     emit_popa();
3648     //restore_regs(0x100f);
3649   /**/
3650 }
3651
3652 void c1ls_assemble(int i,struct regstat *i_regs)
3653 {
3654 #ifndef DISABLE_COP1
3655   int s,th,tl;
3656   int temp,ar;
3657   int map=-1;
3658   int offset;
3659   int c=0;
3660   int jaddr,jaddr2=0,jaddr3,type;
3661   int agr=AGEN1+(i&1);
3662   u_int hr,reglist=0;
3663   th=get_reg(i_regs->regmap,FTEMP|64);
3664   tl=get_reg(i_regs->regmap,FTEMP);
3665   s=get_reg(i_regs->regmap,rs1[i]);
3666   temp=get_reg(i_regs->regmap,agr);
3667   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3668   offset=imm[i];
3669   assert(tl>=0);
3670   assert(rs1[i]>0);
3671   assert(temp>=0);
3672   for(hr=0;hr<HOST_REGS;hr++) {
3673     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3674   }
3675   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3676   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3677   {
3678     // Loads use a temporary register which we need to save
3679     reglist|=1<<temp;
3680   }
3681   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3682     ar=temp;
3683   else // LWC1/LDC1
3684     ar=tl;
3685   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3686   //else c=(i_regs->wasconst>>s)&1;
3687   if(s>=0) c=(i_regs->wasconst>>s)&1;
3688   // Check cop1 unusable
3689   if(!cop1_usable) {
3690     signed char rs=get_reg(i_regs->regmap,CSREG);
3691     assert(rs>=0);
3692     emit_testimm(rs,0x20000000);
3693     jaddr=(int)out;
3694     emit_jeq(0);
3695     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3696     cop1_usable=1;
3697   }
3698   if (opcode[i]==0x39) { // SWC1 (get float address)
3699     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3700   }
3701   if (opcode[i]==0x3D) { // SDC1 (get double address)
3702     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3703   }
3704   // Generate address + offset
3705   if(!using_tlb) {
3706     if(!c)
3707       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3708   }
3709   else
3710   {
3711     map=get_reg(i_regs->regmap,TLREG);
3712     assert(map>=0);
3713     reglist&=~(1<<map);
3714     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3715       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3716     }
3717     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3718       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3719     }
3720   }
3721   if (opcode[i]==0x39) { // SWC1 (read float)
3722     emit_readword_indexed(0,tl,tl);
3723   }
3724   if (opcode[i]==0x3D) { // SDC1 (read double)
3725     emit_readword_indexed(4,tl,th);
3726     emit_readword_indexed(0,tl,tl);
3727   }
3728   if (opcode[i]==0x31) { // LWC1 (get target address)
3729     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3730   }
3731   if (opcode[i]==0x35) { // LDC1 (get target address)
3732     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3733   }
3734   if(!using_tlb) {
3735     if(!c) {
3736       jaddr2=(int)out;
3737       emit_jno(0);
3738     }
3739     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3740       jaddr2=(int)out;
3741       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3742     }
3743     #ifdef DESTRUCTIVE_SHIFT
3744     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3745       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3746     }
3747     #endif
3748   }else{
3749     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3750       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3751     }
3752     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3753       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3754     }
3755   }
3756   if (opcode[i]==0x31) { // LWC1
3757     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3758     //gen_tlb_addr_r(ar,map);
3759     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3760     #ifdef HOST_IMM_ADDR32
3761     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3762     else
3763     #endif
3764     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3765     type=LOADW_STUB;
3766   }
3767   if (opcode[i]==0x35) { // LDC1
3768     assert(th>=0);
3769     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3770     //gen_tlb_addr_r(ar,map);
3771     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3772     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3773     #ifdef HOST_IMM_ADDR32
3774     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3775     else
3776     #endif
3777     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3778     type=LOADD_STUB;
3779   }
3780   if (opcode[i]==0x39) { // SWC1
3781     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3782     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3783     type=STOREW_STUB;
3784   }
3785   if (opcode[i]==0x3D) { // SDC1
3786     assert(th>=0);
3787     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3788     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3789     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3790     type=STORED_STUB;
3791   }
3792   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3793     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3794       #ifndef DESTRUCTIVE_SHIFT
3795       temp=offset||c||s<0?ar:s;
3796       #endif
3797       #if defined(HOST_IMM8)
3798       int ir=get_reg(i_regs->regmap,INVCP);
3799       assert(ir>=0);
3800       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3801       #else
3802       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3803       #endif
3804       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3805       emit_callne(invalidate_addr_reg[temp]);
3806       #else
3807       jaddr3=(int)out;
3808       emit_jne(0);
3809       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3810       #endif
3811     }
3812   }
3813   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3814   if (opcode[i]==0x31) { // LWC1 (write float)
3815     emit_writeword_indexed(tl,0,temp);
3816   }
3817   if (opcode[i]==0x35) { // LDC1 (write double)
3818     emit_writeword_indexed(th,4,temp);
3819     emit_writeword_indexed(tl,0,temp);
3820   }
3821   //if(opcode[i]==0x39)
3822   /*if(opcode[i]==0x39||opcode[i]==0x31)
3823   {
3824     emit_pusha();
3825         emit_readword((int)&last_count,ECX);
3826         if(get_reg(i_regs->regmap,CCREG)<0)
3827           emit_loadreg(CCREG,HOST_CCREG);
3828         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3829         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3830         emit_writeword(HOST_CCREG,(int)&Count);
3831     emit_call((int)memdebug);
3832     emit_popa();
3833   }/**/
3834 #else
3835   cop1_unusable(i, i_regs);
3836 #endif
3837 }
3838
3839 void c2ls_assemble(int i,struct regstat *i_regs)
3840 {
3841   int s,tl;
3842   int ar;
3843   int offset;
3844   int memtarget=0,c=0;
3845   int jaddr2=0,jaddr3,type;
3846   int agr=AGEN1+(i&1);
3847   int fastio_reg_override=0;
3848   u_int hr,reglist=0;
3849   u_int copr=(source[i]>>16)&0x1f;
3850   s=get_reg(i_regs->regmap,rs1[i]);
3851   tl=get_reg(i_regs->regmap,FTEMP);
3852   offset=imm[i];
3853   assert(rs1[i]>0);
3854   assert(tl>=0);
3855   assert(!using_tlb);
3856
3857   for(hr=0;hr<HOST_REGS;hr++) {
3858     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3859   }
3860   if(i_regs->regmap[HOST_CCREG]==CCREG)
3861     reglist&=~(1<<HOST_CCREG);
3862
3863   // get the address
3864   if (opcode[i]==0x3a) { // SWC2
3865     ar=get_reg(i_regs->regmap,agr);
3866     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3867     reglist|=1<<ar;
3868   } else { // LWC2
3869     ar=tl;
3870   }
3871   if(s>=0) c=(i_regs->wasconst>>s)&1;
3872   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3873   if (!offset&&!c&&s>=0) ar=s;
3874   assert(ar>=0);
3875
3876   if (opcode[i]==0x3a) { // SWC2
3877     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3878     type=STOREW_STUB;
3879   }
3880   else
3881     type=LOADW_STUB;
3882
3883   if(c&&!memtarget) {
3884     jaddr2=(int)out;
3885     emit_jmp(0); // inline_readstub/inline_writestub?
3886   }
3887   else {
3888     if(!c) {
3889       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3890     }
3891     else if(ram_offset&&memtarget) {
3892       emit_addimm(ar,ram_offset,HOST_TEMPREG);
3893       fastio_reg_override=HOST_TEMPREG;
3894     }
3895     if (opcode[i]==0x32) { // LWC2
3896       #ifdef HOST_IMM_ADDR32
3897       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3898       else
3899       #endif
3900       int a=ar;
3901       if(fastio_reg_override) a=fastio_reg_override;
3902       emit_readword_indexed(0,a,tl);
3903     }
3904     if (opcode[i]==0x3a) { // SWC2
3905       #ifdef DESTRUCTIVE_SHIFT
3906       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3907       #endif
3908       int a=ar;
3909       if(fastio_reg_override) a=fastio_reg_override;
3910       emit_writeword_indexed(tl,0,a);
3911     }
3912   }
3913   if(jaddr2)
3914     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3915   if(opcode[i]==0x3a) // SWC2
3916   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3917 #if defined(HOST_IMM8)
3918     int ir=get_reg(i_regs->regmap,INVCP);
3919     assert(ir>=0);
3920     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3921 #else
3922     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3923 #endif
3924     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3925     emit_callne(invalidate_addr_reg[ar]);
3926     #else
3927     jaddr3=(int)out;
3928     emit_jne(0);
3929     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3930     #endif
3931   }
3932   if (opcode[i]==0x32) { // LWC2
3933     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3934   }
3935 }
3936
3937 #ifndef multdiv_assemble
3938 void multdiv_assemble(int i,struct regstat *i_regs)
3939 {
3940   printf("Need multdiv_assemble for this architecture.\n");
3941   exit(1);
3942 }
3943 #endif
3944
3945 void mov_assemble(int i,struct regstat *i_regs)
3946 {
3947   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3948   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3949   if(rt1[i]) {
3950     signed char sh,sl,th,tl;
3951     th=get_reg(i_regs->regmap,rt1[i]|64);
3952     tl=get_reg(i_regs->regmap,rt1[i]);
3953     //assert(tl>=0);
3954     if(tl>=0) {
3955       sh=get_reg(i_regs->regmap,rs1[i]|64);
3956       sl=get_reg(i_regs->regmap,rs1[i]);
3957       if(sl>=0) emit_mov(sl,tl);
3958       else emit_loadreg(rs1[i],tl);
3959       if(th>=0) {
3960         if(sh>=0) emit_mov(sh,th);
3961         else emit_loadreg(rs1[i]|64,th);
3962       }