libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <sys/mman.h>
  25
  26 #include "emu_if.h" //emulator interface
  27
  28 //#define DISASM
  29 //#define assem_debug printf
  30 //#define inv_debug printf
  31 #define assem_debug(...)
  32 #define inv_debug(...)
  33
  34 #ifdef __i386__
  35 #include "assem_x86.h"
  36 #endif
  37 #ifdef __x86_64__
  38 #include "assem_x64.h"
  39 #endif
  40 #ifdef __arm__
  41 #include "assem_arm.h"
  42 #endif
  43
  44 #define MAXBLOCK 4096
  45 #define MAX_OUTPUT_BLOCK_SIZE 262144
  46
  47 int cycle_multiplier; // 100 for 1.0
  48 #define CLOCK_ADJUST(x) (((x) * cycle_multiplier + 50) / 100)
  49
  50 struct regstat
  51 {
  52   signed char regmap_entry[HOST_REGS];
  53   signed char regmap[HOST_REGS];
  54   uint64_t was32;
  55   uint64_t is32;
  56   uint64_t wasdirty;
  57   uint64_t dirty;
  58   uint64_t u;
  59   uint64_t uu;
  60   u_int wasconst;
  61   u_int isconst;
  62   u_int loadedconst;             // host regs that have constants loaded
  63   u_int waswritten;              // MIPS regs that were used as store base before
  64   uint64_t constmap[HOST_REGS];
  65 };
  66
  67 struct ll_entry
  68 {
  69   u_int vaddr;
  70   u_int reg32;
  71   void *addr;
  72   struct ll_entry *next;
  73 };
  74
  75   u_int start;
  76   u_int *source;
  77   u_int pagelimit;
  78   char insn[MAXBLOCK][10];
  79   u_char itype[MAXBLOCK];
  80   u_char opcode[MAXBLOCK];
  81   u_char opcode2[MAXBLOCK];
  82   u_char bt[MAXBLOCK];
  83   u_char rs1[MAXBLOCK];
  84   u_char rs2[MAXBLOCK];
  85   u_char rt1[MAXBLOCK];
  86   u_char rt2[MAXBLOCK];
  87   u_char us1[MAXBLOCK];
  88   u_char us2[MAXBLOCK];
  89   u_char dep1[MAXBLOCK];
  90   u_char dep2[MAXBLOCK];
  91   u_char lt1[MAXBLOCK];
  92   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
  93   static uint64_t gte_rt[MAXBLOCK];
  94   static uint64_t gte_unneeded[MAXBLOCK];
  95   static u_int smrv[32]; // speculated MIPS register values
  96   static u_int smrv_strong; // mask or regs that are likely to have correct values
  97   static u_int smrv_weak; // same, but somewhat less likely
  98   static u_int smrv_strong_next; // same, but after current insn executes
  99   static u_int smrv_weak_next;
 100   int imm[MAXBLOCK];
 101   u_int ba[MAXBLOCK];
 102   char likely[MAXBLOCK];
 103   char is_ds[MAXBLOCK];
 104   char ooo[MAXBLOCK];
 105   uint64_t unneeded_reg[MAXBLOCK];
 106   uint64_t unneeded_reg_upper[MAXBLOCK];
 107   uint64_t branch_unneeded_reg[MAXBLOCK];
 108   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 109   uint64_t p32[MAXBLOCK];
 110   uint64_t pr32[MAXBLOCK];
 111   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 112   signed char regmap[MAXBLOCK][HOST_REGS];
 113   signed char regmap_entry[MAXBLOCK][HOST_REGS];
 114   uint64_t constmap[MAXBLOCK][HOST_REGS];
 115   struct regstat regs[MAXBLOCK];
 116   struct regstat branch_regs[MAXBLOCK];
 117   signed char minimum_free_regs[MAXBLOCK];
 118   u_int needed_reg[MAXBLOCK];
 119   uint64_t requires_32bit[MAXBLOCK];
 120   u_int wont_dirty[MAXBLOCK];
 121   u_int will_dirty[MAXBLOCK];
 122   int ccadj[MAXBLOCK];
 123   int slen;
 124   u_int instr_addr[MAXBLOCK];
 125   u_int link_addr[MAXBLOCK][3];
 126   int linkcount;
 127   u_int stubs[MAXBLOCK*3][8];
 128   int stubcount;
 129   u_int literals[1024][2];
 130   int literalcount;
 131   int is_delayslot;
 132   int cop1_usable;
 133   u_char *out;
 134   struct ll_entry *jump_in[4096];
 135   struct ll_entry *jump_out[4096];
 136   struct ll_entry *jump_dirty[4096];
 137   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 138   char shadow[1048576]  __attribute__((aligned(16)));
 139   void *copy;
 140   int expirep;
 141 #ifndef PCSX
 142   u_int using_tlb;
 143 #else
 144   static const u_int using_tlb=0;
 145 #endif
 146   int new_dynarec_did_compile;
 147   int new_dynarec_hacks;
 148   u_int stop_after_jal;
 149   extern u_char restore_candidate[512];
 150   extern int cycle_count;
 151
 152   /* registers that may be allocated */
 153   /* 1-31 gpr */
 154 #define HIREG 32 // hi
 155 #define LOREG 33 // lo
 156 #define FSREG 34 // FPU status (FCSR)
 157 #define CSREG 35 // Coprocessor status
 158 #define CCREG 36 // Cycle count
 159 #define INVCP 37 // Pointer to invalid_code
 160 #define MMREG 38 // Pointer to memory_map
 161 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 162 #define TEMPREG 40
 163 #define FTEMP 40 // FPU temporary register
 164 #define PTEMP 41 // Prefetch temporary register
 165 #define TLREG 42 // TLB mapping offset
 166 #define RHASH 43 // Return address hash
 167 #define RHTBL 44 // Return address hash table address
 168 #define RTEMP 45 // JR/JALR address register
 169 #define MAXREG 45
 170 #define AGEN1 46 // Address generation temporary register
 171 #define AGEN2 47 // Address generation temporary register
 172 #define MGEN1 48 // Maptable address generation temporary register
 173 #define MGEN2 49 // Maptable address generation temporary register
 174 #define BTREG 50 // Branch target temporary register
 175
 176   /* instruction types */
 177 #define NOP 0     // No operation
 178 #define LOAD 1    // Load
 179 #define STORE 2   // Store
 180 #define LOADLR 3  // Unaligned load
 181 #define STORELR 4 // Unaligned store
 182 #define MOV 5     // Move
 183 #define ALU 6     // Arithmetic/logic
 184 #define MULTDIV 7 // Multiply/divide
 185 #define SHIFT 8   // Shift by register
 186 #define SHIFTIMM 9// Shift by immediate
 187 #define IMM16 10  // 16-bit immediate
 188 #define RJUMP 11  // Unconditional jump to register
 189 #define UJUMP 12  // Unconditional jump
 190 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 191 #define SJUMP 14  // Conditional branch (regimm format)
 192 #define COP0 15   // Coprocessor 0
 193 #define COP1 16   // Coprocessor 1
 194 #define C1LS 17   // Coprocessor 1 load/store
 195 #define FJUMP 18  // Conditional branch (floating point)
 196 #define FLOAT 19  // Floating point unit
 197 #define FCONV 20  // Convert integer to float
 198 #define FCOMP 21  // Floating point compare (sets FSREG)
 199 #define SYSCALL 22// SYSCALL
 200 #define OTHER 23  // Other
 201 #define SPAN 24   // Branch/delay slot spans 2 pages
 202 #define NI 25     // Not implemented
 203 #define HLECALL 26// PCSX fake opcodes for HLE
 204 #define COP2 27   // Coprocessor 2 move
 205 #define C2LS 28   // Coprocessor 2 load/store
 206 #define C2OP 29   // Coprocessor 2 operation
 207 #define INTCALL 30// Call interpreter to handle rare corner cases
 208
 209   /* stubs */
 210 #define CC_STUB 1
 211 #define FP_STUB 2
 212 #define LOADB_STUB 3
 213 #define LOADH_STUB 4
 214 #define LOADW_STUB 5
 215 #define LOADD_STUB 6
 216 #define LOADBU_STUB 7
 217 #define LOADHU_STUB 8
 218 #define STOREB_STUB 9
 219 #define STOREH_STUB 10
 220 #define STOREW_STUB 11
 221 #define STORED_STUB 12
 222 #define STORELR_STUB 13
 223 #define INVCODE_STUB 14
 224
 225   /* branch codes */
 226 #define TAKEN 1
 227 #define NOTTAKEN 2
 228 #define NULLDS 3
 229
 230 // asm linkage
 231 int new_recompile_block(int addr);
 232 void *get_addr_ht(u_int vaddr);
 233 void invalidate_block(u_int block);
 234 void invalidate_addr(u_int addr);
 235 void remove_hash(int vaddr);
 236 void jump_vaddr();
 237 void dyna_linker();
 238 void dyna_linker_ds();
 239 void verify_code();
 240 void verify_code_vm();
 241 void verify_code_ds();
 242 void cc_interrupt();
 243 void fp_exception();
 244 void fp_exception_ds();
 245 void jump_syscall();
 246 void jump_syscall_hle();
 247 void jump_eret();
 248 void jump_hlecall();
 249 void jump_intcall();
 250 void new_dyna_leave();
 251
 252 // TLB
 253 void TLBWI_new();
 254 void TLBWR_new();
 255 void read_nomem_new();
 256 void read_nomemb_new();
 257 void read_nomemh_new();
 258 void read_nomemd_new();
 259 void write_nomem_new();
 260 void write_nomemb_new();
 261 void write_nomemh_new();
 262 void write_nomemd_new();
 263 void write_rdram_new();
 264 void write_rdramb_new();
 265 void write_rdramh_new();
 266 void write_rdramd_new();
 267 extern u_int memory_map[1048576];
 268
 269 // Needed by assembler
 270 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 271 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 272 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 273 void load_all_regs(signed char i_regmap[]);
 274 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 275 void load_regs_entry(int t);
 276 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 277
 278 int tracedebug=0;
 279
 280 //#define DEBUG_CYCLE_COUNT 1
 281
 282 static void tlb_hacks()
 283 {
 284 #ifndef DISABLE_TLB
 285   // Goldeneye hack
 286   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 287   {
 288     u_int addr;
 289     int n;
 290     switch (ROM_HEADER->Country_code&0xFF)
 291     {
 292       case 0x45: // U
 293         addr=0x34b30;
 294         break;
 295       case 0x4A: // J
 296         addr=0x34b70;
 297         break;
 298       case 0x50: // E
 299         addr=0x329f0;
 300         break;
 301       default:
 302         // Unknown country code
 303         addr=0;
 304         break;
 305     }
 306     u_int rom_addr=(u_int)rom;
 307     #ifdef ROM_COPY
 308     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 309     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 310     if((void *)rom>(void *)0xffffffff) {
 311       munmap(ROM_COPY, 67108864);
 312       if(mmap(ROM_COPY, 12582912,
 313               PROT_READ | PROT_WRITE,
 314               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 315               -1, 0) <= 0) {printf("mmap() failed\n");}
 316       memcpy(ROM_COPY,rom,12582912);
 317       rom_addr=(u_int)ROM_COPY;
 318     }
 319     #endif
 320     if(addr) {
 321       for(n=0x7F000;n<0x80000;n++) {
 322         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 323       }
 324     }
 325   }
 326 #endif
 327 }
 328
 329 static u_int get_page(u_int vaddr)
 330 {
 331 #ifndef PCSX
 332   u_int page=(vaddr^0x80000000)>>12;
 333 #else
 334   u_int page=vaddr&~0xe0000000;
 335   if (page < 0x1000000)
 336     page &= ~0x0e00000; // RAM mirrors
 337   page>>=12;
 338 #endif
 339 #ifndef DISABLE_TLB
 340   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 341 #endif
 342   if(page>2048) page=2048+(page&2047);
 343   return page;
 344 }
 345
 346 static u_int get_vpage(u_int vaddr)
 347 {
 348   u_int vpage=(vaddr^0x80000000)>>12;
 349 #ifndef DISABLE_TLB
 350   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 351 #endif
 352   if(vpage>2048) vpage=2048+(vpage&2047);
 353   return vpage;
 354 }
 355
 356 // Get address from virtual address
 357 // This is called from the recompiled JR/JALR instructions
 358 void *get_addr(u_int vaddr)
 359 {
 360   u_int page=get_page(vaddr);
 361   u_int vpage=get_vpage(vaddr);
 362   struct ll_entry *head;
 363   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 364   head=jump_in[page];
 365   while(head!=NULL) {
 366     if(head->vaddr==vaddr&&head->reg32==0) {
 367   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 368       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 369       ht_bin[3]=ht_bin[1];
 370       ht_bin[2]=ht_bin[0];
 371       ht_bin[1]=(int)head->addr;
 372       ht_bin[0]=vaddr;
 373       return head->addr;
 374     }
 375     head=head->next;
 376   }
 377   head=jump_dirty[vpage];
 378   while(head!=NULL) {
 379     if(head->vaddr==vaddr&&head->reg32==0) {
 380       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 381       // Don't restore blocks which are about to expire from the cache
 382       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 383       if(verify_dirty(head->addr)) {
 384         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 385         invalid_code[vaddr>>12]=0;
 386         inv_code_start=inv_code_end=~0;
 387 #ifndef DISABLE_TLB
 388         memory_map[vaddr>>12]|=0x40000000;
 389 #endif
 390         if(vpage<2048) {
 391 #ifndef DISABLE_TLB
 392           if(tlb_LUT_r[vaddr>>12]) {
 393             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 394             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 395           }
 396 #endif
 397           restore_candidate[vpage>>3]|=1<<(vpage&7);
 398         }
 399         else restore_candidate[page>>3]|=1<<(page&7);
 400         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 401         if(ht_bin[0]==vaddr) {
 402           ht_bin[1]=(int)head->addr; // Replace existing entry
 403         }
 404         else
 405         {
 406           ht_bin[3]=ht_bin[1];
 407           ht_bin[2]=ht_bin[0];
 408           ht_bin[1]=(int)head->addr;
 409           ht_bin[0]=vaddr;
 410         }
 411         return head->addr;
 412       }
 413     }
 414     head=head->next;
 415   }
 416   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 417   int r=new_recompile_block(vaddr);
 418   if(r==0) return get_addr(vaddr);
 419   // Execute in unmapped page, generate pagefault execption
 420   Status|=2;
 421   Cause=(vaddr<<31)|0x8;
 422   EPC=(vaddr&1)?vaddr-5:vaddr;
 423   BadVAddr=(vaddr&~1);
 424   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 425   EntryHi=BadVAddr&0xFFFFE000;
 426   return get_addr_ht(0x80000000);
 427 }
 428 // Look up address in hash table first
 429 void *get_addr_ht(u_int vaddr)
 430 {
 431   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 432   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 433   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 434   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 435   return get_addr(vaddr);
 436 }
 437
 438 void *get_addr_32(u_int vaddr,u_int flags)
 439 {
 440 #ifdef FORCE32
 441   return get_addr(vaddr);
 442 #else
 443   //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 444   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 445   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 446   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 447   u_int page=get_page(vaddr);
 448   u_int vpage=get_vpage(vaddr);
 449   struct ll_entry *head;
 450   head=jump_in[page];
 451   while(head!=NULL) {
 452     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 453       //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 454       if(head->reg32==0) {
 455         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 456         if(ht_bin[0]==-1) {
 457           ht_bin[1]=(int)head->addr;
 458           ht_bin[0]=vaddr;
 459         }else if(ht_bin[2]==-1) {
 460           ht_bin[3]=(int)head->addr;
 461           ht_bin[2]=vaddr;
 462         }
 463         //ht_bin[3]=ht_bin[1];
 464         //ht_bin[2]=ht_bin[0];
 465         //ht_bin[1]=(int)head->addr;
 466         //ht_bin[0]=vaddr;
 467       }
 468       return head->addr;
 469     }
 470     head=head->next;
 471   }
 472   head=jump_dirty[vpage];
 473   while(head!=NULL) {
 474     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 475       //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 476       // Don't restore blocks which are about to expire from the cache
 477       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 478       if(verify_dirty(head->addr)) {
 479         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 480         invalid_code[vaddr>>12]=0;
 481         inv_code_start=inv_code_end=~0;
 482         memory_map[vaddr>>12]|=0x40000000;
 483         if(vpage<2048) {
 484 #ifndef DISABLE_TLB
 485           if(tlb_LUT_r[vaddr>>12]) {
 486             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 487             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 488           }
 489 #endif
 490           restore_candidate[vpage>>3]|=1<<(vpage&7);
 491         }
 492         else restore_candidate[page>>3]|=1<<(page&7);
 493         if(head->reg32==0) {
 494           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 495           if(ht_bin[0]==-1) {
 496             ht_bin[1]=(int)head->addr;
 497             ht_bin[0]=vaddr;
 498           }else if(ht_bin[2]==-1) {
 499             ht_bin[3]=(int)head->addr;
 500             ht_bin[2]=vaddr;
 501           }
 502           //ht_bin[3]=ht_bin[1];
 503           //ht_bin[2]=ht_bin[0];
 504           //ht_bin[1]=(int)head->addr;
 505           //ht_bin[0]=vaddr;
 506         }
 507         return head->addr;
 508       }
 509     }
 510     head=head->next;
 511   }
 512   //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
 513   int r=new_recompile_block(vaddr);
 514   if(r==0) return get_addr(vaddr);
 515   // Execute in unmapped page, generate pagefault execption
 516   Status|=2;
 517   Cause=(vaddr<<31)|0x8;
 518   EPC=(vaddr&1)?vaddr-5:vaddr;
 519   BadVAddr=(vaddr&~1);
 520   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 521   EntryHi=BadVAddr&0xFFFFE000;
 522   return get_addr_ht(0x80000000);
 523 #endif
 524 }
 525
 526 void clear_all_regs(signed char regmap[])
 527 {
 528   int hr;
 529   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 530 }
 531
 532 signed char get_reg(signed char regmap[],int r)
 533 {
 534   int hr;
 535   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 536   return -1;
 537 }
 538
 539 // Find a register that is available for two consecutive cycles
 540 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 541 {
 542   int hr;
 543   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 544   return -1;
 545 }
 546
 547 int count_free_regs(signed char regmap[])
 548 {
 549   int count=0;
 550   int hr;
 551   for(hr=0;hr<HOST_REGS;hr++)
 552   {
 553     if(hr!=EXCLUDE_REG) {
 554       if(regmap[hr]<0) count++;
 555     }
 556   }
 557   return count;
 558 }
 559
 560 void dirty_reg(struct regstat *cur,signed char reg)
 561 {
 562   int hr;
 563   if(!reg) return;
 564   for (hr=0;hr<HOST_REGS;hr++) {
 565     if((cur->regmap[hr]&63)==reg) {
 566       cur->dirty|=1<<hr;
 567     }
 568   }
 569 }
 570
 571 // If we dirty the lower half of a 64 bit register which is now being
 572 // sign-extended, we need to dump the upper half.
 573 // Note: Do this only after completion of the instruction, because
 574 // some instructions may need to read the full 64-bit value even if
 575 // overwriting it (eg SLTI, DSRA32).
 576 static void flush_dirty_uppers(struct regstat *cur)
 577 {
 578   int hr,reg;
 579   for (hr=0;hr<HOST_REGS;hr++) {
 580     if((cur->dirty>>hr)&1) {
 581       reg=cur->regmap[hr];
 582       if(reg>=64)
 583         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 584     }
 585   }
 586 }
 587
 588 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 589 {
 590   int hr;
 591   if(!reg) return;
 592   for (hr=0;hr<HOST_REGS;hr++) {
 593     if(cur->regmap[hr]==reg) {
 594       cur->isconst|=1<<hr;
 595       cur->constmap[hr]=value;
 596     }
 597     else if((cur->regmap[hr]^64)==reg) {
 598       cur->isconst|=1<<hr;
 599       cur->constmap[hr]=value>>32;
 600     }
 601   }
 602 }
 603
 604 void clear_const(struct regstat *cur,signed char reg)
 605 {
 606   int hr;
 607   if(!reg) return;
 608   for (hr=0;hr<HOST_REGS;hr++) {
 609     if((cur->regmap[hr]&63)==reg) {
 610       cur->isconst&=~(1<<hr);
 611     }
 612   }
 613 }
 614
 615 int is_const(struct regstat *cur,signed char reg)
 616 {
 617   int hr;
 618   if(reg<0) return 0;
 619   if(!reg) return 1;
 620   for (hr=0;hr<HOST_REGS;hr++) {
 621     if((cur->regmap[hr]&63)==reg) {
 622       return (cur->isconst>>hr)&1;
 623     }
 624   }
 625   return 0;
 626 }
 627 uint64_t get_const(struct regstat *cur,signed char reg)
 628 {
 629   int hr;
 630   if(!reg) return 0;
 631   for (hr=0;hr<HOST_REGS;hr++) {
 632     if(cur->regmap[hr]==reg) {
 633       return cur->constmap[hr];
 634     }
 635   }
 636   printf("Unknown constant in r%d\n",reg);
 637   exit(1);
 638 }
 639
 640 // Least soon needed registers
 641 // Look at the next ten instructions and see which registers
 642 // will be used.  Try not to reallocate these.
 643 void lsn(u_char hsn[], int i, int *preferred_reg)
 644 {
 645   int j;
 646   int b=-1;
 647   for(j=0;j<9;j++)
 648   {
 649     if(i+j>=slen) {
 650       j=slen-i-1;
 651       break;
 652     }
 653     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 654     {
 655       // Don't go past an unconditonal jump
 656       j++;
 657       break;
 658     }
 659   }
 660   for(;j>=0;j--)
 661   {
 662     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 663     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 664     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 665     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 666     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 667       // Stores can allocate zero
 668       hsn[rs1[i+j]]=j;
 669       hsn[rs2[i+j]]=j;
 670     }
 671     // On some architectures stores need invc_ptr
 672     #if defined(HOST_IMM8)
 673     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 674       hsn[INVCP]=j;
 675     }
 676     #endif
 677     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 678     {
 679       hsn[CCREG]=j;
 680       b=j;
 681     }
 682   }
 683   if(b>=0)
 684   {
 685     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 686     {
 687       // Follow first branch
 688       int t=(ba[i+b]-start)>>2;
 689       j=7-b;if(t+j>=slen) j=slen-t-1;
 690       for(;j>=0;j--)
 691       {
 692         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 693         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 694         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 695         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 696       }
 697     }
 698     // TODO: preferred register based on backward branch
 699   }
 700   // Delay slot should preferably not overwrite branch conditions or cycle count
 701   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 702     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 703     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 704     hsn[CCREG]=1;
 705     // ...or hash tables
 706     hsn[RHASH]=1;
 707     hsn[RHTBL]=1;
 708   }
 709   // Coprocessor load/store needs FTEMP, even if not declared
 710   if(itype[i]==C1LS||itype[i]==C2LS) {
 711     hsn[FTEMP]=0;
 712   }
 713   // Load L/R also uses FTEMP as a temporary register
 714   if(itype[i]==LOADLR) {
 715     hsn[FTEMP]=0;
 716   }
 717   // Also SWL/SWR/SDL/SDR
 718   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 719     hsn[FTEMP]=0;
 720   }
 721   // Don't remove the TLB registers either
 722   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 723     hsn[TLREG]=0;
 724   }
 725   // Don't remove the miniht registers
 726   if(itype[i]==UJUMP||itype[i]==RJUMP)
 727   {
 728     hsn[RHASH]=0;
 729     hsn[RHTBL]=0;
 730   }
 731 }
 732
 733 // We only want to allocate registers if we're going to use them again soon
 734 int needed_again(int r, int i)
 735 {
 736   int j;
 737   int b=-1;
 738   int rn=10;
 739
 740   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 741   {
 742     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 743       return 0; // Don't need any registers if exiting the block
 744   }
 745   for(j=0;j<9;j++)
 746   {
 747     if(i+j>=slen) {
 748       j=slen-i-1;
 749       break;
 750     }
 751     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 752     {
 753       // Don't go past an unconditonal jump
 754       j++;
 755       break;
 756     }
 757     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 758     {
 759       break;
 760     }
 761   }
 762   for(;j>=1;j--)
 763   {
 764     if(rs1[i+j]==r) rn=j;
 765     if(rs2[i+j]==r) rn=j;
 766     if((unneeded_reg[i+j]>>r)&1) rn=10;
 767     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 768     {
 769       b=j;
 770     }
 771   }
 772   /*
 773   if(b>=0)
 774   {
 775     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 776     {
 777       // Follow first branch
 778       int o=rn;
 779       int t=(ba[i+b]-start)>>2;
 780       j=7-b;if(t+j>=slen) j=slen-t-1;
 781       for(;j>=0;j--)
 782       {
 783         if(!((unneeded_reg[t+j]>>r)&1)) {
 784           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 785           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 786         }
 787         else rn=o;
 788       }
 789     }
 790   }*/
 791   if(rn<10) return 1;
 792   return 0;
 793 }
 794
 795 // Try to match register allocations at the end of a loop with those
 796 // at the beginning
 797 int loop_reg(int i, int r, int hr)
 798 {
 799   int j,k;
 800   for(j=0;j<9;j++)
 801   {
 802     if(i+j>=slen) {
 803       j=slen-i-1;
 804       break;
 805     }
 806     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 807     {
 808       // Don't go past an unconditonal jump
 809       j++;
 810       break;
 811     }
 812   }
 813   k=0;
 814   if(i>0){
 815     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 816       k--;
 817   }
 818   for(;k<j;k++)
 819   {
 820     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 821     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 822     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 823     {
 824       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 825       {
 826         int t=(ba[i+k]-start)>>2;
 827         int reg=get_reg(regs[t].regmap_entry,r);
 828         if(reg>=0) return reg;
 829         //reg=get_reg(regs[t+1].regmap_entry,r);
 830         //if(reg>=0) return reg;
 831       }
 832     }
 833   }
 834   return hr;
 835 }
 836
 837
 838 // Allocate every register, preserving source/target regs
 839 void alloc_all(struct regstat *cur,int i)
 840 {
 841   int hr;
 842
 843   for(hr=0;hr<HOST_REGS;hr++) {
 844     if(hr!=EXCLUDE_REG) {
 845       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 846          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 847       {
 848         cur->regmap[hr]=-1;
 849         cur->dirty&=~(1<<hr);
 850       }
 851       // Don't need zeros
 852       if((cur->regmap[hr]&63)==0)
 853       {
 854         cur->regmap[hr]=-1;
 855         cur->dirty&=~(1<<hr);
 856       }
 857     }
 858   }
 859 }
 860
 861 #ifndef FORCE32
 862 void div64(int64_t dividend,int64_t divisor)
 863 {
 864   lo=dividend/divisor;
 865   hi=dividend%divisor;
 866   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 867   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 868 }
 869 void divu64(uint64_t dividend,uint64_t divisor)
 870 {
 871   lo=dividend/divisor;
 872   hi=dividend%divisor;
 873   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 874   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 875 }
 876
 877 void mult64(uint64_t m1,uint64_t m2)
 878 {
 879    unsigned long long int op1, op2, op3, op4;
 880    unsigned long long int result1, result2, result3, result4;
 881    unsigned long long int temp1, temp2, temp3, temp4;
 882    int sign = 0;
 883
 884    if (m1 < 0)
 885      {
 886     op2 = -m1;
 887     sign = 1 - sign;
 888      }
 889    else op2 = m1;
 890    if (m2 < 0)
 891      {
 892     op4 = -m2;
 893     sign = 1 - sign;
 894      }
 895    else op4 = m2;
 896
 897    op1 = op2 & 0xFFFFFFFF;
 898    op2 = (op2 >> 32) & 0xFFFFFFFF;
 899    op3 = op4 & 0xFFFFFFFF;
 900    op4 = (op4 >> 32) & 0xFFFFFFFF;
 901
 902    temp1 = op1 * op3;
 903    temp2 = (temp1 >> 32) + op1 * op4;
 904    temp3 = op2 * op3;
 905    temp4 = (temp3 >> 32) + op2 * op4;
 906
 907    result1 = temp1 & 0xFFFFFFFF;
 908    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 909    result3 = (result2 >> 32) + temp4;
 910    result4 = (result3 >> 32);
 911
 912    lo = result1 | (result2 << 32);
 913    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 914    if (sign)
 915      {
 916     hi = ~hi;
 917     if (!lo) hi++;
 918     else lo = ~lo + 1;
 919      }
 920 }
 921
 922 void multu64(uint64_t m1,uint64_t m2)
 923 {
 924    unsigned long long int op1, op2, op3, op4;
 925    unsigned long long int result1, result2, result3, result4;
 926    unsigned long long int temp1, temp2, temp3, temp4;
 927
 928    op1 = m1 & 0xFFFFFFFF;
 929    op2 = (m1 >> 32) & 0xFFFFFFFF;
 930    op3 = m2 & 0xFFFFFFFF;
 931    op4 = (m2 >> 32) & 0xFFFFFFFF;
 932
 933    temp1 = op1 * op3;
 934    temp2 = (temp1 >> 32) + op1 * op4;
 935    temp3 = op2 * op3;
 936    temp4 = (temp3 >> 32) + op2 * op4;
 937
 938    result1 = temp1 & 0xFFFFFFFF;
 939    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 940    result3 = (result2 >> 32) + temp4;
 941    result4 = (result3 >> 32);
 942
 943    lo = result1 | (result2 << 32);
 944    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 945
 946   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 947   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 948 }
 949
 950 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 951 {
 952   if(bits) {
 953     original<<=64-bits;
 954     original>>=64-bits;
 955     loaded<<=bits;
 956     original|=loaded;
 957   }
 958   else original=loaded;
 959   return original;
 960 }
 961 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 962 {
 963   if(bits^56) {
 964     original>>=64-(bits^56);
 965     original<<=64-(bits^56);
 966     loaded>>=bits^56;
 967     original|=loaded;
 968   }
 969   else original=loaded;
 970   return original;
 971 }
 972 #endif
 973
 974 #ifdef __i386__
 975 #include "assem_x86.c"
 976 #endif
 977 #ifdef __x86_64__
 978 #include "assem_x64.c"
 979 #endif
 980 #ifdef __arm__
 981 #include "assem_arm.c"
 982 #endif
 983
 984 // Add virtual address mapping to linked list
 985 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 986 {
 987   struct ll_entry *new_entry;
 988   new_entry=malloc(sizeof(struct ll_entry));
 989   assert(new_entry!=NULL);
 990   new_entry->vaddr=vaddr;
 991   new_entry->reg32=0;
 992   new_entry->addr=addr;
 993   new_entry->next=*head;
 994   *head=new_entry;
 995 }
 996
 997 // Add virtual address mapping for 32-bit compiled block
 998 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
 999 {
1000   ll_add(head,vaddr,addr);
1001 #ifndef FORCE32
1002   (*head)->reg32=reg32;
1003 #endif
1004 }
1005
1006 // Check if an address is already compiled
1007 // but don't return addresses which are about to expire from the cache
1008 void *check_addr(u_int vaddr)
1009 {
1010   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1011   if(ht_bin[0]==vaddr) {
1012     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1013       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1014   }
1015   if(ht_bin[2]==vaddr) {
1016     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1017       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1018   }
1019   u_int page=get_page(vaddr);
1020   struct ll_entry *head;
1021   head=jump_in[page];
1022   while(head!=NULL) {
1023     if(head->vaddr==vaddr&&head->reg32==0) {
1024       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1025         // Update existing entry with current address
1026         if(ht_bin[0]==vaddr) {
1027           ht_bin[1]=(int)head->addr;
1028           return head->addr;
1029         }
1030         if(ht_bin[2]==vaddr) {
1031           ht_bin[3]=(int)head->addr;
1032           return head->addr;
1033         }
1034         // Insert into hash table with low priority.
1035         // Don't evict existing entries, as they are probably
1036         // addresses that are being accessed frequently.
1037         if(ht_bin[0]==-1) {
1038           ht_bin[1]=(int)head->addr;
1039           ht_bin[0]=vaddr;
1040         }else if(ht_bin[2]==-1) {
1041           ht_bin[3]=(int)head->addr;
1042           ht_bin[2]=vaddr;
1043         }
1044         return head->addr;
1045       }
1046     }
1047     head=head->next;
1048   }
1049   return 0;
1050 }
1051
1052 void remove_hash(int vaddr)
1053 {
1054   //printf("remove hash: %x\n",vaddr);
1055   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1056   if(ht_bin[2]==vaddr) {
1057     ht_bin[2]=ht_bin[3]=-1;
1058   }
1059   if(ht_bin[0]==vaddr) {
1060     ht_bin[0]=ht_bin[2];
1061     ht_bin[1]=ht_bin[3];
1062     ht_bin[2]=ht_bin[3]=-1;
1063   }
1064 }
1065
1066 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1067 {
1068   struct ll_entry *next;
1069   while(*head) {
1070     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1071        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1072     {
1073       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1074       remove_hash((*head)->vaddr);
1075       next=(*head)->next;
1076       free(*head);
1077       *head=next;
1078     }
1079     else
1080     {
1081       head=&((*head)->next);
1082     }
1083   }
1084 }
1085
1086 // Remove all entries from linked list
1087 void ll_clear(struct ll_entry **head)
1088 {
1089   struct ll_entry *cur;
1090   struct ll_entry *next;
1091   if(cur=*head) {
1092     *head=0;
1093     while(cur) {
1094       next=cur->next;
1095       free(cur);
1096       cur=next;
1097     }
1098   }
1099 }
1100
1101 // Dereference the pointers and remove if it matches
1102 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1103 {
1104   while(head) {
1105     int ptr=get_pointer(head->addr);
1106     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1107     if(((ptr>>shift)==(addr>>shift)) ||
1108        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1109     {
1110       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1111       u_int host_addr=(u_int)kill_pointer(head->addr);
1112       #ifdef __arm__
1113         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1114       #endif
1115     }
1116     head=head->next;
1117   }
1118 }
1119
1120 // This is called when we write to a compiled block (see do_invstub)
1121 void invalidate_page(u_int page)
1122 {
1123   struct ll_entry *head;
1124   struct ll_entry *next;
1125   head=jump_in[page];
1126   jump_in[page]=0;
1127   while(head!=NULL) {
1128     inv_debug("INVALIDATE: %x\n",head->vaddr);
1129     remove_hash(head->vaddr);
1130     next=head->next;
1131     free(head);
1132     head=next;
1133   }
1134   head=jump_out[page];
1135   jump_out[page]=0;
1136   while(head!=NULL) {
1137     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1138     u_int host_addr=(u_int)kill_pointer(head->addr);
1139     #ifdef __arm__
1140       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1141     #endif
1142     next=head->next;
1143     free(head);
1144     head=next;
1145   }
1146 }
1147
1148 static void invalidate_block_range(u_int block, u_int first, u_int last)
1149 {
1150   u_int page=get_page(block<<12);
1151   //printf("first=%d last=%d\n",first,last);
1152   invalidate_page(page);
1153   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1154   assert(last<page+5);
1155   // Invalidate the adjacent pages if a block crosses a 4K boundary
1156   while(first<page) {
1157     invalidate_page(first);
1158     first++;
1159   }
1160   for(first=page+1;first<last;first++) {
1161     invalidate_page(first);
1162   }
1163   #ifdef __arm__
1164     do_clear_cache();
1165   #endif
1166
1167   // Don't trap writes
1168   invalid_code[block]=1;
1169 #ifndef DISABLE_TLB
1170   // If there is a valid TLB entry for this page, remove write protect
1171   if(tlb_LUT_w[block]) {
1172     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1173     // CHECK: Is this right?
1174     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1175     u_int real_block=tlb_LUT_w[block]>>12;
1176     invalid_code[real_block]=1;
1177     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1178   }
1179   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1180 #endif
1181
1182   #ifdef USE_MINI_HT
1183   memset(mini_ht,-1,sizeof(mini_ht));
1184   #endif
1185 }
1186
1187 void invalidate_block(u_int block)
1188 {
1189   u_int page=get_page(block<<12);
1190   u_int vpage=get_vpage(block<<12);
1191   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1192   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1193   u_int first,last;
1194   first=last=page;
1195   struct ll_entry *head;
1196   head=jump_dirty[vpage];
1197   //printf("page=%d vpage=%d\n",page,vpage);
1198   while(head!=NULL) {
1199     u_int start,end;
1200     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1201       get_bounds((int)head->addr,&start,&end);
1202       //printf("start: %x end: %x\n",start,end);
1203       if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1204         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1205           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1206           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1207         }
1208       }
1209 #ifndef DISABLE_TLB
1210       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1211         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1212           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1213           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1214         }
1215       }
1216 #endif
1217     }
1218     head=head->next;
1219   }
1220   invalidate_block_range(block,first,last);
1221 }
1222
1223 void invalidate_addr(u_int addr)
1224 {
1225 #ifdef PCSX
1226   //static int rhits;
1227   // this check is done by the caller
1228   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1229   u_int page=get_page(addr);
1230   if(page<2048) { // RAM
1231     struct ll_entry *head;
1232     u_int addr_min=~0, addr_max=0;
1233     int mask=RAM_SIZE-1;
1234     int pg1;
1235     inv_code_start=addr&~0xfff;
1236     inv_code_end=addr|0xfff;
1237     pg1=page;
1238     if (pg1>0) {
1239       // must check previous page too because of spans..
1240       pg1--;
1241       inv_code_start-=0x1000;
1242     }
1243     for(;pg1<=page;pg1++) {
1244       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1245         u_int start,end;
1246         get_bounds((int)head->addr,&start,&end);
1247         if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1248           if(start<addr_min) addr_min=start;
1249           if(end>addr_max) addr_max=end;
1250         }
1251         else if(addr<start) {
1252           if(start<inv_code_end)
1253             inv_code_end=start-1;
1254         }
1255         else {
1256           if(end>inv_code_start)
1257             inv_code_start=end;
1258         }
1259       }
1260     }
1261     if (addr_min!=~0) {
1262       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1263       inv_code_start=inv_code_end=~0;
1264       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1265       return;
1266     }
1267     else {
1268       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);//rhits);
1269     }
1270     //rhits=0;
1271     if(page!=0) // FIXME: don't know what's up with page 0 (Klonoa)
1272       return;
1273   }
1274 #endif
1275   invalidate_block(addr>>12);
1276 }
1277
1278 // This is called when loading a save state.
1279 // Anything could have changed, so invalidate everything.
1280 void invalidate_all_pages()
1281 {
1282   u_int page,n;
1283   for(page=0;page<4096;page++)
1284     invalidate_page(page);
1285   for(page=0;page<1048576;page++)
1286     if(!invalid_code[page]) {
1287       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1288       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1289     }
1290   #ifdef __arm__
1291   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1292   #endif
1293   #ifdef USE_MINI_HT
1294   memset(mini_ht,-1,sizeof(mini_ht));
1295   #endif
1296   #ifndef DISABLE_TLB
1297   // TLB
1298   for(page=0;page<0x100000;page++) {
1299     if(tlb_LUT_r[page]) {
1300       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1301       if(!tlb_LUT_w[page]||!invalid_code[page])
1302         memory_map[page]|=0x40000000; // Write protect
1303     }
1304     else memory_map[page]=-1;
1305     if(page==0x80000) page=0xC0000;
1306   }
1307   tlb_hacks();
1308   #endif
1309 }
1310
1311 // Add an entry to jump_out after making a link
1312 void add_link(u_int vaddr,void *src)
1313 {
1314   u_int page=get_page(vaddr);
1315   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1316   int *ptr=(int *)(src+4);
1317   assert((*ptr&0x0fff0000)==0x059f0000);
1318   ll_add(jump_out+page,vaddr,src);
1319   //int ptr=get_pointer(src);
1320   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1321 }
1322
1323 // If a code block was found to be unmodified (bit was set in
1324 // restore_candidate) and it remains unmodified (bit is clear
1325 // in invalid_code) then move the entries for that 4K page from
1326 // the dirty list to the clean list.
1327 void clean_blocks(u_int page)
1328 {
1329   struct ll_entry *head;
1330   inv_debug("INV: clean_blocks page=%d\n",page);
1331   head=jump_dirty[page];
1332   while(head!=NULL) {
1333     if(!invalid_code[head->vaddr>>12]) {
1334       // Don't restore blocks which are about to expire from the cache
1335       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1336         u_int start,end;
1337         if(verify_dirty((int)head->addr)) {
1338           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1339           u_int i;
1340           u_int inv=0;
1341           get_bounds((int)head->addr,&start,&end);
1342           if(start-(u_int)rdram<RAM_SIZE) {
1343             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1344               inv|=invalid_code[i];
1345             }
1346           }
1347 #ifndef DISABLE_TLB
1348           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1349             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1350             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1351             if(addr<start||addr>=end) inv=1;
1352           }
1353 #endif
1354           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1355             inv=1;
1356           }
1357           if(!inv) {
1358             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1359             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1360               u_int ppage=page;
1361 #ifndef DISABLE_TLB
1362               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1363 #endif
1364               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1365               //printf("page=%x, addr=%x\n",page,head->vaddr);
1366               //assert(head->vaddr>>12==(page|0x80000));
1367               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1368               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1369               if(!head->reg32) {
1370                 if(ht_bin[0]==head->vaddr) {
1371                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1372                 }
1373                 if(ht_bin[2]==head->vaddr) {
1374                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1375                 }
1376               }
1377             }
1378           }
1379         }
1380       }
1381     }
1382     head=head->next;
1383   }
1384 }
1385
1386
1387 void mov_alloc(struct regstat *current,int i)
1388 {
1389   // Note: Don't need to actually alloc the source registers
1390   if((~current->is32>>rs1[i])&1) {
1391     //alloc_reg64(current,i,rs1[i]);
1392     alloc_reg64(current,i,rt1[i]);
1393     current->is32&=~(1LL<<rt1[i]);
1394   } else {
1395     //alloc_reg(current,i,rs1[i]);
1396     alloc_reg(current,i,rt1[i]);
1397     current->is32|=(1LL<<rt1[i]);
1398   }
1399   clear_const(current,rs1[i]);
1400   clear_const(current,rt1[i]);
1401   dirty_reg(current,rt1[i]);
1402 }
1403
1404 void shiftimm_alloc(struct regstat *current,int i)
1405 {
1406   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1407   {
1408     if(rt1[i]) {
1409       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1410       else lt1[i]=rs1[i];
1411       alloc_reg(current,i,rt1[i]);
1412       current->is32|=1LL<<rt1[i];
1413       dirty_reg(current,rt1[i]);
1414       if(is_const(current,rs1[i])) {
1415         int v=get_const(current,rs1[i]);
1416         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1417         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1418         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1419       }
1420       else clear_const(current,rt1[i]);
1421     }
1422   }
1423   else
1424   {
1425     clear_const(current,rs1[i]);
1426     clear_const(current,rt1[i]);
1427   }
1428
1429   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1430   {
1431     if(rt1[i]) {
1432       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1433       alloc_reg64(current,i,rt1[i]);
1434       current->is32&=~(1LL<<rt1[i]);
1435       dirty_reg(current,rt1[i]);
1436     }
1437   }
1438   if(opcode2[i]==0x3c) // DSLL32
1439   {
1440     if(rt1[i]) {
1441       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1442       alloc_reg64(current,i,rt1[i]);
1443       current->is32&=~(1LL<<rt1[i]);
1444       dirty_reg(current,rt1[i]);
1445     }
1446   }
1447   if(opcode2[i]==0x3e) // DSRL32
1448   {
1449     if(rt1[i]) {
1450       alloc_reg64(current,i,rs1[i]);
1451       if(imm[i]==32) {
1452         alloc_reg64(current,i,rt1[i]);
1453         current->is32&=~(1LL<<rt1[i]);
1454       } else {
1455         alloc_reg(current,i,rt1[i]);
1456         current->is32|=1LL<<rt1[i];
1457       }
1458       dirty_reg(current,rt1[i]);
1459     }
1460   }
1461   if(opcode2[i]==0x3f) // DSRA32
1462   {
1463     if(rt1[i]) {
1464       alloc_reg64(current,i,rs1[i]);
1465       alloc_reg(current,i,rt1[i]);
1466       current->is32|=1LL<<rt1[i];
1467       dirty_reg(current,rt1[i]);
1468     }
1469   }
1470 }
1471
1472 void shift_alloc(struct regstat *current,int i)
1473 {
1474   if(rt1[i]) {
1475     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1476     {
1477       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1478       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1479       alloc_reg(current,i,rt1[i]);
1480       if(rt1[i]==rs2[i]) {
1481         alloc_reg_temp(current,i,-1);
1482         minimum_free_regs[i]=1;
1483       }
1484       current->is32|=1LL<<rt1[i];
1485     } else { // DSLLV/DSRLV/DSRAV
1486       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1487       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1488       alloc_reg64(current,i,rt1[i]);
1489       current->is32&=~(1LL<<rt1[i]);
1490       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1491       {
1492         alloc_reg_temp(current,i,-1);
1493         minimum_free_regs[i]=1;
1494       }
1495     }
1496     clear_const(current,rs1[i]);
1497     clear_const(current,rs2[i]);
1498     clear_const(current,rt1[i]);
1499     dirty_reg(current,rt1[i]);
1500   }
1501 }
1502
1503 void alu_alloc(struct regstat *current,int i)
1504 {
1505   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1506     if(rt1[i]) {
1507       if(rs1[i]&&rs2[i]) {
1508         alloc_reg(current,i,rs1[i]);
1509         alloc_reg(current,i,rs2[i]);
1510       }
1511       else {
1512         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1513         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1514       }
1515       alloc_reg(current,i,rt1[i]);
1516     }
1517     current->is32|=1LL<<rt1[i];
1518   }
1519   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1520     if(rt1[i]) {
1521       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1522       {
1523         alloc_reg64(current,i,rs1[i]);
1524         alloc_reg64(current,i,rs2[i]);
1525         alloc_reg(current,i,rt1[i]);
1526       } else {
1527         alloc_reg(current,i,rs1[i]);
1528         alloc_reg(current,i,rs2[i]);
1529         alloc_reg(current,i,rt1[i]);
1530       }
1531     }
1532     current->is32|=1LL<<rt1[i];
1533   }
1534   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1535     if(rt1[i]) {
1536       if(rs1[i]&&rs2[i]) {
1537         alloc_reg(current,i,rs1[i]);
1538         alloc_reg(current,i,rs2[i]);
1539       }
1540       else
1541       {
1542         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1543         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1544       }
1545       alloc_reg(current,i,rt1[i]);
1546       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1547       {
1548         if(!((current->uu>>rt1[i])&1)) {
1549           alloc_reg64(current,i,rt1[i]);
1550         }
1551         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1552           if(rs1[i]&&rs2[i]) {
1553             alloc_reg64(current,i,rs1[i]);
1554             alloc_reg64(current,i,rs2[i]);
1555           }
1556           else
1557           {
1558             // Is is really worth it to keep 64-bit values in registers?
1559             #ifdef NATIVE_64BIT
1560             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1562             #endif
1563           }
1564         }
1565         current->is32&=~(1LL<<rt1[i]);
1566       } else {
1567         current->is32|=1LL<<rt1[i];
1568       }
1569     }
1570   }
1571   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1572     if(rt1[i]) {
1573       if(rs1[i]&&rs2[i]) {
1574         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1575           alloc_reg64(current,i,rs1[i]);
1576           alloc_reg64(current,i,rs2[i]);
1577           alloc_reg64(current,i,rt1[i]);
1578         } else {
1579           alloc_reg(current,i,rs1[i]);
1580           alloc_reg(current,i,rs2[i]);
1581           alloc_reg(current,i,rt1[i]);
1582         }
1583       }
1584       else {
1585         alloc_reg(current,i,rt1[i]);
1586         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1587           // DADD used as move, or zeroing
1588           // If we have a 64-bit source, then make the target 64 bits too
1589           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1590             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1591             alloc_reg64(current,i,rt1[i]);
1592           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1593             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1594             alloc_reg64(current,i,rt1[i]);
1595           }
1596           if(opcode2[i]>=0x2e&&rs2[i]) {
1597             // DSUB used as negation - 64-bit result
1598             // If we have a 32-bit register, extend it to 64 bits
1599             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1600             alloc_reg64(current,i,rt1[i]);
1601           }
1602         }
1603       }
1604       if(rs1[i]&&rs2[i]) {
1605         current->is32&=~(1LL<<rt1[i]);
1606       } else if(rs1[i]) {
1607         current->is32&=~(1LL<<rt1[i]);
1608         if((current->is32>>rs1[i])&1)
1609           current->is32|=1LL<<rt1[i];
1610       } else if(rs2[i]) {
1611         current->is32&=~(1LL<<rt1[i]);
1612         if((current->is32>>rs2[i])&1)
1613           current->is32|=1LL<<rt1[i];
1614       } else {
1615         current->is32|=1LL<<rt1[i];
1616       }
1617     }
1618   }
1619   clear_const(current,rs1[i]);
1620   clear_const(current,rs2[i]);
1621   clear_const(current,rt1[i]);
1622   dirty_reg(current,rt1[i]);
1623 }
1624
1625 void imm16_alloc(struct regstat *current,int i)
1626 {
1627   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1628   else lt1[i]=rs1[i];
1629   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1630   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1631     current->is32&=~(1LL<<rt1[i]);
1632     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1633       // TODO: Could preserve the 32-bit flag if the immediate is zero
1634       alloc_reg64(current,i,rt1[i]);
1635       alloc_reg64(current,i,rs1[i]);
1636     }
1637     clear_const(current,rs1[i]);
1638     clear_const(current,rt1[i]);
1639   }
1640   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1641     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1642     current->is32|=1LL<<rt1[i];
1643     clear_const(current,rs1[i]);
1644     clear_const(current,rt1[i]);
1645   }
1646   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1647     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1648       if(rs1[i]!=rt1[i]) {
1649         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1650         alloc_reg64(current,i,rt1[i]);
1651         current->is32&=~(1LL<<rt1[i]);
1652       }
1653     }
1654     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1655     if(is_const(current,rs1[i])) {
1656       int v=get_const(current,rs1[i]);
1657       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1658       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1659       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1660     }
1661     else clear_const(current,rt1[i]);
1662   }
1663   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1664     if(is_const(current,rs1[i])) {
1665       int v=get_const(current,rs1[i]);
1666       set_const(current,rt1[i],v+imm[i]);
1667     }
1668     else clear_const(current,rt1[i]);
1669     current->is32|=1LL<<rt1[i];
1670   }
1671   else {
1672     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1673     current->is32|=1LL<<rt1[i];
1674   }
1675   dirty_reg(current,rt1[i]);
1676 }
1677
1678 void load_alloc(struct regstat *current,int i)
1679 {
1680   clear_const(current,rt1[i]);
1681   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1682   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1683   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1684   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1685     alloc_reg(current,i,rt1[i]);
1686     assert(get_reg(current->regmap,rt1[i])>=0);
1687     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1688     {
1689       current->is32&=~(1LL<<rt1[i]);
1690       alloc_reg64(current,i,rt1[i]);
1691     }
1692     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1693     {
1694       current->is32&=~(1LL<<rt1[i]);
1695       alloc_reg64(current,i,rt1[i]);
1696       alloc_all(current,i);
1697       alloc_reg64(current,i,FTEMP);
1698       minimum_free_regs[i]=HOST_REGS;
1699     }
1700     else current->is32|=1LL<<rt1[i];
1701     dirty_reg(current,rt1[i]);
1702     // If using TLB, need a register for pointer to the mapping table
1703     if(using_tlb) alloc_reg(current,i,TLREG);
1704     // LWL/LWR need a temporary register for the old value
1705     if(opcode[i]==0x22||opcode[i]==0x26)
1706     {
1707       alloc_reg(current,i,FTEMP);
1708       alloc_reg_temp(current,i,-1);
1709       minimum_free_regs[i]=1;
1710     }
1711   }
1712   else
1713   {
1714     // Load to r0 or unneeded register (dummy load)
1715     // but we still need a register to calculate the address
1716     if(opcode[i]==0x22||opcode[i]==0x26)
1717     {
1718       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1719     }
1720     // If using TLB, need a register for pointer to the mapping table
1721     if(using_tlb) alloc_reg(current,i,TLREG);
1722     alloc_reg_temp(current,i,-1);
1723     minimum_free_regs[i]=1;
1724     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1725     {
1726       alloc_all(current,i);
1727       alloc_reg64(current,i,FTEMP);
1728       minimum_free_regs[i]=HOST_REGS;
1729     }
1730   }
1731 }
1732
1733 void store_alloc(struct regstat *current,int i)
1734 {
1735   clear_const(current,rs2[i]);
1736   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1737   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1738   alloc_reg(current,i,rs2[i]);
1739   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1740     alloc_reg64(current,i,rs2[i]);
1741     if(rs2[i]) alloc_reg(current,i,FTEMP);
1742   }
1743   // If using TLB, need a register for pointer to the mapping table
1744   if(using_tlb) alloc_reg(current,i,TLREG);
1745   #if defined(HOST_IMM8)
1746   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1747   else alloc_reg(current,i,INVCP);
1748   #endif
1749   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1750     alloc_reg(current,i,FTEMP);
1751   }
1752   // We need a temporary register for address generation
1753   alloc_reg_temp(current,i,-1);
1754   minimum_free_regs[i]=1;
1755 }
1756
1757 void c1ls_alloc(struct regstat *current,int i)
1758 {
1759   //clear_const(current,rs1[i]); // FIXME
1760   clear_const(current,rt1[i]);
1761   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1762   alloc_reg(current,i,CSREG); // Status
1763   alloc_reg(current,i,FTEMP);
1764   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1765     alloc_reg64(current,i,FTEMP);
1766   }
1767   // If using TLB, need a register for pointer to the mapping table
1768   if(using_tlb) alloc_reg(current,i,TLREG);
1769   #if defined(HOST_IMM8)
1770   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1771   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1772     alloc_reg(current,i,INVCP);
1773   #endif
1774   // We need a temporary register for address generation
1775   alloc_reg_temp(current,i,-1);
1776 }
1777
1778 void c2ls_alloc(struct regstat *current,int i)
1779 {
1780   clear_const(current,rt1[i]);
1781   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1782   alloc_reg(current,i,FTEMP);
1783   // If using TLB, need a register for pointer to the mapping table
1784   if(using_tlb) alloc_reg(current,i,TLREG);
1785   #if defined(HOST_IMM8)
1786   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1787   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1788     alloc_reg(current,i,INVCP);
1789   #endif
1790   // We need a temporary register for address generation
1791   alloc_reg_temp(current,i,-1);
1792   minimum_free_regs[i]=1;
1793 }
1794
1795 #ifndef multdiv_alloc
1796 void multdiv_alloc(struct regstat *current,int i)
1797 {
1798   //  case 0x18: MULT
1799   //  case 0x19: MULTU
1800   //  case 0x1A: DIV
1801   //  case 0x1B: DIVU
1802   //  case 0x1C: DMULT
1803   //  case 0x1D: DMULTU
1804   //  case 0x1E: DDIV
1805   //  case 0x1F: DDIVU
1806   clear_const(current,rs1[i]);
1807   clear_const(current,rs2[i]);
1808   if(rs1[i]&&rs2[i])
1809   {
1810     if((opcode2[i]&4)==0) // 32-bit
1811     {
1812       current->u&=~(1LL<<HIREG);
1813       current->u&=~(1LL<<LOREG);
1814       alloc_reg(current,i,HIREG);
1815       alloc_reg(current,i,LOREG);
1816       alloc_reg(current,i,rs1[i]);
1817       alloc_reg(current,i,rs2[i]);
1818       current->is32|=1LL<<HIREG;
1819       current->is32|=1LL<<LOREG;
1820       dirty_reg(current,HIREG);
1821       dirty_reg(current,LOREG);
1822     }
1823     else // 64-bit
1824     {
1825       current->u&=~(1LL<<HIREG);
1826       current->u&=~(1LL<<LOREG);
1827       current->uu&=~(1LL<<HIREG);
1828       current->uu&=~(1LL<<LOREG);
1829       alloc_reg64(current,i,HIREG);
1830       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1831       alloc_reg64(current,i,rs1[i]);
1832       alloc_reg64(current,i,rs2[i]);
1833       alloc_all(current,i);
1834       current->is32&=~(1LL<<HIREG);
1835       current->is32&=~(1LL<<LOREG);
1836       dirty_reg(current,HIREG);
1837       dirty_reg(current,LOREG);
1838       minimum_free_regs[i]=HOST_REGS;
1839     }
1840   }
1841   else
1842   {
1843     // Multiply by zero is zero.
1844     // MIPS does not have a divide by zero exception.
1845     // The result is undefined, we return zero.
1846     alloc_reg(current,i,HIREG);
1847     alloc_reg(current,i,LOREG);
1848     current->is32|=1LL<<HIREG;
1849     current->is32|=1LL<<LOREG;
1850     dirty_reg(current,HIREG);
1851     dirty_reg(current,LOREG);
1852   }
1853 }
1854 #endif
1855
1856 void cop0_alloc(struct regstat *current,int i)
1857 {
1858   if(opcode2[i]==0) // MFC0
1859   {
1860     if(rt1[i]) {
1861       clear_const(current,rt1[i]);
1862       alloc_all(current,i);
1863       alloc_reg(current,i,rt1[i]);
1864       current->is32|=1LL<<rt1[i];
1865       dirty_reg(current,rt1[i]);
1866     }
1867   }
1868   else if(opcode2[i]==4) // MTC0
1869   {
1870     if(rs1[i]){
1871       clear_const(current,rs1[i]);
1872       alloc_reg(current,i,rs1[i]);
1873       alloc_all(current,i);
1874     }
1875     else {
1876       alloc_all(current,i); // FIXME: Keep r0
1877       current->u&=~1LL;
1878       alloc_reg(current,i,0);
1879     }
1880   }
1881   else
1882   {
1883     // TLBR/TLBWI/TLBWR/TLBP/ERET
1884     assert(opcode2[i]==0x10);
1885     alloc_all(current,i);
1886   }
1887   minimum_free_regs[i]=HOST_REGS;
1888 }
1889
1890 void cop1_alloc(struct regstat *current,int i)
1891 {
1892   alloc_reg(current,i,CSREG); // Load status
1893   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1894   {
1895     if(rt1[i]){
1896       clear_const(current,rt1[i]);
1897       if(opcode2[i]==1) {
1898         alloc_reg64(current,i,rt1[i]); // DMFC1
1899         current->is32&=~(1LL<<rt1[i]);
1900       }else{
1901         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1902         current->is32|=1LL<<rt1[i];
1903       }
1904       dirty_reg(current,rt1[i]);
1905     }
1906     alloc_reg_temp(current,i,-1);
1907   }
1908   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1909   {
1910     if(rs1[i]){
1911       clear_const(current,rs1[i]);
1912       if(opcode2[i]==5)
1913         alloc_reg64(current,i,rs1[i]); // DMTC1
1914       else
1915         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1916       alloc_reg_temp(current,i,-1);
1917     }
1918     else {
1919       current->u&=~1LL;
1920       alloc_reg(current,i,0);
1921       alloc_reg_temp(current,i,-1);
1922     }
1923   }
1924   minimum_free_regs[i]=1;
1925 }
1926 void fconv_alloc(struct regstat *current,int i)
1927 {
1928   alloc_reg(current,i,CSREG); // Load status
1929   alloc_reg_temp(current,i,-1);
1930   minimum_free_regs[i]=1;
1931 }
1932 void float_alloc(struct regstat *current,int i)
1933 {
1934   alloc_reg(current,i,CSREG); // Load status
1935   alloc_reg_temp(current,i,-1);
1936   minimum_free_regs[i]=1;
1937 }
1938 void c2op_alloc(struct regstat *current,int i)
1939 {
1940   alloc_reg_temp(current,i,-1);
1941 }
1942 void fcomp_alloc(struct regstat *current,int i)
1943 {
1944   alloc_reg(current,i,CSREG); // Load status
1945   alloc_reg(current,i,FSREG); // Load flags
1946   dirty_reg(current,FSREG); // Flag will be modified
1947   alloc_reg_temp(current,i,-1);
1948   minimum_free_regs[i]=1;
1949 }
1950
1951 void syscall_alloc(struct regstat *current,int i)
1952 {
1953   alloc_cc(current,i);
1954   dirty_reg(current,CCREG);
1955   alloc_all(current,i);
1956   minimum_free_regs[i]=HOST_REGS;
1957   current->isconst=0;
1958 }
1959
1960 void delayslot_alloc(struct regstat *current,int i)
1961 {
1962   switch(itype[i]) {
1963     case UJUMP:
1964     case CJUMP:
1965     case SJUMP:
1966     case RJUMP:
1967     case FJUMP:
1968     case SYSCALL:
1969     case HLECALL:
1970     case SPAN:
1971       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1972       printf("Disabled speculative precompilation\n");
1973       stop_after_jal=1;
1974       break;
1975     case IMM16:
1976       imm16_alloc(current,i);
1977       break;
1978     case LOAD:
1979     case LOADLR:
1980       load_alloc(current,i);
1981       break;
1982     case STORE:
1983     case STORELR:
1984       store_alloc(current,i);
1985       break;
1986     case ALU:
1987       alu_alloc(current,i);
1988       break;
1989     case SHIFT:
1990       shift_alloc(current,i);
1991       break;
1992     case MULTDIV:
1993       multdiv_alloc(current,i);
1994       break;
1995     case SHIFTIMM:
1996       shiftimm_alloc(current,i);
1997       break;
1998     case MOV:
1999       mov_alloc(current,i);
2000       break;
2001     case COP0:
2002       cop0_alloc(current,i);
2003       break;
2004     case COP1:
2005     case COP2:
2006       cop1_alloc(current,i);
2007       break;
2008     case C1LS:
2009       c1ls_alloc(current,i);
2010       break;
2011     case C2LS:
2012       c2ls_alloc(current,i);
2013       break;
2014     case FCONV:
2015       fconv_alloc(current,i);
2016       break;
2017     case FLOAT:
2018       float_alloc(current,i);
2019       break;
2020     case FCOMP:
2021       fcomp_alloc(current,i);
2022       break;
2023     case C2OP:
2024       c2op_alloc(current,i);
2025       break;
2026   }
2027 }
2028
2029 // Special case where a branch and delay slot span two pages in virtual memory
2030 static void pagespan_alloc(struct regstat *current,int i)
2031 {
2032   current->isconst=0;
2033   current->wasconst=0;
2034   regs[i].wasconst=0;
2035   minimum_free_regs[i]=HOST_REGS;
2036   alloc_all(current,i);
2037   alloc_cc(current,i);
2038   dirty_reg(current,CCREG);
2039   if(opcode[i]==3) // JAL
2040   {
2041     alloc_reg(current,i,31);
2042     dirty_reg(current,31);
2043   }
2044   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2045   {
2046     alloc_reg(current,i,rs1[i]);
2047     if (rt1[i]!=0) {
2048       alloc_reg(current,i,rt1[i]);
2049       dirty_reg(current,rt1[i]);
2050     }
2051   }
2052   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2053   {
2054     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2055     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2056     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2057     {
2058       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2059       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2060     }
2061   }
2062   else
2063   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2064   {
2065     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2066     if(!((current->is32>>rs1[i])&1))
2067     {
2068       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2069     }
2070   }
2071   else
2072   if(opcode[i]==0x11) // BC1
2073   {
2074     alloc_reg(current,i,FSREG);
2075     alloc_reg(current,i,CSREG);
2076   }
2077   //else ...
2078 }
2079
2080 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2081 {
2082   stubs[stubcount][0]=type;
2083   stubs[stubcount][1]=addr;
2084   stubs[stubcount][2]=retaddr;
2085   stubs[stubcount][3]=a;
2086   stubs[stubcount][4]=b;
2087   stubs[stubcount][5]=c;
2088   stubs[stubcount][6]=d;
2089   stubs[stubcount][7]=e;
2090   stubcount++;
2091 }
2092
2093 // Write out a single register
2094 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2095 {
2096   int hr;
2097   for(hr=0;hr<HOST_REGS;hr++) {
2098     if(hr!=EXCLUDE_REG) {
2099       if((regmap[hr]&63)==r) {
2100         if((dirty>>hr)&1) {
2101           if(regmap[hr]<64) {
2102             emit_storereg(r,hr);
2103 #ifndef FORCE32
2104             if((is32>>regmap[hr])&1) {
2105               emit_sarimm(hr,31,hr);
2106               emit_storereg(r|64,hr);
2107             }
2108 #endif
2109           }else{
2110             emit_storereg(r|64,hr);
2111           }
2112         }
2113       }
2114     }
2115   }
2116 }
2117
2118 int mchecksum()
2119 {
2120   //if(!tracedebug) return 0;
2121   int i;
2122   int sum=0;
2123   for(i=0;i<2097152;i++) {
2124     unsigned int temp=sum;
2125     sum<<=1;
2126     sum|=(~temp)>>31;
2127     sum^=((u_int *)rdram)[i];
2128   }
2129   return sum;
2130 }
2131 int rchecksum()
2132 {
2133   int i;
2134   int sum=0;
2135   for(i=0;i<64;i++)
2136     sum^=((u_int *)reg)[i];
2137   return sum;
2138 }
2139 void rlist()
2140 {
2141   int i;
2142   printf("TRACE: ");
2143   for(i=0;i<32;i++)
2144     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2145   printf("\n");
2146 #ifndef DISABLE_COP1
2147   printf("TRACE: ");
2148   for(i=0;i<32;i++)
2149     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2150   printf("\n");
2151 #endif
2152 }
2153
2154 void enabletrace()
2155 {
2156   tracedebug=1;
2157 }
2158
2159 void memdebug(int i)
2160 {
2161   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2162   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2163   //rlist();
2164   //if(tracedebug) {
2165   //if(Count>=-2084597794) {
2166   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2167   //if(0) {
2168     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2169     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2170     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2171     rlist();
2172     #ifdef __i386__
2173     printf("TRACE: %x\n",(&i)[-1]);
2174     #endif
2175     #ifdef __arm__
2176     int j;
2177     printf("TRACE: %x \n",(&j)[10]);
2178     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2179     #endif
2180     //fflush(stdout);
2181   }
2182   //printf("TRACE: %x\n",(&i)[-1]);
2183 }
2184
2185 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2186 {
2187   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2188 }
2189
2190 void alu_assemble(int i,struct regstat *i_regs)
2191 {
2192   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2193     if(rt1[i]) {
2194       signed char s1,s2,t;
2195       t=get_reg(i_regs->regmap,rt1[i]);
2196       if(t>=0) {
2197         s1=get_reg(i_regs->regmap,rs1[i]);
2198         s2=get_reg(i_regs->regmap,rs2[i]);
2199         if(rs1[i]&&rs2[i]) {
2200           assert(s1>=0);
2201           assert(s2>=0);
2202           if(opcode2[i]&2) emit_sub(s1,s2,t);
2203           else emit_add(s1,s2,t);
2204         }
2205         else if(rs1[i]) {
2206           if(s1>=0) emit_mov(s1,t);
2207           else emit_loadreg(rs1[i],t);
2208         }
2209         else if(rs2[i]) {
2210           if(s2>=0) {
2211             if(opcode2[i]&2) emit_neg(s2,t);
2212             else emit_mov(s2,t);
2213           }
2214           else {
2215             emit_loadreg(rs2[i],t);
2216             if(opcode2[i]&2) emit_neg(t,t);
2217           }
2218         }
2219         else emit_zeroreg(t);
2220       }
2221     }
2222   }
2223   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2224     if(rt1[i]) {
2225       signed char s1l,s2l,s1h,s2h,tl,th;
2226       tl=get_reg(i_regs->regmap,rt1[i]);
2227       th=get_reg(i_regs->regmap,rt1[i]|64);
2228       if(tl>=0) {
2229         s1l=get_reg(i_regs->regmap,rs1[i]);
2230         s2l=get_reg(i_regs->regmap,rs2[i]);
2231         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2232         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2233         if(rs1[i]&&rs2[i]) {
2234           assert(s1l>=0);
2235           assert(s2l>=0);
2236           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2237           else emit_adds(s1l,s2l,tl);
2238           if(th>=0) {
2239             #ifdef INVERTED_CARRY
2240             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2241             #else
2242             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2243             #endif
2244             else emit_add(s1h,s2h,th);
2245           }
2246         }
2247         else if(rs1[i]) {
2248           if(s1l>=0) emit_mov(s1l,tl);
2249           else emit_loadreg(rs1[i],tl);
2250           if(th>=0) {
2251             if(s1h>=0) emit_mov(s1h,th);
2252             else emit_loadreg(rs1[i]|64,th);
2253           }
2254         }
2255         else if(rs2[i]) {
2256           if(s2l>=0) {
2257             if(opcode2[i]&2) emit_negs(s2l,tl);
2258             else emit_mov(s2l,tl);
2259           }
2260           else {
2261             emit_loadreg(rs2[i],tl);
2262             if(opcode2[i]&2) emit_negs(tl,tl);
2263           }
2264           if(th>=0) {
2265             #ifdef INVERTED_CARRY
2266             if(s2h>=0) emit_mov(s2h,th);
2267             else emit_loadreg(rs2[i]|64,th);
2268             if(opcode2[i]&2) {
2269               emit_adcimm(-1,th); // x86 has inverted carry flag
2270               emit_not(th,th);
2271             }
2272             #else
2273             if(opcode2[i]&2) {
2274               if(s2h>=0) emit_rscimm(s2h,0,th);
2275               else {
2276                 emit_loadreg(rs2[i]|64,th);
2277                 emit_rscimm(th,0,th);
2278               }
2279             }else{
2280               if(s2h>=0) emit_mov(s2h,th);
2281               else emit_loadreg(rs2[i]|64,th);
2282             }
2283             #endif
2284           }
2285         }
2286         else {
2287           emit_zeroreg(tl);
2288           if(th>=0) emit_zeroreg(th);
2289         }
2290       }
2291     }
2292   }
2293   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2294     if(rt1[i]) {
2295       signed char s1l,s1h,s2l,s2h,t;
2296       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2297       {
2298         t=get_reg(i_regs->regmap,rt1[i]);
2299         //assert(t>=0);
2300         if(t>=0) {
2301           s1l=get_reg(i_regs->regmap,rs1[i]);
2302           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2303           s2l=get_reg(i_regs->regmap,rs2[i]);
2304           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2305           if(rs2[i]==0) // rx<r0
2306           {
2307             assert(s1h>=0);
2308             if(opcode2[i]==0x2a) // SLT
2309               emit_shrimm(s1h,31,t);
2310             else // SLTU (unsigned can not be less than zero)
2311               emit_zeroreg(t);
2312           }
2313           else if(rs1[i]==0) // r0<rx
2314           {
2315             assert(s2h>=0);
2316             if(opcode2[i]==0x2a) // SLT
2317               emit_set_gz64_32(s2h,s2l,t);
2318             else // SLTU (set if not zero)
2319               emit_set_nz64_32(s2h,s2l,t);
2320           }
2321           else {
2322             assert(s1l>=0);assert(s1h>=0);
2323             assert(s2l>=0);assert(s2h>=0);
2324             if(opcode2[i]==0x2a) // SLT
2325               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2326             else // SLTU
2327               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2328           }
2329         }
2330       } else {
2331         t=get_reg(i_regs->regmap,rt1[i]);
2332         //assert(t>=0);
2333         if(t>=0) {
2334           s1l=get_reg(i_regs->regmap,rs1[i]);
2335           s2l=get_reg(i_regs->regmap,rs2[i]);
2336           if(rs2[i]==0) // rx<r0
2337           {
2338             assert(s1l>=0);
2339             if(opcode2[i]==0x2a) // SLT
2340               emit_shrimm(s1l,31,t);
2341             else // SLTU (unsigned can not be less than zero)
2342               emit_zeroreg(t);
2343           }
2344           else if(rs1[i]==0) // r0<rx
2345           {
2346             assert(s2l>=0);
2347             if(opcode2[i]==0x2a) // SLT
2348               emit_set_gz32(s2l,t);
2349             else // SLTU (set if not zero)
2350               emit_set_nz32(s2l,t);
2351           }
2352           else{
2353             assert(s1l>=0);assert(s2l>=0);
2354             if(opcode2[i]==0x2a) // SLT
2355               emit_set_if_less32(s1l,s2l,t);
2356             else // SLTU
2357               emit_set_if_carry32(s1l,s2l,t);
2358           }
2359         }
2360       }
2361     }
2362   }
2363   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2364     if(rt1[i]) {
2365       signed char s1l,s1h,s2l,s2h,th,tl;
2366       tl=get_reg(i_regs->regmap,rt1[i]);
2367       th=get_reg(i_regs->regmap,rt1[i]|64);
2368       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2369       {
2370         assert(tl>=0);
2371         if(tl>=0) {
2372           s1l=get_reg(i_regs->regmap,rs1[i]);
2373           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2374           s2l=get_reg(i_regs->regmap,rs2[i]);
2375           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2376           if(rs1[i]&&rs2[i]) {
2377             assert(s1l>=0);assert(s1h>=0);
2378             assert(s2l>=0);assert(s2h>=0);
2379             if(opcode2[i]==0x24) { // AND
2380               emit_and(s1l,s2l,tl);
2381               emit_and(s1h,s2h,th);
2382             } else
2383             if(opcode2[i]==0x25) { // OR
2384               emit_or(s1l,s2l,tl);
2385               emit_or(s1h,s2h,th);
2386             } else
2387             if(opcode2[i]==0x26) { // XOR
2388               emit_xor(s1l,s2l,tl);
2389               emit_xor(s1h,s2h,th);
2390             } else
2391             if(opcode2[i]==0x27) { // NOR
2392               emit_or(s1l,s2l,tl);
2393               emit_or(s1h,s2h,th);
2394               emit_not(tl,tl);
2395               emit_not(th,th);
2396             }
2397           }
2398           else
2399           {
2400             if(opcode2[i]==0x24) { // AND
2401               emit_zeroreg(tl);
2402               emit_zeroreg(th);
2403             } else
2404             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2405               if(rs1[i]){
2406                 if(s1l>=0) emit_mov(s1l,tl);
2407                 else emit_loadreg(rs1[i],tl);
2408                 if(s1h>=0) emit_mov(s1h,th);
2409                 else emit_loadreg(rs1[i]|64,th);
2410               }
2411               else
2412               if(rs2[i]){
2413                 if(s2l>=0) emit_mov(s2l,tl);
2414                 else emit_loadreg(rs2[i],tl);
2415                 if(s2h>=0) emit_mov(s2h,th);
2416                 else emit_loadreg(rs2[i]|64,th);
2417               }
2418               else{
2419                 emit_zeroreg(tl);
2420                 emit_zeroreg(th);
2421               }
2422             } else
2423             if(opcode2[i]==0x27) { // NOR
2424               if(rs1[i]){
2425                 if(s1l>=0) emit_not(s1l,tl);
2426                 else{
2427                   emit_loadreg(rs1[i],tl);
2428                   emit_not(tl,tl);
2429                 }
2430                 if(s1h>=0) emit_not(s1h,th);
2431                 else{
2432                   emit_loadreg(rs1[i]|64,th);
2433                   emit_not(th,th);
2434                 }
2435               }
2436               else
2437               if(rs2[i]){
2438                 if(s2l>=0) emit_not(s2l,tl);
2439                 else{
2440                   emit_loadreg(rs2[i],tl);
2441                   emit_not(tl,tl);
2442                 }
2443                 if(s2h>=0) emit_not(s2h,th);
2444                 else{
2445                   emit_loadreg(rs2[i]|64,th);
2446                   emit_not(th,th);
2447                 }
2448               }
2449               else {
2450                 emit_movimm(-1,tl);
2451                 emit_movimm(-1,th);
2452               }
2453             }
2454           }
2455         }
2456       }
2457       else
2458       {
2459         // 32 bit
2460         if(tl>=0) {
2461           s1l=get_reg(i_regs->regmap,rs1[i]);
2462           s2l=get_reg(i_regs->regmap,rs2[i]);
2463           if(rs1[i]&&rs2[i]) {
2464             assert(s1l>=0);
2465             assert(s2l>=0);
2466             if(opcode2[i]==0x24) { // AND
2467               emit_and(s1l,s2l,tl);
2468             } else
2469             if(opcode2[i]==0x25) { // OR
2470               emit_or(s1l,s2l,tl);
2471             } else
2472             if(opcode2[i]==0x26) { // XOR
2473               emit_xor(s1l,s2l,tl);
2474             } else
2475             if(opcode2[i]==0x27) { // NOR
2476               emit_or(s1l,s2l,tl);
2477               emit_not(tl,tl);
2478             }
2479           }
2480           else
2481           {
2482             if(opcode2[i]==0x24) { // AND
2483               emit_zeroreg(tl);
2484             } else
2485             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2486               if(rs1[i]){
2487                 if(s1l>=0) emit_mov(s1l,tl);
2488                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2489               }
2490               else
2491               if(rs2[i]){
2492                 if(s2l>=0) emit_mov(s2l,tl);
2493                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2494               }
2495               else emit_zeroreg(tl);
2496             } else
2497             if(opcode2[i]==0x27) { // NOR
2498               if(rs1[i]){
2499                 if(s1l>=0) emit_not(s1l,tl);
2500                 else {
2501                   emit_loadreg(rs1[i],tl);
2502                   emit_not(tl,tl);
2503                 }
2504               }
2505               else
2506               if(rs2[i]){
2507                 if(s2l>=0) emit_not(s2l,tl);
2508                 else {
2509                   emit_loadreg(rs2[i],tl);
2510                   emit_not(tl,tl);
2511                 }
2512               }
2513               else emit_movimm(-1,tl);
2514             }
2515           }
2516         }
2517       }
2518     }
2519   }
2520 }
2521
2522 void imm16_assemble(int i,struct regstat *i_regs)
2523 {
2524   if (opcode[i]==0x0f) { // LUI
2525     if(rt1[i]) {
2526       signed char t;
2527       t=get_reg(i_regs->regmap,rt1[i]);
2528       //assert(t>=0);
2529       if(t>=0) {
2530         if(!((i_regs->isconst>>t)&1))
2531           emit_movimm(imm[i]<<16,t);
2532       }
2533     }
2534   }
2535   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2536     if(rt1[i]) {
2537       signed char s,t;
2538       t=get_reg(i_regs->regmap,rt1[i]);
2539       s=get_reg(i_regs->regmap,rs1[i]);
2540       if(rs1[i]) {
2541         //assert(t>=0);
2542         //assert(s>=0);
2543         if(t>=0) {
2544           if(!((i_regs->isconst>>t)&1)) {
2545             if(s<0) {
2546               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2547               emit_addimm(t,imm[i],t);
2548             }else{
2549               if(!((i_regs->wasconst>>s)&1))
2550                 emit_addimm(s,imm[i],t);
2551               else
2552                 emit_movimm(constmap[i][s]+imm[i],t);
2553             }
2554           }
2555         }
2556       } else {
2557         if(t>=0) {
2558           if(!((i_regs->isconst>>t)&1))
2559             emit_movimm(imm[i],t);
2560         }
2561       }
2562     }
2563   }
2564   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2565     if(rt1[i]) {
2566       signed char sh,sl,th,tl;
2567       th=get_reg(i_regs->regmap,rt1[i]|64);
2568       tl=get_reg(i_regs->regmap,rt1[i]);
2569       sh=get_reg(i_regs->regmap,rs1[i]|64);
2570       sl=get_reg(i_regs->regmap,rs1[i]);
2571       if(tl>=0) {
2572         if(rs1[i]) {
2573           assert(sh>=0);
2574           assert(sl>=0);
2575           if(th>=0) {
2576             emit_addimm64_32(sh,sl,imm[i],th,tl);
2577           }
2578           else {
2579             emit_addimm(sl,imm[i],tl);
2580           }
2581         } else {
2582           emit_movimm(imm[i],tl);
2583           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2584         }
2585       }
2586     }
2587   }
2588   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2589     if(rt1[i]) {
2590       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2591       signed char sh,sl,t;
2592       t=get_reg(i_regs->regmap,rt1[i]);
2593       sh=get_reg(i_regs->regmap,rs1[i]|64);
2594       sl=get_reg(i_regs->regmap,rs1[i]);
2595       //assert(t>=0);
2596       if(t>=0) {
2597         if(rs1[i]>0) {
2598           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2599           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2600             if(opcode[i]==0x0a) { // SLTI
2601               if(sl<0) {
2602                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2603                 emit_slti32(t,imm[i],t);
2604               }else{
2605                 emit_slti32(sl,imm[i],t);
2606               }
2607             }
2608             else { // SLTIU
2609               if(sl<0) {
2610                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2611                 emit_sltiu32(t,imm[i],t);
2612               }else{
2613                 emit_sltiu32(sl,imm[i],t);
2614               }
2615             }
2616           }else{ // 64-bit
2617             assert(sl>=0);
2618             if(opcode[i]==0x0a) // SLTI
2619               emit_slti64_32(sh,sl,imm[i],t);
2620             else // SLTIU
2621               emit_sltiu64_32(sh,sl,imm[i],t);
2622           }
2623         }else{
2624           // SLTI(U) with r0 is just stupid,
2625           // nonetheless examples can be found
2626           if(opcode[i]==0x0a) // SLTI
2627             if(0<imm[i]) emit_movimm(1,t);
2628             else emit_zeroreg(t);
2629           else // SLTIU
2630           {
2631             if(imm[i]) emit_movimm(1,t);
2632             else emit_zeroreg(t);
2633           }
2634         }
2635       }
2636     }
2637   }
2638   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2639     if(rt1[i]) {
2640       signed char sh,sl,th,tl;
2641       th=get_reg(i_regs->regmap,rt1[i]|64);
2642       tl=get_reg(i_regs->regmap,rt1[i]);
2643       sh=get_reg(i_regs->regmap,rs1[i]|64);
2644       sl=get_reg(i_regs->regmap,rs1[i]);
2645       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2646         if(opcode[i]==0x0c) //ANDI
2647         {
2648           if(rs1[i]) {
2649             if(sl<0) {
2650               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2651               emit_andimm(tl,imm[i],tl);
2652             }else{
2653               if(!((i_regs->wasconst>>sl)&1))
2654                 emit_andimm(sl,imm[i],tl);
2655               else
2656                 emit_movimm(constmap[i][sl]&imm[i],tl);
2657             }
2658           }
2659           else
2660             emit_zeroreg(tl);
2661           if(th>=0) emit_zeroreg(th);
2662         }
2663         else
2664         {
2665           if(rs1[i]) {
2666             if(sl<0) {
2667               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2668             }
2669             if(th>=0) {
2670               if(sh<0) {
2671                 emit_loadreg(rs1[i]|64,th);
2672               }else{
2673                 emit_mov(sh,th);
2674               }
2675             }
2676             if(opcode[i]==0x0d) //ORI
2677             if(sl<0) {
2678               emit_orimm(tl,imm[i],tl);
2679             }else{
2680               if(!((i_regs->wasconst>>sl)&1))
2681                 emit_orimm(sl,imm[i],tl);
2682               else
2683                 emit_movimm(constmap[i][sl]|imm[i],tl);
2684             }
2685             if(opcode[i]==0x0e) //XORI
2686             if(sl<0) {
2687               emit_xorimm(tl,imm[i],tl);
2688             }else{
2689               if(!((i_regs->wasconst>>sl)&1))
2690                 emit_xorimm(sl,imm[i],tl);
2691               else
2692                 emit_movimm(constmap[i][sl]^imm[i],tl);
2693             }
2694           }
2695           else {
2696             emit_movimm(imm[i],tl);
2697             if(th>=0) emit_zeroreg(th);
2698           }
2699         }
2700       }
2701     }
2702   }
2703 }
2704
2705 void shiftimm_assemble(int i,struct regstat *i_regs)
2706 {
2707   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2708   {
2709     if(rt1[i]) {
2710       signed char s,t;
2711       t=get_reg(i_regs->regmap,rt1[i]);
2712       s=get_reg(i_regs->regmap,rs1[i]);
2713       //assert(t>=0);
2714       if(t>=0&&!((i_regs->isconst>>t)&1)){
2715         if(rs1[i]==0)
2716         {
2717           emit_zeroreg(t);
2718         }
2719         else
2720         {
2721           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2722           if(imm[i]) {
2723             if(opcode2[i]==0) // SLL
2724             {
2725               emit_shlimm(s<0?t:s,imm[i],t);
2726             }
2727             if(opcode2[i]==2) // SRL
2728             {
2729               emit_shrimm(s<0?t:s,imm[i],t);
2730             }
2731             if(opcode2[i]==3) // SRA
2732             {
2733               emit_sarimm(s<0?t:s,imm[i],t);
2734             }
2735           }else{
2736             // Shift by zero
2737             if(s>=0 && s!=t) emit_mov(s,t);
2738           }
2739         }
2740       }
2741       //emit_storereg(rt1[i],t); //DEBUG
2742     }
2743   }
2744   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2745   {
2746     if(rt1[i]) {
2747       signed char sh,sl,th,tl;
2748       th=get_reg(i_regs->regmap,rt1[i]|64);
2749       tl=get_reg(i_regs->regmap,rt1[i]);
2750       sh=get_reg(i_regs->regmap,rs1[i]|64);
2751       sl=get_reg(i_regs->regmap,rs1[i]);
2752       if(tl>=0) {
2753         if(rs1[i]==0)
2754         {
2755           emit_zeroreg(tl);
2756           if(th>=0) emit_zeroreg(th);
2757         }
2758         else
2759         {
2760           assert(sl>=0);
2761           assert(sh>=0);
2762           if(imm[i]) {
2763             if(opcode2[i]==0x38) // DSLL
2764             {
2765               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2766               emit_shlimm(sl,imm[i],tl);
2767             }
2768             if(opcode2[i]==0x3a) // DSRL
2769             {
2770               emit_shrdimm(sl,sh,imm[i],tl);
2771               if(th>=0) emit_shrimm(sh,imm[i],th);
2772             }
2773             if(opcode2[i]==0x3b) // DSRA
2774             {
2775               emit_shrdimm(sl,sh,imm[i],tl);
2776               if(th>=0) emit_sarimm(sh,imm[i],th);
2777             }
2778           }else{
2779             // Shift by zero
2780             if(sl!=tl) emit_mov(sl,tl);
2781             if(th>=0&&sh!=th) emit_mov(sh,th);
2782           }
2783         }
2784       }
2785     }
2786   }
2787   if(opcode2[i]==0x3c) // DSLL32
2788   {
2789     if(rt1[i]) {
2790       signed char sl,tl,th;
2791       tl=get_reg(i_regs->regmap,rt1[i]);
2792       th=get_reg(i_regs->regmap,rt1[i]|64);
2793       sl=get_reg(i_regs->regmap,rs1[i]);
2794       if(th>=0||tl>=0){
2795         assert(tl>=0);
2796         assert(th>=0);
2797         assert(sl>=0);
2798         emit_mov(sl,th);
2799         emit_zeroreg(tl);
2800         if(imm[i]>32)
2801         {
2802           emit_shlimm(th,imm[i]&31,th);
2803         }
2804       }
2805     }
2806   }
2807   if(opcode2[i]==0x3e) // DSRL32
2808   {
2809     if(rt1[i]) {
2810       signed char sh,tl,th;
2811       tl=get_reg(i_regs->regmap,rt1[i]);
2812       th=get_reg(i_regs->regmap,rt1[i]|64);
2813       sh=get_reg(i_regs->regmap,rs1[i]|64);
2814       if(tl>=0){
2815         assert(sh>=0);
2816         emit_mov(sh,tl);
2817         if(th>=0) emit_zeroreg(th);
2818         if(imm[i]>32)
2819         {
2820           emit_shrimm(tl,imm[i]&31,tl);
2821         }
2822       }
2823     }
2824   }
2825   if(opcode2[i]==0x3f) // DSRA32
2826   {
2827     if(rt1[i]) {
2828       signed char sh,tl;
2829       tl=get_reg(i_regs->regmap,rt1[i]);
2830       sh=get_reg(i_regs->regmap,rs1[i]|64);
2831       if(tl>=0){
2832         assert(sh>=0);
2833         emit_mov(sh,tl);
2834         if(imm[i]>32)
2835         {
2836           emit_sarimm(tl,imm[i]&31,tl);
2837         }
2838       }
2839     }
2840   }
2841 }
2842
2843 #ifndef shift_assemble
2844 void shift_assemble(int i,struct regstat *i_regs)
2845 {
2846   printf("Need shift_assemble for this architecture.\n");
2847   exit(1);
2848 }
2849 #endif
2850
2851 void load_assemble(int i,struct regstat *i_regs)
2852 {
2853   int s,th,tl,addr,map=-1;
2854   int offset;
2855   int jaddr=0;
2856   int memtarget=0,c=0;
2857   int fastload_reg_override=0;
2858   u_int hr,reglist=0;
2859   th=get_reg(i_regs->regmap,rt1[i]|64);
2860   tl=get_reg(i_regs->regmap,rt1[i]);
2861   s=get_reg(i_regs->regmap,rs1[i]);
2862   offset=imm[i];
2863   for(hr=0;hr<HOST_REGS;hr++) {
2864     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2865   }
2866   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2867   if(s>=0) {
2868     c=(i_regs->wasconst>>s)&1;
2869     if (c) {
2870       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2871       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2872     }
2873   }
2874   //printf("load_assemble: c=%d\n",c);
2875   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2876   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2877 #ifdef PCSX
2878   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2879     ||rt1[i]==0) {
2880       // could be FIFO, must perform the read
2881       // ||dummy read
2882       assem_debug("(forced read)\n");
2883       tl=get_reg(i_regs->regmap,-1);
2884       assert(tl>=0);
2885   }
2886 #endif
2887   if(offset||s<0||c) addr=tl;
2888   else addr=s;
2889   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2890  if(tl>=0) {
2891   //printf("load_assemble: c=%d\n",c);
2892   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2893   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2894   reglist&=~(1<<tl);
2895   if(th>=0) reglist&=~(1<<th);
2896   if(!using_tlb) {
2897     if(!c) {
2898       #ifdef RAM_OFFSET
2899       map=get_reg(i_regs->regmap,ROREG);
2900       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2901       #endif
2902 //#define R29_HACK 1
2903       #ifdef R29_HACK
2904       // Strmnnrmn's speed hack
2905       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2906       #endif
2907       {
2908         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2909       }
2910     }
2911   }else{ // using tlb
2912     int x=0;
2913     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2914     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2915     map=get_reg(i_regs->regmap,TLREG);
2916     assert(map>=0);
2917     reglist&=~(1<<map);
2918     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2919     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2920   }
2921   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2922   if (opcode[i]==0x20) { // LB
2923     if(!c||memtarget) {
2924       if(!dummy) {
2925         #ifdef HOST_IMM_ADDR32
2926         if(c)
2927           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2928         else
2929         #endif
2930         {
2931           //emit_xorimm(addr,3,tl);
2932           //gen_tlb_addr_r(tl,map);
2933           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2934           int x=0,a=tl;
2935 #ifdef BIG_ENDIAN_MIPS
2936           if(!c) emit_xorimm(addr,3,tl);
2937           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2938 #else
2939           if(!c) a=addr;
2940 #endif
2941           if(fastload_reg_override) a=fastload_reg_override;
2942
2943           emit_movsbl_indexed_tlb(x,a,map,tl);
2944         }
2945       }
2946       if(jaddr)
2947         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2948     }
2949     else
2950       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2951   }
2952   if (opcode[i]==0x21) { // LH
2953     if(!c||memtarget) {
2954       if(!dummy) {
2955         #ifdef HOST_IMM_ADDR32
2956         if(c)
2957           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2958         else
2959         #endif
2960         {
2961           int x=0,a=tl;
2962 #ifdef BIG_ENDIAN_MIPS
2963           if(!c) emit_xorimm(addr,2,tl);
2964           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2965 #else
2966           if(!c) a=addr;
2967 #endif
2968           if(fastload_reg_override) a=fastload_reg_override;
2969           //#ifdef
2970           //emit_movswl_indexed_tlb(x,tl,map,tl);
2971           //else
2972           if(map>=0) {
2973             gen_tlb_addr_r(a,map);
2974             emit_movswl_indexed(x,a,tl);
2975           }else{
2976             #ifdef RAM_OFFSET
2977             emit_movswl_indexed(x,a,tl);
2978             #else
2979             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2980             #endif
2981           }
2982         }
2983       }
2984       if(jaddr)
2985         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2986     }
2987     else
2988       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2989   }
2990   if (opcode[i]==0x23) { // LW
2991     if(!c||memtarget) {
2992       if(!dummy) {
2993         int a=addr;
2994         if(fastload_reg_override) a=fastload_reg_override;
2995         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2996         #ifdef HOST_IMM_ADDR32
2997         if(c)
2998           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2999         else
3000         #endif
3001         emit_readword_indexed_tlb(0,a,map,tl);
3002       }
3003       if(jaddr)
3004         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3005     }
3006     else
3007       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3008   }
3009   if (opcode[i]==0x24) { // LBU
3010     if(!c||memtarget) {
3011       if(!dummy) {
3012         #ifdef HOST_IMM_ADDR32
3013         if(c)
3014           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3015         else
3016         #endif
3017         {
3018           //emit_xorimm(addr,3,tl);
3019           //gen_tlb_addr_r(tl,map);
3020           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3021           int x=0,a=tl;
3022 #ifdef BIG_ENDIAN_MIPS
3023           if(!c) emit_xorimm(addr,3,tl);
3024           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3025 #else
3026           if(!c) a=addr;
3027 #endif
3028           if(fastload_reg_override) a=fastload_reg_override;
3029
3030           emit_movzbl_indexed_tlb(x,a,map,tl);
3031         }
3032       }
3033       if(jaddr)
3034         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3035     }
3036     else
3037       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3038   }
3039   if (opcode[i]==0x25) { // LHU
3040     if(!c||memtarget) {
3041       if(!dummy) {
3042         #ifdef HOST_IMM_ADDR32
3043         if(c)
3044           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3045         else
3046         #endif
3047         {
3048           int x=0,a=tl;
3049 #ifdef BIG_ENDIAN_MIPS
3050           if(!c) emit_xorimm(addr,2,tl);
3051           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3052 #else
3053           if(!c) a=addr;
3054 #endif
3055           if(fastload_reg_override) a=fastload_reg_override;
3056           //#ifdef
3057           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3058           //#else
3059           if(map>=0) {
3060             gen_tlb_addr_r(a,map);
3061             emit_movzwl_indexed(x,a,tl);
3062           }else{
3063             #ifdef RAM_OFFSET
3064             emit_movzwl_indexed(x,a,tl);
3065             #else
3066             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3067             #endif
3068           }
3069         }
3070       }
3071       if(jaddr)
3072         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3073     }
3074     else
3075       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3076   }
3077   if (opcode[i]==0x27) { // LWU
3078     assert(th>=0);
3079     if(!c||memtarget) {
3080       if(!dummy) {
3081         int a=addr;
3082         if(fastload_reg_override) a=fastload_reg_override;
3083         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3084         #ifdef HOST_IMM_ADDR32
3085         if(c)
3086           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3087         else
3088         #endif
3089         emit_readword_indexed_tlb(0,a,map,tl);
3090       }
3091       if(jaddr)
3092         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3093     }
3094     else {
3095       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3096     }
3097     emit_zeroreg(th);
3098   }
3099   if (opcode[i]==0x37) { // LD
3100     if(!c||memtarget) {
3101       if(!dummy) {
3102         int a=addr;
3103         if(fastload_reg_override) a=fastload_reg_override;
3104         //gen_tlb_addr_r(tl,map);
3105         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3106         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3107         #ifdef HOST_IMM_ADDR32
3108         if(c)
3109           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3110         else
3111         #endif
3112         emit_readdword_indexed_tlb(0,a,map,th,tl);
3113       }
3114       if(jaddr)
3115         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3116     }
3117     else
3118       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3119   }
3120  }
3121   //emit_storereg(rt1[i],tl); // DEBUG
3122   //if(opcode[i]==0x23)
3123   //if(opcode[i]==0x24)
3124   //if(opcode[i]==0x23||opcode[i]==0x24)
3125   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3126   {
3127     //emit_pusha();
3128     save_regs(0x100f);
3129         emit_readword((int)&last_count,ECX);
3130         #ifdef __i386__
3131         if(get_reg(i_regs->regmap,CCREG)<0)
3132           emit_loadreg(CCREG,HOST_CCREG);
3133         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3134         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3135         emit_writeword(HOST_CCREG,(int)&Count);
3136         #endif
3137         #ifdef __arm__
3138         if(get_reg(i_regs->regmap,CCREG)<0)
3139           emit_loadreg(CCREG,0);
3140         else
3141           emit_mov(HOST_CCREG,0);
3142         emit_add(0,ECX,0);
3143         emit_addimm(0,2*ccadj[i],0);
3144         emit_writeword(0,(int)&Count);
3145         #endif
3146     emit_call((int)memdebug);
3147     //emit_popa();
3148     restore_regs(0x100f);
3149   }/**/
3150 }
3151
3152 #ifndef loadlr_assemble
3153 void loadlr_assemble(int i,struct regstat *i_regs)
3154 {
3155   printf("Need loadlr_assemble for this architecture.\n");
3156   exit(1);
3157 }
3158 #endif
3159
3160 void store_assemble(int i,struct regstat *i_regs)
3161 {
3162   int s,th,tl,map=-1;
3163   int addr,temp;
3164   int offset;
3165   int jaddr=0,jaddr2,type;
3166   int memtarget=0,c=0;
3167   int agr=AGEN1+(i&1);
3168   int faststore_reg_override=0;
3169   u_int hr,reglist=0;
3170   th=get_reg(i_regs->regmap,rs2[i]|64);
3171   tl=get_reg(i_regs->regmap,rs2[i]);
3172   s=get_reg(i_regs->regmap,rs1[i]);
3173   temp=get_reg(i_regs->regmap,agr);
3174   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3175   offset=imm[i];
3176   if(s>=0) {
3177     c=(i_regs->wasconst>>s)&1;
3178     if(c) {
3179       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3180       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3181     }
3182   }
3183   assert(tl>=0);
3184   assert(temp>=0);
3185   for(hr=0;hr<HOST_REGS;hr++) {
3186     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3187   }
3188   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3189   if(offset||s<0||c) addr=temp;
3190   else addr=s;
3191   if(!using_tlb) {
3192     if(!c) {
3193       #ifndef PCSX
3194       #ifdef R29_HACK
3195       // Strmnnrmn's speed hack
3196       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3197       #endif
3198       emit_cmpimm(addr,RAM_SIZE);
3199       #ifdef DESTRUCTIVE_SHIFT
3200       if(s==addr) emit_mov(s,temp);
3201       #endif
3202       #ifdef R29_HACK
3203       memtarget=1;
3204       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3205       #endif
3206       {
3207         jaddr=(int)out;
3208         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3209         // Hint to branch predictor that the branch is unlikely to be taken
3210         if(rs1[i]>=28)
3211           emit_jno_unlikely(0);
3212         else
3213         #endif
3214         emit_jno(0);
3215       }
3216       #else
3217         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3218       #endif
3219     }
3220   }else{ // using tlb
3221     int x=0;
3222     if (opcode[i]==0x28) x=3; // SB
3223     if (opcode[i]==0x29) x=2; // SH
3224     map=get_reg(i_regs->regmap,TLREG);
3225     assert(map>=0);
3226     reglist&=~(1<<map);
3227     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3228     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3229   }
3230
3231   if (opcode[i]==0x28) { // SB
3232     if(!c||memtarget) {
3233       int x=0,a=temp;
3234 #ifdef BIG_ENDIAN_MIPS
3235       if(!c) emit_xorimm(addr,3,temp);
3236       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3237 #else
3238       if(!c) a=addr;
3239 #endif
3240       if(faststore_reg_override) a=faststore_reg_override;
3241       //gen_tlb_addr_w(temp,map);
3242       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3243       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3244     }
3245     type=STOREB_STUB;
3246   }
3247   if (opcode[i]==0x29) { // SH
3248     if(!c||memtarget) {
3249       int x=0,a=temp;
3250 #ifdef BIG_ENDIAN_MIPS
3251       if(!c) emit_xorimm(addr,2,temp);
3252       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3253 #else
3254       if(!c) a=addr;
3255 #endif
3256       if(faststore_reg_override) a=faststore_reg_override;
3257       //#ifdef
3258       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3259       //#else
3260       if(map>=0) {
3261         gen_tlb_addr_w(a,map);
3262         emit_writehword_indexed(tl,x,a);
3263       }else
3264         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3265     }
3266     type=STOREH_STUB;
3267   }
3268   if (opcode[i]==0x2B) { // SW
3269     if(!c||memtarget) {
3270       int a=addr;
3271       if(faststore_reg_override) a=faststore_reg_override;
3272       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3273       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3274     }
3275     type=STOREW_STUB;
3276   }
3277   if (opcode[i]==0x3F) { // SD
3278     if(!c||memtarget) {
3279       int a=addr;
3280       if(faststore_reg_override) a=faststore_reg_override;
3281       if(rs2[i]) {
3282         assert(th>=0);
3283         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3284         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3285         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3286       }else{
3287         // Store zero
3288         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3289         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3290         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3291       }
3292     }
3293     type=STORED_STUB;
3294   }
3295 #ifdef PCSX
3296   if(jaddr) {
3297     // PCSX store handlers don't check invcode again
3298     reglist|=1<<addr;
3299     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3300     jaddr=0;
3301   }
3302 #endif
3303   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3304     if(!c||memtarget) {
3305       #ifdef DESTRUCTIVE_SHIFT
3306       // The x86 shift operation is 'destructive'; it overwrites the
3307       // source register, so we need to make a copy first and use that.
3308       addr=temp;
3309       #endif
3310       #if defined(HOST_IMM8)
3311       int ir=get_reg(i_regs->regmap,INVCP);
3312       assert(ir>=0);
3313       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3314       #else
3315       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3316       #endif
3317       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3318       emit_callne(invalidate_addr_reg[addr]);
3319       #else
3320       jaddr2=(int)out;
3321       emit_jne(0);
3322       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3323       #endif
3324     }
3325   }
3326   if(jaddr) {
3327     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3328   } else if(c&&!memtarget) {
3329     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3330   }
3331   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3332   //if(opcode[i]==0x2B || opcode[i]==0x28)
3333   //if(opcode[i]==0x2B || opcode[i]==0x29)
3334   //if(opcode[i]==0x2B)
3335   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3336   {
3337     #ifdef __i386__
3338     emit_pusha();
3339     #endif
3340     #ifdef __arm__
3341     save_regs(0x100f);
3342     #endif
3343         emit_readword((int)&last_count,ECX);
3344         #ifdef __i386__
3345         if(get_reg(i_regs->regmap,CCREG)<0)
3346           emit_loadreg(CCREG,HOST_CCREG);
3347         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3348         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3349         emit_writeword(HOST_CCREG,(int)&Count);
3350         #endif
3351         #ifdef __arm__
3352         if(get_reg(i_regs->regmap,CCREG)<0)
3353           emit_loadreg(CCREG,0);
3354         else
3355           emit_mov(HOST_CCREG,0);
3356         emit_add(0,ECX,0);
3357         emit_addimm(0,2*ccadj[i],0);
3358         emit_writeword(0,(int)&Count);
3359         #endif
3360     emit_call((int)memdebug);
3361     #ifdef __i386__
3362     emit_popa();
3363     #endif
3364     #ifdef __arm__
3365     restore_regs(0x100f);
3366     #endif
3367   }/**/
3368 }
3369
3370 void storelr_assemble(int i,struct regstat *i_regs)
3371 {
3372   int s,th,tl;
3373   int temp;
3374   int temp2;
3375   int offset;
3376   int jaddr=0,jaddr2;
3377   int case1,case2,case3;
3378   int done0,done1,done2;
3379   int memtarget=0,c=0;
3380   int agr=AGEN1+(i&1);
3381   u_int hr,reglist=0;
3382   th=get_reg(i_regs->regmap,rs2[i]|64);
3383   tl=get_reg(i_regs->regmap,rs2[i]);
3384   s=get_reg(i_regs->regmap,rs1[i]);
3385   temp=get_reg(i_regs->regmap,agr);
3386   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3387   offset=imm[i];
3388   if(s>=0) {
3389     c=(i_regs->isconst>>s)&1;
3390     if(c) {
3391       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3392       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3393     }
3394   }
3395   assert(tl>=0);
3396   for(hr=0;hr<HOST_REGS;hr++) {
3397     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3398   }
3399   assert(temp>=0);
3400   if(!using_tlb) {
3401     if(!c) {
3402       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3403       if(!offset&&s!=temp) emit_mov(s,temp);
3404       jaddr=(int)out;
3405       emit_jno(0);
3406     }
3407     else
3408     {
3409       if(!memtarget||!rs1[i]) {
3410         jaddr=(int)out;
3411         emit_jmp(0);
3412       }
3413     }
3414     #ifdef RAM_OFFSET
3415     int map=get_reg(i_regs->regmap,ROREG);
3416     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3417     gen_tlb_addr_w(temp,map);
3418     #else
3419     if((u_int)rdram!=0x80000000)
3420       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3421     #endif
3422   }else{ // using tlb
3423     int map=get_reg(i_regs->regmap,TLREG);
3424     assert(map>=0);
3425     reglist&=~(1<<map);
3426     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3427     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3428     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3429     if(!jaddr&&!memtarget) {
3430       jaddr=(int)out;
3431       emit_jmp(0);
3432     }
3433     gen_tlb_addr_w(temp,map);
3434   }
3435
3436   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3437     temp2=get_reg(i_regs->regmap,FTEMP);
3438     if(!rs2[i]) temp2=th=tl;
3439   }
3440
3441 #ifndef BIG_ENDIAN_MIPS
3442     emit_xorimm(temp,3,temp);
3443 #endif
3444   emit_testimm(temp,2);
3445   case2=(int)out;
3446   emit_jne(0);
3447   emit_testimm(temp,1);
3448   case1=(int)out;
3449   emit_jne(0);
3450   // 0
3451   if (opcode[i]==0x2A) { // SWL
3452     emit_writeword_indexed(tl,0,temp);
3453   }
3454   if (opcode[i]==0x2E) { // SWR
3455     emit_writebyte_indexed(tl,3,temp);
3456   }
3457   if (opcode[i]==0x2C) { // SDL
3458     emit_writeword_indexed(th,0,temp);
3459     if(rs2[i]) emit_mov(tl,temp2);
3460   }
3461   if (opcode[i]==0x2D) { // SDR
3462     emit_writebyte_indexed(tl,3,temp);
3463     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3464   }
3465   done0=(int)out;
3466   emit_jmp(0);
3467   // 1
3468   set_jump_target(case1,(int)out);
3469   if (opcode[i]==0x2A) { // SWL
3470     // Write 3 msb into three least significant bytes
3471     if(rs2[i]) emit_rorimm(tl,8,tl);
3472     emit_writehword_indexed(tl,-1,temp);
3473     if(rs2[i]) emit_rorimm(tl,16,tl);
3474     emit_writebyte_indexed(tl,1,temp);
3475     if(rs2[i]) emit_rorimm(tl,8,tl);
3476   }
3477   if (opcode[i]==0x2E) { // SWR
3478     // Write two lsb into two most significant bytes
3479     emit_writehword_indexed(tl,1,temp);
3480   }
3481   if (opcode[i]==0x2C) { // SDL
3482     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3483     // Write 3 msb into three least significant bytes
3484     if(rs2[i]) emit_rorimm(th,8,th);
3485     emit_writehword_indexed(th,-1,temp);
3486     if(rs2[i]) emit_rorimm(th,16,th);
3487     emit_writebyte_indexed(th,1,temp);
3488     if(rs2[i]) emit_rorimm(th,8,th);
3489   }
3490   if (opcode[i]==0x2D) { // SDR
3491     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3492     // Write two lsb into two most significant bytes
3493     emit_writehword_indexed(tl,1,temp);
3494   }
3495   done1=(int)out;
3496   emit_jmp(0);
3497   // 2
3498   set_jump_target(case2,(int)out);
3499   emit_testimm(temp,1);
3500   case3=(int)out;
3501   emit_jne(0);
3502   if (opcode[i]==0x2A) { // SWL
3503     // Write two msb into two least significant bytes
3504     if(rs2[i]) emit_rorimm(tl,16,tl);
3505     emit_writehword_indexed(tl,-2,temp);
3506     if(rs2[i]) emit_rorimm(tl,16,tl);
3507   }
3508   if (opcode[i]==0x2E) { // SWR
3509     // Write 3 lsb into three most significant bytes
3510     emit_writebyte_indexed(tl,-1,temp);
3511     if(rs2[i]) emit_rorimm(tl,8,tl);
3512     emit_writehword_indexed(tl,0,temp);
3513     if(rs2[i]) emit_rorimm(tl,24,tl);
3514   }
3515   if (opcode[i]==0x2C) { // SDL
3516     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3517     // Write two msb into two least significant bytes
3518     if(rs2[i]) emit_rorimm(th,16,th);
3519     emit_writehword_indexed(th,-2,temp);
3520     if(rs2[i]) emit_rorimm(th,16,th);
3521   }
3522   if (opcode[i]==0x2D) { // SDR
3523     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3524     // Write 3 lsb into three most significant bytes
3525     emit_writebyte_indexed(tl,-1,temp);
3526     if(rs2[i]) emit_rorimm(tl,8,tl);
3527     emit_writehword_indexed(tl,0,temp);
3528     if(rs2[i]) emit_rorimm(tl,24,tl);
3529   }
3530   done2=(int)out;
3531   emit_jmp(0);
3532   // 3
3533   set_jump_target(case3,(int)out);
3534   if (opcode[i]==0x2A) { // SWL
3535     // Write msb into least significant byte
3536     if(rs2[i]) emit_rorimm(tl,24,tl);
3537     emit_writebyte_indexed(tl,-3,temp);
3538     if(rs2[i]) emit_rorimm(tl,8,tl);
3539   }
3540   if (opcode[i]==0x2E) { // SWR
3541     // Write entire word
3542     emit_writeword_indexed(tl,-3,temp);
3543   }
3544   if (opcode[i]==0x2C) { // SDL
3545     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3546     // Write msb into least significant byte
3547     if(rs2[i]) emit_rorimm(th,24,th);
3548     emit_writebyte_indexed(th,-3,temp);
3549     if(rs2[i]) emit_rorimm(th,8,th);
3550   }
3551   if (opcode[i]==0x2D) { // SDR
3552     if(rs2[i]) emit_mov(th,temp2);
3553     // Write entire word
3554     emit_writeword_indexed(tl,-3,temp);
3555   }
3556   set_jump_target(done0,(int)out);
3557   set_jump_target(done1,(int)out);
3558   set_jump_target(done2,(int)out);
3559   if (opcode[i]==0x2C) { // SDL
3560     emit_testimm(temp,4);
3561     done0=(int)out;
3562     emit_jne(0);
3563     emit_andimm(temp,~3,temp);
3564     emit_writeword_indexed(temp2,4,temp);
3565     set_jump_target(done0,(int)out);
3566   }
3567   if (opcode[i]==0x2D) { // SDR
3568     emit_testimm(temp,4);
3569     done0=(int)out;
3570     emit_jeq(0);
3571     emit_andimm(temp,~3,temp);
3572     emit_writeword_indexed(temp2,-4,temp);
3573     set_jump_target(done0,(int)out);
3574   }
3575   if(!c||!memtarget)
3576     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3577   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3578     #ifdef RAM_OFFSET
3579     int map=get_reg(i_regs->regmap,ROREG);
3580     if(map<0) map=HOST_TEMPREG;
3581     gen_orig_addr_w(temp,map);
3582     #else
3583     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3584     #endif
3585     #if defined(HOST_IMM8)
3586     int ir=get_reg(i_regs->regmap,INVCP);
3587     assert(ir>=0);
3588     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3589     #else
3590     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3591     #endif
3592     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3593     emit_callne(invalidate_addr_reg[temp]);
3594     #else
3595     jaddr2=(int)out;
3596     emit_jne(0);
3597     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3598     #endif
3599   }
3600   /*
3601     emit_pusha();
3602     //save_regs(0x100f);
3603         emit_readword((int)&last_count,ECX);
3604         if(get_reg(i_regs->regmap,CCREG)<0)
3605           emit_loadreg(CCREG,HOST_CCREG);
3606         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3607         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3608         emit_writeword(HOST_CCREG,(int)&Count);
3609     emit_call((int)memdebug);
3610     emit_popa();
3611     //restore_regs(0x100f);
3612   /**/
3613 }
3614
3615 void c1ls_assemble(int i,struct regstat *i_regs)
3616 {
3617 #ifndef DISABLE_COP1
3618   int s,th,tl;
3619   int temp,ar;
3620   int map=-1;
3621   int offset;
3622   int c=0;
3623   int jaddr,jaddr2=0,jaddr3,type;
3624   int agr=AGEN1+(i&1);
3625   u_int hr,reglist=0;
3626   th=get_reg(i_regs->regmap,FTEMP|64);
3627   tl=get_reg(i_regs->regmap,FTEMP);
3628   s=get_reg(i_regs->regmap,rs1[i]);
3629   temp=get_reg(i_regs->regmap,agr);
3630   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3631   offset=imm[i];
3632   assert(tl>=0);
3633   assert(rs1[i]>0);
3634   assert(temp>=0);
3635   for(hr=0;hr<HOST_REGS;hr++) {
3636     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3637   }
3638   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3639   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3640   {
3641     // Loads use a temporary register which we need to save
3642     reglist|=1<<temp;
3643   }
3644   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3645     ar=temp;
3646   else // LWC1/LDC1
3647     ar=tl;
3648   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3649   //else c=(i_regs->wasconst>>s)&1;
3650   if(s>=0) c=(i_regs->wasconst>>s)&1;
3651   // Check cop1 unusable
3652   if(!cop1_usable) {
3653     signed char rs=get_reg(i_regs->regmap,CSREG);
3654     assert(rs>=0);
3655     emit_testimm(rs,0x20000000);
3656     jaddr=(int)out;
3657     emit_jeq(0);
3658     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3659     cop1_usable=1;
3660   }
3661   if (opcode[i]==0x39) { // SWC1 (get float address)
3662     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3663   }
3664   if (opcode[i]==0x3D) { // SDC1 (get double address)
3665     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3666   }
3667   // Generate address + offset
3668   if(!using_tlb) {
3669     if(!c)
3670       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3671   }
3672   else
3673   {
3674     map=get_reg(i_regs->regmap,TLREG);
3675     assert(map>=0);
3676     reglist&=~(1<<map);
3677     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3678       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3679     }
3680     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3681       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3682     }
3683   }
3684   if (opcode[i]==0x39) { // SWC1 (read float)
3685     emit_readword_indexed(0,tl,tl);
3686   }
3687   if (opcode[i]==0x3D) { // SDC1 (read double)
3688     emit_readword_indexed(4,tl,th);
3689     emit_readword_indexed(0,tl,tl);
3690   }
3691   if (opcode[i]==0x31) { // LWC1 (get target address)
3692     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3693   }
3694   if (opcode[i]==0x35) { // LDC1 (get target address)
3695     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3696   }
3697   if(!using_tlb) {
3698     if(!c) {
3699       jaddr2=(int)out;
3700       emit_jno(0);
3701     }
3702     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3703       jaddr2=(int)out;
3704       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3705     }
3706     #ifdef DESTRUCTIVE_SHIFT
3707     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3708       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3709     }
3710     #endif
3711   }else{
3712     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3713       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3714     }
3715     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3716       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3717     }
3718   }
3719   if (opcode[i]==0x31) { // LWC1
3720     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3721     //gen_tlb_addr_r(ar,map);
3722     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3723     #ifdef HOST_IMM_ADDR32
3724     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3725     else
3726     #endif
3727     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3728     type=LOADW_STUB;
3729   }
3730   if (opcode[i]==0x35) { // LDC1
3731     assert(th>=0);
3732     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3733     //gen_tlb_addr_r(ar,map);
3734     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3735     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3736     #ifdef HOST_IMM_ADDR32
3737     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3738     else
3739     #endif
3740     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3741     type=LOADD_STUB;
3742   }
3743   if (opcode[i]==0x39) { // SWC1
3744     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3745     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3746     type=STOREW_STUB;
3747   }
3748   if (opcode[i]==0x3D) { // SDC1
3749     assert(th>=0);
3750     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3751     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3752     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3753     type=STORED_STUB;
3754   }
3755   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3756     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3757       #ifndef DESTRUCTIVE_SHIFT
3758       temp=offset||c||s<0?ar:s;
3759       #endif
3760       #if defined(HOST_IMM8)
3761       int ir=get_reg(i_regs->regmap,INVCP);
3762       assert(ir>=0);
3763       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3764       #else
3765       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3766       #endif
3767       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3768       emit_callne(invalidate_addr_reg[temp]);
3769       #else
3770       jaddr3=(int)out;
3771       emit_jne(0);
3772       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3773       #endif
3774     }
3775   }
3776   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3777   if (opcode[i]==0x31) { // LWC1 (write float)
3778     emit_writeword_indexed(tl,0,temp);
3779   }
3780   if (opcode[i]==0x35) { // LDC1 (write double)
3781     emit_writeword_indexed(th,4,temp);
3782     emit_writeword_indexed(tl,0,temp);
3783   }
3784   //if(opcode[i]==0x39)
3785   /*if(opcode[i]==0x39||opcode[i]==0x31)
3786   {
3787     emit_pusha();
3788         emit_readword((int)&last_count,ECX);
3789         if(get_reg(i_regs->regmap,CCREG)<0)
3790           emit_loadreg(CCREG,HOST_CCREG);
3791         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3792         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3793         emit_writeword(HOST_CCREG,(int)&Count);
3794     emit_call((int)memdebug);
3795     emit_popa();
3796   }/**/
3797 #else
3798   cop1_unusable(i, i_regs);
3799 #endif
3800 }
3801
3802 void c2ls_assemble(int i,struct regstat *i_regs)
3803 {
3804   int s,tl;
3805   int ar;
3806   int offset;
3807   int memtarget=0,c=0;
3808   int jaddr2=0,jaddr3,type;
3809   int agr=AGEN1+(i&1);
3810   int fastio_reg_override=0;
3811   u_int hr,reglist=0;
3812   u_int copr=(source[i]>>16)&0x1f;
3813   s=get_reg(i_regs->regmap,rs1[i]);
3814   tl=get_reg(i_regs->regmap,FTEMP);
3815   offset=imm[i];
3816   assert(rs1[i]>0);
3817   assert(tl>=0);
3818   assert(!using_tlb);
3819
3820   for(hr=0;hr<HOST_REGS;hr++) {
3821     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3822   }
3823   if(i_regs->regmap[HOST_CCREG]==CCREG)
3824     reglist&=~(1<<HOST_CCREG);
3825
3826   // get the address
3827   if (opcode[i]==0x3a) { // SWC2
3828     ar=get_reg(i_regs->regmap,agr);
3829     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3830     reglist|=1<<ar;
3831   } else { // LWC2
3832     ar=tl;
3833   }
3834   if(s>=0) c=(i_regs->wasconst>>s)&1;
3835   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3836   if (!offset&&!c&&s>=0) ar=s;
3837   assert(ar>=0);
3838
3839   if (opcode[i]==0x3a) { // SWC2
3840     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3841     type=STOREW_STUB;
3842   }
3843   else
3844     type=LOADW_STUB;
3845
3846   if(c&&!memtarget) {
3847     jaddr2=(int)out;
3848     emit_jmp(0); // inline_readstub/inline_writestub?
3849   }
3850   else {
3851     if(!c) {
3852       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3853     }
3854     if (opcode[i]==0x32) { // LWC2
3855       #ifdef HOST_IMM_ADDR32
3856       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3857       else
3858       #endif
3859       int a=ar;
3860       if(fastio_reg_override) a=fastio_reg_override;
3861       emit_readword_indexed(0,a,tl);
3862     }
3863     if (opcode[i]==0x3a) { // SWC2
3864       #ifdef DESTRUCTIVE_SHIFT
3865       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3866       #endif
3867       int a=ar;
3868       if(fastio_reg_override) a=fastio_reg_override;
3869       emit_writeword_indexed(tl,0,a);
3870     }
3871   }
3872   if(jaddr2)
3873     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3874   if(opcode[i]==0x3a) // SWC2
3875   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3876 #if defined(HOST_IMM8)
3877     int ir=get_reg(i_regs->regmap,INVCP);
3878     assert(ir>=0);
3879     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3880 #else
3881     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3882 #endif
3883     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3884     emit_callne(invalidate_addr_reg[ar]);
3885     #else
3886     jaddr3=(int)out;
3887     emit_jne(0);
3888     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3889     #endif
3890   }
3891   if (opcode[i]==0x32) { // LWC2
3892     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3893   }
3894 }
3895
3896 #ifndef multdiv_assemble
3897 void multdiv_assemble(int i,struct regstat *i_regs)
3898 {
3899   printf("Need multdiv_assemble for this architecture.\n");
3900   exit(1);
3901 }
3902 #endif
3903
3904 void mov_assemble(int i,struct regstat *i_regs)
3905 {
3906   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3907   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3908   if(rt1[i]) {
3909     signed char sh,sl,th,tl;
3910     th=get_reg(i_regs->regmap,rt1[i]|64);
3911     tl=get_reg(i_regs->regmap,rt1[i]);
3912     //assert(tl>=0);
3913     if(tl>=0) {
3914       sh=get_reg(i_regs->regmap,rs1[i]|64);
3915       sl=get_reg(i_regs->regmap,rs1[i]);
3916       if(sl>=0) emit_mov(sl,tl);
3917       else emit_loadreg(rs1[i],tl);
3918       if(th>=0) {
3919         if(sh>=0) emit_mov(sh,th);
3920         else emit_loadreg(rs1[i]|64,th);
3921       }
3922     }
3923   }
3924 }
3925
3926 #ifndef fconv_assemble
3927 void fconv_assemble(int i,struct regstat *i_regs)
3928 {
3929   printf("Need fconv_assemble for this architecture.\n");
3930   exit(1);
3931 }
3932 #endif
3933
3934 #if 0
3935 void float_assemble(int i,struct regstat *i_regs)
3936 {
3937   printf("Need float_assemble for this architecture.\n");
3938   exit(1);
3939 }
3940 #endif
3941
3942 void syscall_assemble(int i,struct regstat *i_regs)
3943 {
3944   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3945   assert(ccreg==HOST_CCREG);
3946   assert(!is_delayslot);
3947   emit_movimm(start+i*4,EAX); // Get PC
3948   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3949   emit_jmp((int)jump_syscall_hle); // XXX
3950 }
3951
3952 void hlecall_assemble(int i,struct regstat *i_regs)
3953 {
3954   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3955   assert(ccreg==HOST_CCREG);
3956   assert(!is_delayslot);
3957   emit_movimm(start+i*4+4,0); // Get PC
3958   emit_movimm((int)psxHLEt[source[i]&7],1);
3959   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3960   emit_jmp((int)jump_hlecall);
3961 }
3962
3963 void intcall_assemble(int i,struct regstat *i_regs)
3964 {
3965   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3966   assert(ccreg==HOST_CCREG);
3967   assert(!is_delayslot);
3968   emit_movimm(start+i*4,0); // Get PC
3969   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3970   emit_jmp((int)jump_intcall);
3971 }
3972
3973 void ds_assemble(int i,struct regstat *i_regs)
3974 {
3975   speculate_register_values(i);
3976   is_delayslot=1;
3977   switch(itype[i]) {
3978     case ALU:
3979       alu_assemble(i,i_regs);break;
3980     case IMM16:
3981       imm16_assemble(i,i_regs);break;
3982     case SHIFT:
3983       shift_assemble(i,i_regs);break;
3984     case SHIFTIMM:
3985       shiftimm_assemble(i,i_regs);break;
3986     case LOAD:
3987       load_assemble(i,i_regs);break;
3988     case LOADLR:
3989       loadlr_assemble(i,i_regs);break;
3990     case STORE:
3991       store_assemble(i,i_regs);break;
3992     case STORELR:
3993       storelr_assemble(i,i_regs);break;
3994     case COP0:
3995       cop0_assemble(i,i_regs);break;
3996     case COP1:
3997       cop1_assemble(i,i_regs);break;
3998     case C1LS:
3999       c1ls_assemble(i,i_regs);break;
4000     case COP2:
4001       cop2_assemble(i,i_regs);break;
4002     case C2LS:
4003       c2ls_assemble(i,i_regs);break;
4004     case C2OP:
4005       c2op_assemble(i,i_regs);break;
4006     case FCONV:
4007       fconv_assemble(i,i_regs);break;
4008     case FLOAT:
4009       float_assemble(i,i_regs);break;
4010     case FCOMP:
4011       fcomp_assemble(i,i_regs);break;
4012     case MULTDIV:
4013       multdiv_assemble(i,i_regs);break;
4014     case MOV:
4015       mov_assemble(i,i_regs);break;
4016     case SYSCALL:
4017     case HLECALL:
4018     case INTCALL:
4019     case SPAN:
4020     case UJUMP:
4021     case RJUMP:
4022     case CJUMP:
4023     case SJUMP:
4024     case FJUMP:
4025       printf("Jump in the delay slot.  This is probably a bug.\n");
4026   }
4027   is_delayslot=0;
4028 }
4029
4030 // Is the branch target a valid internal jump?
4031 int internal_branch(uint64_t i_is32,int addr)
4032 {
4033   if(addr&1) return 0; // Indirect (register) jump
4034   if(addr>=start && addr<start+slen*4-4)
4035   {
4036     int t=(addr-start)>>2;
4037     // Delay slots are not valid branch targets
4038     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4039     // 64 -> 32 bit transition requires a recompile
4040     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4041     {
4042       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4043       else printf("optimizable: yes\n");
4044     }*/
4045     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4046 #ifndef FORCE32
4047     if(requires_32bit[t]&~i_is32) return 0;
4048     else
4049 #endif
4050       return 1;
4051   }
4052   return 0;
4053 }
4054
4055 #ifndef wb_invalidate
4056 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4057   uint64_t u,uint64_t uu)
4058 {
4059   int hr;
4060   for(hr=0;hr<HOST_REGS;hr++) {
4061     if(hr!=EXCLUDE_REG) {
4062       if(pre[hr]!=entry[hr]) {
4063         if(pre[hr]>=0) {
4064           if((dirty>>hr)&1) {
4065             if(get_reg(entry,pre[hr])<0) {
4066               if(pre[hr]<64) {
4067                 if(!((u>>pre[hr])&1)) {
4068                   emit_storereg(pre[hr],hr);
4069                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4070                     emit_sarimm(hr,31,hr);
4071                     emit_storereg(pre[hr]|64,hr);
4072                   }
4073                 }
4074               }else{
4075                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4076                   emit_storereg(pre[hr],hr);
4077                 }
4078               }
4079             }
4080           }
4081         }
4082       }
4083     }
4084   }
4085   // Move from one register to another (no writeback)
4086   for(hr=0;hr<HOST_REGS;hr++) {
4087     if(hr!=EXCLUDE_REG) {
4088       if(pre[hr]!=entry[hr]) {
4089         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4090           int nr;
4091           if((nr=get_reg(entry,pre[hr]))>=0) {
4092             emit_mov(hr,nr);
4093           }
4094         }
4095       }
4096     }
4097   }
4098 }
4099 #endif
4100
4101 // Load the specified registers
4102 // This only loads the registers given as arguments because
4103 // we don't want to load things that will be overwritten
4104 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4105 {
4106   int hr;
4107   // Load 32-bit regs
4108   for(hr=0;hr<HOST_REGS;hr++) {
4109     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4110       if(entry[hr]!=regmap[hr]) {
4111         if(regmap[hr]==rs1||regmap[hr]==rs2)
4112         {
4113           if(regmap[hr]==0) {
4114             emit_zeroreg(hr);
4115           }
4116           else
4117           {
4118             emit_loadreg(regmap[hr],hr);
4119           }
4120         }
4121       }
4122     }
4123   }
4124   //Load 64-bit regs
4125   for(hr=0;hr<HOST_REGS;hr++) {
4126     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4127       if(entry[hr]!=regmap[hr]) {
4128         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4129         {
4130           assert(regmap[hr]!=64);
4131           if((is32>>(regmap[hr]&63))&1) {
4132             int lr=get_reg(regmap,regmap[hr]-64);
4133             if(lr>=0)
4134               emit_sarimm(lr,31,hr);
4135             else
4136               emit_loadreg(regmap[hr],hr);
4137           }
4138           else
4139           {
4140             emit_loadreg(regmap[hr],hr);
4141           }
4142         }
4143       }
4144     }
4145   }
4146 }
4147
4148 // Load registers prior to the start of a loop
4149 // so that they are not loaded within the loop
4150 static void loop_preload(signed char pre[],signed char entry[])
4151 {
4152   int hr;
4153   for(hr=0;hr<HOST_REGS;hr++) {
4154     if(hr!=EXCLUDE_REG) {
4155       if(pre[hr]!=entry[hr]) {
4156         if(entry[hr]>=0) {
4157           if(get_reg(pre,entry[hr])<0) {
4158             assem_debug("loop preload:\n");
4159             //printf("loop preload: %d\n",hr);
4160             if(entry[hr]==0) {
4161               emit_zeroreg(hr);
4162             }
4163             else if(entry[hr]<TEMPREG)
4164             {
4165               emit_loadreg(entry[hr],hr);
4166             }
4167             else if(entry[hr]-64<TEMPREG)
4168             {
4169               emit_loadreg(entry[hr],hr);
4170             }
4171           }
4172         }
4173       }
4174     }
4175   }
4176 }
4177
4178 // Generate address for load/store instruction
4179 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4180 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4181 {
4182   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4183     int ra=-1;
4184     int agr=AGEN1+(i&1);
4185     int mgr=MGEN1+(i&1);
4186     if(itype[i]==LOAD) {
4187       ra=get_reg(i_regs->regmap,rt1[i]);
4188       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4189       assert(ra>=0);
4190     }
4191     if(itype[i]==LOADLR) {
4192       ra=get_reg(i_regs->regmap,FTEMP);
4193     }
4194     if(itype[i]==STORE||itype[i]==STORELR) {
4195       ra=get_reg(i_regs->regmap,agr);
4196       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4197     }
4198     if(itype[i]==C1LS||itype[i]==C2LS) {
4199       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4200         ra=get_reg(i_regs->regmap,FTEMP);
4201       else { // SWC1/SDC1/SWC2/SDC2
4202         ra=get_reg(i_regs->regmap,agr);
4203         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4204       }
4205     }
4206     int rs=get_reg(i_regs->regmap,rs1[i]);
4207     int rm=get_reg(i_regs->regmap,TLREG);
4208     if(ra>=0) {
4209       int offset=imm[i];
4210       int c=(i_regs->wasconst>>rs)&1;
4211       if(rs1[i]==0) {
4212         // Using r0 as a base address
4213         /*if(rm>=0) {
4214           if(!entry||entry[rm]!=mgr) {
4215             generate_map_const(offset,rm);
4216           } // else did it in the previous cycle
4217         }*/
4218         if(!entry||entry[ra]!=agr) {
4219           if (opcode[i]==0x22||opcode[i]==0x26) {
4220             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4221           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4222             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4223           }else{
4224             emit_movimm(offset,ra);
4225           }
4226         } // else did it in the previous cycle
4227       }
4228       else if(rs<0) {
4229         if(!entry||entry[ra]!=rs1[i])
4230           emit_loadreg(rs1[i],ra);
4231         //if(!entry||entry[ra]!=rs1[i])
4232         //  printf("poor load scheduling!\n");
4233       }
4234       else if(c) {
4235 #ifndef DISABLE_TLB
4236         if(rm>=0) {
4237           if(!entry||entry[rm]!=mgr) {
4238             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4239               // Stores to memory go thru the mapper to detect self-modifying
4240               // code, loads don't.
4241               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4242                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4243                 generate_map_const(constmap[i][rs]+offset,rm);
4244             }else{
4245               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4246                 generate_map_const(constmap[i][rs]+offset,rm);
4247             }
4248           }
4249         }
4250 #endif
4251         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4252           if(!entry||entry[ra]!=agr) {
4253             if (opcode[i]==0x22||opcode[i]==0x26) {
4254               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4255             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4256               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4257             }else{
4258               #ifdef HOST_IMM_ADDR32
4259               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4260                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4261               #endif
4262               emit_movimm(constmap[i][rs]+offset,ra);
4263               regs[i].loadedconst|=1<<ra;
4264             }
4265           } // else did it in the previous cycle
4266         } // else load_consts already did it
4267       }
4268       if(offset&&!c&&rs1[i]) {
4269         if(rs>=0) {
4270           emit_addimm(rs,offset,ra);
4271         }else{
4272           emit_addimm(ra,offset,ra);
4273         }
4274       }
4275     }
4276   }
4277   // Preload constants for next instruction
4278   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4279     int agr,ra;
4280     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4281     // Mapper entry
4282     agr=MGEN1+((i+1)&1);
4283     ra=get_reg(i_regs->regmap,agr);
4284     if(ra>=0) {
4285       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4286       int offset=imm[i+1];
4287       int c=(regs[i+1].wasconst>>rs)&1;
4288       if(c) {
4289         if(itype[i+1]==STORE||itype[i+1]==STORELR
4290            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4291           // Stores to memory go thru the mapper to detect self-modifying
4292           // code, loads don't.
4293           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4294              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4295             generate_map_const(constmap[i+1][rs]+offset,ra);
4296         }else{
4297           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4298             generate_map_const(constmap[i+1][rs]+offset,ra);
4299         }
4300       }
4301       /*else if(rs1[i]==0) {
4302         generate_map_const(offset,ra);
4303       }*/
4304     }
4305     #endif
4306     // Actual address
4307     agr=AGEN1+((i+1)&1);
4308     ra=get_reg(i_regs->regmap,agr);
4309     if(ra>=0) {
4310       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4311       int offset=imm[i+1];
4312       int c=(regs[i+1].wasconst>>rs)&1;
4313       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4314         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4315           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4316         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4317           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4318         }else{
4319           #ifdef HOST_IMM_ADDR32
4320           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4321              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4322           #endif
4323           emit_movimm(constmap[i+1][rs]+offset,ra);
4324           regs[i+1].loadedconst|=1<<ra;
4325         }
4326       }
4327       else if(rs1[i+1]==0) {
4328         // Using r0 as a base address
4329         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4330           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4331         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4332           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4333         }else{
4334           emit_movimm(offset,ra);
4335         }
4336       }
4337     }
4338   }
4339 }
4340
4341 int get_final_value(int hr, int i, int *value)
4342 {
4343   int reg=regs[i].regmap[hr];
4344   while(i<slen-1) {
4345     if(regs[i+1].regmap[hr]!=reg) break;
4346     if(!((regs[i+1].isconst>>hr)&1)) break;
4347     if(bt[i+1]) break;
4348     i++;
4349   }
4350   if(i<slen-1) {
4351     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4352       *value=constmap[i][hr];
4353       return 1;
4354     }
4355     if(!bt[i+1]) {
4356       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4357         // Load in delay slot, out-of-order execution
4358         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4359         {
4360           #ifdef HOST_IMM_ADDR32
4361           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4362           #endif
4363           // Precompute load address
4364           *value=constmap[i][hr]+imm[i+2];
4365           return 1;
4366         }
4367       }
4368       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4369       {
4370         #ifdef HOST_IMM_ADDR32
4371         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4372         #endif
4373         // Precompute load address
4374         *value=constmap[i][hr]+imm[i+1];
4375         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4376         return 1;
4377       }
4378     }
4379   }
4380   *value=constmap[i][hr];
4381   //printf("c=%x\n",(int)constmap[i][hr]);
4382   if(i==slen-1) return 1;
4383   if(reg<64) {
4384     return !((unneeded_reg[i+1]>>reg)&1);
4385   }else{
4386     return !((unneeded_reg_upper[i+1]>>reg)&1);
4387   }
4388 }
4389
4390 // Load registers with known constants
4391 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4392 {
4393   int hr,hr2;
4394   // propagate loaded constant flags
4395   if(i==0||bt[i])
4396     regs[i].loadedconst=0;
4397   else {
4398     for(hr=0;hr<HOST_REGS;hr++) {
4399       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4400          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4401       {
4402         regs[i].loadedconst|=1<<hr;
4403       }
4404     }
4405   }
4406   // Load 32-bit regs
4407   for(hr=0;hr<HOST_REGS;hr++) {
4408     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4409       //if(entry[hr]!=regmap[hr]) {
4410       if(!((regs[i].loadedconst>>hr)&1)) {
4411         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4412           int value,similar=0;
4413           if(get_final_value(hr,i,&value)) {
4414             // see if some other register has similar value
4415             for(hr2=0;hr2<HOST_REGS;hr2++) {
4416               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4417                 if(is_similar_value(value,constmap[i][hr2])) {
4418                   similar=1;
4419                   break;
4420                 }
4421               }
4422             }
4423             if(similar) {
4424               int value2;
4425               if(get_final_value(hr2,i,&value2)) // is this needed?
4426                 emit_movimm_from(value2,hr2,value,hr);
4427               else
4428                 emit_movimm(value,hr);
4429             }
4430             else if(value==0) {
4431               emit_zeroreg(hr);
4432             }
4433             else {
4434               emit_movimm(value,hr);
4435             }
4436           }
4437           regs[i].loadedconst|=1<<hr;
4438         }
4439       }
4440     }
4441   }
4442   // Load 64-bit regs
4443   for(hr=0;hr<HOST_REGS;hr++) {
4444     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4445       //if(entry[hr]!=regmap[hr]) {
4446       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4447         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4448           if((is32>>(regmap[hr]&63))&1) {
4449             int lr=get_reg(regmap,regmap[hr]-64);
4450             assert(lr>=0);
4451             emit_sarimm(lr,31,hr);
4452           }
4453           else
4454           {
4455             int value;
4456             if(get_final_value(hr,i,&value)) {
4457               if(value==0) {
4458                 emit_zeroreg(hr);
4459               }
4460               else {
4461                 emit_movimm(value,hr);
4462               }
4463             }
4464           }
4465         }
4466       }
4467     }
4468   }
4469 }
4470 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4471 {
4472   int hr;
4473   // Load 32-bit regs
4474   for(hr=0;hr<HOST_REGS;hr++) {
4475     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4476       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4477         int value=constmap[i][hr];
4478         if(value==0) {
4479           emit_zeroreg(hr);
4480         }
4481         else {
4482           emit_movimm(value,hr);
4483         }
4484       }
4485     }
4486   }
4487   // Load 64-bit regs
4488   for(hr=0;hr<HOST_REGS;hr++) {
4489     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4490       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4491         if((is32>>(regmap[hr]&63))&1) {
4492           int lr=get_reg(regmap,regmap[hr]-64);
4493           assert(lr>=0);
4494           emit_sarimm(lr,31,hr);
4495         }
4496         else
4497         {
4498           int value=constmap[i][hr];
4499           if(value==0) {
4500             emit_zeroreg(hr);
4501           }
4502           else {
4503             emit_movimm(value,hr);
4504           }
4505         }
4506       }
4507     }
4508   }
4509 }
4510
4511 // Write out all dirty registers (except cycle count)
4512 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4513 {
4514   int hr;
4515   for(hr=0;hr<HOST_REGS;hr++) {
4516     if(hr!=EXCLUDE_REG) {
4517       if(i_regmap[hr]>0) {
4518         if(i_regmap[hr]!=CCREG) {
4519           if((i_dirty>>hr)&1) {
4520             if(i_regmap[hr]<64) {
4521               emit_storereg(i_regmap[hr],hr);
4522 #ifndef FORCE32
4523               if( ((i_is32>>i_regmap[hr])&1) ) {
4524                 #ifdef DESTRUCTIVE_WRITEBACK
4525                 emit_sarimm(hr,31,hr);
4526                 emit_storereg(i_regmap[hr]|64,hr);
4527                 #else
4528                 emit_sarimm(hr,31,HOST_TEMPREG);
4529                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4530                 #endif
4531               }
4532 #endif
4533             }else{
4534               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4535                 emit_storereg(i_regmap[hr],hr);
4536               }
4537             }
4538           }
4539         }
4540       }
4541     }
4542   }
4543 }
4544 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4545 // This writes the registers not written by store_regs_bt
4546 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4547 {
4548   int hr;
4549   int t=(addr-start)>>2;
4550   for(hr=0;hr<HOST_REGS;hr++) {
4551     if(hr!=EXCLUDE_REG) {
4552       if(i_regmap[hr]>0) {
4553         if(i_regmap[hr]!=CCREG) {
4554           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4555             if((i_dirty>>hr)&1) {
4556               if(i_regmap[hr]<64) {
4557                 emit_storereg(i_regmap[hr],hr);
4558 #ifndef FORCE32
4559                 if( ((i_is32>>i_regmap[hr])&1) ) {
4560                   #ifdef DESTRUCTIVE_WRITEBACK
4561                   emit_sarimm(hr,31,hr);
4562                   emit_storereg(i_regmap[hr]|64,hr);
4563                   #else
4564                   emit_sarimm(hr,31,HOST_TEMPREG);
4565                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4566                   #endif
4567                 }
4568 #endif
4569               }else{
4570                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4571                   emit_storereg(i_regmap[hr],hr);
4572                 }
4573               }
4574             }
4575           }
4576         }
4577       }
4578     }
4579   }
4580 }
4581
4582 // Load all registers (except cycle count)
4583 void load_all_regs(signed char i_regmap[])
4584 {
4585   int hr;
4586   for(hr=0;hr<HOST_REGS;hr++) {
4587     if(hr!=EXCLUDE_REG) {
4588       if(i_regmap[hr]==0) {
4589         emit_zeroreg(hr);
4590       }
4591       else
4592       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4593       {
4594         emit_loadreg(i_regmap[hr],hr);
4595       }
4596     }
4597   }
4598 }
4599
4600 // Load all current registers also needed by next instruction
4601 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4602 {
4603   int hr;
4604   for(hr=0;hr<HOST_REGS;hr++) {
4605     if(hr!=EXCLUDE_REG) {
4606       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4607         if(i_regmap[hr]==0) {
4608           emit_zeroreg(hr);
4609         }
4610         else
4611         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4612         {
4613           emit_loadreg(i_regmap[hr],hr);
4614         }
4615       }
4616     }
4617   }
4618 }
4619
4620 // Load all regs, storing cycle count if necessary
4621 void load_regs_entry(int t)
4622 {
4623   int hr;
4624   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4625   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4626   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4627     emit_storereg(CCREG,HOST_CCREG);
4628   }
4629   // Load 32-bit regs
4630   for(hr=0;hr<HOST_REGS;hr++) {
4631     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4632       if(regs[t].regmap_entry[hr]==0) {
4633         emit_zeroreg(hr);
4634       }
4635       else if(regs[t].regmap_entry[hr]!=CCREG)
4636       {
4637         emit_loadreg(regs[t].regmap_entry[hr],hr);
4638       }
4639     }
4640   }
4641   // Load 64-bit regs
4642   for(hr=0;hr<HOST_REGS;hr++) {
4643     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4644       assert(regs[t].regmap_entry[hr]!=64);
4645       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4646         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4647         if(lr<0) {
4648           emit_loadreg(regs[t].regmap_entry[hr],hr);
4649         }
4650         else
4651         {
4652           emit_sarimm(lr,31,hr);
4653         }
4654       }
4655       else
4656       {
4657         emit_loadreg(regs[t].regmap_entry[hr],hr);
4658       }
4659     }
4660   }
4661 }
4662
4663 // Store dirty registers prior to branch
4664 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4665 {
4666   if(internal_branch(i_is32,addr))
4667   {
4668     int t=(addr-start)>>2;
4669     int hr;
4670     for(hr=0;hr<HOST_REGS;hr++) {
4671       if(hr!=EXCLUDE_REG) {
4672         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4673           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4674             if((i_dirty>>hr)&1) {
4675               if(i_regmap[hr]<64) {
4676                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4677                   emit_storereg(i_regmap[hr],hr);
4678                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4679                     #ifdef DESTRUCTIVE_WRITEBACK
4680                     emit_sarimm(hr,31,hr);
4681                     emit_storereg(i_regmap[hr]|64,hr);
4682                     #else
4683                     emit_sarimm(hr,31,HOST_TEMPREG);
4684                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4685                     #endif
4686                   }
4687                 }
4688               }else{
4689                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4690                   emit_storereg(i_regmap[hr],hr);
4691                 }
4692               }
4693             }
4694           }
4695         }
4696       }
4697     }
4698   }
4699   else
4700   {
4701     // Branch out of this block, write out all dirty regs
4702     wb_dirtys(i_regmap,i_is32,i_dirty);
4703   }
4704 }
4705
4706 // Load all needed registers for branch target
4707 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4708 {
4709   //if(addr>=start && addr<(start+slen*4))
4710   if(internal_branch(i_is32,addr))
4711   {
4712     int t=(addr-start)>>2;
4713     int hr;
4714     // Store the cycle count before loading something else
4715     if(i_regmap[HOST_CCREG]!=CCREG) {
4716       assert(i_regmap[HOST_CCREG]==-1);
4717     }
4718     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4719       emit_storereg(CCREG,HOST_CCREG);
4720     }
4721     // Load 32-bit regs
4722     for(hr=0;hr<HOST_REGS;hr++) {
4723       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4724         #ifdef DESTRUCTIVE_WRITEBACK
4725         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4726         #else
4727         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4728         #endif
4729           if(regs[t].regmap_entry[hr]==0) {
4730             emit_zeroreg(hr);
4731           }
4732           else if(regs[t].regmap_entry[hr]!=CCREG)
4733           {
4734             emit_loadreg(regs[t].regmap_entry[hr],hr);
4735           }
4736         }
4737       }
4738     }
4739     //Load 64-bit regs
4740     for(hr=0;hr<HOST_REGS;hr++) {
4741       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4742         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4743           assert(regs[t].regmap_entry[hr]!=64);
4744           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4745             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4746             if(lr<0) {
4747               emit_loadreg(regs[t].regmap_entry[hr],hr);
4748             }
4749             else
4750             {
4751               emit_sarimm(lr,31,hr);
4752             }
4753           }
4754           else
4755           {
4756             emit_loadreg(regs[t].regmap_entry[hr],hr);
4757           }
4758         }
4759         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4760           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4761           assert(lr>=0);
4762           emit_sarimm(lr,31,hr);
4763         }
4764       }
4765     }
4766   }
4767 }
4768
4769 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4770 {
4771   if(addr>=start && addr<start+slen*4-4)
4772   {
4773     int t=(addr-start)>>2;
4774     int hr;
4775     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4776     for(hr=0;hr<HOST_REGS;hr++)
4777     {
4778       if(hr!=EXCLUDE_REG)
4779       {
4780         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4781         {
4782           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4783           {
4784             return 0;
4785           }
4786           else
4787           if((i_dirty>>hr)&1)
4788           {
4789             if(i_regmap[hr]<TEMPREG)
4790             {
4791               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4792                 return 0;
4793             }
4794             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4795             {
4796               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4797                 return 0;
4798             }
4799           }
4800         }
4801         else // Same register but is it 32-bit or dirty?
4802         if(i_regmap[hr]>=0)
4803         {
4804           if(!((regs[t].dirty>>hr)&1))
4805           {
4806             if((i_dirty>>hr)&1)
4807             {
4808               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4809               {
4810                 //printf("%x: dirty no match\n",addr);
4811                 return 0;
4812               }
4813             }
4814           }
4815           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4816           {
4817             //printf("%x: is32 no match\n",addr);
4818             return 0;
4819           }
4820         }
4821       }
4822     }
4823     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4824 #ifndef FORCE32
4825     if(requires_32bit[t]&~i_is32) return 0;
4826 #endif
4827     // Delay slots are not valid branch targets
4828     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4829     // Delay slots require additional processing, so do not match
4830     if(is_ds[t]) return 0;
4831   }
4832   else
4833   {
4834     int hr;
4835     for(hr=0;hr<HOST_REGS;hr++)
4836     {
4837       if(hr!=EXCLUDE_REG)
4838       {
4839         if(i_regmap[hr]>=0)
4840         {
4841           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4842           {
4843             if((i_dirty>>hr)&1)
4844             {
4845               return 0;
4846             }
4847           }
4848         }
4849       }
4850     }
4851   }
4852   return 1;
4853 }
4854
4855 // Used when a branch jumps into the delay slot of another branch
4856 void ds_assemble_entry(int i)
4857 {
4858   int t=(ba[i]-start)>>2;
4859   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4860   assem_debug("Assemble delay slot at %x\n",ba[i]);
4861   assem_debug("<->\n");
4862   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4863     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4864   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4865   address_generation(t,&regs[t],regs[t].regmap_entry);
4866   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4867     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4868   cop1_usable=0;
4869   is_delayslot=0;
4870   switch(itype[t]) {
4871     case ALU:
4872       alu_assemble(t,&regs[t]);break;
4873     case IMM16:
4874       imm16_assemble(t,&regs[t]);break;
4875     case SHIFT:
4876       shift_assemble(t,&regs[t]);break;
4877     case SHIFTIMM:
4878       shiftimm_assemble(t,&regs[t]);break;
4879     case LOAD:
4880       load_assemble(t,&regs[t]);break;
4881     case LOADLR:
4882       loadlr_assemble(t,&regs[t]);break;
4883     case STORE:
4884       store_assemble(t,&regs[t]);break;
4885     case STORELR:
4886       storelr_assemble(t,&regs[t]);break;
4887     case COP0:
4888       cop0_assemble(t,&regs[t]);break;
4889     case COP1:
4890       cop1_assemble(t,&regs[t]);break;
4891     case C1LS:
4892       c1ls_assemble(t,&regs[t]);break;
4893     case COP2:
4894       cop2_assemble(t,&regs[t]);break;
4895     case C2LS:
4896       c2ls_assemble(t,&regs[t]);break;
4897     case C2OP:
4898       c2op_assemble(t,&regs[t]);break;
4899     case FCONV:
4900       fconv_assemble(t,&regs[t]);break;
4901     case FLOAT:
4902       float_assemble(t,&regs[t]);break;
4903     case FCOMP:
4904       fcomp_assemble(t,&regs[t]);break;
4905     case MULTDIV:
4906       multdiv_assemble(t,&regs[t]);break;
4907     case MOV:
4908       mov_assemble(t,&regs[t]);break;
4909     case SYSCALL:
4910     case HLECALL:
4911     case INTCALL:
4912     case SPAN:
4913     case UJUMP:
4914     case RJUMP:
4915     case CJUMP:
4916     case SJUMP:
4917     case FJUMP:
4918       printf("Jump in the delay slot.  This is probably a bug.\n");
4919   }
4920   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4921   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4922   if(internal_branch(regs[t].is32,ba[i]+4))
4923     assem_debug("branch: internal\n");
4924   else
4925     assem_debug("branch: external\n");
4926   assert(internal_branch(regs[t].is32,ba[i]+4));
4927   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4928   emit_jmp(0);
4929 }
4930
4931 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4932 {
4933   int count;
4934   int jaddr;
4935   int idle=0;
4936   if(itype[i]==RJUMP)
4937   {
4938     *adj=0;
4939   }
4940   //if(ba[i]>=start && ba[i]<(start+slen*4))
4941   if(internal_branch(branch_regs[i].is32,ba[i]))
4942   {
4943     int t=(ba[i]-start)>>2;
4944     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4945     else *adj=ccadj[t];
4946   }
4947   else
4948   {
4949     *adj=0;
4950   }
4951   count=ccadj[i];
4952   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4953     // Idle loop
4954     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4955     idle=(int)out;
4956     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4957     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4958     jaddr=(int)out;
4959     emit_jmp(0);
4960   }
4961   else if(*adj==0||invert) {
4962     emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4963     jaddr=(int)out;
4964     emit_jns(0);
4965   }
4966   else
4967   {
4968     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4969     jaddr=(int)out;
4970     emit_jns(0);
4971   }
4972   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4973 }
4974
4975 void do_ccstub(int n)
4976 {
4977   literal_pool(256);
4978   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4979   set_jump_target(stubs[n][1],(int)out);
4980   int i=stubs[n][4];
4981   if(stubs[n][6]==NULLDS) {
4982     // Delay slot instruction is nullified ("likely" branch)
4983     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4984   }
4985   else if(stubs[n][6]!=TAKEN) {
4986     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4987   }
4988   else {
4989     if(internal_branch(branch_regs[i].is32,ba[i]))
4990       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4991   }
4992   if(stubs[n][5]!=-1)
4993   {
4994     // Save PC as return address
4995     emit_movimm(stubs[n][5],EAX);
4996     emit_writeword(EAX,(int)&pcaddr);
4997   }
4998   else
4999   {
5000     // Return address depends on which way the branch goes
5001     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5002     {
5003       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5004       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5005       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5006       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5007       if(rs1[i]==0)
5008       {
5009         s1l=s2l;s1h=s2h;
5010         s2l=s2h=-1;
5011       }
5012       else if(rs2[i]==0)
5013       {
5014         s2l=s2h=-1;
5015       }
5016       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5017         s1h=s2h=-1;
5018       }
5019       assert(s1l>=0);
5020       #ifdef DESTRUCTIVE_WRITEBACK
5021       if(rs1[i]) {
5022         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5023           emit_loadreg(rs1[i],s1l);
5024       }
5025       else {
5026         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5027           emit_loadreg(rs2[i],s1l);
5028       }
5029       if(s2l>=0)
5030         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5031           emit_loadreg(rs2[i],s2l);
5032       #endif
5033       int hr=0;
5034       int addr=-1,alt=-1,ntaddr=-1;
5035       while(hr<HOST_REGS)
5036       {
5037         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5038            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5039            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5040         {
5041           addr=hr++;break;
5042         }
5043         hr++;
5044       }
5045       while(hr<HOST_REGS)
5046       {
5047         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5048            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5049            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5050         {
5051           alt=hr++;break;
5052         }
5053         hr++;
5054       }
5055       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5056       {
5057         while(hr<HOST_REGS)
5058         {
5059           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5060              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5061              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5062           {
5063             ntaddr=hr;break;
5064           }
5065           hr++;
5066         }
5067         assert(hr<HOST_REGS);
5068       }
5069       if((opcode[i]&0x2f)==4) // BEQ
5070       {
5071         #ifdef HAVE_CMOV_IMM
5072         if(s1h<0) {
5073           if(s2l>=0) emit_cmp(s1l,s2l);
5074           else emit_test(s1l,s1l);
5075           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5076         }
5077         else
5078         #endif
5079         {
5080           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5081           if(s1h>=0) {
5082             if(s2h>=0) emit_cmp(s1h,s2h);
5083             else emit_test(s1h,s1h);
5084             emit_cmovne_reg(alt,addr);
5085           }
5086           if(s2l>=0) emit_cmp(s1l,s2l);
5087           else emit_test(s1l,s1l);
5088           emit_cmovne_reg(alt,addr);
5089         }
5090       }
5091       if((opcode[i]&0x2f)==5) // BNE
5092       {
5093         #ifdef HAVE_CMOV_IMM
5094         if(s1h<0) {
5095           if(s2l>=0) emit_cmp(s1l,s2l);
5096           else emit_test(s1l,s1l);
5097           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5098         }
5099         else
5100         #endif
5101         {
5102           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5103           if(s1h>=0) {
5104             if(s2h>=0) emit_cmp(s1h,s2h);
5105             else emit_test(s1h,s1h);
5106             emit_cmovne_reg(alt,addr);
5107           }
5108           if(s2l>=0) emit_cmp(s1l,s2l);
5109           else emit_test(s1l,s1l);
5110           emit_cmovne_reg(alt,addr);
5111         }
5112       }
5113       if((opcode[i]&0x2f)==6) // BLEZ
5114       {
5115         //emit_movimm(ba[i],alt);
5116         //emit_movimm(start+i*4+8,addr);
5117         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5118         emit_cmpimm(s1l,1);
5119         if(s1h>=0) emit_mov(addr,ntaddr);
5120         emit_cmovl_reg(alt,addr);
5121         if(s1h>=0) {
5122           emit_test(s1h,s1h);
5123           emit_cmovne_reg(ntaddr,addr);
5124           emit_cmovs_reg(alt,addr);
5125         }
5126       }
5127       if((opcode[i]&0x2f)==7) // BGTZ
5128       {
5129         //emit_movimm(ba[i],addr);
5130         //emit_movimm(start+i*4+8,ntaddr);
5131         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5132         emit_cmpimm(s1l,1);
5133         if(s1h>=0) emit_mov(addr,alt);
5134         emit_cmovl_reg(ntaddr,addr);
5135         if(s1h>=0) {
5136           emit_test(s1h,s1h);
5137           emit_cmovne_reg(alt,addr);
5138           emit_cmovs_reg(ntaddr,addr);
5139         }
5140       }
5141       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5142       {
5143         //emit_movimm(ba[i],alt);
5144         //emit_movimm(start+i*4+8,addr);
5145         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5146         if(s1h>=0) emit_test(s1h,s1h);
5147         else emit_test(s1l,s1l);
5148         emit_cmovs_reg(alt,addr);
5149       }
5150       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5151       {
5152         //emit_movimm(ba[i],addr);
5153         //emit_movimm(start+i*4+8,alt);
5154         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5155         if(s1h>=0) emit_test(s1h,s1h);
5156         else emit_test(s1l,s1l);
5157         emit_cmovs_reg(alt,addr);
5158       }
5159       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5160         if(source[i]&0x10000) // BC1T
5161         {
5162           //emit_movimm(ba[i],alt);
5163           //emit_movimm(start+i*4+8,addr);
5164           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5165           emit_testimm(s1l,0x800000);
5166           emit_cmovne_reg(alt,addr);
5167         }
5168         else // BC1F
5169         {
5170           //emit_movimm(ba[i],addr);
5171           //emit_movimm(start+i*4+8,alt);
5172           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5173           emit_testimm(s1l,0x800000);
5174           emit_cmovne_reg(alt,addr);
5175         }
5176       }
5177       emit_writeword(addr,(int)&pcaddr);
5178     }
5179     else
5180     if(itype[i]==RJUMP)
5181     {
5182       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5183       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5184         r=get_reg(branch_regs[i].regmap,RTEMP);
5185       }
5186       emit_writeword(r,(int)&pcaddr);
5187     }
5188     else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5189   }
5190   // Update cycle count
5191   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5192   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5193   emit_call((int)cc_interrupt);
5194   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5195   if(stubs[n][6]==TAKEN) {
5196     if(internal_branch(branch_regs[i].is32,ba[i]))
5197       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5198     else if(itype[i]==RJUMP) {
5199       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5200         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5201       else
5202         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5203     }
5204   }else if(stubs[n][6]==NOTTAKEN) {
5205     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5206     else load_all_regs(branch_regs[i].regmap);
5207   }else if(stubs[n][6]==NULLDS) {
5208     // Delay slot instruction is nullified ("likely" branch)
5209     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5210     else load_all_regs(regs[i].regmap);
5211   }else{
5212     load_all_regs(branch_regs[i].regmap);
5213   }
5214   emit_jmp(stubs[n][2]); // return address
5215
5216   /* This works but uses a lot of memory...
5217   emit_readword((int)&last_count,ECX);
5218   emit_add(HOST_CCREG,ECX,EAX);
5219   emit_writeword(EAX,(int)&Count);
5220   emit_call((int)gen_interupt);
5221   emit_readword((int)&Count,HOST_CCREG);
5222   emit_readword((int)&next_interupt,EAX);
5223   emit_readword((int)&pending_exception,EBX);
5224   emit_writeword(EAX,(int)&last_count);
5225   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5226   emit_test(EBX,EBX);
5227   int jne_instr=(int)out;
5228   emit_jne(0);
5229   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5230   load_all_regs(branch_regs[i].regmap);
5231   emit_jmp(stubs[n][2]); // return address
5232   set_jump_target(jne_instr,(int)out);
5233   emit_readword((int)&pcaddr,EAX);
5234   // Call get_addr_ht instead of doing the hash table here.
5235   // This code is executed infrequently and takes up a lot of space
5236   // so smaller is better.
5237   emit_storereg(CCREG,HOST_CCREG);
5238   emit_pushreg(EAX);
5239   emit_call((int)get_addr_ht);
5240   emit_loadreg(CCREG,HOST_CCREG);
5241   emit_addimm(ESP,4,ESP);
5242   emit_jmpreg(EAX);*/
5243 }
5244
5245 add_to_linker(int addr,int target,int ext)
5246 {
5247   link_addr[linkcount][0]=addr;
5248   link_addr[linkcount][1]=target;
5249   link_addr[linkcount][2]=ext;
5250   linkcount++;
5251 }
5252
5253 static void ujump_assemble_write_ra(int i)
5254 {
5255   int rt;
5256   unsigned int return_address;
5257   rt=get_reg(branch_regs[i].regmap,31);
5258   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5259   //assert(rt>=0);
5260   return_address=start+i*4+8;
5261   if(rt>=0) {
5262     #ifdef USE_MINI_HT
5263     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5264       int temp=-1; // note: must be ds-safe
5265       #ifdef HOST_TEMPREG
5266       temp=HOST_TEMPREG;
5267       #endif
5268       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5269       else emit_movimm(return_address,rt);
5270     }
5271     else
5272     #endif
5273     {
5274       #ifdef REG_PREFETCH
5275       if(temp>=0)
5276       {
5277         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5278       }
5279       #endif
5280       emit_movimm(return_address,rt); // PC into link register
5281       #ifdef IMM_PREFETCH
5282       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5283       #endif
5284     }
5285   }
5286 }
5287
5288 void ujump_assemble(int i,struct regstat *i_regs)
5289 {
5290   signed char *i_regmap=i_regs->regmap;
5291   int ra_done=0;
5292   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5293   address_generation(i+1,i_regs,regs[i].regmap_entry);
5294   #ifdef REG_PREFETCH
5295   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5296   if(rt1[i]==31&&temp>=0)
5297   {
5298     int return_address=start+i*4+8;
5299     if(get_reg(branch_regs[i].regmap,31)>0)
5300     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5301   }
5302   #endif
5303   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5304     ujump_assemble_write_ra(i); // writeback ra for DS
5305     ra_done=1;
5306   }
5307   ds_assemble(i+1,i_regs);
5308   uint64_t bc_unneeded=branch_regs[i].u;
5309   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5310   bc_unneeded|=1|(1LL<<rt1[i]);
5311   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5312   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5313                 bc_unneeded,bc_unneeded_upper);
5314   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5315   if(!ra_done&&rt1[i]==31)
5316     ujump_assemble_write_ra(i);
5317   int cc,adj;
5318   cc=get_reg(branch_regs[i].regmap,CCREG);
5319   assert(cc==HOST_CCREG);
5320   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5321   #ifdef REG_PREFETCH
5322   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5323   #endif
5324   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5325   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5326   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5327   if(internal_branch(branch_regs[i].is32,ba[i]))
5328     assem_debug("branch: internal\n");
5329   else
5330     assem_debug("branch: external\n");
5331   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5332     ds_assemble_entry(i);
5333   }
5334   else {
5335     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5336     emit_jmp(0);
5337   }
5338 }
5339
5340 static void rjump_assemble_write_ra(int i)
5341 {
5342   int rt,return_address;
5343   assert(rt1[i+1]!=rt1[i]);
5344   assert(rt2[i+1]!=rt1[i]);
5345   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5346   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5347   assert(rt>=0);
5348   return_address=start+i*4+8;
5349   #ifdef REG_PREFETCH
5350   if(temp>=0)
5351   {
5352     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5353   }
5354   #endif
5355   emit_movimm(return_address,rt); // PC into link register
5356   #ifdef IMM_PREFETCH
5357   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5358   #endif
5359 }
5360
5361 void rjump_assemble(int i,struct regstat *i_regs)
5362 {
5363   signed char *i_regmap=i_regs->regmap;
5364   int temp;
5365   int rs,cc,adj;
5366   int ra_done=0;
5367   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5368   assert(rs>=0);
5369   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5370     // Delay slot abuse, make a copy of the branch address register
5371     temp=get_reg(branch_regs[i].regmap,RTEMP);
5372     assert(temp>=0);
5373     assert(regs[i].regmap[temp]==RTEMP);
5374     emit_mov(rs,temp);
5375     rs=temp;
5376   }
5377   address_generation(i+1,i_regs,regs[i].regmap_entry);
5378   #ifdef REG_PREFETCH
5379   if(rt1[i]==31)
5380   {
5381     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5382       int return_address=start+i*4+8;
5383       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5384     }
5385   }
5386   #endif
5387   #ifdef USE_MINI_HT
5388   if(rs1[i]==31) {
5389     int rh=get_reg(regs[i].regmap,RHASH);
5390     if(rh>=0) do_preload_rhash(rh);
5391   }
5392   #endif
5393   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5394     rjump_assemble_write_ra(i);
5395     ra_done=1;
5396   }
5397   ds_assemble(i+1,i_regs);
5398   uint64_t bc_unneeded=branch_regs[i].u;
5399   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5400   bc_unneeded|=1|(1LL<<rt1[i]);
5401   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5402   bc_unneeded&=~(1LL<<rs1[i]);
5403   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5404                 bc_unneeded,bc_unneeded_upper);
5405   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5406   if(!ra_done&&rt1[i]!=0)
5407     rjump_assemble_write_ra(i);
5408   cc=get_reg(branch_regs[i].regmap,CCREG);
5409   assert(cc==HOST_CCREG);
5410   #ifdef USE_MINI_HT
5411   int rh=get_reg(branch_regs[i].regmap,RHASH);
5412   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5413   if(rs1[i]==31) {
5414     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5415     do_preload_rhtbl(ht);
5416     do_rhash(rs,rh);
5417   }
5418   #endif
5419   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5420   #ifdef DESTRUCTIVE_WRITEBACK
5421   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5422     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5423       emit_loadreg(rs1[i],rs);
5424     }
5425   }
5426   #endif
5427   #ifdef REG_PREFETCH
5428   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5429   #endif
5430   #ifdef USE_MINI_HT
5431   if(rs1[i]==31) {
5432     do_miniht_load(ht,rh);
5433   }
5434   #endif
5435   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5436   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5437   //assert(adj==0);
5438   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5439   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5440 #ifdef PCSX
5441   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5442     // special case for RFE
5443     emit_jmp(0);
5444   else
5445 #endif
5446   emit_jns(0);
5447   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5448   #ifdef USE_MINI_HT
5449   if(rs1[i]==31) {
5450     do_miniht_jump(rs,rh,ht);
5451   }
5452   else
5453   #endif
5454   {
5455     //if(rs!=EAX) emit_mov(rs,EAX);
5456     //emit_jmp((int)jump_vaddr_eax);
5457     emit_jmp(jump_vaddr_reg[rs]);
5458   }
5459   /* Check hash table
5460   temp=!rs;
5461   emit_mov(rs,temp);
5462   emit_shrimm(rs,16,rs);
5463   emit_xor(temp,rs,rs);
5464   emit_movzwl_reg(rs,rs);
5465   emit_shlimm(rs,4,rs);
5466   emit_cmpmem_indexed((int)hash_table,rs,temp);
5467   emit_jne((int)out+14);
5468   emit_readword_indexed((int)hash_table+4,rs,rs);
5469   emit_jmpreg(rs);
5470   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5471   emit_addimm_no_flags(8,rs);
5472   emit_jeq((int)out-17);
5473   // No hit on hash table, call compiler
5474   emit_pushreg(temp);
5475 //DEBUG >
5476 #ifdef DEBUG_CYCLE_COUNT
5477   emit_readword((int)&last_count,ECX);
5478   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5479   emit_readword((int)&next_interupt,ECX);
5480   emit_writeword(HOST_CCREG,(int)&Count);
5481   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5482   emit_writeword(ECX,(int)&last_count);
5483 #endif
5484 //DEBUG <
5485   emit_storereg(CCREG,HOST_CCREG);
5486   emit_call((int)get_addr);
5487   emit_loadreg(CCREG,HOST_CCREG);
5488   emit_addimm(ESP,4,ESP);
5489   emit_jmpreg(EAX);*/
5490   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5491   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5492   #endif
5493 }
5494
5495 void cjump_assemble(int i,struct regstat *i_regs)
5496 {
5497   signed char *i_regmap=i_regs->regmap;
5498   int cc;
5499   int match;
5500   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5501   assem_debug("match=%d\n",match);
5502   int s1h,s1l,s2h,s2l;
5503   int prev_cop1_usable=cop1_usable;
5504   int unconditional=0,nop=0;
5505   int only32=0;
5506   int invert=0;
5507   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5508   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5509   if(!match) invert=1;
5510   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5511   if(i>(ba[i]-start)>>2) invert=1;
5512   #endif
5513
5514   if(ooo[i]) {
5515     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5516     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5517     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5518     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5519   }
5520   else {
5521     s1l=get_reg(i_regmap,rs1[i]);
5522     s1h=get_reg(i_regmap,rs1[i]|64);
5523     s2l=get_reg(i_regmap,rs2[i]);
5524     s2h=get_reg(i_regmap,rs2[i]|64);
5525   }
5526   if(rs1[i]==0&&rs2[i]==0)
5527   {
5528     if(opcode[i]&1) nop=1;
5529     else unconditional=1;
5530     //assert(opcode[i]!=5);
5531     //assert(opcode[i]!=7);
5532     //assert(opcode[i]!=0x15);
5533     //assert(opcode[i]!=0x17);
5534   }
5535   else if(rs1[i]==0)
5536   {
5537     s1l=s2l;s1h=s2h;
5538     s2l=s2h=-1;
5539     only32=(regs[i].was32>>rs2[i])&1;
5540   }
5541   else if(rs2[i]==0)
5542   {
5543     s2l=s2h=-1;
5544     only32=(regs[i].was32>>rs1[i])&1;
5545   }
5546   else {
5547     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5548   }
5549
5550   if(ooo[i]) {
5551     // Out of order execution (delay slot first)
5552     //printf("OOOE\n");
5553     address_generation(i+1,i_regs,regs[i].regmap_entry);
5554     ds_assemble(i+1,i_regs);
5555     int adj;
5556     uint64_t bc_unneeded=branch_regs[i].u;
5557     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5558     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5559     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5560     bc_unneeded|=1;
5561     bc_unneeded_upper|=1;
5562     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5563                   bc_unneeded,bc_unneeded_upper);
5564     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5565     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5566     cc=get_reg(branch_regs[i].regmap,CCREG);
5567     assert(cc==HOST_CCREG);
5568     if(unconditional)
5569       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5570     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5571     //assem_debug("cycle count (adj)\n");
5572     if(unconditional) {
5573       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5574       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5575         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5576         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5577         if(internal)
5578           assem_debug("branch: internal\n");
5579         else
5580           assem_debug("branch: external\n");
5581         if(internal&&is_ds[(ba[i]-start)>>2]) {
5582           ds_assemble_entry(i);
5583         }
5584         else {
5585           add_to_linker((int)out,ba[i],internal);
5586           emit_jmp(0);
5587         }
5588         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5589         if(((u_int)out)&7) emit_addnop(0);
5590         #endif
5591       }
5592     }
5593     else if(nop) {
5594       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5595       int jaddr=(int)out;
5596       emit_jns(0);
5597       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5598     }
5599     else {
5600       int taken=0,nottaken=0,nottaken1=0;
5601       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5602       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5603       if(!only32)
5604       {
5605         assert(s1h>=0);
5606         if(opcode[i]==4) // BEQ
5607         {
5608           if(s2h>=0) emit_cmp(s1h,s2h);
5609           else emit_test(s1h,s1h);
5610           nottaken1=(int)out;
5611           emit_jne(1);
5612         }
5613         if(opcode[i]==5) // BNE
5614         {
5615           if(s2h>=0) emit_cmp(s1h,s2h);
5616           else emit_test(s1h,s1h);
5617           if(invert) taken=(int)out;
5618           else add_to_linker((int)out,ba[i],internal);
5619           emit_jne(0);
5620         }
5621         if(opcode[i]==6) // BLEZ
5622         {
5623           emit_test(s1h,s1h);
5624           if(invert) taken=(int)out;
5625           else add_to_linker((int)out,ba[i],internal);
5626           emit_js(0);
5627           nottaken1=(int)out;
5628           emit_jne(1);
5629         }
5630         if(opcode[i]==7) // BGTZ
5631         {
5632           emit_test(s1h,s1h);
5633           nottaken1=(int)out;
5634           emit_js(1);
5635           if(invert) taken=(int)out;
5636           else add_to_linker((int)out,ba[i],internal);
5637           emit_jne(0);
5638         }
5639       } // if(!only32)
5640
5641       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5642       assert(s1l>=0);
5643       if(opcode[i]==4) // BEQ
5644       {
5645         if(s2l>=0) emit_cmp(s1l,s2l);
5646         else emit_test(s1l,s1l);
5647         if(invert){
5648           nottaken=(int)out;
5649           emit_jne(1);
5650         }else{
5651           add_to_linker((int)out,ba[i],internal);
5652           emit_jeq(0);
5653         }
5654       }
5655       if(opcode[i]==5) // BNE
5656       {
5657         if(s2l>=0) emit_cmp(s1l,s2l);
5658         else emit_test(s1l,s1l);
5659         if(invert){
5660           nottaken=(int)out;
5661           emit_jeq(1);
5662         }else{
5663           add_to_linker((int)out,ba[i],internal);
5664           emit_jne(0);
5665         }
5666       }
5667       if(opcode[i]==6) // BLEZ
5668       {
5669         emit_cmpimm(s1l,1);
5670         if(invert){
5671           nottaken=(int)out;
5672           emit_jge(1);
5673         }else{
5674           add_to_linker((int)out,ba[i],internal);
5675           emit_jl(0);
5676         }
5677       }
5678       if(opcode[i]==7) // BGTZ
5679       {
5680         emit_cmpimm(s1l,1);
5681         if(invert){
5682           nottaken=(int)out;
5683           emit_jl(1);
5684         }else{
5685           add_to_linker((int)out,ba[i],internal);
5686           emit_jge(0);
5687         }
5688       }
5689       if(invert) {
5690         if(taken) set_jump_target(taken,(int)out);
5691         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5692         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5693           if(adj) {
5694             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5695             add_to_linker((int)out,ba[i],internal);
5696           }else{
5697             emit_addnop(13);
5698             add_to_linker((int)out,ba[i],internal*2);
5699           }
5700           emit_jmp(0);
5701         }else
5702         #endif
5703         {
5704           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5705           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5706           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5707           if(internal)
5708             assem_debug("branch: internal\n");
5709           else
5710             assem_debug("branch: external\n");
5711           if(internal&&is_ds[(ba[i]-start)>>2]) {
5712             ds_assemble_entry(i);
5713           }
5714           else {
5715             add_to_linker((int)out,ba[i],internal);
5716             emit_jmp(0);
5717           }
5718         }
5719         set_jump_target(nottaken,(int)out);
5720       }
5721
5722       if(nottaken1) set_jump_target(nottaken1,(int)out);
5723       if(adj) {
5724         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5725       }
5726     } // (!unconditional)
5727   } // if(ooo)
5728   else
5729   {
5730     // In-order execution (branch first)
5731     //if(likely[i]) printf("IOL\n");
5732     //else
5733     //printf("IOE\n");
5734     int taken=0,nottaken=0,nottaken1=0;
5735     if(!unconditional&&!nop) {
5736       if(!only32)
5737       {
5738         assert(s1h>=0);
5739         if((opcode[i]&0x2f)==4) // BEQ
5740         {
5741           if(s2h>=0) emit_cmp(s1h,s2h);
5742           else emit_test(s1h,s1h);
5743           nottaken1=(int)out;
5744           emit_jne(2);
5745         }
5746         if((opcode[i]&0x2f)==5) // BNE
5747         {
5748           if(s2h>=0) emit_cmp(s1h,s2h);
5749           else emit_test(s1h,s1h);
5750           taken=(int)out;
5751           emit_jne(1);
5752         }
5753         if((opcode[i]&0x2f)==6) // BLEZ
5754         {
5755           emit_test(s1h,s1h);
5756           taken=(int)out;
5757           emit_js(1);
5758           nottaken1=(int)out;
5759           emit_jne(2);
5760         }
5761         if((opcode[i]&0x2f)==7) // BGTZ
5762         {
5763           emit_test(s1h,s1h);
5764           nottaken1=(int)out;
5765           emit_js(2);
5766           taken=(int)out;
5767           emit_jne(1);
5768         }
5769       } // if(!only32)
5770
5771       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5772       assert(s1l>=0);
5773       if((opcode[i]&0x2f)==4) // BEQ
5774       {
5775         if(s2l>=0) emit_cmp(s1l,s2l);
5776         else emit_test(s1l,s1l);
5777         nottaken=(int)out;
5778         emit_jne(2);
5779       }
5780       if((opcode[i]&0x2f)==5) // BNE
5781       {
5782         if(s2l>=0) emit_cmp(s1l,s2l);
5783         else emit_test(s1l,s1l);
5784         nottaken=(int)out;
5785         emit_jeq(2);
5786       }
5787       if((opcode[i]&0x2f)==6) // BLEZ
5788       {
5789         emit_cmpimm(s1l,1);
5790         nottaken=(int)out;
5791         emit_jge(2);
5792       }
5793       if((opcode[i]&0x2f)==7) // BGTZ
5794       {
5795         emit_cmpimm(s1l,1);
5796         nottaken=(int)out;
5797         emit_jl(2);
5798       }
5799     } // if(!unconditional)
5800     int adj;
5801     uint64_t ds_unneeded=branch_regs[i].u;
5802     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5803     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5804     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5805     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5806     ds_unneeded|=1;
5807     ds_unneeded_upper|=1;
5808     // branch taken
5809     if(!nop) {
5810       if(taken) set_jump_target(taken,(int)out);
5811       assem_debug("1:\n");
5812       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5813                     ds_unneeded,ds_unneeded_upper);
5814       // load regs
5815       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5816       address_generation(i+1,&branch_regs[i],0);
5817       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5818       ds_assemble(i+1,&branch_regs[i]);
5819       cc=get_reg(branch_regs[i].regmap,CCREG);
5820       if(cc==-1) {
5821         emit_loadreg(CCREG,cc=HOST_CCREG);
5822         // CHECK: Is the following instruction (fall thru) allocated ok?
5823       }
5824       assert(cc==HOST_CCREG);
5825       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5826       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5827       assem_debug("cycle count (adj)\n");
5828       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5829       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5830       if(internal)
5831         assem_debug("branch: internal\n");
5832       else
5833         assem_debug("branch: external\n");
5834       if(internal&&is_ds[(ba[i]-start)>>2]) {
5835         ds_assemble_entry(i);
5836       }
5837       else {
5838         add_to_linker((int)out,ba[i],internal);
5839         emit_jmp(0);
5840       }
5841     }
5842     // branch not taken
5843     cop1_usable=prev_cop1_usable;
5844     if(!unconditional) {
5845       if(nottaken1) set_jump_target(nottaken1,(int)out);
5846       set_jump_target(nottaken,(int)out);
5847       assem_debug("2:\n");
5848       if(!likely[i]) {
5849         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5850                       ds_unneeded,ds_unneeded_upper);
5851         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5852         address_generation(i+1,&branch_regs[i],0);
5853         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5854         ds_assemble(i+1,&branch_regs[i]);
5855       }
5856       cc=get_reg(branch_regs[i].regmap,CCREG);
5857       if(cc==-1&&!likely[i]) {
5858         // Cycle count isn't in a register, temporarily load it then write it out
5859         emit_loadreg(CCREG,HOST_CCREG);
5860         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5861         int jaddr=(int)out;
5862         emit_jns(0);
5863         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5864         emit_storereg(CCREG,HOST_CCREG);
5865       }
5866       else{
5867         cc=get_reg(i_regmap,CCREG);
5868         assert(cc==HOST_CCREG);
5869         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5870         int jaddr=(int)out;
5871         emit_jns(0);
5872         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5873       }
5874     }
5875   }
5876 }
5877
5878 void sjump_assemble(int i,struct regstat *i_regs)
5879 {
5880   signed char *i_regmap=i_regs->regmap;
5881   int cc;
5882   int match;
5883   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5884   assem_debug("smatch=%d\n",match);
5885   int s1h,s1l;
5886   int prev_cop1_usable=cop1_usable;
5887   int unconditional=0,nevertaken=0;
5888   int only32=0;
5889   int invert=0;
5890   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5891   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5892   if(!match) invert=1;
5893   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5894   if(i>(ba[i]-start)>>2) invert=1;
5895   #endif
5896
5897   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5898   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5899
5900   if(ooo[i]) {
5901     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5902     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5903   }
5904   else {
5905     s1l=get_reg(i_regmap,rs1[i]);
5906     s1h=get_reg(i_regmap,rs1[i]|64);
5907   }
5908   if(rs1[i]==0)
5909   {
5910     if(opcode2[i]&1) unconditional=1;
5911     else nevertaken=1;
5912     // These are never taken (r0 is never less than zero)
5913     //assert(opcode2[i]!=0);
5914     //assert(opcode2[i]!=2);
5915     //assert(opcode2[i]!=0x10);
5916     //assert(opcode2[i]!=0x12);
5917   }
5918   else {
5919     only32=(regs[i].was32>>rs1[i])&1;
5920   }
5921
5922   if(ooo[i]) {
5923     // Out of order execution (delay slot first)
5924     //printf("OOOE\n");
5925     address_generation(i+1,i_regs,regs[i].regmap_entry);
5926     ds_assemble(i+1,i_regs);
5927     int adj;
5928     uint64_t bc_unneeded=branch_regs[i].u;
5929     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5930     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5931     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5932     bc_unneeded|=1;
5933     bc_unneeded_upper|=1;
5934     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5935                   bc_unneeded,bc_unneeded_upper);
5936     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5937     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5938     if(rt1[i]==31) {
5939       int rt,return_address;
5940       rt=get_reg(branch_regs[i].regmap,31);
5941       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5942       if(rt>=0) {
5943         // Save the PC even if the branch is not taken
5944         return_address=start+i*4+8;
5945         emit_movimm(return_address,rt); // PC into link register
5946         #ifdef IMM_PREFETCH
5947         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5948         #endif
5949       }
5950     }
5951     cc=get_reg(branch_regs[i].regmap,CCREG);
5952     assert(cc==HOST_CCREG);
5953     if(unconditional)
5954       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5955     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5956     assem_debug("cycle count (adj)\n");
5957     if(unconditional) {
5958       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5959       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5960         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5961         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5962         if(internal)
5963           assem_debug("branch: internal\n");
5964         else
5965           assem_debug("branch: external\n");
5966         if(internal&&is_ds[(ba[i]-start)>>2]) {
5967           ds_assemble_entry(i);
5968         }
5969         else {
5970           add_to_linker((int)out,ba[i],internal);
5971           emit_jmp(0);
5972         }
5973         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5974         if(((u_int)out)&7) emit_addnop(0);
5975         #endif
5976       }
5977     }
5978     else if(nevertaken) {
5979       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5980       int jaddr=(int)out;
5981       emit_jns(0);
5982       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5983     }
5984     else {
5985       int nottaken=0;
5986       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5987       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5988       if(!only32)
5989       {
5990         assert(s1h>=0);
5991         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5992         {
5993           emit_test(s1h,s1h);
5994           if(invert){
5995             nottaken=(int)out;
5996             emit_jns(1);
5997           }else{
5998             add_to_linker((int)out,ba[i],internal);
5999             emit_js(0);
6000           }
6001         }
6002         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6003         {
6004           emit_test(s1h,s1h);
6005           if(invert){
6006             nottaken=(int)out;
6007             emit_js(1);
6008           }else{
6009             add_to_linker((int)out,ba[i],internal);
6010             emit_jns(0);
6011           }
6012         }
6013       } // if(!only32)
6014       else
6015       {
6016         assert(s1l>=0);
6017         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6018         {
6019           emit_test(s1l,s1l);
6020           if(invert){
6021             nottaken=(int)out;
6022             emit_jns(1);
6023           }else{
6024             add_to_linker((int)out,ba[i],internal);
6025             emit_js(0);
6026           }
6027         }
6028         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6029         {
6030           emit_test(s1l,s1l);
6031           if(invert){
6032             nottaken=(int)out;
6033             emit_js(1);
6034           }else{
6035             add_to_linker((int)out,ba[i],internal);
6036             emit_jns(0);
6037           }
6038         }
6039       } // if(!only32)
6040
6041       if(invert) {
6042         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6043         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6044           if(adj) {
6045             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6046             add_to_linker((int)out,ba[i],internal);
6047           }else{
6048             emit_addnop(13);
6049             add_to_linker((int)out,ba[i],internal*2);
6050           }
6051           emit_jmp(0);
6052         }else
6053         #endif
6054         {
6055           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6056           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6057           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6058           if(internal)
6059             assem_debug("branch: internal\n");
6060           else
6061             assem_debug("branch: external\n");
6062           if(internal&&is_ds[(ba[i]-start)>>2]) {
6063             ds_assemble_entry(i);
6064           }
6065           else {
6066             add_to_linker((int)out,ba[i],internal);
6067             emit_jmp(0);
6068           }
6069         }
6070         set_jump_target(nottaken,(int)out);
6071       }
6072
6073       if(adj) {
6074         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6075       }
6076     } // (!unconditional)
6077   } // if(ooo)
6078   else
6079   {
6080     // In-order execution (branch first)
6081     //printf("IOE\n");
6082     int nottaken=0;
6083     if(rt1[i]==31) {
6084       int rt,return_address;
6085       rt=get_reg(branch_regs[i].regmap,31);
6086       if(rt>=0) {
6087         // Save the PC even if the branch is not taken
6088         return_address=start+i*4+8;
6089         emit_movimm(return_address,rt); // PC into link register
6090         #ifdef IMM_PREFETCH
6091         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6092         #endif
6093       }
6094     }
6095     if(!unconditional) {
6096       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6097       if(!only32)
6098       {
6099         assert(s1h>=0);
6100         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6101         {
6102           emit_test(s1h,s1h);
6103           nottaken=(int)out;
6104           emit_jns(1);
6105         }
6106         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6107         {
6108           emit_test(s1h,s1h);
6109           nottaken=(int)out;
6110           emit_js(1);
6111         }
6112       } // if(!only32)
6113       else
6114       {
6115         assert(s1l>=0);
6116         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6117         {
6118           emit_test(s1l,s1l);
6119           nottaken=(int)out;
6120           emit_jns(1);
6121         }
6122         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6123         {
6124           emit_test(s1l,s1l);
6125           nottaken=(int)out;
6126           emit_js(1);
6127         }
6128       }
6129     } // if(!unconditional)
6130     int adj;
6131     uint64_t ds_unneeded=branch_regs[i].u;
6132     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6133     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6134     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6135     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6136     ds_unneeded|=1;
6137     ds_unneeded_upper|=1;
6138     // branch taken
6139     if(!nevertaken) {
6140       //assem_debug("1:\n");
6141       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6142                     ds_unneeded,ds_unneeded_upper);
6143       // load regs
6144       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6145       address_generation(i+1,&branch_regs[i],0);
6146       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6147       ds_assemble(i+1,&branch_regs[i]);
6148       cc=get_reg(branch_regs[i].regmap,CCREG);
6149       if(cc==-1) {
6150         emit_loadreg(CCREG,cc=HOST_CCREG);
6151         // CHECK: Is the following instruction (fall thru) allocated ok?
6152       }
6153       assert(cc==HOST_CCREG);
6154       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6155       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6156       assem_debug("cycle count (adj)\n");
6157       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6158       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6159       if(internal)
6160         assem_debug("branch: internal\n");
6161       else
6162         assem_debug("branch: external\n");
6163       if(internal&&is_ds[(ba[i]-start)>>2]) {
6164         ds_assemble_entry(i);
6165       }
6166       else {
6167         add_to_linker((int)out,ba[i],internal);
6168         emit_jmp(0);
6169       }
6170     }
6171     // branch not taken
6172     cop1_usable=prev_cop1_usable;
6173     if(!unconditional) {
6174       set_jump_target(nottaken,(int)out);
6175       assem_debug("1:\n");
6176       if(!likely[i]) {
6177         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6178                       ds_unneeded,ds_unneeded_upper);
6179         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6180         address_generation(i+1,&branch_regs[i],0);
6181         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6182         ds_assemble(i+1,&branch_regs[i]);
6183       }
6184       cc=get_reg(branch_regs[i].regmap,CCREG);
6185       if(cc==-1&&!likely[i]) {
6186         // Cycle count isn't in a register, temporarily load it then write it out
6187         emit_loadreg(CCREG,HOST_CCREG);
6188         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6189         int jaddr=(int)out;
6190         emit_jns(0);
6191         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6192         emit_storereg(CCREG,HOST_CCREG);
6193       }
6194       else{
6195         cc=get_reg(i_regmap,CCREG);
6196         assert(cc==HOST_CCREG);
6197         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6198         int jaddr=(int)out;
6199         emit_jns(0);
6200         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6201       }
6202     }
6203   }
6204 }
6205
6206 void fjump_assemble(int i,struct regstat *i_regs)
6207 {
6208   signed char *i_regmap=i_regs->regmap;
6209   int cc;
6210   int match;
6211   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6212   assem_debug("fmatch=%d\n",match);
6213   int fs,cs;
6214   int eaddr;
6215   int invert=0;
6216   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6217   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6218   if(!match) invert=1;
6219   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6220   if(i>(ba[i]-start)>>2) invert=1;
6221   #endif
6222
6223   if(ooo[i]) {
6224     fs=get_reg(branch_regs[i].regmap,FSREG);
6225     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6226   }
6227   else {
6228     fs=get_reg(i_regmap,FSREG);
6229   }
6230
6231   // Check cop1 unusable
6232   if(!cop1_usable) {
6233     cs=get_reg(i_regmap,CSREG);
6234     assert(cs>=0);
6235     emit_testimm(cs,0x20000000);
6236     eaddr=(int)out;
6237     emit_jeq(0);
6238     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6239     cop1_usable=1;
6240   }
6241
6242   if(ooo[i]) {
6243     // Out of order execution (delay slot first)
6244     //printf("OOOE\n");
6245     ds_assemble(i+1,i_regs);
6246     int adj;
6247     uint64_t bc_unneeded=branch_regs[i].u;
6248     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6249     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6250     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6251     bc_unneeded|=1;
6252     bc_unneeded_upper|=1;
6253     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6254                   bc_unneeded,bc_unneeded_upper);
6255     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6256     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6257     cc=get_reg(branch_regs[i].regmap,CCREG);
6258     assert(cc==HOST_CCREG);
6259     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6260     assem_debug("cycle count (adj)\n");
6261     if(1) {
6262       int nottaken=0;
6263       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6264       if(1) {
6265         assert(fs>=0);
6266         emit_testimm(fs,0x800000);
6267         if(source[i]&0x10000) // BC1T
6268         {
6269           if(invert){
6270             nottaken=(int)out;
6271             emit_jeq(1);
6272           }else{
6273             add_to_linker((int)out,ba[i],internal);
6274             emit_jne(0);
6275           }
6276         }
6277         else // BC1F
6278           if(invert){
6279             nottaken=(int)out;
6280             emit_jne(1);
6281           }else{
6282             add_to_linker((int)out,ba[i],internal);
6283             emit_jeq(0);
6284           }
6285         {
6286         }
6287       } // if(!only32)
6288
6289       if(invert) {
6290         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6291         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6292         else if(match) emit_addnop(13);
6293         #endif
6294         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6295         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6296         if(internal)
6297           assem_debug("branch: internal\n");
6298         else
6299           assem_debug("branch: external\n");
6300         if(internal&&is_ds[(ba[i]-start)>>2]) {
6301           ds_assemble_entry(i);
6302         }
6303         else {
6304           add_to_linker((int)out,ba[i],internal);
6305           emit_jmp(0);
6306         }
6307         set_jump_target(nottaken,(int)out);
6308       }
6309
6310       if(adj) {
6311         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6312       }
6313     } // (!unconditional)
6314   } // if(ooo)
6315   else
6316   {
6317     // In-order execution (branch first)
6318     //printf("IOE\n");
6319     int nottaken=0;
6320     if(1) {
6321       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6322       if(1) {
6323         assert(fs>=0);
6324         emit_testimm(fs,0x800000);
6325         if(source[i]&0x10000) // BC1T
6326         {
6327           nottaken=(int)out;
6328           emit_jeq(1);
6329         }
6330         else // BC1F
6331         {
6332           nottaken=(int)out;
6333           emit_jne(1);
6334         }
6335       }
6336     } // if(!unconditional)
6337     int adj;
6338     uint64_t ds_unneeded=branch_regs[i].u;
6339     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6340     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6341     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6342     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6343     ds_unneeded|=1;
6344     ds_unneeded_upper|=1;
6345     // branch taken
6346     //assem_debug("1:\n");
6347     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6348                   ds_unneeded,ds_unneeded_upper);
6349     // load regs
6350     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6351     address_generation(i+1,&branch_regs[i],0);
6352     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6353     ds_assemble(i+1,&branch_regs[i]);
6354     cc=get_reg(branch_regs[i].regmap,CCREG);
6355     if(cc==-1) {
6356       emit_loadreg(CCREG,cc=HOST_CCREG);
6357       // CHECK: Is the following instruction (fall thru) allocated ok?
6358     }
6359     assert(cc==HOST_CCREG);
6360     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6361     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6362     assem_debug("cycle count (adj)\n");
6363     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6364     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6365     if(internal)
6366       assem_debug("branch: internal\n");
6367     else
6368       assem_debug("branch: external\n");
6369     if(internal&&is_ds[(ba[i]-start)>>2]) {
6370       ds_assemble_entry(i);
6371     }
6372     else {
6373       add_to_linker((int)out,ba[i],internal);
6374       emit_jmp(0);
6375     }
6376
6377     // branch not taken
6378     if(1) { // <- FIXME (don't need this)
6379       set_jump_target(nottaken,(int)out);
6380       assem_debug("1:\n");
6381       if(!likely[i]) {
6382         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6383                       ds_unneeded,ds_unneeded_upper);
6384         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6385         address_generation(i+1,&branch_regs[i],0);
6386         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6387         ds_assemble(i+1,&branch_regs[i]);
6388       }
6389       cc=get_reg(branch_regs[i].regmap,CCREG);
6390       if(cc==-1&&!likely[i]) {
6391         // Cycle count isn't in a register, temporarily load it then write it out
6392         emit_loadreg(CCREG,HOST_CCREG);
6393         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6394         int jaddr=(int)out;
6395         emit_jns(0);
6396         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6397         emit_storereg(CCREG,HOST_CCREG);
6398       }
6399       else{
6400         cc=get_reg(i_regmap,CCREG);
6401         assert(cc==HOST_CCREG);
6402         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6403         int jaddr=(int)out;
6404         emit_jns(0);
6405         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6406       }
6407     }
6408   }
6409 }
6410
6411 static void pagespan_assemble(int i,struct regstat *i_regs)
6412 {
6413   int s1l=get_reg(i_regs->regmap,rs1[i]);
6414   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6415   int s2l=get_reg(i_regs->regmap,rs2[i]);
6416   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6417   void *nt_branch=NULL;
6418   int taken=0;
6419   int nottaken=0;
6420   int unconditional=0;
6421   if(rs1[i]==0)
6422   {
6423     s1l=s2l;s1h=s2h;
6424     s2l=s2h=-1;
6425   }
6426   else if(rs2[i]==0)
6427   {
6428     s2l=s2h=-1;
6429   }
6430   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6431     s1h=s2h=-1;
6432   }
6433   int hr=0;
6434   int addr,alt,ntaddr;
6435   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6436   else {
6437     while(hr<HOST_REGS)
6438     {
6439       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6440          (i_regs->regmap[hr]&63)!=rs1[i] &&
6441          (i_regs->regmap[hr]&63)!=rs2[i] )
6442       {
6443         addr=hr++;break;
6444       }
6445       hr++;
6446     }
6447   }
6448   while(hr<HOST_REGS)
6449   {
6450     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6451        (i_regs->regmap[hr]&63)!=rs1[i] &&
6452        (i_regs->regmap[hr]&63)!=rs2[i] )
6453     {
6454       alt=hr++;break;
6455     }
6456     hr++;
6457   }
6458   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6459   {
6460     while(hr<HOST_REGS)
6461     {
6462       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6463          (i_regs->regmap[hr]&63)!=rs1[i] &&
6464          (i_regs->regmap[hr]&63)!=rs2[i] )
6465       {
6466         ntaddr=hr;break;
6467       }
6468       hr++;
6469     }
6470   }
6471   assert(hr<HOST_REGS);
6472   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6473     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6474   }
6475   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6476   if(opcode[i]==2) // J
6477   {
6478     unconditional=1;
6479   }
6480   if(opcode[i]==3) // JAL
6481   {
6482     // TODO: mini_ht
6483     int rt=get_reg(i_regs->regmap,31);
6484     emit_movimm(start+i*4+8,rt);
6485     unconditional=1;
6486   }
6487   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6488   {
6489     emit_mov(s1l,addr);
6490     if(opcode2[i]==9) // JALR
6491     {
6492       int rt=get_reg(i_regs->regmap,rt1[i]);
6493       emit_movimm(start+i*4+8,rt);
6494     }
6495   }
6496   if((opcode[i]&0x3f)==4) // BEQ
6497   {
6498     if(rs1[i]==rs2[i])
6499     {
6500       unconditional=1;
6501     }
6502     else
6503     #ifdef HAVE_CMOV_IMM
6504     if(s1h<0) {
6505       if(s2l>=0) emit_cmp(s1l,s2l);
6506       else emit_test(s1l,s1l);
6507       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6508     }
6509     else
6510     #endif
6511     {
6512       assert(s1l>=0);
6513       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6514       if(s1h>=0) {
6515         if(s2h>=0) emit_cmp(s1h,s2h);
6516         else emit_test(s1h,s1h);
6517         emit_cmovne_reg(alt,addr);
6518       }
6519       if(s2l>=0) emit_cmp(s1l,s2l);
6520       else emit_test(s1l,s1l);
6521       emit_cmovne_reg(alt,addr);
6522     }
6523   }
6524   if((opcode[i]&0x3f)==5) // BNE
6525   {
6526     #ifdef HAVE_CMOV_IMM
6527     if(s1h<0) {
6528       if(s2l>=0) emit_cmp(s1l,s2l);
6529       else emit_test(s1l,s1l);
6530       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6531     }
6532     else
6533     #endif
6534     {
6535       assert(s1l>=0);
6536       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6537       if(s1h>=0) {
6538         if(s2h>=0) emit_cmp(s1h,s2h);
6539         else emit_test(s1h,s1h);
6540         emit_cmovne_reg(alt,addr);
6541       }
6542       if(s2l>=0) emit_cmp(s1l,s2l);
6543       else emit_test(s1l,s1l);
6544       emit_cmovne_reg(alt,addr);
6545     }
6546   }
6547   if((opcode[i]&0x3f)==0x14) // BEQL
6548   {
6549     if(s1h>=0) {
6550       if(s2h>=0) emit_cmp(s1h,s2h);
6551       else emit_test(s1h,s1h);
6552       nottaken=(int)out;
6553       emit_jne(0);
6554     }
6555     if(s2l>=0) emit_cmp(s1l,s2l);
6556     else emit_test(s1l,s1l);
6557     if(nottaken) set_jump_target(nottaken,(int)out);
6558     nottaken=(int)out;
6559     emit_jne(0);
6560   }
6561   if((opcode[i]&0x3f)==0x15) // BNEL
6562   {
6563     if(s1h>=0) {
6564       if(s2h>=0) emit_cmp(s1h,s2h);
6565       else emit_test(s1h,s1h);
6566       taken=(int)out;
6567       emit_jne(0);
6568     }
6569     if(s2l>=0) emit_cmp(s1l,s2l);
6570     else emit_test(s1l,s1l);
6571     nottaken=(int)out;
6572     emit_jeq(0);
6573     if(taken) set_jump_target(taken,(int)out);
6574   }
6575   if((opcode[i]&0x3f)==6) // BLEZ
6576   {
6577     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6578     emit_cmpimm(s1l,1);
6579     if(s1h>=0) emit_mov(addr,ntaddr);
6580     emit_cmovl_reg(alt,addr);
6581     if(s1h>=0) {
6582       emit_test(s1h,s1h);
6583       emit_cmovne_reg(ntaddr,addr);
6584       emit_cmovs_reg(alt,addr);
6585     }
6586   }
6587   if((opcode[i]&0x3f)==7) // BGTZ
6588   {
6589     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6590     emit_cmpimm(s1l,1);
6591     if(s1h>=0) emit_mov(addr,alt);
6592     emit_cmovl_reg(ntaddr,addr);
6593     if(s1h>=0) {
6594       emit_test(s1h,s1h);
6595       emit_cmovne_reg(alt,addr);
6596       emit_cmovs_reg(ntaddr,addr);
6597     }
6598   }
6599   if((opcode[i]&0x3f)==0x16) // BLEZL
6600   {
6601     assert((opcode[i]&0x3f)!=0x16);
6602   }
6603   if((opcode[i]&0x3f)==0x17) // BGTZL
6604   {
6605     assert((opcode[i]&0x3f)!=0x17);
6606   }
6607   assert(opcode[i]!=1); // BLTZ/BGEZ
6608
6609   //FIXME: Check CSREG
6610   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6611     if((source[i]&0x30000)==0) // BC1F
6612     {
6613       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6614       emit_testimm(s1l,0x800000);
6615       emit_cmovne_reg(alt,addr);
6616     }
6617     if((source[i]&0x30000)==0x10000) // BC1T
6618     {
6619       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6620       emit_testimm(s1l,0x800000);
6621       emit_cmovne_reg(alt,addr);
6622     }
6623     if((source[i]&0x30000)==0x20000) // BC1FL
6624     {
6625       emit_testimm(s1l,0x800000);
6626       nottaken=(int)out;
6627       emit_jne(0);
6628     }
6629     if((source[i]&0x30000)==0x30000) // BC1TL
6630     {
6631       emit_testimm(s1l,0x800000);
6632       nottaken=(int)out;
6633       emit_jeq(0);
6634     }
6635   }
6636
6637   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6638   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6639   if(likely[i]||unconditional)
6640   {
6641     emit_movimm(ba[i],HOST_BTREG);
6642   }
6643   else if(addr!=HOST_BTREG)
6644   {
6645     emit_mov(addr,HOST_BTREG);
6646   }
6647   void *branch_addr=out;
6648   emit_jmp(0);
6649   int target_addr=start+i*4+5;
6650   void *stub=out;
6651   void *compiled_target_addr=check_addr(target_addr);
6652   emit_extjump_ds((int)branch_addr,target_addr);
6653   if(compiled_target_addr) {
6654     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6655     add_link(target_addr,stub);
6656   }
6657   else set_jump_target((int)branch_addr,(int)stub);
6658   if(likely[i]) {
6659     // Not-taken path
6660     set_jump_target((int)nottaken,(int)out);
6661     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6662     void *branch_addr=out;
6663     emit_jmp(0);
6664     int target_addr=start+i*4+8;
6665     void *stub=out;
6666     void *compiled_target_addr=check_addr(target_addr);
6667     emit_extjump_ds((int)branch_addr,target_addr);
6668     if(compiled_target_addr) {
6669       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6670       add_link(target_addr,stub);
6671     }
6672     else set_jump_target((int)branch_addr,(int)stub);
6673   }
6674 }
6675
6676 // Assemble the delay slot for the above
6677 static void pagespan_ds()
6678 {
6679   assem_debug("initial delay slot:\n");
6680   u_int vaddr=start+1;
6681   u_int page=get_page(vaddr);
6682   u_int vpage=get_vpage(vaddr);
6683   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6684   do_dirty_stub_ds();
6685   ll_add(jump_in+page,vaddr,(void *)out);
6686   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6687   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6688     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6689   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6690     emit_writeword(HOST_BTREG,(int)&branch_target);
6691   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6692   address_generation(0,&regs[0],regs[0].regmap_entry);
6693   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6694     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6695   cop1_usable=0;
6696   is_delayslot=0;
6697   switch(itype[0]) {
6698     case ALU:
6699       alu_assemble(0,&regs[0]);break;
6700     case IMM16:
6701       imm16_assemble(0,&regs[0]);break;
6702     case SHIFT:
6703       shift_assemble(0,&regs[0]);break;
6704     case SHIFTIMM:
6705       shiftimm_assemble(0,&regs[0]);break;
6706     case LOAD:
6707       load_assemble(0,&regs[0]);break;
6708     case LOADLR:
6709       loadlr_assemble(0,&regs[0]);break;
6710     case STORE:
6711       store_assemble(0,&regs[0]);break;
6712     case STORELR:
6713       storelr_assemble(0,&regs[0]);break;
6714     case COP0:
6715       cop0_assemble(0,&regs[0]);break;
6716     case COP1:
6717       cop1_assemble(0,&regs[0]);break;
6718     case C1LS:
6719       c1ls_assemble(0,&regs[0]);break;
6720     case COP2:
6721       cop2_assemble(0,&regs[0]);break;
6722     case C2LS:
6723       c2ls_assemble(0,&regs[0]);break;
6724     case C2OP:
6725       c2op_assemble(0,&regs[0]);break;
6726     case FCONV:
6727       fconv_assemble(0,&regs[0]);break;
6728     case FLOAT:
6729       float_assemble(0,&regs[0]);break;
6730     case FCOMP:
6731       fcomp_assemble(0,&regs[0]);break;
6732     case MULTDIV:
6733       multdiv_assemble(0,&regs[0]);break;
6734     case MOV:
6735       mov_assemble(0,&regs[0]);break;
6736     case SYSCALL:
6737     case HLECALL:
6738     case INTCALL:
6739     case SPAN:
6740     case UJUMP:
6741     case RJUMP:
6742     case CJUMP:
6743     case SJUMP:
6744     case FJUMP:
6745       printf("Jump in the delay slot.  This is probably a bug.\n");
6746   }
6747   int btaddr=get_reg(regs[0].regmap,BTREG);
6748   if(btaddr<0) {
6749     btaddr=get_reg(regs[0].regmap,-1);
6750     emit_readword((int)&branch_target,btaddr);
6751   }
6752   assert(btaddr!=HOST_CCREG);
6753   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6754 #ifdef HOST_IMM8
6755   emit_movimm(start+4,HOST_TEMPREG);
6756   emit_cmp(btaddr,HOST_TEMPREG);
6757 #else
6758   emit_cmpimm(btaddr,start+4);
6759 #endif
6760   int branch=(int)out;
6761   emit_jeq(0);
6762   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6763   emit_jmp(jump_vaddr_reg[btaddr]);
6764   set_jump_target(branch,(int)out);
6765   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6766   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6767 }
6768
6769 // Basic liveness analysis for MIPS registers
6770 void unneeded_registers(int istart,int iend,int r)
6771 {
6772   int i;
6773   uint64_t u,uu,gte_u,b,bu,gte_bu;
6774   uint64_t temp_u,temp_uu,temp_gte_u=0;
6775   uint64_t tdep;
6776   uint64_t gte_u_unknown=0;
6777   if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6778     gte_u_unknown=~0ll;
6779   if(iend==slen-1) {
6780     u=1;uu=1;
6781     gte_u=gte_u_unknown;
6782   }else{
6783     u=unneeded_reg[iend+1];
6784     uu=unneeded_reg_upper[iend+1];
6785     u=1;uu=1;
6786     gte_u=gte_unneeded[iend+1];
6787   }
6788
6789   for (i=iend;i>=istart;i--)
6790   {
6791     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6792     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6793     {
6794       // If subroutine call, flag return address as a possible branch target
6795       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6796
6797       if(ba[i]<start || ba[i]>=(start+slen*4))
6798       {
6799         // Branch out of this block, flush all regs
6800         u=1;
6801         uu=1;
6802         gte_u=gte_u_unknown;
6803         /* Hexagon hack
6804         if(itype[i]==UJUMP&&rt1[i]==31)
6805         {
6806           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6807         }
6808         if(itype[i]==RJUMP&&rs1[i]==31)
6809         {
6810           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6811         }
6812         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6813           if(itype[i]==UJUMP&&rt1[i]==31)
6814           {
6815             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6816             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6817           }
6818           if(itype[i]==RJUMP&&rs1[i]==31)
6819           {
6820             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6821             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6822           }
6823         }*/
6824         branch_unneeded_reg[i]=u;
6825         branch_unneeded_reg_upper[i]=uu;
6826         // Merge in delay slot
6827         tdep=(~uu>>rt1[i+1])&1;
6828         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6829         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6830         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6831         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6832         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6833         u|=1;uu|=1;
6834         gte_u|=gte_rt[i+1];
6835         gte_u&=~gte_rs[i+1];
6836         // If branch is "likely" (and conditional)
6837         // then we skip the delay slot on the fall-thru path
6838         if(likely[i]) {
6839           if(i<slen-1) {
6840             u&=unneeded_reg[i+2];
6841             uu&=unneeded_reg_upper[i+2];
6842             gte_u&=gte_unneeded[i+2];
6843           }
6844           else
6845           {
6846             u=1;
6847             uu=1;
6848             gte_u=gte_u_unknown;
6849           }
6850         }
6851       }
6852       else
6853       {
6854         // Internal branch, flag target
6855         bt[(ba[i]-start)>>2]=1;
6856         if(ba[i]<=start+i*4) {
6857           // Backward branch
6858           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6859           {
6860             // Unconditional branch
6861             temp_u=1;temp_uu=1;
6862             temp_gte_u=0;
6863           } else {
6864             // Conditional branch (not taken case)
6865             temp_u=unneeded_reg[i+2];
6866             temp_uu=unneeded_reg_upper[i+2];
6867             temp_gte_u&=gte_unneeded[i+2];
6868           }
6869           // Merge in delay slot
6870           tdep=(~temp_uu>>rt1[i+1])&1;
6871           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6872           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6873           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6874           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6875           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6876           temp_u|=1;temp_uu|=1;
6877           temp_gte_u|=gte_rt[i+1];
6878           temp_gte_u&=~gte_rs[i+1];
6879           // If branch is "likely" (and conditional)
6880           // then we skip the delay slot on the fall-thru path
6881           if(likely[i]) {
6882             if(i<slen-1) {
6883               temp_u&=unneeded_reg[i+2];
6884               temp_uu&=unneeded_reg_upper[i+2];
6885               temp_gte_u&=gte_unneeded[i+2];
6886             }
6887             else
6888             {
6889               temp_u=1;
6890               temp_uu=1;
6891               temp_gte_u=gte_u_unknown;
6892             }
6893           }
6894           tdep=(~temp_uu>>rt1[i])&1;
6895           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6896           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6897           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6898           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6899           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6900           temp_u|=1;temp_uu|=1;
6901           temp_gte_u|=gte_rt[i];
6902           temp_gte_u&=~gte_rs[i];
6903           unneeded_reg[i]=temp_u;
6904           unneeded_reg_upper[i]=temp_uu;
6905           gte_unneeded[i]=temp_gte_u;
6906           // Only go three levels deep.  This recursion can take an
6907           // excessive amount of time if there are a lot of nested loops.
6908           if(r<2) {
6909             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6910           }else{
6911             unneeded_reg[(ba[i]-start)>>2]=1;
6912             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6913             gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6914           }
6915         } /*else*/ if(1) {
6916           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6917           {
6918             // Unconditional branch
6919             u=unneeded_reg[(ba[i]-start)>>2];
6920             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6921             gte_u=gte_unneeded[(ba[i]-start)>>2];
6922             branch_unneeded_reg[i]=u;
6923             branch_unneeded_reg_upper[i]=uu;
6924         //u=1;
6925         //uu=1;
6926         //branch_unneeded_reg[i]=u;
6927         //branch_unneeded_reg_upper[i]=uu;
6928             // Merge in delay slot
6929             tdep=(~uu>>rt1[i+1])&1;
6930             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6931             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6932             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6933             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6934             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6935             u|=1;uu|=1;
6936             gte_u|=gte_rt[i+1];
6937             gte_u&=~gte_rs[i+1];
6938           } else {
6939             // Conditional branch
6940             b=unneeded_reg[(ba[i]-start)>>2];
6941             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6942             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6943             branch_unneeded_reg[i]=b;
6944             branch_unneeded_reg_upper[i]=bu;
6945         //b=1;
6946         //bu=1;
6947         //branch_unneeded_reg[i]=b;
6948         //branch_unneeded_reg_upper[i]=bu;
6949             // Branch delay slot
6950             tdep=(~uu>>rt1[i+1])&1;
6951             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6952             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6953             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6954             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6955             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6956             b|=1;bu|=1;
6957             gte_bu|=gte_rt[i+1];
6958             gte_bu&=~gte_rs[i+1];
6959             // If branch is "likely" then we skip the
6960             // delay slot on the fall-thru path
6961             if(likely[i]) {
6962               u=b;
6963               uu=bu;
6964               gte_u=gte_bu;
6965               if(i<slen-1) {
6966                 u&=unneeded_reg[i+2];
6967                 uu&=unneeded_reg_upper[i+2];
6968                 gte_u&=gte_unneeded[i+2];
6969         //u=1;
6970         //uu=1;
6971               }
6972             } else {
6973               u&=b;
6974               uu&=bu;
6975               gte_u&=gte_bu;
6976         //u=1;
6977         //uu=1;
6978             }
6979             if(i<slen-1) {
6980               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6981               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6982         //branch_unneeded_reg[i]=1;
6983         //branch_unneeded_reg_upper[i]=1;
6984             } else {
6985               branch_unneeded_reg[i]=1;
6986               branch_unneeded_reg_upper[i]=1;
6987             }
6988           }
6989         }
6990       }
6991     }
6992     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6993     {
6994       // SYSCALL instruction (software interrupt)
6995       u=1;
6996       uu=1;
6997     }
6998     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6999     {
7000       // ERET instruction (return from interrupt)
7001       u=1;
7002       uu=1;
7003     }
7004     //u=uu=1; // DEBUG
7005     tdep=(~uu>>rt1[i])&1;
7006     // Written registers are unneeded
7007     u|=1LL<<rt1[i];
7008     u|=1LL<<rt2[i];
7009     uu|=1LL<<rt1[i];
7010     uu|=1LL<<rt2[i];
7011     gte_u|=gte_rt[i];
7012     // Accessed registers are needed
7013     u&=~(1LL<<rs1[i]);
7014     u&=~(1LL<<rs2[i]);
7015     uu&=~(1LL<<us1[i]);
7016     uu&=~(1LL<<us2[i]);
7017     gte_u&=~gte_rs[i];
7018     // Source-target dependencies
7019     uu&=~(tdep<<dep1[i]);
7020     uu&=~(tdep<<dep2[i]);
7021     // R0 is always unneeded
7022     u|=1;uu|=1;
7023     // Save it
7024     unneeded_reg[i]=u;
7025     unneeded_reg_upper[i]=uu;
7026     gte_unneeded[i]=gte_u;
7027     /*
7028     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7029     printf("U:");
7030     int r;
7031     for(r=1;r<=CCREG;r++) {
7032       if((unneeded_reg[i]>>r)&1) {
7033         if(r==HIREG) printf(" HI");
7034         else if(r==LOREG) printf(" LO");
7035         else printf(" r%d",r);
7036       }
7037     }
7038     printf(" UU:");
7039     for(r=1;r<=CCREG;r++) {
7040       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7041         if(r==HIREG) printf(" HI");
7042         else if(r==LOREG) printf(" LO");
7043         else printf(" r%d",r);
7044       }
7045     }
7046     printf("\n");*/
7047   }
7048 #ifdef FORCE32
7049   for (i=iend;i>=istart;i--)
7050   {
7051     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7052   }
7053 #endif
7054 }
7055
7056 // Identify registers which are likely to contain 32-bit values
7057 // This is used to predict whether any branches will jump to a
7058 // location with 64-bit values in registers.
7059 static void provisional_32bit()
7060 {
7061   int i,j;
7062   uint64_t is32=1;
7063   uint64_t lastbranch=1;
7064
7065   for(i=0;i<slen;i++)
7066   {
7067     if(i>0) {
7068       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7069         if(i>1) is32=lastbranch;
7070         else is32=1;
7071       }
7072     }
7073     if(i>1)
7074     {
7075       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7076         if(likely[i-2]) {
7077           if(i>2) is32=lastbranch;
7078           else is32=1;
7079         }
7080       }
7081       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7082       {
7083         if(rs1[i-2]==0||rs2[i-2]==0)
7084         {
7085           if(rs1[i-2]) {
7086             is32|=1LL<<rs1[i-2];
7087           }
7088           if(rs2[i-2]) {
7089             is32|=1LL<<rs2[i-2];
7090           }
7091         }
7092       }
7093     }
7094     // If something jumps here with 64-bit values
7095     // then promote those registers to 64 bits
7096     if(bt[i])
7097     {
7098       uint64_t temp_is32=is32;
7099       for(j=i-1;j>=0;j--)
7100       {
7101         if(ba[j]==start+i*4)
7102           //temp_is32&=branch_regs[j].is32;
7103           temp_is32&=p32[j];
7104       }
7105       for(j=i;j<slen;j++)
7106       {
7107         if(ba[j]==start+i*4)
7108           temp_is32=1;
7109       }
7110       is32=temp_is32;
7111     }
7112     int type=itype[i];
7113     int op=opcode[i];
7114     int op2=opcode2[i];
7115     int rt=rt1[i];
7116     int s1=rs1[i];
7117     int s2=rs2[i];
7118     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7119       // Branches don't write registers, consider the delay slot instead.
7120       type=itype[i+1];
7121       op=opcode[i+1];
7122       op2=opcode2[i+1];
7123       rt=rt1[i+1];
7124       s1=rs1[i+1];
7125       s2=rs2[i+1];
7126       lastbranch=is32;
7127     }
7128     switch(type) {
7129       case LOAD:
7130         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7131            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7132           is32&=~(1LL<<rt);
7133         else
7134           is32|=1LL<<rt;
7135         break;
7136       case STORE:
7137       case STORELR:
7138         break;
7139       case LOADLR:
7140         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7141         if(op==0x22) is32|=1LL<<rt; // LWL
7142         break;
7143       case IMM16:
7144         if (op==0x08||op==0x09|| // ADDI/ADDIU
7145             op==0x0a||op==0x0b|| // SLTI/SLTIU
7146             op==0x0c|| // ANDI
7147             op==0x0f)  // LUI
7148         {
7149           is32|=1LL<<rt;
7150         }
7151         if(op==0x18||op==0x19) { // DADDI/DADDIU
7152           is32&=~(1LL<<rt);
7153           //if(imm[i]==0)
7154           //  is32|=((is32>>s1)&1LL)<<rt;
7155         }
7156         if(op==0x0d||op==0x0e) { // ORI/XORI
7157           uint64_t sr=((is32>>s1)&1LL);
7158           is32&=~(1LL<<rt);
7159           is32|=sr<<rt;
7160         }
7161         break;
7162       case UJUMP:
7163         break;
7164       case RJUMP:
7165         break;
7166       case CJUMP:
7167         break;
7168       case SJUMP:
7169         break;
7170       case FJUMP:
7171         break;
7172       case ALU:
7173         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7174           is32|=1LL<<rt;
7175         }
7176         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7177           is32|=1LL<<rt;
7178         }
7179         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7180           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7181           is32&=~(1LL<<rt);
7182           is32|=sr<<rt;
7183         }
7184         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7185           if(s1==0&&s2==0) {
7186             is32|=1LL<<rt;
7187           }
7188           else if(s2==0) {
7189             uint64_t sr=((is32>>s1)&1LL);
7190             is32&=~(1LL<<rt);
7191             is32|=sr<<rt;
7192           }
7193           else if(s1==0) {
7194             uint64_t sr=((is32>>s2)&1LL);
7195             is32&=~(1LL<<rt);
7196             is32|=sr<<rt;
7197           }
7198           else {
7199             is32&=~(1LL<<rt);
7200           }
7201         }
7202         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7203           if(s1==0&&s2==0) {
7204             is32|=1LL<<rt;
7205           }
7206           else if(s2==0) {
7207             uint64_t sr=((is32>>s1)&1LL);
7208             is32&=~(1LL<<rt);
7209             is32|=sr<<rt;
7210           }
7211           else {
7212             is32&=~(1LL<<rt);
7213           }
7214         }
7215         break;
7216       case MULTDIV:
7217         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7218           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7219         }
7220         else {
7221           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7222         }
7223         break;
7224       case MOV:
7225         {
7226           uint64_t sr=((is32>>s1)&1LL);
7227           is32&=~(1LL<<rt);
7228           is32|=sr<<rt;
7229         }
7230         break;
7231       case SHIFT:
7232         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7233         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7234         break;
7235       case SHIFTIMM:
7236         is32|=1LL<<rt;
7237         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7238         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7239         break;
7240       case COP0:
7241         if(op2==0) is32|=1LL<<rt; // MFC0
7242         break;
7243       case COP1:
7244       case COP2:
7245         if(op2==0) is32|=1LL<<rt; // MFC1
7246         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7247         if(op2==2) is32|=1LL<<rt; // CFC1
7248         break;
7249       case C1LS:
7250       case C2LS:
7251         break;
7252       case FLOAT:
7253       case FCONV:
7254         break;
7255       case FCOMP:
7256         break;
7257       case C2OP:
7258       case SYSCALL:
7259       case HLECALL:
7260         break;
7261       default:
7262         break;
7263     }
7264     is32|=1;
7265     p32[i]=is32;
7266
7267     if(i>0)
7268     {
7269       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7270       {
7271         if(rt1[i-1]==31) // JAL/JALR
7272         {
7273           // Subroutine call will return here, don't alloc any registers
7274           is32=1;
7275         }
7276         else if(i+1<slen)
7277         {
7278           // Internal branch will jump here, match registers to caller
7279           is32=0x3FFFFFFFFLL;
7280         }
7281       }
7282     }
7283   }
7284 }
7285
7286 // Identify registers which may be assumed to contain 32-bit values
7287 // and where optimizations will rely on this.
7288 // This is used to determine whether backward branches can safely
7289 // jump to a location with 64-bit values in registers.
7290 static void provisional_r32()
7291 {
7292   u_int r32=0;
7293   int i;
7294
7295   for (i=slen-1;i>=0;i--)
7296   {
7297     int hr;
7298     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7299     {
7300       if(ba[i]<start || ba[i]>=(start+slen*4))
7301       {
7302         // Branch out of this block, don't need anything
7303         r32=0;
7304       }
7305       else
7306       {
7307         // Internal branch
7308         // Need whatever matches the target
7309         // (and doesn't get overwritten by the delay slot instruction)
7310         r32=0;
7311         int t=(ba[i]-start)>>2;
7312         if(ba[i]>start+i*4) {
7313           // Forward branch
7314           //if(!(requires_32bit[t]&~regs[i].was32))
7315           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7316           if(!(pr32[t]&~regs[i].was32))
7317             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7318         }else{
7319           // Backward branch
7320           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7321             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7322         }
7323       }
7324       // Conditional branch may need registers for following instructions
7325       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7326       {
7327         if(i<slen-2) {
7328           //r32|=requires_32bit[i+2];
7329           r32|=pr32[i+2];
7330           r32&=regs[i].was32;
7331           // Mark this address as a branch target since it may be called
7332           // upon return from interrupt
7333           //bt[i+2]=1;
7334         }
7335       }
7336       // Merge in delay slot
7337       if(!likely[i]) {
7338         // These are overwritten unless the branch is "likely"
7339         // and the delay slot is nullified if not taken
7340         r32&=~(1LL<<rt1[i+1]);
7341         r32&=~(1LL<<rt2[i+1]);
7342       }
7343       // Assume these are needed (delay slot)
7344       if(us1[i+1]>0)
7345       {
7346         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7347       }
7348       if(us2[i+1]>0)
7349       {
7350         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7351       }
7352       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7353       {
7354         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7355       }
7356       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7357       {
7358         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7359       }
7360     }
7361     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7362     {
7363       // SYSCALL instruction (software interrupt)
7364       r32=0;
7365     }
7366     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7367     {
7368       // ERET instruction (return from interrupt)
7369       r32=0;
7370     }
7371     // Check 32 bits
7372     r32&=~(1LL<<rt1[i]);
7373     r32&=~(1LL<<rt2[i]);
7374     if(us1[i]>0)
7375     {
7376       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7377     }
7378     if(us2[i]>0)
7379     {
7380       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7381     }
7382     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7383     {
7384       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7385     }
7386     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7387     {
7388       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7389     }
7390     //requires_32bit[i]=r32;
7391     pr32[i]=r32;
7392
7393     // Dirty registers which are 32-bit, require 32-bit input
7394     // as they will be written as 32-bit values
7395     for(hr=0;hr<HOST_REGS;hr++)
7396     {
7397       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7398         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7399           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7400           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7401           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7402         }
7403       }
7404     }
7405   }
7406 }
7407
7408 // Write back dirty registers as soon as we will no longer modify them,
7409 // so that we don't end up with lots of writes at the branches.
7410 void clean_registers(int istart,int iend,int wr)
7411 {
7412   int i;
7413   int r;
7414   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7415   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7416   if(iend==slen-1) {
7417     will_dirty_i=will_dirty_next=0;
7418     wont_dirty_i=wont_dirty_next=0;
7419   }else{
7420     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7421     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7422   }
7423   for (i=iend;i>=istart;i--)
7424   {
7425     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7426     {
7427       if(ba[i]<start || ba[i]>=(start+slen*4))
7428       {
7429         // Branch out of this block, flush all regs
7430         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7431         {
7432           // Unconditional branch
7433           will_dirty_i=0;
7434           wont_dirty_i=0;
7435           // Merge in delay slot (will dirty)
7436           for(r=0;r<HOST_REGS;r++) {
7437             if(r!=EXCLUDE_REG) {
7438               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7439               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7440               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7441               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7442               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7443               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7444               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7445               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7446               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7447               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7448               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7449               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7450               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7451               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7452             }
7453           }
7454         }
7455         else
7456         {
7457           // Conditional branch
7458           will_dirty_i=0;
7459           wont_dirty_i=wont_dirty_next;
7460           // Merge in delay slot (will dirty)
7461           for(r=0;r<HOST_REGS;r++) {
7462             if(r!=EXCLUDE_REG) {
7463               if(!likely[i]) {
7464                 // Might not dirty if likely branch is not taken
7465                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7466                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7467                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7468                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7469                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7470                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7471                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7472                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7473                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7474                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7475                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7476                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7477                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7478                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7479               }
7480             }
7481           }
7482         }
7483         // Merge in delay slot (wont dirty)
7484         for(r=0;r<HOST_REGS;r++) {
7485           if(r!=EXCLUDE_REG) {
7486             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7487             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7488             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7489             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7490             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7491             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7492             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7493             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7494             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7495             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7496           }
7497         }
7498         if(wr) {
7499           #ifndef DESTRUCTIVE_WRITEBACK
7500           branch_regs[i].dirty&=wont_dirty_i;
7501           #endif
7502           branch_regs[i].dirty|=will_dirty_i;
7503         }
7504       }
7505       else
7506       {
7507         // Internal branch
7508         if(ba[i]<=start+i*4) {
7509           // Backward branch
7510           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7511           {
7512             // Unconditional branch
7513             temp_will_dirty=0;
7514             temp_wont_dirty=0;
7515             // Merge in delay slot (will dirty)
7516             for(r=0;r<HOST_REGS;r++) {
7517               if(r!=EXCLUDE_REG) {
7518                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7519                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7520                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7521                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7522                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7523                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7524                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7525                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7526                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7527                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7528                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7529                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7530                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7531                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7532               }
7533             }
7534           } else {
7535             // Conditional branch (not taken case)
7536             temp_will_dirty=will_dirty_next;
7537             temp_wont_dirty=wont_dirty_next;
7538             // Merge in delay slot (will dirty)
7539             for(r=0;r<HOST_REGS;r++) {
7540               if(r!=EXCLUDE_REG) {
7541                 if(!likely[i]) {
7542                   // Will not dirty if likely branch is not taken
7543                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7544                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7545                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7546                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7547                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7548                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7549                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7550                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7551                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7552                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7553                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7554                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7555                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7556                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7557                 }
7558               }
7559             }
7560           }
7561           // Merge in delay slot (wont dirty)
7562           for(r=0;r<HOST_REGS;r++) {
7563             if(r!=EXCLUDE_REG) {
7564               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7565               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7566               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7567               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7568               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7569               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7570               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7571               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7572               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7573               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7574             }
7575           }
7576           // Deal with changed mappings
7577           if(i<iend) {
7578             for(r=0;r<HOST_REGS;r++) {
7579               if(r!=EXCLUDE_REG) {
7580                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7581                   temp_will_dirty&=~(1<<r);
7582                   temp_wont_dirty&=~(1<<r);
7583                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7584                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7585                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7586                   } else {
7587                     temp_will_dirty|=1<<r;
7588                     temp_wont_dirty|=1<<r;
7589                   }
7590                 }
7591               }
7592             }
7593           }
7594           if(wr) {
7595             will_dirty[i]=temp_will_dirty;
7596             wont_dirty[i]=temp_wont_dirty;
7597             clean_registers((ba[i]-start)>>2,i-1,0);
7598           }else{
7599             // Limit recursion.  It can take an excessive amount
7600             // of time if there are a lot of nested loops.
7601             will_dirty[(ba[i]-start)>>2]=0;
7602             wont_dirty[(ba[i]-start)>>2]=-1;
7603           }
7604         }
7605         /*else*/ if(1)
7606         {
7607           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7608           {
7609             // Unconditional branch
7610             will_dirty_i=0;
7611             wont_dirty_i=0;
7612           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7613             for(r=0;r<HOST_REGS;r++) {
7614               if(r!=EXCLUDE_REG) {
7615                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7616                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7617                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7618                 }
7619                 if(branch_regs[i].regmap[r]>=0) {
7620                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7621                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7622                 }
7623               }
7624             }
7625           //}
7626             // Merge in delay slot
7627             for(r=0;r<HOST_REGS;r++) {
7628               if(r!=EXCLUDE_REG) {
7629                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7630                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7631                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7632                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7633                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7634                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7635                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7636                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7637                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7638                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7639                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7640                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7641                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7642                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7643               }
7644             }
7645           } else {
7646             // Conditional branch
7647             will_dirty_i=will_dirty_next;
7648             wont_dirty_i=wont_dirty_next;
7649           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7650             for(r=0;r<HOST_REGS;r++) {
7651               if(r!=EXCLUDE_REG) {
7652                 signed char target_reg=branch_regs[i].regmap[r];
7653                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7654                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7655                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7656                 }
7657                 else if(target_reg>=0) {
7658                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7659                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7660                 }
7661                 // Treat delay slot as part of branch too
7662                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7663                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7664                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7665                 }
7666                 else
7667                 {
7668                   will_dirty[i+1]&=~(1<<r);
7669                 }*/
7670               }
7671             }
7672           //}
7673             // Merge in delay slot
7674             for(r=0;r<HOST_REGS;r++) {
7675               if(r!=EXCLUDE_REG) {
7676                 if(!likely[i]) {
7677                   // Might not dirty if likely branch is not taken
7678                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7679                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7680                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7681                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7682                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7683                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7684                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7685                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7686                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7687                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7688                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7689                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7690                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7691                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7692                 }
7693               }
7694             }
7695           }
7696           // Merge in delay slot (won't dirty)
7697           for(r=0;r<HOST_REGS;r++) {
7698             if(r!=EXCLUDE_REG) {
7699               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7700               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7701               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7702               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7703               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7704               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7705               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7706               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7707               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7708               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7709             }
7710           }
7711           if(wr) {
7712             #ifndef DESTRUCTIVE_WRITEBACK
7713             branch_regs[i].dirty&=wont_dirty_i;
7714             #endif
7715             branch_regs[i].dirty|=will_dirty_i;
7716           }
7717         }
7718       }
7719     }
7720     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7721     {
7722       // SYSCALL instruction (software interrupt)
7723       will_dirty_i=0;
7724       wont_dirty_i=0;
7725     }
7726     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7727     {
7728       // ERET instruction (return from interrupt)
7729       will_dirty_i=0;
7730       wont_dirty_i=0;
7731     }
7732     will_dirty_next=will_dirty_i;
7733     wont_dirty_next=wont_dirty_i;
7734     for(r=0;r<HOST_REGS;r++) {
7735       if(r!=EXCLUDE_REG) {
7736         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7737         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7738         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7739         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7740         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7741         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7742         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7743         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7744         if(i>istart) {
7745           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7746           {
7747             // Don't store a register immediately after writing it,
7748             // may prevent dual-issue.
7749             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7750             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7751           }
7752         }
7753       }
7754     }
7755     // Save it
7756     will_dirty[i]=will_dirty_i;
7757     wont_dirty[i]=wont_dirty_i;
7758     // Mark registers that won't be dirtied as not dirty
7759     if(wr) {
7760       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7761       for(r=0;r<HOST_REGS;r++) {
7762         if((will_dirty_i>>r)&1) {
7763           printf(" r%d",r);
7764         }
7765       }
7766       printf("\n");*/
7767
7768       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7769         regs[i].dirty|=will_dirty_i;
7770         #ifndef DESTRUCTIVE_WRITEBACK
7771         regs[i].dirty&=wont_dirty_i;
7772         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7773         {
7774           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7775             for(r=0;r<HOST_REGS;r++) {
7776               if(r!=EXCLUDE_REG) {
7777                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7778                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7779                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7780               }
7781             }
7782           }
7783         }
7784         else
7785         {
7786           if(i<iend) {
7787             for(r=0;r<HOST_REGS;r++) {
7788               if(r!=EXCLUDE_REG) {
7789                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7790                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7791                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7792               }
7793             }
7794           }
7795         }
7796         #endif
7797       //}
7798     }
7799     // Deal with changed mappings
7800     temp_will_dirty=will_dirty_i;
7801     temp_wont_dirty=wont_dirty_i;
7802     for(r=0;r<HOST_REGS;r++) {
7803       if(r!=EXCLUDE_REG) {
7804         int nr;
7805         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7806           if(wr) {
7807             #ifndef DESTRUCTIVE_WRITEBACK
7808             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7809             #endif
7810             regs[i].wasdirty|=will_dirty_i&(1<<r);
7811           }
7812         }
7813         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7814           // Register moved to a different register
7815           will_dirty_i&=~(1<<r);
7816           wont_dirty_i&=~(1<<r);
7817           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7818           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7819           if(wr) {
7820             #ifndef DESTRUCTIVE_WRITEBACK
7821             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7822             #endif
7823             regs[i].wasdirty|=will_dirty_i&(1<<r);
7824           }
7825         }
7826         else {
7827           will_dirty_i&=~(1<<r);
7828           wont_dirty_i&=~(1<<r);
7829           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7830             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7831             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7832           } else {
7833             wont_dirty_i|=1<<r;
7834             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7835           }
7836         }
7837       }
7838     }
7839   }
7840 }
7841
7842 #ifdef DISASM
7843   /* disassembly */
7844 void disassemble_inst(int i)
7845 {
7846     if (bt[i]) printf("*"); else printf(" ");
7847     switch(itype[i]) {
7848       case UJUMP:
7849         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7850       case CJUMP:
7851         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7852       case SJUMP:
7853         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7854       case FJUMP:
7855         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7856       case RJUMP:
7857         if (opcode[i]==0x9&&rt1[i]!=31)
7858           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7859         else
7860           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7861         break;
7862       case SPAN:
7863         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7864       case IMM16:
7865         if(opcode[i]==0xf) //LUI
7866           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7867         else
7868           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7869         break;
7870       case LOAD:
7871       case LOADLR:
7872         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7873         break;
7874       case STORE:
7875       case STORELR:
7876         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7877         break;
7878       case ALU:
7879       case SHIFT:
7880         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7881         break;
7882       case MULTDIV:
7883         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7884         break;
7885       case SHIFTIMM:
7886         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7887         break;
7888       case MOV:
7889         if((opcode2[i]&0x1d)==0x10)
7890           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7891         else if((opcode2[i]&0x1d)==0x11)
7892           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7893         else
7894           printf (" %x: %s\n",start+i*4,insn[i]);
7895         break;
7896       case COP0:
7897         if(opcode2[i]==0)
7898           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7899         else if(opcode2[i]==4)
7900           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7901         else printf (" %x: %s\n",start+i*4,insn[i]);
7902         break;
7903       case COP1:
7904         if(opcode2[i]<3)
7905           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7906         else if(opcode2[i]>3)
7907           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7908         else printf (" %x: %s\n",start+i*4,insn[i]);
7909         break;
7910       case COP2:
7911         if(opcode2[i]<3)
7912           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7913         else if(opcode2[i]>3)
7914           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7915         else printf (" %x: %s\n",start+i*4,insn[i]);
7916         break;
7917       case C1LS:
7918         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7919         break;
7920       case C2LS:
7921         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7922         break;
7923       case INTCALL:
7924         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7925         break;
7926       default:
7927         //printf (" %s %8x\n",insn[i],source[i]);
7928         printf (" %x: %s\n",start+i*4,insn[i]);
7929     }
7930 }
7931 #else
7932 static void disassemble_inst(int i) {}
7933 #endif // DISASM
7934
7935 // clear the state completely, instead of just marking
7936 // things invalid like invalidate_all_pages() does
7937 void new_dynarec_clear_full()
7938 {
7939   int n;
7940   out=(u_char *)BASE_ADDR;
7941   memset(invalid_code,1,sizeof(invalid_code));
7942   memset(hash_table,0xff,sizeof(hash_table));
7943   memset(mini_ht,-1,sizeof(mini_ht));
7944   memset(restore_candidate,0,sizeof(restore_candidate));
7945   memset(shadow,0,sizeof(shadow));
7946   copy=shadow;
7947   expirep=16384; // Expiry pointer, +2 blocks
7948   pending_exception=0;
7949   literalcount=0;
7950   stop_after_jal=0;
7951   inv_code_start=inv_code_end=~0;
7952   // TLB
7953 #ifndef DISABLE_TLB
7954   using_tlb=0;
7955   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7956     memory_map[n]=-1;
7957   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7958     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7959   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7960     memory_map[n]=-1;
7961 #endif
7962   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7963   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7964   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7965 }
7966
7967 void new_dynarec_init()
7968 {
7969   printf("Init new dynarec\n");
7970   out=(u_char *)BASE_ADDR;
7971   if (mmap (out, 1<<TARGET_SIZE_2,
7972             PROT_READ | PROT_WRITE | PROT_EXEC,
7973             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7974             -1, 0) <= 0) {printf("mmap() failed\n");}
7975 #ifdef MUPEN64
7976   rdword=&readmem_dword;
7977   fake_pc.f.r.rs=&readmem_dword;
7978   fake_pc.f.r.rt=&readmem_dword;
7979   fake_pc.f.r.rd=&readmem_dword;
7980 #endif
7981   int n;
7982   cycle_multiplier=200;
7983   new_dynarec_clear_full();
7984 #ifdef HOST_IMM8
7985   // Copy this into local area so we don't have to put it in every literal pool
7986   invc_ptr=invalid_code;
7987 #endif
7988 #ifdef MUPEN64
7989   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7990     writemem[n] = write_nomem_new;
7991     writememb[n] = write_nomemb_new;
7992     writememh[n] = write_nomemh_new;
7993 #ifndef FORCE32
7994     writememd[n] = write_nomemd_new;
7995 #endif
7996     readmem[n] = read_nomem_new;
7997     readmemb[n] = read_nomemb_new;
7998     readmemh[n] = read_nomemh_new;
7999 #ifndef FORCE32
8000     readmemd[n] = read_nomemd_new;
8001 #endif
8002   }
8003   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8004     writemem[n] = write_rdram_new;
8005     writememb[n] = write_rdramb_new;
8006     writememh[n] = write_rdramh_new;
8007 #ifndef FORCE32
8008     writememd[n] = write_rdramd_new;
8009 #endif
8010   }
8011   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8012     writemem[n] = write_nomem_new;
8013     writememb[n] = write_nomemb_new;
8014     writememh[n] = write_nomemh_new;
8015 #ifndef FORCE32
8016     writememd[n] = write_nomemd_new;
8017 #endif
8018     readmem[n] = read_nomem_new;
8019     readmemb[n] = read_nomemb_new;
8020     readmemh[n] = read_nomemh_new;
8021 #ifndef FORCE32
8022     readmemd[n] = read_nomemd_new;
8023 #endif
8024   }
8025 #endif
8026   tlb_hacks();
8027   arch_init();
8028 }
8029
8030 void new_dynarec_cleanup()
8031 {
8032   int n;
8033   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8034   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8035   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8036   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8037   #ifdef ROM_COPY
8038   if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8039   #endif
8040 }
8041
8042 int new_recompile_block(int addr)
8043 {
8044 /*
8045   if(addr==0x800cd050) {
8046     int block;
8047     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8048     int n;
8049     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8050   }
8051 */
8052   //if(Count==365117028) tracedebug=1;
8053   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8054   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8055   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8056   //if(debug)
8057   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8058   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8059   /*if(Count>=312978186) {
8060     rlist();
8061   }*/
8062   //rlist();
8063   start = (u_int)addr&~3;
8064   //assert(((u_int)addr&1)==0);
8065   new_dynarec_did_compile=1;
8066 #ifdef PCSX
8067   if (Config.HLE && start == 0x80001000) // hlecall
8068   {
8069     // XXX: is this enough? Maybe check hleSoftCall?
8070     u_int beginning=(u_int)out;
8071     u_int page=get_page(start);
8072     invalid_code[start>>12]=0;
8073     emit_movimm(start,0);
8074     emit_writeword(0,(int)&pcaddr);
8075     emit_jmp((int)new_dyna_leave);
8076     literal_pool(0);
8077 #ifdef __arm__
8078     __clear_cache((void *)beginning,out);
8079 #endif
8080     ll_add(jump_in+page,start,(void *)beginning);
8081     return 0;
8082   }
8083   else if ((u_int)addr < 0x00200000 ||
8084     (0xa0000000 <= addr && addr < 0xa0200000)) {
8085     // used for BIOS calls mostly?
8086     source = (u_int *)((u_int)rdram+(start&0x1fffff));
8087     pagelimit = (addr&0xa0000000)|0x00200000;
8088   }
8089   else if (!Config.HLE && (
8090 /*    (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8091     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8092     // BIOS
8093     source = (u_int *)((u_int)psxR+(start&0x7ffff));
8094     pagelimit = (addr&0xfff00000)|0x80000;
8095   }
8096   else
8097 #endif
8098 #ifdef MUPEN64
8099   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8100     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8101     pagelimit = 0xa4001000;
8102   }
8103   else
8104 #endif
8105   if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8106     source = (u_int *)((u_int)rdram+start-0x80000000);
8107     pagelimit = 0x80000000+RAM_SIZE;
8108   }
8109 #ifndef DISABLE_TLB
8110   else if ((signed int)addr >= (signed int)0xC0000000) {
8111     //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8112     //if(tlb_LUT_r[start>>12])
8113       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8114     if((signed int)memory_map[start>>12]>=0) {
8115       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8116       pagelimit=(start+4096)&0xFFFFF000;
8117       int map=memory_map[start>>12];
8118       int i;
8119       for(i=0;i<5;i++) {
8120         //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8121         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8122       }
8123       assem_debug("pagelimit=%x\n",pagelimit);
8124       assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8125     }
8126     else {
8127       assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8128       //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8129       return -1; // Caller will invoke exception handler
8130     }
8131     //printf("source= %x\n",(int)source);
8132   }
8133 #endif
8134   else {
8135     printf("Compile at bogus memory address: %x \n", (int)addr);
8136     exit(1);
8137   }
8138
8139   /* Pass 1: disassemble */
8140   /* Pass 2: register dependencies, branch targets */
8141   /* Pass 3: register allocation */
8142   /* Pass 4: branch dependencies */
8143   /* Pass 5: pre-alloc */
8144   /* Pass 6: optimize clean/dirty state */
8145   /* Pass 7: flag 32-bit registers */
8146   /* Pass 8: assembly */
8147   /* Pass 9: linker */
8148   /* Pass 10: garbage collection / free memory */
8149
8150   int i,j;
8151   int done=0;
8152   unsigned int type,op,op2;
8153
8154   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8155
8156   /* Pass 1 disassembly */
8157
8158   for(i=0;!done;i++) {
8159     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8160     minimum_free_regs[i]=0;
8161     opcode[i]=op=source[i]>>26;
8162     switch(op)
8163     {
8164       case 0x00: strcpy(insn[i],"special"); type=NI;
8165         op2=source[i]&0x3f;
8166         switch(op2)
8167         {
8168           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8169           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8170           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8171           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8172           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8173           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8174           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8175           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8176           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8177           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8178           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8179           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8180           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8181           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8182           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8183           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8184           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8185           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8186           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8187           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8188           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8189           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8190           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8191           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8192           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8193           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8194           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8195           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8196           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8197           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8198           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8199           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8200           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8201           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8202           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8203 #ifndef FORCE32
8204           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8205           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8206           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8207           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8208           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8209           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8210           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8211           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8212           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8213           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8214           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8215           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8216           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8217           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8218           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8219           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8220           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8221 #endif
8222         }
8223         break;
8224       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8225         op2=(source[i]>>16)&0x1f;
8226         switch(op2)
8227         {
8228           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8229           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8230           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8231           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8232           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8233           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8234           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8235           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8236           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8237           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8238           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8239           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8240           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8241           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8242         }
8243         break;
8244       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8245       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8246       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8247       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8248       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8249       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8250       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8251       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8252       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8253       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8254       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8255       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8256       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8257       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8258       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8259         op2=(source[i]>>21)&0x1f;
8260         switch(op2)
8261         {
8262           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8263           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8264           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8265           switch(source[i]&0x3f)
8266           {
8267             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8268             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8269             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8270             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8271 #ifdef PCSX
8272             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8273 #else
8274             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8275 #endif
8276           }
8277         }
8278         break;
8279       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8280         op2=(source[i]>>21)&0x1f;
8281         switch(op2)
8282         {
8283           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8284           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8285           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8286           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8287           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8288           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8289           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8290           switch((source[i]>>16)&0x3)
8291           {
8292             case 0x00: strcpy(insn[i],"BC1F"); break;
8293             case 0x01: strcpy(insn[i],"BC1T"); break;
8294             case 0x02: strcpy(insn[i],"BC1FL"); break;
8295             case 0x03: strcpy(insn[i],"BC1TL"); break;
8296           }
8297           break;
8298           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8299           switch(source[i]&0x3f)
8300           {
8301             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8302             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8303             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8304             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8305             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8306             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8307             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8308             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8309             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8310             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8311             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8312             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8313             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8314             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8315             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8316             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8317             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8318             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8319             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8320             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8321             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8322             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8323             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8324             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8325             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8326             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8327             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8328             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8329             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8330             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8331             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8332             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8333             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8334             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8335             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8336           }
8337           break;
8338           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8339           switch(source[i]&0x3f)
8340           {
8341             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8342             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8343             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8344             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8345             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8346             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8347             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8348             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8349             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8350             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8351             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8352             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8353             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8354             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8355             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8356             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8357             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8358             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8359             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8360             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8361             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8362             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8363             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8364             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8365             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8366             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8367             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8368             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8369             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8370             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8371             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8372             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8373             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8374             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8375             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8376           }
8377           break;
8378           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8379           switch(source[i]&0x3f)
8380           {
8381             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8382             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8383           }
8384           break;
8385           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8386           switch(source[i]&0x3f)
8387           {
8388             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8389             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8390           }
8391           break;
8392         }
8393         break;
8394 #ifndef FORCE32
8395       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8396       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8397       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8398       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8399       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8400       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8401       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8402       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8403 #endif
8404       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8405       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8406       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8407       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8408       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8409       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8410       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8411 #ifndef FORCE32
8412       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8413 #endif
8414       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8415       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8416       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8417       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8418 #ifndef FORCE32
8419       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8420       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8421 #endif
8422       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8423       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8424       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8425       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8426 #ifndef FORCE32
8427       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8428       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8429       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8430 #endif
8431       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8432       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8433 #ifndef FORCE32
8434       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8435       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8436       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8437 #endif
8438 #ifdef PCSX
8439       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8440         op2=(source[i]>>21)&0x1f;
8441         //if (op2 & 0x10) {
8442         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8443           if (gte_handlers[source[i]&0x3f]!=NULL) {
8444             if (gte_regnames[source[i]&0x3f]!=NULL)
8445               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8446             else
8447               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8448             type=C2OP;
8449           }
8450         }
8451         else switch(op2)
8452         {
8453           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8454           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8455           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8456           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8457         }
8458         break;
8459       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8460       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8461       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8462 #endif
8463       default: strcpy(insn[i],"???"); type=NI;
8464         printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8465         break;
8466     }
8467     itype[i]=type;
8468     opcode2[i]=op2;
8469     /* Get registers/immediates */
8470     lt1[i]=0;
8471     us1[i]=0;
8472     us2[i]=0;
8473     dep1[i]=0;
8474     dep2[i]=0;
8475     gte_rs[i]=gte_rt[i]=0;
8476     switch(type) {
8477       case LOAD:
8478         rs1[i]=(source[i]>>21)&0x1f;
8479         rs2[i]=0;
8480         rt1[i]=(source[i]>>16)&0x1f;
8481         rt2[i]=0;
8482         imm[i]=(short)source[i];
8483         break;
8484       case STORE:
8485       case STORELR:
8486         rs1[i]=(source[i]>>21)&0x1f;
8487         rs2[i]=(source[i]>>16)&0x1f;
8488         rt1[i]=0;
8489         rt2[i]=0;
8490         imm[i]=(short)source[i];
8491         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8492         break;
8493       case LOADLR:
8494         // LWL/LWR only load part of the register,
8495         // therefore the target register must be treated as a source too
8496         rs1[i]=(source[i]>>21)&0x1f;
8497         rs2[i]=(source[i]>>16)&0x1f;
8498         rt1[i]=(source[i]>>16)&0x1f;
8499         rt2[i]=0;
8500         imm[i]=(short)source[i];
8501         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8502         if(op==0x26) dep1[i]=rt1[i]; // LWR
8503         break;
8504       case IMM16:
8505         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8506         else rs1[i]=(source[i]>>21)&0x1f;
8507         rs2[i]=0;
8508         rt1[i]=(source[i]>>16)&0x1f;
8509         rt2[i]=0;
8510         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8511           imm[i]=(unsigned short)source[i];
8512         }else{
8513           imm[i]=(short)source[i];
8514         }
8515         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8516         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8517         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8518         break;
8519       case UJUMP:
8520         rs1[i]=0;
8521         rs2[i]=0;
8522         rt1[i]=0;
8523         rt2[i]=0;
8524         // The JAL instruction writes to r31.
8525         if (op&1) {
8526           rt1[i]=31;
8527         }
8528         rs2[i]=CCREG;
8529         break;
8530       case RJUMP:
8531         rs1[i]=(source[i]>>21)&0x1f;
8532         rs2[i]=0;
8533         rt1[i]=0;
8534         rt2[i]=0;
8535         // The JALR instruction writes to rd.
8536         if (op2&1) {
8537           rt1[i]=(source[i]>>11)&0x1f;
8538         }
8539         rs2[i]=CCREG;
8540         break;
8541       case CJUMP:
8542         rs1[i]=(source[i]>>21)&0x1f;
8543         rs2[i]=(source[i]>>16)&0x1f;
8544         rt1[i]=0;
8545         rt2[i]=0;
8546         if(op&2) { // BGTZ/BLEZ
8547           rs2[i]=0;
8548         }
8549         us1[i]=rs1[i];
8550         us2[i]=rs2[i];
8551         likely[i]=op>>4;
8552         break;
8553       case SJUMP:
8554         rs1[i]=(source[i]>>21)&0x1f;
8555         rs2[i]=CCREG;
8556         rt1[i]=0;
8557         rt2[i]=0;
8558         us1[i]=rs1[i];
8559         if(op2&0x10) { // BxxAL
8560           rt1[i]=31;
8561           // NOTE: If the branch is not taken, r31 is still overwritten
8562         }
8563         likely[i]=(op2&2)>>1;
8564         break;
8565       case FJUMP:
8566         rs1[i]=FSREG;
8567         rs2[i]=CSREG;
8568         rt1[i]=0;
8569         rt2[i]=0;
8570         likely[i]=((source[i])>>17)&1;
8571         break;
8572       case ALU:
8573         rs1[i]=(source[i]>>21)&0x1f; // source
8574         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8575         rt1[i]=(source[i]>>11)&0x1f; // destination
8576         rt2[i]=0;
8577         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8578           us1[i]=rs1[i];us2[i]=rs2[i];
8579         }
8580         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8581           dep1[i]=rs1[i];dep2[i]=rs2[i];
8582         }
8583         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8584           dep1[i]=rs1[i];dep2[i]=rs2[i];
8585         }
8586         break;
8587       case MULTDIV:
8588         rs1[i]=(source[i]>>21)&0x1f; // source
8589         rs2[i]=(source[i]>>16)&0x1f; // divisor
8590         rt1[i]=HIREG;
8591         rt2[i]=LOREG;
8592         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8593           us1[i]=rs1[i];us2[i]=rs2[i];
8594         }
8595         break;
8596       case MOV:
8597         rs1[i]=0;
8598         rs2[i]=0;
8599         rt1[i]=0;
8600         rt2[i]=0;
8601         if(op2==0x10) rs1[i]=HIREG; // MFHI
8602         if(op2==0x11) rt1[i]=HIREG; // MTHI
8603         if(op2==0x12) rs1[i]=LOREG; // MFLO
8604         if(op2==0x13) rt1[i]=LOREG; // MTLO
8605         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8606         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8607         dep1[i]=rs1[i];
8608         break;
8609       case SHIFT:
8610         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8611         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8612         rt1[i]=(source[i]>>11)&0x1f; // destination
8613         rt2[i]=0;
8614         // DSLLV/DSRLV/DSRAV are 64-bit
8615         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8616         break;
8617       case SHIFTIMM:
8618         rs1[i]=(source[i]>>16)&0x1f;
8619         rs2[i]=0;
8620         rt1[i]=(source[i]>>11)&0x1f;
8621         rt2[i]=0;
8622         imm[i]=(source[i]>>6)&0x1f;
8623         // DSxx32 instructions
8624         if(op2>=0x3c) imm[i]|=0x20;
8625         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8626         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8627         break;
8628       case COP0:
8629         rs1[i]=0;
8630         rs2[i]=0;
8631         rt1[i]=0;
8632         rt2[i]=0;
8633         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8634         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8635         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8636         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8637         break;
8638       case COP1:
8639         rs1[i]=0;
8640         rs2[i]=0;
8641         rt1[i]=0;
8642         rt2[i]=0;
8643         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8644         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8645         if(op2==5) us1[i]=rs1[i]; // DMTC1
8646         rs2[i]=CSREG;
8647         break;
8648       case COP2:
8649         rs1[i]=0;
8650         rs2[i]=0;
8651         rt1[i]=0;
8652         rt2[i]=0;
8653         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8654         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8655         rs2[i]=CSREG;
8656         int gr=(source[i]>>11)&0x1F;
8657         switch(op2)
8658         {
8659           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8660           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8661           case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8662           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8663         }
8664         break;
8665       case C1LS:
8666         rs1[i]=(source[i]>>21)&0x1F;
8667         rs2[i]=CSREG;
8668         rt1[i]=0;
8669         rt2[i]=0;
8670         imm[i]=(short)source[i];
8671         break;
8672       case C2LS:
8673         rs1[i]=(source[i]>>21)&0x1F;
8674         rs2[i]=0;
8675         rt1[i]=0;
8676         rt2[i]=0;
8677         imm[i]=(short)source[i];
8678         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8679         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8680         break;
8681       case C2OP:
8682         rs1[i]=0;
8683         rs2[i]=0;
8684         rt1[i]=0;
8685         rt2[i]=0;
8686         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8687         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8688         gte_rt[i]|=1ll<<63; // every op changes flags
8689         break;
8690       case FLOAT:
8691       case FCONV:
8692         rs1[i]=0;
8693         rs2[i]=CSREG;
8694         rt1[i]=0;
8695         rt2[i]=0;
8696         break;
8697       case FCOMP:
8698         rs1[i]=FSREG;
8699         rs2[i]=CSREG;
8700         rt1[i]=FSREG;
8701         rt2[i]=0;
8702         break;
8703       case SYSCALL:
8704       case HLECALL:
8705       case INTCALL:
8706         rs1[i]=CCREG;
8707         rs2[i]=0;
8708         rt1[i]=0;
8709         rt2[i]=0;
8710         break;
8711       default:
8712         rs1[i]=0;
8713         rs2[i]=0;
8714         rt1[i]=0;
8715         rt2[i]=0;
8716     }
8717     /* Calculate branch target addresses */
8718     if(type==UJUMP)
8719       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8720     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8721       ba[i]=start+i*4+8; // Ignore never taken branch
8722     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8723       ba[i]=start+i*4+8; // Ignore never taken branch
8724     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8725       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8726     else ba[i]=-1;
8727 #ifdef PCSX
8728     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8729       int do_in_intrp=0;
8730       // branch in delay slot?
8731       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8732         // don't handle first branch and call interpreter if it's hit
8733         printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8734         do_in_intrp=1;
8735       }
8736       // basic load delay detection
8737       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8738         int t=(ba[i-1]-start)/4;
8739         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8740           // jump target wants DS result - potential load delay effect
8741           printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8742           do_in_intrp=1;
8743           bt[t+1]=1; // expected return from interpreter
8744         }
8745         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8746               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8747           // v0 overwrite like this is a sign of trouble, bail out
8748           printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8749           do_in_intrp=1;
8750         }
8751       }
8752       if(do_in_intrp) {
8753         rs1[i-1]=CCREG;
8754         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8755         ba[i-1]=-1;
8756         itype[i-1]=INTCALL;
8757         done=2;
8758         i--; // don't compile the DS
8759       }
8760     }
8761 #endif
8762     /* Is this the end of the block? */
8763     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8764       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8765         done=2;
8766       }
8767       else {
8768         if(stop_after_jal) done=1;
8769         // Stop on BREAK
8770         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8771       }
8772       // Don't recompile stuff that's already compiled
8773       if(check_addr(start+i*4+4)) done=1;
8774       // Don't get too close to the limit
8775       if(i>MAXBLOCK/2) done=1;
8776     }
8777     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8778     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8779     if(done==2) {
8780       // Does the block continue due to a branch?
8781       for(j=i-1;j>=0;j--)
8782       {
8783         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8784         if(ba[j]==start+i*4+4) done=j=0;
8785         if(ba[j]==start+i*4+8) done=j=0;
8786       }
8787     }
8788     //assert(i<MAXBLOCK-1);
8789     if(start+i*4==pagelimit-4) done=1;
8790     assert(start+i*4<pagelimit);
8791     if (i==MAXBLOCK-1) done=1;
8792     // Stop if we're compiling junk
8793     if(itype[i]==NI&&opcode[i]==0x11) {
8794       done=stop_after_jal=1;
8795       printf("Disabled speculative precompilation\n");
8796     }
8797   }
8798   slen=i;
8799   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8800     if(start+i*4==pagelimit) {
8801       itype[i-1]=SPAN;
8802     }
8803   }
8804   assert(slen>0);
8805
8806   /* Pass 2 - Register dependencies and branch targets */
8807
8808   unneeded_registers(0,slen-1,0);
8809
8810   /* Pass 3 - Register allocation */
8811
8812   struct regstat current; // Current register allocations/status
8813   current.is32=1;
8814   current.dirty=0;
8815   current.u=unneeded_reg[0];
8816   current.uu=unneeded_reg_upper[0];
8817   clear_all_regs(current.regmap);
8818   alloc_reg(&current,0,CCREG);
8819   dirty_reg(&current,CCREG);
8820   current.isconst=0;
8821   current.wasconst=0;
8822   current.waswritten=0;
8823   int ds=0;
8824   int cc=0;
8825   int hr=-1;
8826
8827 #ifndef FORCE32
8828   provisional_32bit();
8829 #endif
8830   if((u_int)addr&1) {
8831     // First instruction is delay slot
8832     cc=-1;
8833     bt[1]=1;
8834     ds=1;
8835     unneeded_reg[0]=1;
8836     unneeded_reg_upper[0]=1;
8837     current.regmap[HOST_BTREG]=BTREG;
8838   }
8839
8840   for(i=0;i<slen;i++)
8841   {
8842     if(bt[i])
8843     {
8844       int hr;
8845       for(hr=0;hr<HOST_REGS;hr++)
8846       {
8847         // Is this really necessary?
8848         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8849       }
8850       current.isconst=0;
8851       current.waswritten=0;
8852     }
8853     if(i>1)
8854     {
8855       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8856       {
8857         if(rs1[i-2]==0||rs2[i-2]==0)
8858         {
8859           if(rs1[i-2]) {
8860             current.is32|=1LL<<rs1[i-2];
8861             int hr=get_reg(current.regmap,rs1[i-2]|64);
8862             if(hr>=0) current.regmap[hr]=-1;
8863           }
8864           if(rs2[i-2]) {
8865             current.is32|=1LL<<rs2[i-2];
8866             int hr=get_reg(current.regmap,rs2[i-2]|64);
8867             if(hr>=0) current.regmap[hr]=-1;
8868           }
8869         }
8870       }
8871     }
8872 #ifndef FORCE32
8873     // If something jumps here with 64-bit values
8874     // then promote those registers to 64 bits
8875     if(bt[i])
8876     {
8877       uint64_t temp_is32=current.is32;
8878       for(j=i-1;j>=0;j--)
8879       {
8880         if(ba[j]==start+i*4)
8881           temp_is32&=branch_regs[j].is32;
8882       }
8883       for(j=i;j<slen;j++)
8884       {
8885         if(ba[j]==start+i*4)
8886           //temp_is32=1;
8887           temp_is32&=p32[j];
8888       }
8889       if(temp_is32!=current.is32) {
8890         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8891         #ifndef DESTRUCTIVE_WRITEBACK
8892         if(ds)
8893         #endif
8894         for(hr=0;hr<HOST_REGS;hr++)
8895         {
8896           int r=current.regmap[hr];
8897           if(r>0&&r<64)
8898           {
8899             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8900               temp_is32|=1LL<<r;
8901               //printf("restore %d\n",r);
8902             }
8903           }
8904         }
8905         current.is32=temp_is32;
8906       }
8907     }
8908 #else
8909     current.is32=-1LL;
8910 #endif
8911
8912     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8913     regs[i].wasconst=current.isconst;
8914     regs[i].was32=current.is32;
8915     regs[i].wasdirty=current.dirty;
8916     regs[i].loadedconst=0;
8917     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8918     // To change a dirty register from 32 to 64 bits, we must write
8919     // it out during the previous cycle (for branches, 2 cycles)
8920     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8921     {
8922       uint64_t temp_is32=current.is32;
8923       for(j=i-1;j>=0;j--)
8924       {
8925         if(ba[j]==start+i*4+4)
8926           temp_is32&=branch_regs[j].is32;
8927       }
8928       for(j=i;j<slen;j++)
8929       {
8930         if(ba[j]==start+i*4+4)
8931           //temp_is32=1;
8932           temp_is32&=p32[j];
8933       }
8934       if(temp_is32!=current.is32) {
8935         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8936         for(hr=0;hr<HOST_REGS;hr++)
8937         {
8938           int r=current.regmap[hr];
8939           if(r>0)
8940           {
8941             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8942               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8943               {
8944                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8945                 {
8946                   //printf("dump %d/r%d\n",hr,r);
8947                   current.regmap[hr]=-1;
8948                   if(get_reg(current.regmap,r|64)>=0)
8949                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8950                 }
8951               }
8952             }
8953           }
8954         }
8955       }
8956     }
8957     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8958     {
8959       uint64_t temp_is32=current.is32;
8960       for(j=i-1;j>=0;j--)
8961       {
8962         if(ba[j]==start+i*4+8)
8963           temp_is32&=branch_regs[j].is32;
8964       }
8965       for(j=i;j<slen;j++)
8966       {
8967         if(ba[j]==start+i*4+8)
8968           //temp_is32=1;
8969           temp_is32&=p32[j];
8970       }
8971       if(temp_is32!=current.is32) {
8972         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8973         for(hr=0;hr<HOST_REGS;hr++)
8974         {
8975           int r=current.regmap[hr];
8976           if(r>0)
8977           {
8978             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8979               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8980               {
8981                 //printf("dump %d/r%d\n",hr,r);
8982                 current.regmap[hr]=-1;
8983                 if(get_reg(current.regmap,r|64)>=0)
8984                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8985               }
8986             }
8987           }
8988         }
8989       }
8990     }
8991     #endif
8992     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8993       if(i+1<slen) {
8994         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8995         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8996         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8997         current.u|=1;
8998         current.uu|=1;
8999       } else {
9000         current.u=1;
9001         current.uu=1;
9002       }
9003     } else {
9004       if(i+1<slen) {
9005         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9006         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9007         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9008         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9009         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9010         current.u|=1;
9011         current.uu|=1;
9012       } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9013     }
9014     is_ds[i]=ds;
9015     if(ds) {
9016       ds=0; // Skip delay slot, already allocated as part of branch
9017       // ...but we need to alloc it in case something jumps here
9018       if(i+1<slen) {
9019         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9020         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9021       }else{
9022         current.u=branch_unneeded_reg[i-1];
9023         current.uu=branch_unneeded_reg_upper[i-1];
9024       }
9025       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9026       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9027       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9028       current.u|=1;
9029       current.uu|=1;
9030       struct regstat temp;
9031       memcpy(&temp,&current,sizeof(current));
9032       temp.wasdirty=temp.dirty;
9033       temp.was32=temp.is32;
9034       // TODO: Take into account unconditional branches, as below
9035       delayslot_alloc(&temp,i);
9036       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9037       regs[i].wasdirty=temp.wasdirty;
9038       regs[i].was32=temp.was32;
9039       regs[i].dirty=temp.dirty;
9040       regs[i].is32=temp.is32;
9041       regs[i].isconst=0;
9042       regs[i].wasconst=0;
9043       current.isconst=0;
9044       // Create entry (branch target) regmap
9045       for(hr=0;hr<HOST_REGS;hr++)
9046       {
9047         int r=temp.regmap[hr];
9048         if(r>=0) {
9049           if(r!=regmap_pre[i][hr]) {
9050             regs[i].regmap_entry[hr]=-1;
9051           }
9052           else
9053           {
9054             if(r<64){
9055               if((current.u>>r)&1) {
9056                 regs[i].regmap_entry[hr]=-1;
9057                 regs[i].regmap[hr]=-1;
9058                 //Don't clear regs in the delay slot as the branch might need them
9059                 //current.regmap[hr]=-1;
9060               }else
9061                 regs[i].regmap_entry[hr]=r;
9062             }
9063             else {
9064               if((current.uu>>(r&63))&1) {
9065                 regs[i].regmap_entry[hr]=-1;
9066                 regs[i].regmap[hr]=-1;
9067                 //Don't clear regs in the delay slot as the branch might need them
9068                 //current.regmap[hr]=-1;
9069               }else
9070                 regs[i].regmap_entry[hr]=r;
9071             }
9072           }
9073         } else {
9074           // First instruction expects CCREG to be allocated
9075           if(i==0&&hr==HOST_CCREG)
9076             regs[i].regmap_entry[hr]=CCREG;
9077           else
9078             regs[i].regmap_entry[hr]=-1;
9079         }
9080       }
9081     }
9082     else { // Not delay slot
9083       switch(itype[i]) {
9084         case UJUMP:
9085           //current.isconst=0; // DEBUG
9086           //current.wasconst=0; // DEBUG
9087           //regs[i].wasconst=0; // DEBUG
9088           clear_const(&current,rt1[i]);
9089           alloc_cc(&current,i);
9090           dirty_reg(&current,CCREG);
9091           if (rt1[i]==31) {
9092             alloc_reg(&current,i,31);
9093             dirty_reg(&current,31);
9094             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9095             //assert(rt1[i+1]!=rt1[i]);
9096             #ifdef REG_PREFETCH
9097             alloc_reg(&current,i,PTEMP);
9098             #endif
9099             //current.is32|=1LL<<rt1[i];
9100           }
9101           ooo[i]=1;
9102           delayslot_alloc(&current,i+1);
9103           //current.isconst=0; // DEBUG
9104           ds=1;
9105           //printf("i=%d, isconst=%x\n",i,current.isconst);
9106           break;
9107         case RJUMP:
9108           //current.isconst=0;
9109           //current.wasconst=0;
9110           //regs[i].wasconst=0;
9111           clear_const(&current,rs1[i]);
9112           clear_const(&current,rt1[i]);
9113           alloc_cc(&current,i);
9114           dirty_reg(&current,CCREG);
9115           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9116             alloc_reg(&current,i,rs1[i]);
9117             if (rt1[i]!=0) {
9118               alloc_reg(&current,i,rt1[i]);
9119               dirty_reg(&current,rt1[i]);
9120               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9121               assert(rt1[i+1]!=rt1[i]);
9122               #ifdef REG_PREFETCH
9123               alloc_reg(&current,i,PTEMP);
9124               #endif
9125             }
9126             #ifdef USE_MINI_HT
9127             if(rs1[i]==31) { // JALR
9128               alloc_reg(&current,i,RHASH);
9129               #ifndef HOST_IMM_ADDR32
9130               alloc_reg(&current,i,RHTBL);
9131               #endif
9132             }
9133             #endif
9134             delayslot_alloc(&current,i+1);
9135           } else {
9136             // The delay slot overwrites our source register,
9137             // allocate a temporary register to hold the old value.
9138             current.isconst=0;
9139             current.wasconst=0;
9140             regs[i].wasconst=0;
9141             delayslot_alloc(&current,i+1);
9142             current.isconst=0;
9143             alloc_reg(&current,i,RTEMP);
9144           }
9145           //current.isconst=0; // DEBUG
9146           ooo[i]=1;
9147           ds=1;
9148           break;
9149         case CJUMP:
9150           //current.isconst=0;
9151           //current.wasconst=0;
9152           //regs[i].wasconst=0;
9153           clear_const(&current,rs1[i]);
9154           clear_const(&current,rs2[i]);
9155           if((opcode[i]&0x3E)==4) // BEQ/BNE
9156           {
9157             alloc_cc(&current,i);
9158             dirty_reg(&current,CCREG);
9159             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9160             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9161             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9162             {
9163               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9164               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9165             }
9166             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9167                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9168               // The delay slot overwrites one of our conditions.
9169               // Allocate the branch condition registers instead.
9170               current.isconst=0;
9171               current.wasconst=0;
9172               regs[i].wasconst=0;
9173               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9174               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9175               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9176               {
9177                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9178                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9179               }
9180             }
9181             else
9182             {
9183               ooo[i]=1;
9184               delayslot_alloc(&current,i+1);
9185             }
9186           }
9187           else
9188           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9189           {
9190             alloc_cc(&current,i);
9191             dirty_reg(&current,CCREG);
9192             alloc_reg(&current,i,rs1[i]);
9193             if(!(current.is32>>rs1[i]&1))
9194             {
9195               alloc_reg64(&current,i,rs1[i]);
9196             }
9197             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9198               // The delay slot overwrites one of our conditions.
9199               // Allocate the branch condition registers instead.
9200               current.isconst=0;
9201               current.wasconst=0;
9202               regs[i].wasconst=0;
9203               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9204               if(!((current.is32>>rs1[i])&1))
9205               {
9206                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9207               }
9208             }
9209             else
9210             {
9211               ooo[i]=1;
9212               delayslot_alloc(&current,i+1);
9213             }
9214           }
9215           else
9216           // Don't alloc the delay slot yet because we might not execute it
9217           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9218           {
9219             current.isconst=0;
9220             current.wasconst=0;
9221             regs[i].wasconst=0;
9222             alloc_cc(&current,i);
9223             dirty_reg(&current,CCREG);
9224             alloc_reg(&current,i,rs1[i]);
9225             alloc_reg(&current,i,rs2[i]);
9226             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9227             {
9228               alloc_reg64(&current,i,rs1[i]);
9229               alloc_reg64(&current,i,rs2[i]);
9230             }
9231           }
9232           else
9233           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9234           {
9235             current.isconst=0;
9236             current.wasconst=0;
9237             regs[i].wasconst=0;
9238             alloc_cc(&current,i);
9239             dirty_reg(&current,CCREG);
9240             alloc_reg(&current,i,rs1[i]);
9241             if(!(current.is32>>rs1[i]&1))
9242             {
9243               alloc_reg64(&current,i,rs1[i]);
9244             }
9245           }
9246           ds=1;
9247           //current.isconst=0;
9248           break;
9249         case SJUMP:
9250           //current.isconst=0;
9251           //current.wasconst=0;
9252           //regs[i].wasconst=0;
9253           clear_const(&current,rs1[i]);
9254           clear_const(&current,rt1[i]);
9255           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9256           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9257           {
9258             alloc_cc(&current,i);
9259             dirty_reg(&current,CCREG);
9260             alloc_reg(&current,i,rs1[i]);
9261             if(!(current.is32>>rs1[i]&1))
9262             {
9263               alloc_reg64(&current,i,rs1[i]);
9264             }
9265             if (rt1[i]==31) { // BLTZAL/BGEZAL
9266               alloc_reg(&current,i,31);
9267               dirty_reg(&current,31);
9268               //#ifdef REG_PREFETCH
9269               //alloc_reg(&current,i,PTEMP);
9270               //#endif
9271               //current.is32|=1LL<<rt1[i];
9272             }
9273             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9274                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9275               // Allocate the branch condition registers instead.
9276               current.isconst=0;
9277               current.wasconst=0;
9278               regs[i].wasconst=0;
9279               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9280               if(!((current.is32>>rs1[i])&1))
9281               {
9282                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9283               }
9284             }
9285             else
9286             {
9287               ooo[i]=1;
9288               delayslot_alloc(&current,i+1);
9289             }
9290           }
9291           else
9292           // Don't alloc the delay slot yet because we might not execute it
9293           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9294           {
9295             current.isconst=0;
9296             current.wasconst=0;
9297             regs[i].wasconst=0;
9298             alloc_cc(&current,i);
9299             dirty_reg(&current,CCREG);
9300             alloc_reg(&current,i,rs1[i]);
9301             if(!(current.is32>>rs1[i]&1))
9302             {
9303               alloc_reg64(&current,i,rs1[i]);
9304             }
9305           }
9306           ds=1;
9307           //current.isconst=0;
9308           break;
9309         case FJUMP:
9310           current.isconst=0;
9311           current.wasconst=0;
9312           regs[i].wasconst=0;
9313           if(likely[i]==0) // BC1F/BC1T
9314           {
9315             // TODO: Theoretically we can run out of registers here on x86.
9316             // The delay slot can allocate up to six, and we need to check
9317             // CSREG before executing the delay slot.  Possibly we can drop
9318             // the cycle count and then reload it after checking that the
9319             // FPU is in a usable state, or don't do out-of-order execution.
9320             alloc_cc(&current,i);
9321             dirty_reg(&current,CCREG);
9322             alloc_reg(&current,i,FSREG);
9323             alloc_reg(&current,i,CSREG);
9324             if(itype[i+1]==FCOMP) {
9325               // The delay slot overwrites the branch condition.
9326               // Allocate the branch condition registers instead.
9327               alloc_cc(&current,i);
9328               dirty_reg(&current,CCREG);
9329               alloc_reg(&current,i,CSREG);
9330               alloc_reg(&current,i,FSREG);
9331             }
9332             else {
9333               ooo[i]=1;
9334               delayslot_alloc(&current,i+1);
9335               alloc_reg(&current,i+1,CSREG);
9336             }
9337           }
9338           else
9339           // Don't alloc the delay slot yet because we might not execute it
9340           if(likely[i]) // BC1FL/BC1TL
9341           {
9342             alloc_cc(&current,i);
9343             dirty_reg(&current,CCREG);
9344             alloc_reg(&current,i,CSREG);
9345             alloc_reg(&current,i,FSREG);
9346           }
9347           ds=1;
9348           current.isconst=0;
9349           break;
9350         case IMM16:
9351           imm16_alloc(&current,i);
9352           break;
9353         case LOAD:
9354         case LOADLR:
9355           load_alloc(&current,i);
9356           break;
9357         case STORE:
9358         case STORELR:
9359           store_alloc(&current,i);
9360           break;
9361         case ALU:
9362           alu_alloc(&current,i);
9363           break;
9364         case SHIFT:
9365           shift_alloc(&current,i);
9366           break;
9367         case MULTDIV:
9368           multdiv_alloc(&current,i);
9369           break;
9370         case SHIFTIMM:
9371           shiftimm_alloc(&current,i);
9372           break;
9373         case MOV:
9374           mov_alloc(&current,i);
9375           break;
9376         case COP0:
9377           cop0_alloc(&current,i);
9378           break;
9379         case COP1:
9380         case COP2:
9381           cop1_alloc(&current,i);
9382           break;
9383         case C1LS:
9384           c1ls_alloc(&current,i);
9385           break;
9386         case C2LS:
9387           c2ls_alloc(&current,i);
9388           break;
9389         case C2OP:
9390           c2op_alloc(&current,i);
9391           break;
9392         case FCONV:
9393           fconv_alloc(&current,i);
9394           break;
9395         case FLOAT:
9396           float_alloc(&current,i);
9397           break;
9398         case FCOMP:
9399           fcomp_alloc(&current,i);
9400           break;
9401         case SYSCALL:
9402         case HLECALL:
9403         case INTCALL:
9404           syscall_alloc(&current,i);
9405           break;
9406         case SPAN:
9407           pagespan_alloc(&current,i);
9408           break;
9409       }
9410
9411       // Drop the upper half of registers that have become 32-bit
9412       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9413       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9414         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9415         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9416         current.uu|=1;
9417       } else {
9418         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9419         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9420         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9421         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9422         current.uu|=1;
9423       }
9424
9425       // Create entry (branch target) regmap
9426       for(hr=0;hr<HOST_REGS;hr++)
9427       {
9428         int r,or,er;
9429         r=current.regmap[hr];
9430         if(r>=0) {
9431           if(r!=regmap_pre[i][hr]) {
9432             // TODO: delay slot (?)
9433             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9434             if(or<0||(r&63)>=TEMPREG){
9435               regs[i].regmap_entry[hr]=-1;
9436             }
9437             else
9438             {
9439               // Just move it to a different register
9440               regs[i].regmap_entry[hr]=r;
9441               // If it was dirty before, it's still dirty
9442               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9443             }
9444           }
9445           else
9446           {
9447             // Unneeded
9448             if(r==0){
9449               regs[i].regmap_entry[hr]=0;
9450             }
9451             else
9452             if(r<64){
9453               if((current.u>>r)&1) {
9454                 regs[i].regmap_entry[hr]=-1;
9455                 //regs[i].regmap[hr]=-1;
9456                 current.regmap[hr]=-1;
9457               }else
9458                 regs[i].regmap_entry[hr]=r;
9459             }
9460             else {
9461               if((current.uu>>(r&63))&1) {
9462                 regs[i].regmap_entry[hr]=-1;
9463                 //regs[i].regmap[hr]=-1;
9464                 current.regmap[hr]=-1;
9465               }else
9466                 regs[i].regmap_entry[hr]=r;
9467             }
9468           }
9469         } else {
9470           // Branches expect CCREG to be allocated at the target
9471           if(regmap_pre[i][hr]==CCREG)
9472             regs[i].regmap_entry[hr]=CCREG;
9473           else
9474             regs[i].regmap_entry[hr]=-1;
9475         }
9476       }
9477       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9478     }
9479
9480     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9481       current.waswritten|=1<<rs1[i-1];
9482     current.waswritten&=~(1<<rt1[i]);
9483     current.waswritten&=~(1<<rt2[i]);
9484     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9485       current.waswritten&=~(1<<rs1[i]);
9486
9487     /* Branch post-alloc */
9488     if(i>0)
9489     {
9490       current.was32=current.is32;
9491       current.wasdirty=current.dirty;
9492       switch(itype[i-1]) {
9493         case UJUMP:
9494           memcpy(&branch_regs[i-1],&current,sizeof(current));
9495           branch_regs[i-1].isconst=0;
9496           branch_regs[i-1].wasconst=0;
9497           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9498           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9499           alloc_cc(&branch_regs[i-1],i-1);
9500           dirty_reg(&branch_regs[i-1],CCREG);
9501           if(rt1[i-1]==31) { // JAL
9502             alloc_reg(&branch_regs[i-1],i-1,31);
9503             dirty_reg(&branch_regs[i-1],31);
9504             branch_regs[i-1].is32|=1LL<<31;
9505           }
9506           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9507           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9508           break;
9509         case RJUMP:
9510           memcpy(&branch_regs[i-1],&current,sizeof(current));
9511           branch_regs[i-1].isconst=0;
9512           branch_regs[i-1].wasconst=0;
9513           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9514           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9515           alloc_cc(&branch_regs[i-1],i-1);
9516           dirty_reg(&branch_regs[i-1],CCREG);
9517           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9518           if(rt1[i-1]!=0) { // JALR
9519             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9520             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9521             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9522           }
9523           #ifdef USE_MINI_HT
9524           if(rs1[i-1]==31) { // JALR
9525             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9526             #ifndef HOST_IMM_ADDR32
9527             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9528             #endif
9529           }
9530           #endif
9531           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9532           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9533           break;
9534         case CJUMP:
9535           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9536           {
9537             alloc_cc(&current,i-1);
9538             dirty_reg(&current,CCREG);
9539             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9540                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9541               // The delay slot overwrote one of our conditions
9542               // Delay slot goes after the test (in order)
9543               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9544               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9545               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9546               current.u|=1;
9547               current.uu|=1;
9548               delayslot_alloc(&current,i);
9549               current.isconst=0;
9550             }
9551             else
9552             {
9553               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9554               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9555               // Alloc the branch condition registers
9556               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9557               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9558               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9559               {
9560                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9561                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9562               }
9563             }
9564             memcpy(&branch_regs[i-1],&current,sizeof(current));
9565             branch_regs[i-1].isconst=0;
9566             branch_regs[i-1].wasconst=0;
9567             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9568             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9569           }
9570           else
9571           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9572           {
9573             alloc_cc(&current,i-1);
9574             dirty_reg(&current,CCREG);
9575             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9576               // The delay slot overwrote the branch condition
9577               // Delay slot goes after the test (in order)
9578               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9579               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9580               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9581               current.u|=1;
9582               current.uu|=1;
9583               delayslot_alloc(&current,i);
9584               current.isconst=0;
9585             }
9586             else
9587             {
9588               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9589               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9590               // Alloc the branch condition register
9591               alloc_reg(&current,i-1,rs1[i-1]);
9592               if(!(current.is32>>rs1[i-1]&1))
9593               {
9594                 alloc_reg64(&current,i-1,rs1[i-1]);
9595               }
9596             }
9597             memcpy(&branch_regs[i-1],&current,sizeof(current));
9598             branch_regs[i-1].isconst=0;
9599             branch_regs[i-1].wasconst=0;
9600             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9601             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9602           }
9603           else
9604           // Alloc the delay slot in case the branch is taken
9605           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9606           {
9607             memcpy(&branch_regs[i-1],&current,sizeof(current));
9608             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9609             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9610             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9611             alloc_cc(&branch_regs[i-1],i);
9612             dirty_reg(&branch_regs[i-1],CCREG);
9613             delayslot_alloc(&branch_regs[i-1],i);
9614             branch_regs[i-1].isconst=0;
9615             alloc_reg(&current,i,CCREG); // Not taken path
9616             dirty_reg(&current,CCREG);
9617             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9618           }
9619           else
9620           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9621           {
9622             memcpy(&branch_regs[i-1],&current,sizeof(current));
9623             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9624             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9625             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9626             alloc_cc(&branch_regs[i-1],i);
9627             dirty_reg(&branch_regs[i-1],CCREG);
9628             delayslot_alloc(&branch_regs[i-1],i);
9629             branch_regs[i-1].isconst=0;
9630             alloc_reg(&current,i,CCREG); // Not taken path
9631             dirty_reg(&current,CCREG);
9632             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9633           }
9634           break;
9635         case SJUMP:
9636           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9637           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9638           {
9639             alloc_cc(&current,i-1);
9640             dirty_reg(&current,CCREG);
9641             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9642               // The delay slot overwrote the branch condition
9643               // Delay slot goes after the test (in order)
9644               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9645               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9646               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9647               current.u|=1;
9648               current.uu|=1;
9649               delayslot_alloc(&current,i);
9650               current.isconst=0;
9651             }
9652             else
9653             {
9654               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9655               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9656               // Alloc the branch condition register
9657               alloc_reg(&current,i-1,rs1[i-1]);
9658               if(!(current.is32>>rs1[i-1]&1))
9659               {
9660                 alloc_reg64(&current,i-1,rs1[i-1]);
9661               }
9662             }
9663             memcpy(&branch_regs[i-1],&current,sizeof(current));
9664             branch_regs[i-1].isconst=0;
9665             branch_regs[i-1].wasconst=0;
9666             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9667             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9668           }
9669           else
9670           // Alloc the delay slot in case the branch is taken
9671           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9672           {
9673             memcpy(&branch_regs[i-1],&current,sizeof(current));
9674             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9675             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9676             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9677             alloc_cc(&branch_regs[i-1],i);
9678             dirty_reg(&branch_regs[i-1],CCREG);
9679             delayslot_alloc(&branch_regs[i-1],i);
9680             branch_regs[i-1].isconst=0;
9681             alloc_reg(&current,i,CCREG); // Not taken path
9682             dirty_reg(&current,CCREG);
9683             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9684           }
9685           // FIXME: BLTZAL/BGEZAL
9686           if(opcode2[i-1]&0x10) { // BxxZAL
9687             alloc_reg(&branch_regs[i-1],i-1,31);
9688             dirty_reg(&branch_regs[i-1],31);
9689             branch_regs[i-1].is32|=1LL<<31;
9690           }
9691           break;
9692         case FJUMP:
9693           if(likely[i-1]==0) // BC1F/BC1T
9694           {
9695             alloc_cc(&current,i-1);
9696             dirty_reg(&current,CCREG);
9697             if(itype[i]==FCOMP) {
9698               // The delay slot overwrote the branch condition
9699               // Delay slot goes after the test (in order)
9700               delayslot_alloc(&current,i);
9701               current.isconst=0;
9702             }
9703             else
9704             {
9705               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9706               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9707               // Alloc the branch condition register
9708               alloc_reg(&current,i-1,FSREG);
9709             }
9710             memcpy(&branch_regs[i-1],&current,sizeof(current));
9711             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9712           }
9713           else // BC1FL/BC1TL
9714           {
9715             // Alloc the delay slot in case the branch is taken
9716             memcpy(&branch_regs[i-1],&current,sizeof(current));
9717             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9718             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9719             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9720             alloc_cc(&branch_regs[i-1],i);
9721             dirty_reg(&branch_regs[i-1],CCREG);
9722             delayslot_alloc(&branch_regs[i-1],i);
9723             branch_regs[i-1].isconst=0;
9724             alloc_reg(&current,i,CCREG); // Not taken path
9725             dirty_reg(&current,CCREG);
9726             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9727           }
9728           break;
9729       }
9730
9731       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9732       {
9733         if(rt1[i-1]==31) // JAL/JALR
9734         {
9735           // Subroutine call will return here, don't alloc any registers
9736           current.is32=1;
9737           current.dirty=0;
9738           clear_all_regs(current.regmap);
9739           alloc_reg(&current,i,CCREG);
9740           dirty_reg(&current,CCREG);
9741         }
9742         else if(i+1<slen)
9743         {
9744           // Internal branch will jump here, match registers to caller
9745           current.is32=0x3FFFFFFFFLL;
9746           current.dirty=0;
9747           clear_all_regs(current.regmap);
9748           alloc_reg(&current,i,CCREG);
9749           dirty_reg(&current,CCREG);
9750           for(j=i-1;j>=0;j--)
9751           {
9752             if(ba[j]==start+i*4+4) {
9753               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9754               current.is32=branch_regs[j].is32;
9755               current.dirty=branch_regs[j].dirty;
9756               break;
9757             }
9758           }
9759           while(j>=0) {
9760             if(ba[j]==start+i*4+4) {
9761               for(hr=0;hr<HOST_REGS;hr++) {
9762                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9763                   current.regmap[hr]=-1;
9764                 }
9765                 current.is32&=branch_regs[j].is32;
9766                 current.dirty&=branch_regs[j].dirty;
9767               }
9768             }
9769             j--;
9770           }
9771         }
9772       }
9773     }
9774
9775     // Count cycles in between branches
9776     ccadj[i]=cc;
9777     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9778     {
9779       cc=0;
9780     }
9781 #ifdef PCSX
9782     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9783     {
9784       // GTE runs in parallel until accessed, divide by 2 for a rough guess
9785       cc+=gte_cycletab[source[i]&0x3f]/2;
9786     }
9787     else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9788     {
9789       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9790     }
9791     else if(itype[i]==C2LS)
9792     {
9793       cc+=4;
9794     }
9795 #endif
9796     else
9797     {
9798       cc++;
9799     }
9800
9801     flush_dirty_uppers(&current);
9802     if(!is_ds[i]) {
9803       regs[i].is32=current.is32;
9804       regs[i].dirty=current.dirty;
9805       regs[i].isconst=current.isconst;
9806       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9807     }
9808     for(hr=0;hr<HOST_REGS;hr++) {
9809       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9810         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9811           regs[i].wasconst&=~(1<<hr);
9812         }
9813       }
9814     }
9815     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9816     regs[i].waswritten=current.waswritten;
9817   }
9818
9819   /* Pass 4 - Cull unused host registers */
9820
9821   uint64_t nr=0;
9822
9823   for (i=slen-1;i>=0;i--)
9824   {
9825     int hr;
9826     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9827     {
9828       if(ba[i]<start || ba[i]>=(start+slen*4))
9829       {
9830         // Branch out of this block, don't need anything
9831         nr=0;
9832       }
9833       else
9834       {
9835         // Internal branch
9836         // Need whatever matches the target
9837         nr=0;
9838         int t=(ba[i]-start)>>2;
9839         for(hr=0;hr<HOST_REGS;hr++)
9840         {
9841           if(regs[i].regmap_entry[hr]>=0) {
9842             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9843           }
9844         }
9845       }
9846       // Conditional branch may need registers for following instructions
9847       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9848       {
9849         if(i<slen-2) {
9850           nr|=needed_reg[i+2];
9851           for(hr=0;hr<HOST_REGS;hr++)
9852           {
9853             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9854             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9855           }
9856         }
9857       }
9858       // Don't need stuff which is overwritten
9859       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9860       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9861       // Merge in delay slot
9862       for(hr=0;hr<HOST_REGS;hr++)
9863       {
9864         if(!likely[i]) {
9865           // These are overwritten unless the branch is "likely"
9866           // and the delay slot is nullified if not taken
9867           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9868           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9869         }
9870         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9871         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9872         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9873         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9874         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9875         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9876         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9877         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9878         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9879           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9880           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9881         }
9882         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9883           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9884           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9885         }
9886         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9887           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9888           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9889         }
9890       }
9891     }
9892     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9893     {
9894       // SYSCALL instruction (software interrupt)
9895       nr=0;
9896     }
9897     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9898     {
9899       // ERET instruction (return from interrupt)
9900       nr=0;
9901     }
9902     else // Non-branch
9903     {
9904       if(i<slen-1) {
9905         for(hr=0;hr<HOST_REGS;hr++) {
9906           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9907           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9908           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9909           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9910         }
9911       }
9912     }
9913     for(hr=0;hr<HOST_REGS;hr++)
9914     {
9915       // Overwritten registers are not needed
9916       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9917       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9918       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9919       // Source registers are needed
9920       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9921       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9922       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9923       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9924       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9925       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9926       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9927       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9928       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9929         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9930         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9931       }
9932       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9933         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9934         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9935       }
9936       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9937         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9938         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9939       }
9940       // Don't store a register immediately after writing it,
9941       // may prevent dual-issue.
9942       // But do so if this is a branch target, otherwise we
9943       // might have to load the register before the branch.
9944       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9945         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9946            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9947           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9948           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9949         }
9950         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9951            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9952           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9953           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9954         }
9955       }
9956     }
9957     // Cycle count is needed at branches.  Assume it is needed at the target too.
9958     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9959       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9960       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9961     }
9962     // Save it
9963     needed_reg[i]=nr;
9964
9965     // Deallocate unneeded registers
9966     for(hr=0;hr<HOST_REGS;hr++)
9967     {
9968       if(!((nr>>hr)&1)) {
9969         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9970         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9971            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9972            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9973         {
9974           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9975           {
9976             if(likely[i]) {
9977               regs[i].regmap[hr]=-1;
9978               regs[i].isconst&=~(1<<hr);
9979               if(i<slen-2) {
9980                 regmap_pre[i+2][hr]=-1;
9981                 regs[i+2].wasconst&=~(1<<hr);
9982               }
9983             }
9984           }
9985         }
9986         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9987         {
9988           int d1=0,d2=0,map=0,temp=0;
9989           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9990           {
9991             d1=dep1[i+1];
9992             d2=dep2[i+1];
9993           }
9994           if(using_tlb) {
9995             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9996                itype[i+1]==STORE || itype[i+1]==STORELR ||
9997                itype[i+1]==C1LS || itype[i+1]==C2LS)
9998             map=TLREG;
9999           } else
10000           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10001              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10002             map=INVCP;
10003           }
10004           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10005              itype[i+1]==C1LS || itype[i+1]==C2LS)
10006             temp=FTEMP;
10007           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10008              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10009              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10010              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10011              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10012              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10013              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10014              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10015              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10016              regs[i].regmap[hr]!=map )
10017           {
10018             regs[i].regmap[hr]=-1;
10019             regs[i].isconst&=~(1<<hr);
10020             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10021                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10022                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10023                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10024                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10025                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10026                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10027                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10028                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10029                branch_regs[i].regmap[hr]!=map)
10030             {
10031               branch_regs[i].regmap[hr]=-1;
10032               branch_regs[i].regmap_entry[hr]=-1;
10033               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10034               {
10035                 if(!likely[i]&&i<slen-2) {
10036                   regmap_pre[i+2][hr]=-1;
10037                   regs[i+2].wasconst&=~(1<<hr);
10038                 }
10039               }
10040             }
10041           }
10042         }
10043         else
10044         {
10045           // Non-branch
10046           if(i>0)
10047           {
10048             int d1=0,d2=0,map=-1,temp=-1;
10049             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10050             {
10051               d1=dep1[i];
10052               d2=dep2[i];
10053             }
10054             if(using_tlb) {
10055               if(itype[i]==LOAD || itype[i]==LOADLR ||
10056                  itype[i]==STORE || itype[i]==STORELR ||
10057                  itype[i]==C1LS || itype[i]==C2LS)
10058               map=TLREG;
10059             } else if(itype[i]==STORE || itype[i]==STORELR ||
10060                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10061               map=INVCP;
10062             }
10063             if(itype[i]==LOADLR || itype[i]==STORELR ||
10064                itype[i]==C1LS || itype[i]==C2LS)
10065               temp=FTEMP;
10066             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10067                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10068                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10069                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10070                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10071                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10072             {
10073               if(i<slen-1&&!is_ds[i]) {
10074                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10075                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10076                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10077                 {
10078                   printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10079                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10080                 }
10081                 regmap_pre[i+1][hr]=-1;
10082                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10083                 regs[i+1].wasconst&=~(1<<hr);
10084               }
10085               regs[i].regmap[hr]=-1;
10086               regs[i].isconst&=~(1<<hr);
10087             }
10088           }
10089         }
10090       }
10091     }
10092   }
10093
10094   /* Pass 5 - Pre-allocate registers */
10095
10096   // If a register is allocated during a loop, try to allocate it for the
10097   // entire loop, if possible.  This avoids loading/storing registers
10098   // inside of the loop.
10099
10100   signed char f_regmap[HOST_REGS];
10101   clear_all_regs(f_regmap);
10102   for(i=0;i<slen-1;i++)
10103   {
10104     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10105     {
10106       if(ba[i]>=start && ba[i]<(start+i*4))
10107       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10108       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10109       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10110       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10111       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10112       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10113       {
10114         int t=(ba[i]-start)>>2;
10115         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10116         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10117         for(hr=0;hr<HOST_REGS;hr++)
10118         {
10119           if(regs[i].regmap[hr]>64) {
10120             if(!((regs[i].dirty>>hr)&1))
10121               f_regmap[hr]=regs[i].regmap[hr];
10122             else f_regmap[hr]=-1;
10123           }
10124           else if(regs[i].regmap[hr]>=0) {
10125             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10126               // dealloc old register
10127               int n;
10128               for(n=0;n<HOST_REGS;n++)
10129               {
10130                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10131               }
10132               // and alloc new one
10133               f_regmap[hr]=regs[i].regmap[hr];
10134             }
10135           }
10136           if(branch_regs[i].regmap[hr]>64) {
10137             if(!((branch_regs[i].dirty>>hr)&1))
10138               f_regmap[hr]=branch_regs[i].regmap[hr];
10139             else f_regmap[hr]=-1;
10140           }
10141           else if(branch_regs[i].regmap[hr]>=0) {
10142             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10143               // dealloc old register
10144               int n;
10145               for(n=0;n<HOST_REGS;n++)
10146               {
10147                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10148               }
10149               // and alloc new one
10150               f_regmap[hr]=branch_regs[i].regmap[hr];
10151             }
10152           }
10153           if(ooo[i]) {
10154             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10155               f_regmap[hr]=branch_regs[i].regmap[hr];
10156           }else{
10157             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10158               f_regmap[hr]=branch_regs[i].regmap[hr];
10159           }
10160           // Avoid dirty->clean transition
10161           #ifdef DESTRUCTIVE_WRITEBACK
10162           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10163           #endif
10164           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10165           // case above, however it's always a good idea.  We can't hoist the
10166           // load if the register was already allocated, so there's no point
10167           // wasting time analyzing most of these cases.  It only "succeeds"
10168           // when the mapping was different and the load can be replaced with
10169           // a mov, which is of negligible benefit.  So such cases are
10170           // skipped below.
10171           if(f_regmap[hr]>0) {
10172             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10173               int r=f_regmap[hr];
10174               for(j=t;j<=i;j++)
10175               {
10176                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10177                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10178                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10179                 if(r>63) {
10180                   // NB This can exclude the case where the upper-half
10181                   // register is lower numbered than the lower-half
10182                   // register.  Not sure if it's worth fixing...
10183                   if(get_reg(regs[j].regmap,r&63)<0) break;
10184                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10185                   if(regs[j].is32&(1LL<<(r&63))) break;
10186                 }
10187                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10188                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10189                   int k;
10190                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10191                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10192                     if(r>63) {
10193                       if(get_reg(regs[i].regmap,r&63)<0) break;
10194                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10195                     }
10196                     k=i;
10197                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10198                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10199                         //printf("no free regs for store %x\n",start+(k-1)*4);
10200                         break;
10201                       }
10202                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10203                         //printf("no-match due to different register\n");
10204                         break;
10205                       }
10206                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10207                         //printf("no-match due to branch\n");
10208                         break;
10209                       }
10210                       // call/ret fast path assumes no registers allocated
10211                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10212                         break;
10213                       }
10214                       if(r>63) {
10215                         // NB This can exclude the case where the upper-half
10216                         // register is lower numbered than the lower-half
10217                         // register.  Not sure if it's worth fixing...
10218                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10219                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10220                       }
10221                       k--;
10222                     }
10223                     if(i<slen-1) {
10224                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10225                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10226                         //printf("bad match after branch\n");
10227                         break;
10228                       }
10229                     }
10230                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10231                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10232                       while(k<i) {
10233                         regs[k].regmap_entry[hr]=f_regmap[hr];
10234                         regs[k].regmap[hr]=f_regmap[hr];
10235                         regmap_pre[k+1][hr]=f_regmap[hr];
10236                         regs[k].wasdirty&=~(1<<hr);
10237                         regs[k].dirty&=~(1<<hr);
10238                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10239                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10240                         regs[k].wasconst&=~(1<<hr);
10241                         regs[k].isconst&=~(1<<hr);
10242                         k++;
10243                       }
10244                     }
10245                     else {
10246                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10247                       break;
10248                     }
10249                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10250                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10251                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10252                       regs[i].regmap_entry[hr]=f_regmap[hr];
10253                       regs[i].regmap[hr]=f_regmap[hr];
10254                       regs[i].wasdirty&=~(1<<hr);
10255                       regs[i].dirty&=~(1<<hr);
10256                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10257                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10258                       regs[i].wasconst&=~(1<<hr);
10259                       regs[i].isconst&=~(1<<hr);
10260                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10261                       branch_regs[i].wasdirty&=~(1<<hr);
10262                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10263                       branch_regs[i].regmap[hr]=f_regmap[hr];
10264                       branch_regs[i].dirty&=~(1<<hr);
10265                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10266                       branch_regs[i].wasconst&=~(1<<hr);
10267                       branch_regs[i].isconst&=~(1<<hr);
10268                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10269                         regmap_pre[i+2][hr]=f_regmap[hr];
10270                         regs[i+2].wasdirty&=~(1<<hr);
10271                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10272                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10273                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10274                       }
10275                     }
10276                   }
10277                   for(k=t;k<j;k++) {
10278                     // Alloc register clean at beginning of loop,
10279                     // but may dirty it in pass 6
10280                     regs[k].regmap_entry[hr]=f_regmap[hr];
10281                     regs[k].regmap[hr]=f_regmap[hr];
10282                     regs[k].dirty&=~(1<<hr);
10283                     regs[k].wasconst&=~(1<<hr);
10284                     regs[k].isconst&=~(1<<hr);
10285                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10286                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10287                       branch_regs[k].regmap[hr]=f_regmap[hr];
10288                       branch_regs[k].dirty&=~(1<<hr);
10289                       branch_regs[k].wasconst&=~(1<<hr);
10290                       branch_regs[k].isconst&=~(1<<hr);
10291                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10292                         regmap_pre[k+2][hr]=f_regmap[hr];
10293                         regs[k+2].wasdirty&=~(1<<hr);
10294                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10295                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10296                       }
10297                     }
10298                     else
10299                     {
10300                       regmap_pre[k+1][hr]=f_regmap[hr];
10301                       regs[k+1].wasdirty&=~(1<<hr);
10302                     }
10303                   }
10304                   if(regs[j].regmap[hr]==f_regmap[hr])
10305                     regs[j].regmap_entry[hr]=f_regmap[hr];
10306                   break;
10307                 }
10308                 if(j==i) break;
10309                 if(regs[j].regmap[hr]>=0)
10310                   break;
10311                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10312                   //printf("no-match due to different register\n");
10313                   break;
10314                 }
10315                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10316                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10317                   break;
10318                 }
10319                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10320                 {
10321                   // Stop on unconditional branch
10322                   break;
10323                 }
10324                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10325                 {
10326                   if(ooo[j]) {
10327                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10328                       break;
10329                   }else{
10330                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10331                       break;
10332                   }
10333                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10334                     //printf("no-match due to different register (branch)\n");
10335                     break;
10336                   }
10337                 }
10338                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10339                   //printf("No free regs for store %x\n",start+j*4);
10340                   break;
10341                 }
10342                 if(f_regmap[hr]>=64) {
10343                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10344                     break;
10345                   }
10346                   else
10347                   {
10348                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10349                       break;
10350                     }
10351                   }
10352                 }
10353               }
10354             }
10355           }
10356         }
10357       }
10358     }else{
10359       // Non branch or undetermined branch target
10360       for(hr=0;hr<HOST_REGS;hr++)
10361       {
10362         if(hr!=EXCLUDE_REG) {
10363           if(regs[i].regmap[hr]>64) {
10364             if(!((regs[i].dirty>>hr)&1))
10365               f_regmap[hr]=regs[i].regmap[hr];
10366           }
10367           else if(regs[i].regmap[hr]>=0) {
10368             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10369               // dealloc old register
10370               int n;
10371               for(n=0;n<HOST_REGS;n++)
10372               {
10373                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10374               }
10375               // and alloc new one
10376               f_regmap[hr]=regs[i].regmap[hr];
10377             }
10378           }
10379         }
10380       }
10381       // Try to restore cycle count at branch targets
10382       if(bt[i]) {
10383         for(j=i;j<slen-1;j++) {
10384           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10385           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10386             //printf("no free regs for store %x\n",start+j*4);
10387             break;
10388           }
10389         }
10390         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10391           int k=i;
10392           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10393           while(k<j) {
10394             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10395             regs[k].regmap[HOST_CCREG]=CCREG;
10396             regmap_pre[k+1][HOST_CCREG]=CCREG;
10397             regs[k+1].wasdirty|=1<<HOST_CCREG;
10398             regs[k].dirty|=1<<HOST_CCREG;
10399             regs[k].wasconst&=~(1<<HOST_CCREG);
10400             regs[k].isconst&=~(1<<HOST_CCREG);
10401             k++;
10402           }
10403           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10404         }
10405         // Work backwards from the branch target
10406         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10407         {
10408           //printf("Extend backwards\n");
10409           int k;
10410           k=i;
10411           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10412             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10413               //printf("no free regs for store %x\n",start+(k-1)*4);
10414               break;
10415             }
10416             k--;
10417           }
10418           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10419             //printf("Extend CC, %x ->\n",start+k*4);
10420             while(k<=i) {
10421               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10422               regs[k].regmap[HOST_CCREG]=CCREG;
10423               regmap_pre[k+1][HOST_CCREG]=CCREG;
10424               regs[k+1].wasdirty|=1<<HOST_CCREG;
10425               regs[k].dirty|=1<<HOST_CCREG;
10426               regs[k].wasconst&=~(1<<HOST_CCREG);
10427               regs[k].isconst&=~(1<<HOST_CCREG);
10428               k++;
10429             }
10430           }
10431           else {
10432             //printf("Fail Extend CC, %x ->\n",start+k*4);
10433           }
10434         }
10435       }
10436       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10437          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10438          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10439          itype[i]!=FCONV&&itype[i]!=FCOMP)
10440       {
10441         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10442       }
10443     }
10444   }
10445
10446   // Cache memory offset or tlb map pointer if a register is available
10447   #ifndef HOST_IMM_ADDR32
10448   #ifndef RAM_OFFSET
10449   if(using_tlb)
10450   #endif
10451   {
10452     int earliest_available[HOST_REGS];
10453     int loop_start[HOST_REGS];
10454     int score[HOST_REGS];
10455     int end[HOST_REGS];
10456     int reg=using_tlb?MMREG:ROREG;
10457
10458     // Init
10459     for(hr=0;hr<HOST_REGS;hr++) {
10460       score[hr]=0;earliest_available[hr]=0;
10461       loop_start[hr]=MAXBLOCK;
10462     }
10463     for(i=0;i<slen-1;i++)
10464     {
10465       // Can't do anything if no registers are available
10466       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10467         for(hr=0;hr<HOST_REGS;hr++) {
10468           score[hr]=0;earliest_available[hr]=i+1;
10469           loop_start[hr]=MAXBLOCK;
10470         }
10471       }
10472       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10473         if(!ooo[i]) {
10474           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10475             for(hr=0;hr<HOST_REGS;hr++) {
10476               score[hr]=0;earliest_available[hr]=i+1;
10477               loop_start[hr]=MAXBLOCK;
10478             }
10479           }
10480         }else{
10481           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10482             for(hr=0;hr<HOST_REGS;hr++) {
10483               score[hr]=0;earliest_available[hr]=i+1;
10484               loop_start[hr]=MAXBLOCK;
10485             }
10486           }
10487         }
10488       }
10489       // Mark unavailable registers
10490       for(hr=0;hr<HOST_REGS;hr++) {
10491         if(regs[i].regmap[hr]>=0) {
10492           score[hr]=0;earliest_available[hr]=i+1;
10493           loop_start[hr]=MAXBLOCK;
10494         }
10495         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10496           if(branch_regs[i].regmap[hr]>=0) {
10497             score[hr]=0;earliest_available[hr]=i+2;
10498             loop_start[hr]=MAXBLOCK;
10499           }
10500         }
10501       }
10502       // No register allocations after unconditional jumps
10503       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10504       {
10505         for(hr=0;hr<HOST_REGS;hr++) {
10506           score[hr]=0;earliest_available[hr]=i+2;
10507           loop_start[hr]=MAXBLOCK;
10508         }
10509         i++; // Skip delay slot too
10510         //printf("skip delay slot: %x\n",start+i*4);
10511       }
10512       else
10513       // Possible match
10514       if(itype[i]==LOAD||itype[i]==LOADLR||
10515          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10516         for(hr=0;hr<HOST_REGS;hr++) {
10517           if(hr!=EXCLUDE_REG) {
10518             end[hr]=i-1;
10519             for(j=i;j<slen-1;j++) {
10520               if(regs[j].regmap[hr]>=0) break;
10521               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10522                 if(branch_regs[j].regmap[hr]>=0) break;
10523                 if(ooo[j]) {
10524                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10525                 }else{
10526                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10527                 }
10528               }
10529               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10530               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10531                 int t=(ba[j]-start)>>2;
10532                 if(t<j&&t>=earliest_available[hr]) {
10533                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10534                     // Score a point for hoisting loop invariant
10535                     if(t<loop_start[hr]) loop_start[hr]=t;
10536                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10537                     score[hr]++;
10538                     end[hr]=j;
10539                   }
10540                 }
10541                 else if(t<j) {
10542                   if(regs[t].regmap[hr]==reg) {
10543                     // Score a point if the branch target matches this register
10544                     score[hr]++;
10545                     end[hr]=j;
10546                   }
10547                 }
10548                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10549                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10550                   score[hr]++;
10551                   end[hr]=j;
10552                 }
10553               }
10554               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10555               {
10556                 // Stop on unconditional branch
10557                 break;
10558               }
10559               else
10560               if(itype[j]==LOAD||itype[j]==LOADLR||
10561                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10562                 score[hr]++;
10563                 end[hr]=j;
10564               }
10565             }
10566           }
10567         }
10568         // Find highest score and allocate that register
10569         int maxscore=0;
10570         for(hr=0;hr<HOST_REGS;hr++) {
10571           if(hr!=EXCLUDE_REG) {
10572             if(score[hr]>score[maxscore]) {
10573               maxscore=hr;
10574               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10575             }
10576           }
10577         }
10578         if(score[maxscore]>1)
10579         {
10580           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10581           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10582             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10583             assert(regs[j].regmap[maxscore]<0);
10584             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10585             regs[j].regmap[maxscore]=reg;
10586             regs[j].dirty&=~(1<<maxscore);
10587             regs[j].wasconst&=~(1<<maxscore);
10588             regs[j].isconst&=~(1<<maxscore);
10589             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10590               branch_regs[j].regmap[maxscore]=reg;
10591               branch_regs[j].wasdirty&=~(1<<maxscore);
10592               branch_regs[j].dirty&=~(1<<maxscore);
10593               branch_regs[j].wasconst&=~(1<<maxscore);
10594               branch_regs[j].isconst&=~(1<<maxscore);
10595               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10596                 regmap_pre[j+2][maxscore]=reg;
10597                 regs[j+2].wasdirty&=~(1<<maxscore);
10598               }
10599               // loop optimization (loop_preload)
10600               int t=(ba[j]-start)>>2;
10601               if(t==loop_start[maxscore]) {
10602                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10603                   regs[t].regmap_entry[maxscore]=reg;
10604               }
10605             }
10606             else
10607             {
10608               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10609                 regmap_pre[j+1][maxscore]=reg;
10610                 regs[j+1].wasdirty&=~(1<<maxscore);
10611               }
10612             }
10613           }
10614           i=j-1;
10615           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10616           for(hr=0;hr<HOST_REGS;hr++) {
10617             score[hr]=0;earliest_available[hr]=i+i;
10618             loop_start[hr]=MAXBLOCK;
10619           }
10620         }
10621       }
10622     }
10623   }
10624   #endif
10625
10626   // This allocates registers (if possible) one instruction prior
10627   // to use, which can avoid a load-use penalty on certain CPUs.
10628   for(i=0;i<slen-1;i++)
10629   {
10630     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10631     {
10632       if(!bt[i+1])
10633       {
10634         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10635            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10636         {
10637           if(rs1[i+1]) {
10638             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10639             {
10640               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10641               {
10642                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10643                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10644                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10645                 regs[i].isconst&=~(1<<hr);
10646                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10647                 constmap[i][hr]=constmap[i+1][hr];
10648                 regs[i+1].wasdirty&=~(1<<hr);
10649                 regs[i].dirty&=~(1<<hr);
10650               }
10651             }
10652           }
10653           if(rs2[i+1]) {
10654             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10655             {
10656               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10657               {
10658                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10659                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10660                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10661                 regs[i].isconst&=~(1<<hr);
10662                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10663                 constmap[i][hr]=constmap[i+1][hr];
10664                 regs[i+1].wasdirty&=~(1<<hr);
10665                 regs[i].dirty&=~(1<<hr);
10666               }
10667             }
10668           }
10669           // Preload target address for load instruction (non-constant)
10670           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10671             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10672             {
10673               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10674               {
10675                 regs[i].regmap[hr]=rs1[i+1];
10676                 regmap_pre[i+1][hr]=rs1[i+1];
10677                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10678                 regs[i].isconst&=~(1<<hr);
10679                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10680                 constmap[i][hr]=constmap[i+1][hr];
10681                 regs[i+1].wasdirty&=~(1<<hr);
10682                 regs[i].dirty&=~(1<<hr);
10683               }
10684             }
10685           }
10686           // Load source into target register
10687           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10688             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10689             {
10690               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10691               {
10692                 regs[i].regmap[hr]=rs1[i+1];
10693                 regmap_pre[i+1][hr]=rs1[i+1];
10694                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10695                 regs[i].isconst&=~(1<<hr);
10696                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10697                 constmap[i][hr]=constmap[i+1][hr];
10698                 regs[i+1].wasdirty&=~(1<<hr);
10699                 regs[i].dirty&=~(1<<hr);
10700               }
10701             }
10702           }
10703           // Preload map address
10704           #ifndef HOST_IMM_ADDR32
10705           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10706             hr=get_reg(regs[i+1].regmap,TLREG);
10707             if(hr>=0) {
10708               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10709               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10710                 int nr;
10711                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10712                 {
10713                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10714                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10715                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10716                   regs[i].isconst&=~(1<<hr);
10717                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10718                   constmap[i][hr]=constmap[i+1][hr];
10719                   regs[i+1].wasdirty&=~(1<<hr);
10720                   regs[i].dirty&=~(1<<hr);
10721                 }
10722                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10723                 {
10724                   // move it to another register
10725                   regs[i+1].regmap[hr]=-1;
10726                   regmap_pre[i+2][hr]=-1;
10727                   regs[i+1].regmap[nr]=TLREG;
10728                   regmap_pre[i+2][nr]=TLREG;
10729                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10730                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10731                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10732                   regs[i].isconst&=~(1<<nr);
10733                   regs[i+1].isconst&=~(1<<nr);
10734                   regs[i].dirty&=~(1<<nr);
10735                   regs[i+1].wasdirty&=~(1<<nr);
10736                   regs[i+1].dirty&=~(1<<nr);
10737                   regs[i+2].wasdirty&=~(1<<nr);
10738                 }
10739               }
10740             }
10741           }
10742           #endif
10743           // Address for store instruction (non-constant)
10744           if(itype[i+1]==STORE||itype[i+1]==STORELR
10745              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10746             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10747               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10748               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10749               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10750               assert(hr>=0);
10751               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10752               {
10753                 regs[i].regmap[hr]=rs1[i+1];
10754                 regmap_pre[i+1][hr]=rs1[i+1];
10755                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10756                 regs[i].isconst&=~(1<<hr);
10757                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10758                 constmap[i][hr]=constmap[i+1][hr];
10759                 regs[i+1].wasdirty&=~(1<<hr);
10760                 regs[i].dirty&=~(1<<hr);
10761               }
10762             }
10763           }
10764           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10765             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10766               int nr;
10767               hr=get_reg(regs[i+1].regmap,FTEMP);
10768               assert(hr>=0);
10769               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10770               {
10771                 regs[i].regmap[hr]=rs1[i+1];
10772                 regmap_pre[i+1][hr]=rs1[i+1];
10773                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10774                 regs[i].isconst&=~(1<<hr);
10775                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10776                 constmap[i][hr]=constmap[i+1][hr];
10777                 regs[i+1].wasdirty&=~(1<<hr);
10778                 regs[i].dirty&=~(1<<hr);
10779               }
10780               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10781               {
10782                 // move it to another register
10783                 regs[i+1].regmap[hr]=-1;
10784                 regmap_pre[i+2][hr]=-1;
10785                 regs[i+1].regmap[nr]=FTEMP;
10786                 regmap_pre[i+2][nr]=FTEMP;
10787                 regs[i].regmap[nr]=rs1[i+1];
10788                 regmap_pre[i+1][nr]=rs1[i+1];
10789                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10790                 regs[i].isconst&=~(1<<nr);
10791                 regs[i+1].isconst&=~(1<<nr);
10792                 regs[i].dirty&=~(1<<nr);
10793                 regs[i+1].wasdirty&=~(1<<nr);
10794                 regs[i+1].dirty&=~(1<<nr);
10795                 regs[i+2].wasdirty&=~(1<<nr);
10796               }
10797             }
10798           }
10799           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10800             if(itype[i+1]==LOAD)
10801               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10802             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10803               hr=get_reg(regs[i+1].regmap,FTEMP);
10804             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10805               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10806               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10807             }
10808             if(hr>=0&&regs[i].regmap[hr]<0) {
10809               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10810               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10811                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10812                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10813                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10814                 regs[i].isconst&=~(1<<hr);
10815                 regs[i+1].wasdirty&=~(1<<hr);
10816                 regs[i].dirty&=~(1<<hr);
10817               }
10818             }
10819           }
10820         }
10821       }
10822     }
10823   }
10824
10825   /* Pass 6 - Optimize clean/dirty state */
10826   clean_registers(0,slen-1,1);
10827
10828   /* Pass 7 - Identify 32-bit registers */
10829 #ifndef FORCE32
10830   provisional_r32();
10831
10832   u_int r32=0;
10833
10834   for (i=slen-1;i>=0;i--)
10835   {
10836     int hr;
10837     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10838     {
10839       if(ba[i]<start || ba[i]>=(start+slen*4))
10840       {
10841         // Branch out of this block, don't need anything
10842         r32=0;
10843       }
10844       else
10845       {
10846         // Internal branch
10847         // Need whatever matches the target
10848         // (and doesn't get overwritten by the delay slot instruction)
10849         r32=0;
10850         int t=(ba[i]-start)>>2;
10851         if(ba[i]>start+i*4) {
10852           // Forward branch
10853           if(!(requires_32bit[t]&~regs[i].was32))
10854             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10855         }else{
10856           // Backward branch
10857           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10858           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10859           if(!(pr32[t]&~regs[i].was32))
10860             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10861         }
10862       }
10863       // Conditional branch may need registers for following instructions
10864       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10865       {
10866         if(i<slen-2) {
10867           r32|=requires_32bit[i+2];
10868           r32&=regs[i].was32;
10869           // Mark this address as a branch target since it may be called
10870           // upon return from interrupt
10871           bt[i+2]=1;
10872         }
10873       }
10874       // Merge in delay slot
10875       if(!likely[i]) {
10876         // These are overwritten unless the branch is "likely"
10877         // and the delay slot is nullified if not taken
10878         r32&=~(1LL<<rt1[i+1]);
10879         r32&=~(1LL<<rt2[i+1]);
10880       }
10881       // Assume these are needed (delay slot)
10882       if(us1[i+1]>0)
10883       {
10884         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10885       }
10886       if(us2[i+1]>0)
10887       {
10888         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10889       }
10890       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10891       {
10892         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10893       }
10894       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10895       {
10896         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10897       }
10898     }
10899     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10900     {
10901       // SYSCALL instruction (software interrupt)
10902       r32=0;
10903     }
10904     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10905     {
10906       // ERET instruction (return from interrupt)
10907       r32=0;
10908     }
10909     // Check 32 bits
10910     r32&=~(1LL<<rt1[i]);
10911     r32&=~(1LL<<rt2[i]);
10912     if(us1[i]>0)
10913     {
10914       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10915     }
10916     if(us2[i]>0)
10917     {
10918       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10919     }
10920     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10921     {
10922       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10923     }
10924     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10925     {
10926       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10927     }
10928     requires_32bit[i]=r32;
10929
10930     // Dirty registers which are 32-bit, require 32-bit input
10931     // as they will be written as 32-bit values
10932     for(hr=0;hr<HOST_REGS;hr++)
10933     {
10934       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10935         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10936           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10937           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10938         }
10939       }
10940     }
10941     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10942   }
10943 #else
10944   for (i=slen-1;i>=0;i--)
10945   {
10946     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10947     {
10948       // Conditional branch
10949       if((source[i]>>16)!=0x1000&&i<slen-2) {
10950         // Mark this address as a branch target since it may be called
10951         // upon return from interrupt
10952         bt[i+2]=1;
10953       }
10954     }
10955   }
10956 #endif
10957
10958   if(itype[slen-1]==SPAN) {
10959     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10960   }
10961
10962 #ifdef DISASM
10963   /* Debug/disassembly */
10964   for(i=0;i<slen;i++)
10965   {
10966     printf("U:");
10967     int r;
10968     for(r=1;r<=CCREG;r++) {
10969       if((unneeded_reg[i]>>r)&1) {
10970         if(r==HIREG) printf(" HI");
10971         else if(r==LOREG) printf(" LO");
10972         else printf(" r%d",r);
10973       }
10974     }
10975 #ifndef FORCE32
10976     printf(" UU:");
10977     for(r=1;r<=CCREG;r++) {
10978       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10979         if(r==HIREG) printf(" HI");
10980         else if(r==LOREG) printf(" LO");
10981         else printf(" r%d",r);
10982       }
10983     }
10984     printf(" 32:");
10985     for(r=0;r<=CCREG;r++) {
10986       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10987       if((regs[i].was32>>r)&1) {
10988         if(r==CCREG) printf(" CC");
10989         else if(r==HIREG) printf(" HI");
10990         else if(r==LOREG) printf(" LO");
10991         else printf(" r%d",r);
10992       }
10993     }
10994 #endif
10995     printf("\n");
10996     #if defined(__i386__) || defined(__x86_64__)
10997     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10998     #endif
10999     #ifdef __arm__
11000     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11001     #endif
11002     printf("needs: ");
11003     if(needed_reg[i]&1) printf("eax ");
11004     if((needed_reg[i]>>1)&1) printf("ecx ");
11005     if((needed_reg[i]>>2)&1) printf("edx ");
11006     if((needed_reg[i]>>3)&1) printf("ebx ");
11007     if((needed_reg[i]>>5)&1) printf("ebp ");
11008     if((needed_reg[i]>>6)&1) printf("esi ");
11009     if((needed_reg[i]>>7)&1) printf("edi ");
11010     printf("r:");
11011     for(r=0;r<=CCREG;r++) {
11012       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11013       if((requires_32bit[i]>>r)&1) {
11014         if(r==CCREG) printf(" CC");
11015         else if(r==HIREG) printf(" HI");
11016         else if(r==LOREG) printf(" LO");
11017         else printf(" r%d",r);
11018       }
11019     }
11020     printf("\n");
11021     /*printf("pr:");
11022     for(r=0;r<=CCREG;r++) {
11023       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11024       if((pr32[i]>>r)&1) {
11025         if(r==CCREG) printf(" CC");
11026         else if(r==HIREG) printf(" HI");
11027         else if(r==LOREG) printf(" LO");
11028         else printf(" r%d",r);
11029       }
11030     }
11031     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11032     printf("\n");*/
11033     #if defined(__i386__) || defined(__x86_64__)
11034     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11035     printf("dirty: ");
11036     if(regs[i].wasdirty&1) printf("eax ");
11037     if((regs[i].wasdirty>>1)&1) printf("ecx ");
11038     if((regs[i].wasdirty>>2)&1) printf("edx ");
11039     if((regs[i].wasdirty>>3)&1) printf("ebx ");
11040     if((regs[i].wasdirty>>5)&1) printf("ebp ");
11041     if((regs[i].wasdirty>>6)&1) printf("esi ");
11042     if((regs[i].wasdirty>>7)&1) printf("edi ");
11043     #endif
11044     #ifdef __arm__
11045     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11046     printf("dirty: ");
11047     if(regs[i].wasdirty&1) printf("r0 ");
11048     if((regs[i].wasdirty>>1)&1) printf("r1 ");
11049     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11050     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11051     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11052     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11053     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11054     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11055     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11056     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11057     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11058     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11059     #endif
11060     printf("\n");
11061     disassemble_inst(i);
11062     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11063     #if defined(__i386__) || defined(__x86_64__)
11064     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11065     if(regs[i].dirty&1) printf("eax ");
11066     if((regs[i].dirty>>1)&1) printf("ecx ");
11067     if((regs[i].dirty>>2)&1) printf("edx ");
11068     if((regs[i].dirty>>3)&1) printf("ebx ");
11069     if((regs[i].dirty>>5)&1) printf("ebp ");
11070     if((regs[i].dirty>>6)&1) printf("esi ");
11071     if((regs[i].dirty>>7)&1) printf("edi ");
11072     #endif
11073     #ifdef __arm__
11074     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11075     if(regs[i].dirty&1) printf("r0 ");
11076     if((regs[i].dirty>>1)&1) printf("r1 ");
11077     if((regs[i].dirty>>2)&1) printf("r2 ");
11078     if((regs[i].dirty>>3)&1) printf("r3 ");
11079     if((regs[i].dirty>>4)&1) printf("r4 ");
11080     if((regs[i].dirty>>5)&1) printf("r5 ");
11081     if((regs[i].dirty>>6)&1) printf("r6 ");
11082     if((regs[i].dirty>>7)&1) printf("r7 ");
11083     if((regs[i].dirty>>8)&1) printf("r8 ");
11084     if((regs[i].dirty>>9)&1) printf("r9 ");
11085     if((regs[i].dirty>>10)&1) printf("r10 ");
11086     if((regs[i].dirty>>12)&1) printf("r12 ");
11087     #endif
11088     printf("\n");
11089     if(regs[i].isconst) {
11090       printf("constants: ");
11091       #if defined(__i386__) || defined(__x86_64__)
11092       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11093       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11094       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11095       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11096       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11097       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11098       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11099       #endif
11100       #ifdef __arm__
11101       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11102       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11103       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11104       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11105       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11106       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11107       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11108       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11109       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11110       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11111       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11112       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11113       #endif
11114       printf("\n");
11115     }
11116 #ifndef FORCE32
11117     printf(" 32:");
11118     for(r=0;r<=CCREG;r++) {
11119       if((regs[i].is32>>r)&1) {
11120         if(r==CCREG) printf(" CC");
11121         else if(r==HIREG) printf(" HI");
11122         else if(r==LOREG) printf(" LO");
11123         else printf(" r%d",r);
11124       }
11125     }
11126     printf("\n");
11127 #endif
11128     /*printf(" p32:");
11129     for(r=0;r<=CCREG;r++) {
11130       if((p32[i]>>r)&1) {
11131         if(r==CCREG) printf(" CC");
11132         else if(r==HIREG) printf(" HI");
11133         else if(r==LOREG) printf(" LO");
11134         else printf(" r%d",r);
11135       }
11136     }
11137     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11138     else printf("\n");*/
11139     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11140       #if defined(__i386__) || defined(__x86_64__)
11141       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11142       if(branch_regs[i].dirty&1) printf("eax ");
11143       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11144       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11145       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11146       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11147       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11148       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11149       #endif
11150       #ifdef __arm__
11151       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11152       if(branch_regs[i].dirty&1) printf("r0 ");
11153       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11154       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11155       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11156       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11157       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11158       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11159       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11160       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11161       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11162       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11163       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11164       #endif
11165 #ifndef FORCE32
11166       printf(" 32:");
11167       for(r=0;r<=CCREG;r++) {
11168         if((branch_regs[i].is32>>r)&1) {
11169           if(r==CCREG) printf(" CC");
11170           else if(r==HIREG) printf(" HI");
11171           else if(r==LOREG) printf(" LO");
11172           else printf(" r%d",r);
11173         }
11174       }
11175       printf("\n");
11176 #endif
11177     }
11178   }
11179 #endif // DISASM
11180
11181   /* Pass 8 - Assembly */
11182   linkcount=0;stubcount=0;
11183   ds=0;is_delayslot=0;
11184   cop1_usable=0;
11185   uint64_t is32_pre=0;
11186   u_int dirty_pre=0;
11187   u_int beginning=(u_int)out;
11188   if((u_int)addr&1) {
11189     ds=1;
11190     pagespan_ds();
11191   }
11192   u_int instr_addr0_override=0;
11193
11194 #ifdef PCSX
11195   if (start == 0x80030000) {
11196     // nasty hack for fastbios thing
11197     // override block entry to this code
11198     instr_addr0_override=(u_int)out;
11199     emit_movimm(start,0);
11200     // abuse io address var as a flag that we
11201     // have already returned here once
11202     emit_readword((int)&address,1);
11203     emit_writeword(0,(int)&pcaddr);
11204     emit_writeword(0,(int)&address);
11205     emit_cmp(0,1);
11206     emit_jne((int)new_dyna_leave);
11207   }
11208 #endif
11209   for(i=0;i<slen;i++)
11210   {
11211     //if(ds) printf("ds: ");
11212     disassemble_inst(i);
11213     if(ds) {
11214       ds=0; // Skip delay slot
11215       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11216       instr_addr[i]=0;
11217     } else {
11218       speculate_register_values(i);
11219       #ifndef DESTRUCTIVE_WRITEBACK
11220       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11221       {
11222         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11223               unneeded_reg[i],unneeded_reg_upper[i]);
11224         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11225               unneeded_reg[i],unneeded_reg_upper[i]);
11226       }
11227       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11228         is32_pre=branch_regs[i].is32;
11229         dirty_pre=branch_regs[i].dirty;
11230       }else{
11231         is32_pre=regs[i].is32;
11232         dirty_pre=regs[i].dirty;
11233       }
11234       #endif
11235       // write back
11236       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11237       {
11238         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11239                       unneeded_reg[i],unneeded_reg_upper[i]);
11240         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11241       }
11242       // branch target entry point
11243       instr_addr[i]=(u_int)out;
11244       assem_debug("<->\n");
11245       // load regs
11246       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11247         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11248       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11249       address_generation(i,&regs[i],regs[i].regmap_entry);
11250       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11251       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11252       {
11253         // Load the delay slot registers if necessary
11254         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11255           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11256         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11257           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11258         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11259           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11260       }
11261       else if(i+1<slen)
11262       {
11263         // Preload registers for following instruction
11264         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11265           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11266             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11267         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11268           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11269             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11270       }
11271       // TODO: if(is_ooo(i)) address_generation(i+1);
11272       if(itype[i]==CJUMP||itype[i]==FJUMP)
11273         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11274       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11275         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11276       if(bt[i]) cop1_usable=0;
11277       // assemble
11278       switch(itype[i]) {
11279         case ALU:
11280           alu_assemble(i,&regs[i]);break;
11281         case IMM16:
11282           imm16_assemble(i,&regs[i]);break;
11283         case SHIFT:
11284           shift_assemble(i,&regs[i]);break;
11285         case SHIFTIMM:
11286           shiftimm_assemble(i,&regs[i]);break;
11287         case LOAD:
11288           load_assemble(i,&regs[i]);break;
11289         case LOADLR:
11290           loadlr_assemble(i,&regs[i]);break;
11291         case STORE:
11292           store_assemble(i,&regs[i]);break;
11293         case STORELR:
11294           storelr_assemble(i,&regs[i]);break;
11295         case COP0:
11296           cop0_assemble(i,&regs[i]);break;
11297         case COP1:
11298           cop1_assemble(i,&regs[i]);break;
11299         case C1LS:
11300           c1ls_assemble(i,&regs[i]);break;
11301         case COP2:
11302           cop2_assemble(i,&regs[i]);break;
11303         case C2LS:
11304           c2ls_assemble(i,&regs[i]);break;
11305         case C2OP:
11306           c2op_assemble(i,&regs[i]);break;
11307         case FCONV:
11308           fconv_assemble(i,&regs[i]);break;
11309         case FLOAT:
11310           float_assemble(i,&regs[i]);break;
11311         case FCOMP:
11312           fcomp_assemble(i,&regs[i]);break;
11313         case MULTDIV:
11314           multdiv_assemble(i,&regs[i]);break;
11315         case MOV:
11316           mov_assemble(i,&regs[i]);break;
11317         case SYSCALL:
11318           syscall_assemble(i,&regs[i]);break;
11319         case HLECALL:
11320           hlecall_assemble(i,&regs[i]);break;
11321         case INTCALL:
11322           intcall_assemble(i,&regs[i]);break;
11323         case UJUMP:
11324           ujump_assemble(i,&regs[i]);ds=1;break;
11325         case RJUMP:
11326           rjump_assemble(i,&regs[i]);ds=1;break;
11327         case CJUMP:
11328           cjump_assemble(i,&regs[i]);ds=1;break;
11329         case SJUMP:
11330           sjump_assemble(i,&regs[i]);ds=1;break;
11331         case FJUMP:
11332           fjump_assemble(i,&regs[i]);ds=1;break;
11333         case SPAN:
11334           pagespan_assemble(i,&regs[i]);break;
11335       }
11336       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11337         literal_pool(1024);
11338       else
11339         literal_pool_jumpover(256);
11340     }
11341   }
11342   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11343   // If the block did not end with an unconditional branch,
11344   // add a jump to the next instruction.
11345   if(i>1) {
11346     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11347       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11348       assert(i==slen);
11349       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11350         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11351         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11352           emit_loadreg(CCREG,HOST_CCREG);
11353         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11354       }
11355       else if(!likely[i-2])
11356       {
11357         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11358         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11359       }
11360       else
11361       {
11362         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11363         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11364       }
11365       add_to_linker((int)out,start+i*4,0);
11366       emit_jmp(0);
11367     }
11368   }
11369   else
11370   {
11371     assert(i>0);
11372     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11373     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11374     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11375       emit_loadreg(CCREG,HOST_CCREG);
11376     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11377     add_to_linker((int)out,start+i*4,0);
11378     emit_jmp(0);
11379   }
11380
11381   // TODO: delay slot stubs?
11382   // Stubs
11383   for(i=0;i<stubcount;i++)
11384   {
11385     switch(stubs[i][0])
11386     {
11387       case LOADB_STUB:
11388       case LOADH_STUB:
11389       case LOADW_STUB:
11390       case LOADD_STUB:
11391       case LOADBU_STUB:
11392       case LOADHU_STUB:
11393         do_readstub(i);break;
11394       case STOREB_STUB:
11395       case STOREH_STUB:
11396       case STOREW_STUB:
11397       case STORED_STUB:
11398         do_writestub(i);break;
11399       case CC_STUB:
11400         do_ccstub(i);break;
11401       case INVCODE_STUB:
11402         do_invstub(i);break;
11403       case FP_STUB:
11404         do_cop1stub(i);break;
11405       case STORELR_STUB:
11406         do_unalignedwritestub(i);break;
11407     }
11408   }
11409
11410   if (instr_addr0_override)
11411     instr_addr[0] = instr_addr0_override;
11412
11413   /* Pass 9 - Linker */
11414   for(i=0;i<linkcount;i++)
11415   {
11416     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11417     literal_pool(64);
11418     if(!link_addr[i][2])
11419     {
11420       void *stub=out;
11421       void *addr=check_addr(link_addr[i][1]);
11422       emit_extjump(link_addr[i][0],link_addr[i][1]);
11423       if(addr) {
11424         set_jump_target(link_addr[i][0],(int)addr);
11425         add_link(link_addr[i][1],stub);
11426       }
11427       else set_jump_target(link_addr[i][0],(int)stub);
11428     }
11429     else
11430     {
11431       // Internal branch
11432       int target=(link_addr[i][1]-start)>>2;
11433       assert(target>=0&&target<slen);
11434       assert(instr_addr[target]);
11435       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11436       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11437       //#else
11438       set_jump_target(link_addr[i][0],instr_addr[target]);
11439       //#endif
11440     }
11441   }
11442   // External Branch Targets (jump_in)
11443   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11444   for(i=0;i<slen;i++)
11445   {
11446     if(bt[i]||i==0)
11447     {
11448       if(instr_addr[i]) // TODO - delay slots (=null)
11449       {
11450         u_int vaddr=start+i*4;
11451         u_int page=get_page(vaddr);
11452         u_int vpage=get_vpage(vaddr);
11453         literal_pool(256);
11454         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11455 #ifndef FORCE32
11456         if(!requires_32bit[i])
11457 #else
11458         if(1)
11459 #endif
11460         {
11461           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11462           assem_debug("jump_in: %x\n",start+i*4);
11463           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11464           int entry_point=do_dirty_stub(i);
11465           ll_add(jump_in+page,vaddr,(void *)entry_point);
11466           // If there was an existing entry in the hash table,
11467           // replace it with the new address.
11468           // Don't add new entries.  We'll insert the
11469           // ones that actually get used in check_addr().
11470           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11471           if(ht_bin[0]==vaddr) {
11472             ht_bin[1]=entry_point;
11473           }
11474           if(ht_bin[2]==vaddr) {
11475             ht_bin[3]=entry_point;
11476           }
11477         }
11478         else
11479         {
11480           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11481           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11482           assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11483           //int entry_point=(int)out;
11484           ////assem_debug("entry_point: %x\n",entry_point);
11485           //load_regs_entry(i);
11486           //if(entry_point==(int)out)
11487           //  entry_point=instr_addr[i];
11488           //else
11489           //  emit_jmp(instr_addr[i]);
11490           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11491           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11492           int entry_point=do_dirty_stub(i);
11493           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11494         }
11495       }
11496     }
11497   }
11498   // Write out the literal pool if necessary
11499   literal_pool(0);
11500   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11501   // Align code
11502   if(((u_int)out)&7) emit_addnop(13);
11503   #endif
11504   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11505   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11506   memcpy(copy,source,slen*4);
11507   copy+=slen*4;
11508
11509   #ifdef __arm__
11510   __clear_cache((void *)beginning,out);
11511   #endif
11512
11513   // If we're within 256K of the end of the buffer,
11514   // start over from the beginning. (Is 256K enough?)
11515   if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11516
11517   // Trap writes to any of the pages we compiled
11518   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11519     invalid_code[i]=0;
11520 #ifndef DISABLE_TLB
11521     memory_map[i]|=0x40000000;
11522     if((signed int)start>=(signed int)0xC0000000) {
11523       assert(using_tlb);
11524       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11525       invalid_code[j]=0;
11526       memory_map[j]|=0x40000000;
11527       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11528     }
11529 #endif
11530   }
11531   inv_code_start=inv_code_end=~0;
11532 #ifdef PCSX
11533   // for PCSX we need to mark all mirrors too
11534   if(get_page(start)<(RAM_SIZE>>12))
11535     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11536       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11537       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11538       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11539 #endif
11540
11541   /* Pass 10 - Free memory by expiring oldest blocks */
11542
11543   int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11544   while(expirep!=end)
11545   {
11546     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11547     int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11548     inv_debug("EXP: Phase %d\n",expirep);
11549     switch((expirep>>11)&3)
11550     {
11551       case 0:
11552         // Clear jump_in and jump_dirty
11553         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11554         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11555         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11556         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11557         break;
11558       case 1:
11559         // Clear pointers
11560         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11561         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11562         break;
11563       case 2:
11564         // Clear hash table
11565         for(i=0;i<32;i++) {
11566           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11567           if((ht_bin[3]>>shift)==(base>>shift) ||
11568              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11569             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11570             ht_bin[2]=ht_bin[3]=-1;
11571           }
11572           if((ht_bin[1]>>shift)==(base>>shift) ||
11573              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11574             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11575             ht_bin[0]=ht_bin[2];
11576             ht_bin[1]=ht_bin[3];
11577             ht_bin[2]=ht_bin[3]=-1;
11578           }
11579         }
11580         break;
11581       case 3:
11582         // Clear jump_out
11583         #ifdef __arm__
11584         if((expirep&2047)==0)
11585           do_clear_cache();
11586         #endif
11587         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11588         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11589         break;
11590     }
11591     expirep=(expirep+1)&65535;
11592   }
11593   return 0;
11594 }
11595
11596 // vim:shiftwidth=2:expandtab