1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27 // Coprocessor 2 move
180 #define C2LS 28 // Coprocessor 2 load/store
181 #define C2OP 29 // Coprocessor 2 operation
190 #define LOADBU_STUB 7
191 #define LOADHU_STUB 8
192 #define STOREB_STUB 9
193 #define STOREH_STUB 10
194 #define STOREW_STUB 11
195 #define STORED_STUB 12
196 #define STORELR_STUB 13
197 #define INVCODE_STUB 14
205 int new_recompile_block(int addr);
206 void *get_addr_ht(u_int vaddr);
207 void invalidate_block(u_int block);
208 void invalidate_addr(u_int addr);
209 void remove_hash(int vaddr);
212 void dyna_linker_ds();
214 void verify_code_vm();
215 void verify_code_ds();
218 void fp_exception_ds();
220 void jump_syscall_hle();
223 void new_dyna_leave();
228 void read_nomem_new();
229 void read_nomemb_new();
230 void read_nomemh_new();
231 void read_nomemd_new();
232 void write_nomem_new();
233 void write_nomemb_new();
234 void write_nomemh_new();
235 void write_nomemd_new();
236 void write_rdram_new();
237 void write_rdramb_new();
238 void write_rdramh_new();
239 void write_rdramd_new();
240 extern u_int memory_map[1048576];
242 // Needed by assembler
243 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
244 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
245 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
246 void load_all_regs(signed char i_regmap[]);
247 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
248 void load_regs_entry(int t);
249 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
253 //#define DEBUG_CYCLE_COUNT 1
256 //#define assem_debug printf
257 //#define inv_debug printf
258 #define assem_debug nullf
259 #define inv_debug nullf
261 static void tlb_hacks()
265 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
269 switch (ROM_HEADER->Country_code&0xFF)
281 // Unknown country code
285 u_int rom_addr=(u_int)rom;
287 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
288 // in the lower 4G of memory to use this hack. Copy it if necessary.
289 if((void *)rom>(void *)0xffffffff) {
290 munmap(ROM_COPY, 67108864);
291 if(mmap(ROM_COPY, 12582912,
292 PROT_READ | PROT_WRITE,
293 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
294 -1, 0) <= 0) {printf("mmap() failed\n");}
295 memcpy(ROM_COPY,rom,12582912);
296 rom_addr=(u_int)ROM_COPY;
300 for(n=0x7F000;n<0x80000;n++) {
301 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
308 static u_int get_page(u_int vaddr)
310 u_int page=(vaddr^0x80000000)>>12;
312 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
314 if(page>2048) page=2048+(page&2047);
318 static u_int get_vpage(u_int vaddr)
320 u_int vpage=(vaddr^0x80000000)>>12;
322 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
324 if(vpage>2048) vpage=2048+(vpage&2047);
328 // Get address from virtual address
329 // This is called from the recompiled JR/JALR instructions
330 void *get_addr(u_int vaddr)
332 u_int page=get_page(vaddr);
333 u_int vpage=get_vpage(vaddr);
334 struct ll_entry *head;
335 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
338 if(head->vaddr==vaddr&&head->reg32==0) {
339 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
340 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
343 ht_bin[1]=(int)head->addr;
349 head=jump_dirty[vpage];
351 if(head->vaddr==vaddr&&head->reg32==0) {
352 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
353 // Don't restore blocks which are about to expire from the cache
354 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
355 if(verify_dirty(head->addr)) {
356 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
357 invalid_code[vaddr>>12]=0;
358 memory_map[vaddr>>12]|=0x40000000;
361 if(tlb_LUT_r[vaddr>>12]) {
362 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
363 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
366 restore_candidate[vpage>>3]|=1<<(vpage&7);
368 else restore_candidate[page>>3]|=1<<(page&7);
369 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
370 if(ht_bin[0]==vaddr) {
371 ht_bin[1]=(int)head->addr; // Replace existing entry
377 ht_bin[1]=(int)head->addr;
385 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
386 int r=new_recompile_block(vaddr);
387 if(r==0) return get_addr(vaddr);
388 // Execute in unmapped page, generate pagefault execption
390 Cause=(vaddr<<31)|0x8;
391 EPC=(vaddr&1)?vaddr-5:vaddr;
393 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
394 EntryHi=BadVAddr&0xFFFFE000;
395 return get_addr_ht(0x80000000);
397 // Look up address in hash table first
398 void *get_addr_ht(u_int vaddr)
400 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
401 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
402 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
403 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
404 return get_addr(vaddr);
407 void *get_addr_32(u_int vaddr,u_int flags)
410 return get_addr(vaddr);
412 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
413 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
414 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
415 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
416 u_int page=get_page(vaddr);
417 u_int vpage=get_vpage(vaddr);
418 struct ll_entry *head;
421 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
422 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
424 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
426 ht_bin[1]=(int)head->addr;
428 }else if(ht_bin[2]==-1) {
429 ht_bin[3]=(int)head->addr;
432 //ht_bin[3]=ht_bin[1];
433 //ht_bin[2]=ht_bin[0];
434 //ht_bin[1]=(int)head->addr;
441 head=jump_dirty[vpage];
443 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
444 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
445 // Don't restore blocks which are about to expire from the cache
446 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
447 if(verify_dirty(head->addr)) {
448 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
449 invalid_code[vaddr>>12]=0;
450 memory_map[vaddr>>12]|=0x40000000;
453 if(tlb_LUT_r[vaddr>>12]) {
454 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
455 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
458 restore_candidate[vpage>>3]|=1<<(vpage&7);
460 else restore_candidate[page>>3]|=1<<(page&7);
462 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
464 ht_bin[1]=(int)head->addr;
466 }else if(ht_bin[2]==-1) {
467 ht_bin[3]=(int)head->addr;
470 //ht_bin[3]=ht_bin[1];
471 //ht_bin[2]=ht_bin[0];
472 //ht_bin[1]=(int)head->addr;
480 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
481 int r=new_recompile_block(vaddr);
482 if(r==0) return get_addr(vaddr);
483 // Execute in unmapped page, generate pagefault execption
485 Cause=(vaddr<<31)|0x8;
486 EPC=(vaddr&1)?vaddr-5:vaddr;
488 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
489 EntryHi=BadVAddr&0xFFFFE000;
490 return get_addr_ht(0x80000000);
493 void clear_all_regs(signed char regmap[])
496 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
499 signed char get_reg(signed char regmap[],int r)
502 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
506 // Find a register that is available for two consecutive cycles
507 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
510 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
514 int count_free_regs(signed char regmap[])
518 for(hr=0;hr<HOST_REGS;hr++)
520 if(hr!=EXCLUDE_REG) {
521 if(regmap[hr]<0) count++;
527 void dirty_reg(struct regstat *cur,signed char reg)
531 for (hr=0;hr<HOST_REGS;hr++) {
532 if((cur->regmap[hr]&63)==reg) {
538 // If we dirty the lower half of a 64 bit register which is now being
539 // sign-extended, we need to dump the upper half.
540 // Note: Do this only after completion of the instruction, because
541 // some instructions may need to read the full 64-bit value even if
542 // overwriting it (eg SLTI, DSRA32).
543 static void flush_dirty_uppers(struct regstat *cur)
546 for (hr=0;hr<HOST_REGS;hr++) {
547 if((cur->dirty>>hr)&1) {
550 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
555 void set_const(struct regstat *cur,signed char reg,uint64_t value)
559 for (hr=0;hr<HOST_REGS;hr++) {
560 if(cur->regmap[hr]==reg) {
562 cur->constmap[hr]=value;
564 else if((cur->regmap[hr]^64)==reg) {
566 cur->constmap[hr]=value>>32;
571 void clear_const(struct regstat *cur,signed char reg)
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if((cur->regmap[hr]&63)==reg) {
577 cur->isconst&=~(1<<hr);
582 int is_const(struct regstat *cur,signed char reg)
586 for (hr=0;hr<HOST_REGS;hr++) {
587 if((cur->regmap[hr]&63)==reg) {
588 return (cur->isconst>>hr)&1;
593 uint64_t get_const(struct regstat *cur,signed char reg)
597 for (hr=0;hr<HOST_REGS;hr++) {
598 if(cur->regmap[hr]==reg) {
599 return cur->constmap[hr];
602 printf("Unknown constant in r%d\n",reg);
606 // Least soon needed registers
607 // Look at the next ten instructions and see which registers
608 // will be used. Try not to reallocate these.
609 void lsn(u_char hsn[], int i, int *preferred_reg)
619 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
621 // Don't go past an unconditonal jump
628 if(rs1[i+j]) hsn[rs1[i+j]]=j;
629 if(rs2[i+j]) hsn[rs2[i+j]]=j;
630 if(rt1[i+j]) hsn[rt1[i+j]]=j;
631 if(rt2[i+j]) hsn[rt2[i+j]]=j;
632 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
633 // Stores can allocate zero
637 // On some architectures stores need invc_ptr
638 #if defined(HOST_IMM8)
639 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
643 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
651 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
653 // Follow first branch
654 int t=(ba[i+b]-start)>>2;
655 j=7-b;if(t+j>=slen) j=slen-t-1;
658 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
659 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
660 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
661 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
664 // TODO: preferred register based on backward branch
666 // Delay slot should preferably not overwrite branch conditions or cycle count
667 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
668 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
669 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
675 // Coprocessor load/store needs FTEMP, even if not declared
676 if(itype[i]==C1LS||itype[i]==C2LS) {
679 // Load L/R also uses FTEMP as a temporary register
680 if(itype[i]==LOADLR) {
683 // Also SWL/SWR/SDL/SDR
684 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
687 // Don't remove the TLB registers either
688 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
691 // Don't remove the miniht registers
692 if(itype[i]==UJUMP||itype[i]==RJUMP)
699 // We only want to allocate registers if we're going to use them again soon
700 int needed_again(int r, int i)
706 u_char hsn[MAXREG+1];
709 memset(hsn,10,sizeof(hsn));
710 lsn(hsn,i,&preferred_reg);
712 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
714 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
715 return 0; // Don't need any registers if exiting the block
723 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
725 // Don't go past an unconditonal jump
729 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||((source[i+j]&0xfc00003f)==0x0d))
736 if(rs1[i+j]==r) rn=j;
737 if(rs2[i+j]==r) rn=j;
738 if((unneeded_reg[i+j]>>r)&1) rn=10;
739 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
747 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
749 // Follow first branch
751 int t=(ba[i+b]-start)>>2;
752 j=7-b;if(t+j>=slen) j=slen-t-1;
755 if(!((unneeded_reg[t+j]>>r)&1)) {
756 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
757 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
763 for(hr=0;hr<HOST_REGS;hr++) {
764 if(hr!=EXCLUDE_REG) {
765 if(rn<hsn[hr]) return 1;
771 // Try to match register allocations at the end of a loop with those
773 int loop_reg(int i, int r, int hr)
782 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
784 // Don't go past an unconditonal jump
791 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
796 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
797 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
798 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
800 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
802 int t=(ba[i+k]-start)>>2;
803 int reg=get_reg(regs[t].regmap_entry,r);
804 if(reg>=0) return reg;
805 //reg=get_reg(regs[t+1].regmap_entry,r);
806 //if(reg>=0) return reg;
814 // Allocate every register, preserving source/target regs
815 void alloc_all(struct regstat *cur,int i)
819 for(hr=0;hr<HOST_REGS;hr++) {
820 if(hr!=EXCLUDE_REG) {
821 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
822 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
825 cur->dirty&=~(1<<hr);
828 if((cur->regmap[hr]&63)==0)
831 cur->dirty&=~(1<<hr);
838 void div64(int64_t dividend,int64_t divisor)
842 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
843 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
845 void divu64(uint64_t dividend,uint64_t divisor)
849 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
850 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
853 void mult64(uint64_t m1,uint64_t m2)
855 unsigned long long int op1, op2, op3, op4;
856 unsigned long long int result1, result2, result3, result4;
857 unsigned long long int temp1, temp2, temp3, temp4;
873 op1 = op2 & 0xFFFFFFFF;
874 op2 = (op2 >> 32) & 0xFFFFFFFF;
875 op3 = op4 & 0xFFFFFFFF;
876 op4 = (op4 >> 32) & 0xFFFFFFFF;
879 temp2 = (temp1 >> 32) + op1 * op4;
881 temp4 = (temp3 >> 32) + op2 * op4;
883 result1 = temp1 & 0xFFFFFFFF;
884 result2 = temp2 + (temp3 & 0xFFFFFFFF);
885 result3 = (result2 >> 32) + temp4;
886 result4 = (result3 >> 32);
888 lo = result1 | (result2 << 32);
889 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
898 void multu64(uint64_t m1,uint64_t m2)
900 unsigned long long int op1, op2, op3, op4;
901 unsigned long long int result1, result2, result3, result4;
902 unsigned long long int temp1, temp2, temp3, temp4;
904 op1 = m1 & 0xFFFFFFFF;
905 op2 = (m1 >> 32) & 0xFFFFFFFF;
906 op3 = m2 & 0xFFFFFFFF;
907 op4 = (m2 >> 32) & 0xFFFFFFFF;
910 temp2 = (temp1 >> 32) + op1 * op4;
912 temp4 = (temp3 >> 32) + op2 * op4;
914 result1 = temp1 & 0xFFFFFFFF;
915 result2 = temp2 + (temp3 & 0xFFFFFFFF);
916 result3 = (result2 >> 32) + temp4;
917 result4 = (result3 >> 32);
919 lo = result1 | (result2 << 32);
920 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
922 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
923 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
926 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
934 else original=loaded;
937 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
940 original>>=64-(bits^56);
941 original<<=64-(bits^56);
945 else original=loaded;
950 #include "assem_x86.c"
953 #include "assem_x64.c"
956 #include "assem_arm.c"
959 // Add virtual address mapping to linked list
960 void ll_add(struct ll_entry **head,int vaddr,void *addr)
962 struct ll_entry *new_entry;
963 new_entry=malloc(sizeof(struct ll_entry));
964 assert(new_entry!=NULL);
965 new_entry->vaddr=vaddr;
967 new_entry->addr=addr;
968 new_entry->next=*head;
972 // Add virtual address mapping for 32-bit compiled block
973 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
975 ll_add(head,vaddr,addr);
977 (*head)->reg32=reg32;
981 // Check if an address is already compiled
982 // but don't return addresses which are about to expire from the cache
983 void *check_addr(u_int vaddr)
985 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
986 if(ht_bin[0]==vaddr) {
987 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
988 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
990 if(ht_bin[2]==vaddr) {
991 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
992 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
994 u_int page=get_page(vaddr);
995 struct ll_entry *head;
998 if(head->vaddr==vaddr&&head->reg32==0) {
999 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1000 // Update existing entry with current address
1001 if(ht_bin[0]==vaddr) {
1002 ht_bin[1]=(int)head->addr;
1005 if(ht_bin[2]==vaddr) {
1006 ht_bin[3]=(int)head->addr;
1009 // Insert into hash table with low priority.
1010 // Don't evict existing entries, as they are probably
1011 // addresses that are being accessed frequently.
1013 ht_bin[1]=(int)head->addr;
1015 }else if(ht_bin[2]==-1) {
1016 ht_bin[3]=(int)head->addr;
1027 void remove_hash(int vaddr)
1029 //printf("remove hash: %x\n",vaddr);
1030 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1031 if(ht_bin[2]==vaddr) {
1032 ht_bin[2]=ht_bin[3]=-1;
1034 if(ht_bin[0]==vaddr) {
1035 ht_bin[0]=ht_bin[2];
1036 ht_bin[1]=ht_bin[3];
1037 ht_bin[2]=ht_bin[3]=-1;
1041 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1043 struct ll_entry *next;
1045 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1046 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1048 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1049 remove_hash((*head)->vaddr);
1056 head=&((*head)->next);
1061 // Remove all entries from linked list
1062 void ll_clear(struct ll_entry **head)
1064 struct ll_entry *cur;
1065 struct ll_entry *next;
1076 // Dereference the pointers and remove if it matches
1077 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1079 u_int old_host_addr=0;
1081 int ptr=get_pointer(head->addr);
1082 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1083 if(((ptr>>shift)==(addr>>shift)) ||
1084 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1086 printf("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1087 u_int host_addr=(u_int)kill_pointer(head->addr);
1089 if((host_addr>>12)!=(old_host_addr>>12)) {
1091 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1093 old_host_addr=host_addr;
1100 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1104 // This is called when we write to a compiled block (see do_invstub)
1105 void invalidate_page(u_int page)
1107 struct ll_entry *head;
1108 struct ll_entry *next;
1109 u_int old_host_addr=0;
1113 inv_debug("INVALIDATE: %x\n",head->vaddr);
1114 remove_hash(head->vaddr);
1119 head=jump_out[page];
1122 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1123 u_int host_addr=(u_int)kill_pointer(head->addr);
1125 if((host_addr>>12)!=(old_host_addr>>12)) {
1127 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1129 old_host_addr=host_addr;
1137 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1140 void invalidate_block(u_int block)
1142 u_int page=get_page(block<<12);
1143 u_int vpage=get_vpage(block<<12);
1144 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1145 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1148 struct ll_entry *head;
1149 head=jump_dirty[vpage];
1150 //printf("page=%d vpage=%d\n",page,vpage);
1153 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1154 get_bounds((int)head->addr,&start,&end);
1155 //printf("start: %x end: %x\n",start,end);
1156 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1157 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1158 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1159 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1163 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1164 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1165 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1166 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1173 //printf("first=%d last=%d\n",first,last);
1174 invalidate_page(page);
1175 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1176 assert(last<page+5);
1177 // Invalidate the adjacent pages if a block crosses a 4K boundary
1179 invalidate_page(first);
1182 for(first=page+1;first<last;first++) {
1183 invalidate_page(first);
1186 // Don't trap writes
1187 invalid_code[block]=1;
1189 // If there is a valid TLB entry for this page, remove write protect
1190 if(tlb_LUT_w[block]) {
1191 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1192 // CHECK: Is this right?
1193 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1194 u_int real_block=tlb_LUT_w[block]>>12;
1195 invalid_code[real_block]=1;
1196 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1198 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1202 memset(mini_ht,-1,sizeof(mini_ht));
1205 void invalidate_addr(u_int addr)
1207 invalidate_block(addr>>12);
1209 void invalidate_all_pages()
1212 for(page=0;page<4096;page++)
1213 invalidate_page(page);
1214 for(page=0;page<1048576;page++)
1215 if(!invalid_code[page]) {
1216 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1217 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1220 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1223 memset(mini_ht,-1,sizeof(mini_ht));
1227 for(page=0;page<0x100000;page++) {
1228 if(tlb_LUT_r[page]) {
1229 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1230 if(!tlb_LUT_w[page]||!invalid_code[page])
1231 memory_map[page]|=0x40000000; // Write protect
1233 else memory_map[page]=-1;
1234 if(page==0x80000) page=0xC0000;
1240 // Add an entry to jump_out after making a link
1241 void add_link(u_int vaddr,void *src)
1243 u_int page=get_page(vaddr);
1244 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1245 ll_add(jump_out+page,vaddr,src);
1246 //int ptr=get_pointer(src);
1247 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1250 // If a code block was found to be unmodified (bit was set in
1251 // restore_candidate) and it remains unmodified (bit is clear
1252 // in invalid_code) then move the entries for that 4K page from
1253 // the dirty list to the clean list.
1254 void clean_blocks(u_int page)
1256 struct ll_entry *head;
1257 inv_debug("INV: clean_blocks page=%d\n",page);
1258 head=jump_dirty[page];
1260 if(!invalid_code[head->vaddr>>12]) {
1261 // Don't restore blocks which are about to expire from the cache
1262 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1264 if(verify_dirty((int)head->addr)) {
1265 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1268 get_bounds((int)head->addr,&start,&end);
1269 if(start-(u_int)rdram<RAM_SIZE) {
1270 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1271 inv|=invalid_code[i];
1274 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1275 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1276 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1277 if(addr<start||addr>=end) inv=1;
1279 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1283 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1284 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1287 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1289 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1290 //printf("page=%x, addr=%x\n",page,head->vaddr);
1291 //assert(head->vaddr>>12==(page|0x80000));
1292 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1293 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1295 if(ht_bin[0]==head->vaddr) {
1296 ht_bin[1]=(int)clean_addr; // Replace existing entry
1298 if(ht_bin[2]==head->vaddr) {
1299 ht_bin[3]=(int)clean_addr; // Replace existing entry
1312 void mov_alloc(struct regstat *current,int i)
1314 // Note: Don't need to actually alloc the source registers
1315 if((~current->is32>>rs1[i])&1) {
1316 //alloc_reg64(current,i,rs1[i]);
1317 alloc_reg64(current,i,rt1[i]);
1318 current->is32&=~(1LL<<rt1[i]);
1320 //alloc_reg(current,i,rs1[i]);
1321 alloc_reg(current,i,rt1[i]);
1322 current->is32|=(1LL<<rt1[i]);
1324 clear_const(current,rs1[i]);
1325 clear_const(current,rt1[i]);
1326 dirty_reg(current,rt1[i]);
1329 void shiftimm_alloc(struct regstat *current,int i)
1331 clear_const(current,rs1[i]);
1332 clear_const(current,rt1[i]);
1333 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1336 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1338 alloc_reg(current,i,rt1[i]);
1339 current->is32|=1LL<<rt1[i];
1340 dirty_reg(current,rt1[i]);
1343 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1346 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1347 alloc_reg64(current,i,rt1[i]);
1348 current->is32&=~(1LL<<rt1[i]);
1349 dirty_reg(current,rt1[i]);
1352 if(opcode2[i]==0x3c) // DSLL32
1355 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1356 alloc_reg64(current,i,rt1[i]);
1357 current->is32&=~(1LL<<rt1[i]);
1358 dirty_reg(current,rt1[i]);
1361 if(opcode2[i]==0x3e) // DSRL32
1364 alloc_reg64(current,i,rs1[i]);
1366 alloc_reg64(current,i,rt1[i]);
1367 current->is32&=~(1LL<<rt1[i]);
1369 alloc_reg(current,i,rt1[i]);
1370 current->is32|=1LL<<rt1[i];
1372 dirty_reg(current,rt1[i]);
1375 if(opcode2[i]==0x3f) // DSRA32
1378 alloc_reg64(current,i,rs1[i]);
1379 alloc_reg(current,i,rt1[i]);
1380 current->is32|=1LL<<rt1[i];
1381 dirty_reg(current,rt1[i]);
1386 void shift_alloc(struct regstat *current,int i)
1389 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1391 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1392 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1393 alloc_reg(current,i,rt1[i]);
1394 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1395 current->is32|=1LL<<rt1[i];
1396 } else { // DSLLV/DSRLV/DSRAV
1397 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1398 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1399 alloc_reg64(current,i,rt1[i]);
1400 current->is32&=~(1LL<<rt1[i]);
1401 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1402 alloc_reg_temp(current,i,-1);
1404 clear_const(current,rs1[i]);
1405 clear_const(current,rs2[i]);
1406 clear_const(current,rt1[i]);
1407 dirty_reg(current,rt1[i]);
1411 void alu_alloc(struct regstat *current,int i)
1413 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1415 if(rs1[i]&&rs2[i]) {
1416 alloc_reg(current,i,rs1[i]);
1417 alloc_reg(current,i,rs2[i]);
1420 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1421 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1423 alloc_reg(current,i,rt1[i]);
1425 current->is32|=1LL<<rt1[i];
1427 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1429 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1431 alloc_reg64(current,i,rs1[i]);
1432 alloc_reg64(current,i,rs2[i]);
1433 alloc_reg(current,i,rt1[i]);
1435 alloc_reg(current,i,rs1[i]);
1436 alloc_reg(current,i,rs2[i]);
1437 alloc_reg(current,i,rt1[i]);
1440 current->is32|=1LL<<rt1[i];
1442 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1444 if(rs1[i]&&rs2[i]) {
1445 alloc_reg(current,i,rs1[i]);
1446 alloc_reg(current,i,rs2[i]);
1450 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1451 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1453 alloc_reg(current,i,rt1[i]);
1454 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1456 if(!((current->uu>>rt1[i])&1)) {
1457 alloc_reg64(current,i,rt1[i]);
1459 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1460 if(rs1[i]&&rs2[i]) {
1461 alloc_reg64(current,i,rs1[i]);
1462 alloc_reg64(current,i,rs2[i]);
1466 // Is is really worth it to keep 64-bit values in registers?
1468 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1469 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1473 current->is32&=~(1LL<<rt1[i]);
1475 current->is32|=1LL<<rt1[i];
1479 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1481 if(rs1[i]&&rs2[i]) {
1482 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1483 alloc_reg64(current,i,rs1[i]);
1484 alloc_reg64(current,i,rs2[i]);
1485 alloc_reg64(current,i,rt1[i]);
1487 alloc_reg(current,i,rs1[i]);
1488 alloc_reg(current,i,rs2[i]);
1489 alloc_reg(current,i,rt1[i]);
1493 alloc_reg(current,i,rt1[i]);
1494 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1495 // DADD used as move, or zeroing
1496 // If we have a 64-bit source, then make the target 64 bits too
1497 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1498 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1499 alloc_reg64(current,i,rt1[i]);
1500 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1501 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1502 alloc_reg64(current,i,rt1[i]);
1504 if(opcode2[i]>=0x2e&&rs2[i]) {
1505 // DSUB used as negation - 64-bit result
1506 // If we have a 32-bit register, extend it to 64 bits
1507 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1508 alloc_reg64(current,i,rt1[i]);
1512 if(rs1[i]&&rs2[i]) {
1513 current->is32&=~(1LL<<rt1[i]);
1515 current->is32&=~(1LL<<rt1[i]);
1516 if((current->is32>>rs1[i])&1)
1517 current->is32|=1LL<<rt1[i];
1519 current->is32&=~(1LL<<rt1[i]);
1520 if((current->is32>>rs2[i])&1)
1521 current->is32|=1LL<<rt1[i];
1523 current->is32|=1LL<<rt1[i];
1527 clear_const(current,rs1[i]);
1528 clear_const(current,rs2[i]);
1529 clear_const(current,rt1[i]);
1530 dirty_reg(current,rt1[i]);
1533 void imm16_alloc(struct regstat *current,int i)
1535 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1537 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1538 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1539 current->is32&=~(1LL<<rt1[i]);
1540 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1541 // TODO: Could preserve the 32-bit flag if the immediate is zero
1542 alloc_reg64(current,i,rt1[i]);
1543 alloc_reg64(current,i,rs1[i]);
1545 clear_const(current,rs1[i]);
1546 clear_const(current,rt1[i]);
1548 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1549 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1550 current->is32|=1LL<<rt1[i];
1551 clear_const(current,rs1[i]);
1552 clear_const(current,rt1[i]);
1554 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1555 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1556 if(rs1[i]!=rt1[i]) {
1557 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1558 alloc_reg64(current,i,rt1[i]);
1559 current->is32&=~(1LL<<rt1[i]);
1562 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1563 if(is_const(current,rs1[i])) {
1564 int v=get_const(current,rs1[i]);
1565 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1566 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1567 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1569 else clear_const(current,rt1[i]);
1571 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1572 if(is_const(current,rs1[i])) {
1573 int v=get_const(current,rs1[i]);
1574 set_const(current,rt1[i],v+imm[i]);
1576 else clear_const(current,rt1[i]);
1577 current->is32|=1LL<<rt1[i];
1580 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1581 current->is32|=1LL<<rt1[i];
1583 dirty_reg(current,rt1[i]);
1586 void load_alloc(struct regstat *current,int i)
1588 clear_const(current,rt1[i]);
1589 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1590 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1591 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1593 alloc_reg(current,i,rt1[i]);
1594 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1596 current->is32&=~(1LL<<rt1[i]);
1597 alloc_reg64(current,i,rt1[i]);
1599 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1601 current->is32&=~(1LL<<rt1[i]);
1602 alloc_reg64(current,i,rt1[i]);
1603 alloc_all(current,i);
1604 alloc_reg64(current,i,FTEMP);
1606 else current->is32|=1LL<<rt1[i];
1607 dirty_reg(current,rt1[i]);
1608 // If using TLB, need a register for pointer to the mapping table
1609 if(using_tlb) alloc_reg(current,i,TLREG);
1610 // LWL/LWR need a temporary register for the old value
1611 if(opcode[i]==0x22||opcode[i]==0x26)
1613 alloc_reg(current,i,FTEMP);
1614 alloc_reg_temp(current,i,-1);
1619 // Load to r0 (dummy load)
1620 // but we still need a register to calculate the address
1621 alloc_reg_temp(current,i,-1);
1625 void store_alloc(struct regstat *current,int i)
1627 clear_const(current,rs2[i]);
1628 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1629 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1630 alloc_reg(current,i,rs2[i]);
1631 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1632 alloc_reg64(current,i,rs2[i]);
1633 if(rs2[i]) alloc_reg(current,i,FTEMP);
1635 // If using TLB, need a register for pointer to the mapping table
1636 if(using_tlb) alloc_reg(current,i,TLREG);
1637 #if defined(HOST_IMM8)
1638 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1639 else alloc_reg(current,i,INVCP);
1641 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1642 alloc_reg(current,i,FTEMP);
1644 // We need a temporary register for address generation
1645 alloc_reg_temp(current,i,-1);
1648 void c1ls_alloc(struct regstat *current,int i)
1650 //clear_const(current,rs1[i]); // FIXME
1651 clear_const(current,rt1[i]);
1652 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1653 alloc_reg(current,i,CSREG); // Status
1654 alloc_reg(current,i,FTEMP);
1655 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1656 alloc_reg64(current,i,FTEMP);
1658 // If using TLB, need a register for pointer to the mapping table
1659 if(using_tlb) alloc_reg(current,i,TLREG);
1660 #if defined(HOST_IMM8)
1661 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1662 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1663 alloc_reg(current,i,INVCP);
1665 // We need a temporary register for address generation
1666 alloc_reg_temp(current,i,-1);
1669 void c2ls_alloc(struct regstat *current,int i)
1671 clear_const(current,rt1[i]);
1672 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1673 alloc_reg(current,i,FTEMP);
1674 // If using TLB, need a register for pointer to the mapping table
1675 if(using_tlb) alloc_reg(current,i,TLREG);
1676 #if defined(HOST_IMM8)
1677 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1678 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1679 alloc_reg(current,i,INVCP);
1681 // We need a temporary register for address generation
1682 alloc_reg_temp(current,i,-1);
1685 #ifndef multdiv_alloc
1686 void multdiv_alloc(struct regstat *current,int i)
1693 // case 0x1D: DMULTU
1696 clear_const(current,rs1[i]);
1697 clear_const(current,rs2[i]);
1700 if((opcode2[i]&4)==0) // 32-bit
1702 current->u&=~(1LL<<HIREG);
1703 current->u&=~(1LL<<LOREG);
1704 alloc_reg(current,i,HIREG);
1705 alloc_reg(current,i,LOREG);
1706 alloc_reg(current,i,rs1[i]);
1707 alloc_reg(current,i,rs2[i]);
1708 current->is32|=1LL<<HIREG;
1709 current->is32|=1LL<<LOREG;
1710 dirty_reg(current,HIREG);
1711 dirty_reg(current,LOREG);
1715 current->u&=~(1LL<<HIREG);
1716 current->u&=~(1LL<<LOREG);
1717 current->uu&=~(1LL<<HIREG);
1718 current->uu&=~(1LL<<LOREG);
1719 alloc_reg64(current,i,HIREG);
1720 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1721 alloc_reg64(current,i,rs1[i]);
1722 alloc_reg64(current,i,rs2[i]);
1723 alloc_all(current,i);
1724 current->is32&=~(1LL<<HIREG);
1725 current->is32&=~(1LL<<LOREG);
1726 dirty_reg(current,HIREG);
1727 dirty_reg(current,LOREG);
1732 // Multiply by zero is zero.
1733 // MIPS does not have a divide by zero exception.
1734 // The result is undefined, we return zero.
1735 alloc_reg(current,i,HIREG);
1736 alloc_reg(current,i,LOREG);
1737 current->is32|=1LL<<HIREG;
1738 current->is32|=1LL<<LOREG;
1739 dirty_reg(current,HIREG);
1740 dirty_reg(current,LOREG);
1745 void cop0_alloc(struct regstat *current,int i)
1747 if(opcode2[i]==0) // MFC0
1750 clear_const(current,rt1[i]);
1751 alloc_all(current,i);
1752 alloc_reg(current,i,rt1[i]);
1753 current->is32|=1LL<<rt1[i];
1754 dirty_reg(current,rt1[i]);
1757 else if(opcode2[i]==4) // MTC0
1760 clear_const(current,rs1[i]);
1761 alloc_reg(current,i,rs1[i]);
1762 alloc_all(current,i);
1765 alloc_all(current,i); // FIXME: Keep r0
1767 alloc_reg(current,i,0);
1772 // TLBR/TLBWI/TLBWR/TLBP/ERET
1773 assert(opcode2[i]==0x10);
1774 alloc_all(current,i);
1778 void cop1_alloc(struct regstat *current,int i)
1780 alloc_reg(current,i,CSREG); // Load status
1781 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1784 clear_const(current,rt1[i]);
1786 alloc_reg64(current,i,rt1[i]); // DMFC1
1787 current->is32&=~(1LL<<rt1[i]);
1789 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1790 current->is32|=1LL<<rt1[i];
1792 dirty_reg(current,rt1[i]);
1793 alloc_reg_temp(current,i,-1);
1795 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1798 clear_const(current,rs1[i]);
1800 alloc_reg64(current,i,rs1[i]); // DMTC1
1802 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1803 alloc_reg_temp(current,i,-1);
1807 alloc_reg(current,i,0);
1808 alloc_reg_temp(current,i,-1);
1812 void fconv_alloc(struct regstat *current,int i)
1814 alloc_reg(current,i,CSREG); // Load status
1815 alloc_reg_temp(current,i,-1);
1817 void float_alloc(struct regstat *current,int i)
1819 alloc_reg(current,i,CSREG); // Load status
1820 alloc_reg_temp(current,i,-1);
1822 void c2op_alloc(struct regstat *current,int i)
1824 alloc_reg_temp(current,i,-1);
1826 void fcomp_alloc(struct regstat *current,int i)
1828 alloc_reg(current,i,CSREG); // Load status
1829 alloc_reg(current,i,FSREG); // Load flags
1830 dirty_reg(current,FSREG); // Flag will be modified
1831 alloc_reg_temp(current,i,-1);
1834 void syscall_alloc(struct regstat *current,int i)
1836 alloc_cc(current,i);
1837 dirty_reg(current,CCREG);
1838 alloc_all(current,i);
1842 void delayslot_alloc(struct regstat *current,int i)
1853 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1854 printf("Disabled speculative precompilation\n");
1858 imm16_alloc(current,i);
1862 load_alloc(current,i);
1866 store_alloc(current,i);
1869 alu_alloc(current,i);
1872 shift_alloc(current,i);
1875 multdiv_alloc(current,i);
1878 shiftimm_alloc(current,i);
1881 mov_alloc(current,i);
1884 cop0_alloc(current,i);
1888 cop1_alloc(current,i);
1891 c1ls_alloc(current,i);
1894 c2ls_alloc(current,i);
1897 fconv_alloc(current,i);
1900 float_alloc(current,i);
1903 fcomp_alloc(current,i);
1906 c2op_alloc(current,i);
1911 // Special case where a branch and delay slot span two pages in virtual memory
1912 static void pagespan_alloc(struct regstat *current,int i)
1915 current->wasconst=0;
1917 alloc_all(current,i);
1918 alloc_cc(current,i);
1919 dirty_reg(current,CCREG);
1920 if(opcode[i]==3) // JAL
1922 alloc_reg(current,i,31);
1923 dirty_reg(current,31);
1925 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1927 alloc_reg(current,i,rs1[i]);
1929 alloc_reg(current,i,rt1[i]);
1930 dirty_reg(current,rt1[i]);
1933 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1935 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1936 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1937 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1939 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1940 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1944 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1946 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1947 if(!((current->is32>>rs1[i])&1))
1949 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1953 if(opcode[i]==0x11) // BC1
1955 alloc_reg(current,i,FSREG);
1956 alloc_reg(current,i,CSREG);
1961 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1963 stubs[stubcount][0]=type;
1964 stubs[stubcount][1]=addr;
1965 stubs[stubcount][2]=retaddr;
1966 stubs[stubcount][3]=a;
1967 stubs[stubcount][4]=b;
1968 stubs[stubcount][5]=c;
1969 stubs[stubcount][6]=d;
1970 stubs[stubcount][7]=e;
1974 // Write out a single register
1975 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1978 for(hr=0;hr<HOST_REGS;hr++) {
1979 if(hr!=EXCLUDE_REG) {
1980 if((regmap[hr]&63)==r) {
1983 emit_storereg(r,hr);
1985 if((is32>>regmap[hr])&1) {
1986 emit_sarimm(hr,31,hr);
1987 emit_storereg(r|64,hr);
1991 emit_storereg(r|64,hr);
2001 //if(!tracedebug) return 0;
2004 for(i=0;i<2097152;i++) {
2005 unsigned int temp=sum;
2008 sum^=((u_int *)rdram)[i];
2017 sum^=((u_int *)reg)[i];
2025 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2027 #ifndef DISABLE_COP1
2030 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2040 void memdebug(int i)
2042 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2043 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2046 //if(Count>=-2084597794) {
2047 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2049 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2050 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2051 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2054 printf("TRACE: %x\n",(&i)[-1]);
2058 printf("TRACE: %x \n",(&j)[10]);
2059 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2063 //printf("TRACE: %x\n",(&i)[-1]);
2066 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2068 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2071 void alu_assemble(int i,struct regstat *i_regs)
2073 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2075 signed char s1,s2,t;
2076 t=get_reg(i_regs->regmap,rt1[i]);
2078 s1=get_reg(i_regs->regmap,rs1[i]);
2079 s2=get_reg(i_regs->regmap,rs2[i]);
2080 if(rs1[i]&&rs2[i]) {
2083 if(opcode2[i]&2) emit_sub(s1,s2,t);
2084 else emit_add(s1,s2,t);
2087 if(s1>=0) emit_mov(s1,t);
2088 else emit_loadreg(rs1[i],t);
2092 if(opcode2[i]&2) emit_neg(s2,t);
2093 else emit_mov(s2,t);
2096 emit_loadreg(rs2[i],t);
2097 if(opcode2[i]&2) emit_neg(t,t);
2100 else emit_zeroreg(t);
2104 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2106 signed char s1l,s2l,s1h,s2h,tl,th;
2107 tl=get_reg(i_regs->regmap,rt1[i]);
2108 th=get_reg(i_regs->regmap,rt1[i]|64);
2110 s1l=get_reg(i_regs->regmap,rs1[i]);
2111 s2l=get_reg(i_regs->regmap,rs2[i]);
2112 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2113 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2114 if(rs1[i]&&rs2[i]) {
2117 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2118 else emit_adds(s1l,s2l,tl);
2120 #ifdef INVERTED_CARRY
2121 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2123 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2125 else emit_add(s1h,s2h,th);
2129 if(s1l>=0) emit_mov(s1l,tl);
2130 else emit_loadreg(rs1[i],tl);
2132 if(s1h>=0) emit_mov(s1h,th);
2133 else emit_loadreg(rs1[i]|64,th);
2138 if(opcode2[i]&2) emit_negs(s2l,tl);
2139 else emit_mov(s2l,tl);
2142 emit_loadreg(rs2[i],tl);
2143 if(opcode2[i]&2) emit_negs(tl,tl);
2146 #ifdef INVERTED_CARRY
2147 if(s2h>=0) emit_mov(s2h,th);
2148 else emit_loadreg(rs2[i]|64,th);
2150 emit_adcimm(-1,th); // x86 has inverted carry flag
2155 if(s2h>=0) emit_rscimm(s2h,0,th);
2157 emit_loadreg(rs2[i]|64,th);
2158 emit_rscimm(th,0,th);
2161 if(s2h>=0) emit_mov(s2h,th);
2162 else emit_loadreg(rs2[i]|64,th);
2169 if(th>=0) emit_zeroreg(th);
2174 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2176 signed char s1l,s1h,s2l,s2h,t;
2177 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2179 t=get_reg(i_regs->regmap,rt1[i]);
2182 s1l=get_reg(i_regs->regmap,rs1[i]);
2183 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2184 s2l=get_reg(i_regs->regmap,rs2[i]);
2185 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2186 if(rs2[i]==0) // rx<r0
2189 if(opcode2[i]==0x2a) // SLT
2190 emit_shrimm(s1h,31,t);
2191 else // SLTU (unsigned can not be less than zero)
2194 else if(rs1[i]==0) // r0<rx
2197 if(opcode2[i]==0x2a) // SLT
2198 emit_set_gz64_32(s2h,s2l,t);
2199 else // SLTU (set if not zero)
2200 emit_set_nz64_32(s2h,s2l,t);
2203 assert(s1l>=0);assert(s1h>=0);
2204 assert(s2l>=0);assert(s2h>=0);
2205 if(opcode2[i]==0x2a) // SLT
2206 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2208 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2212 t=get_reg(i_regs->regmap,rt1[i]);
2215 s1l=get_reg(i_regs->regmap,rs1[i]);
2216 s2l=get_reg(i_regs->regmap,rs2[i]);
2217 if(rs2[i]==0) // rx<r0
2220 if(opcode2[i]==0x2a) // SLT
2221 emit_shrimm(s1l,31,t);
2222 else // SLTU (unsigned can not be less than zero)
2225 else if(rs1[i]==0) // r0<rx
2228 if(opcode2[i]==0x2a) // SLT
2229 emit_set_gz32(s2l,t);
2230 else // SLTU (set if not zero)
2231 emit_set_nz32(s2l,t);
2234 assert(s1l>=0);assert(s2l>=0);
2235 if(opcode2[i]==0x2a) // SLT
2236 emit_set_if_less32(s1l,s2l,t);
2238 emit_set_if_carry32(s1l,s2l,t);
2244 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2246 signed char s1l,s1h,s2l,s2h,th,tl;
2247 tl=get_reg(i_regs->regmap,rt1[i]);
2248 th=get_reg(i_regs->regmap,rt1[i]|64);
2249 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2253 s1l=get_reg(i_regs->regmap,rs1[i]);
2254 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2255 s2l=get_reg(i_regs->regmap,rs2[i]);
2256 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2257 if(rs1[i]&&rs2[i]) {
2258 assert(s1l>=0);assert(s1h>=0);
2259 assert(s2l>=0);assert(s2h>=0);
2260 if(opcode2[i]==0x24) { // AND
2261 emit_and(s1l,s2l,tl);
2262 emit_and(s1h,s2h,th);
2264 if(opcode2[i]==0x25) { // OR
2265 emit_or(s1l,s2l,tl);
2266 emit_or(s1h,s2h,th);
2268 if(opcode2[i]==0x26) { // XOR
2269 emit_xor(s1l,s2l,tl);
2270 emit_xor(s1h,s2h,th);
2272 if(opcode2[i]==0x27) { // NOR
2273 emit_or(s1l,s2l,tl);
2274 emit_or(s1h,s2h,th);
2281 if(opcode2[i]==0x24) { // AND
2285 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2287 if(s1l>=0) emit_mov(s1l,tl);
2288 else emit_loadreg(rs1[i],tl);
2289 if(s1h>=0) emit_mov(s1h,th);
2290 else emit_loadreg(rs1[i]|64,th);
2294 if(s2l>=0) emit_mov(s2l,tl);
2295 else emit_loadreg(rs2[i],tl);
2296 if(s2h>=0) emit_mov(s2h,th);
2297 else emit_loadreg(rs2[i]|64,th);
2304 if(opcode2[i]==0x27) { // NOR
2306 if(s1l>=0) emit_not(s1l,tl);
2308 emit_loadreg(rs1[i],tl);
2311 if(s1h>=0) emit_not(s1h,th);
2313 emit_loadreg(rs1[i]|64,th);
2319 if(s2l>=0) emit_not(s2l,tl);
2321 emit_loadreg(rs2[i],tl);
2324 if(s2h>=0) emit_not(s2h,th);
2326 emit_loadreg(rs2[i]|64,th);
2342 s1l=get_reg(i_regs->regmap,rs1[i]);
2343 s2l=get_reg(i_regs->regmap,rs2[i]);
2344 if(rs1[i]&&rs2[i]) {
2347 if(opcode2[i]==0x24) { // AND
2348 emit_and(s1l,s2l,tl);
2350 if(opcode2[i]==0x25) { // OR
2351 emit_or(s1l,s2l,tl);
2353 if(opcode2[i]==0x26) { // XOR
2354 emit_xor(s1l,s2l,tl);
2356 if(opcode2[i]==0x27) { // NOR
2357 emit_or(s1l,s2l,tl);
2363 if(opcode2[i]==0x24) { // AND
2366 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2368 if(s1l>=0) emit_mov(s1l,tl);
2369 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2373 if(s2l>=0) emit_mov(s2l,tl);
2374 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2376 else emit_zeroreg(tl);
2378 if(opcode2[i]==0x27) { // NOR
2380 if(s1l>=0) emit_not(s1l,tl);
2382 emit_loadreg(rs1[i],tl);
2388 if(s2l>=0) emit_not(s2l,tl);
2390 emit_loadreg(rs2[i],tl);
2394 else emit_movimm(-1,tl);
2403 void imm16_assemble(int i,struct regstat *i_regs)
2405 if (opcode[i]==0x0f) { // LUI
2408 t=get_reg(i_regs->regmap,rt1[i]);
2411 if(!((i_regs->isconst>>t)&1))
2412 emit_movimm(imm[i]<<16,t);
2416 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2419 t=get_reg(i_regs->regmap,rt1[i]);
2420 s=get_reg(i_regs->regmap,rs1[i]);
2425 if(!((i_regs->isconst>>t)&1)) {
2427 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2428 emit_addimm(t,imm[i],t);
2430 if(!((i_regs->wasconst>>s)&1))
2431 emit_addimm(s,imm[i],t);
2433 emit_movimm(constmap[i][s]+imm[i],t);
2439 if(!((i_regs->isconst>>t)&1))
2440 emit_movimm(imm[i],t);
2445 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2447 signed char sh,sl,th,tl;
2448 th=get_reg(i_regs->regmap,rt1[i]|64);
2449 tl=get_reg(i_regs->regmap,rt1[i]);
2450 sh=get_reg(i_regs->regmap,rs1[i]|64);
2451 sl=get_reg(i_regs->regmap,rs1[i]);
2457 emit_addimm64_32(sh,sl,imm[i],th,tl);
2460 emit_addimm(sl,imm[i],tl);
2463 emit_movimm(imm[i],tl);
2464 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2469 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2471 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2472 signed char sh,sl,t;
2473 t=get_reg(i_regs->regmap,rt1[i]);
2474 sh=get_reg(i_regs->regmap,rs1[i]|64);
2475 sl=get_reg(i_regs->regmap,rs1[i]);
2479 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2480 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2481 if(opcode[i]==0x0a) { // SLTI
2483 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2484 emit_slti32(t,imm[i],t);
2486 emit_slti32(sl,imm[i],t);
2491 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2492 emit_sltiu32(t,imm[i],t);
2494 emit_sltiu32(sl,imm[i],t);
2499 if(opcode[i]==0x0a) // SLTI
2500 emit_slti64_32(sh,sl,imm[i],t);
2502 emit_sltiu64_32(sh,sl,imm[i],t);
2505 // SLTI(U) with r0 is just stupid,
2506 // nonetheless examples can be found
2507 if(opcode[i]==0x0a) // SLTI
2508 if(0<imm[i]) emit_movimm(1,t);
2509 else emit_zeroreg(t);
2512 if(imm[i]) emit_movimm(1,t);
2513 else emit_zeroreg(t);
2519 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2521 signed char sh,sl,th,tl;
2522 th=get_reg(i_regs->regmap,rt1[i]|64);
2523 tl=get_reg(i_regs->regmap,rt1[i]);
2524 sh=get_reg(i_regs->regmap,rs1[i]|64);
2525 sl=get_reg(i_regs->regmap,rs1[i]);
2526 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2527 if(opcode[i]==0x0c) //ANDI
2531 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2532 emit_andimm(tl,imm[i],tl);
2534 if(!((i_regs->wasconst>>sl)&1))
2535 emit_andimm(sl,imm[i],tl);
2537 emit_movimm(constmap[i][sl]&imm[i],tl);
2542 if(th>=0) emit_zeroreg(th);
2548 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2552 emit_loadreg(rs1[i]|64,th);
2557 if(opcode[i]==0x0d) //ORI
2559 emit_orimm(tl,imm[i],tl);
2561 if(!((i_regs->wasconst>>sl)&1))
2562 emit_orimm(sl,imm[i],tl);
2564 emit_movimm(constmap[i][sl]|imm[i],tl);
2566 if(opcode[i]==0x0e) //XORI
2568 emit_xorimm(tl,imm[i],tl);
2570 if(!((i_regs->wasconst>>sl)&1))
2571 emit_xorimm(sl,imm[i],tl);
2573 emit_movimm(constmap[i][sl]^imm[i],tl);
2577 emit_movimm(imm[i],tl);
2578 if(th>=0) emit_zeroreg(th);
2586 void shiftimm_assemble(int i,struct regstat *i_regs)
2588 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2592 t=get_reg(i_regs->regmap,rt1[i]);
2593 s=get_reg(i_regs->regmap,rs1[i]);
2602 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2604 if(opcode2[i]==0) // SLL
2606 emit_shlimm(s<0?t:s,imm[i],t);
2608 if(opcode2[i]==2) // SRL
2610 emit_shrimm(s<0?t:s,imm[i],t);
2612 if(opcode2[i]==3) // SRA
2614 emit_sarimm(s<0?t:s,imm[i],t);
2618 if(s>=0 && s!=t) emit_mov(s,t);
2622 //emit_storereg(rt1[i],t); //DEBUG
2625 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2628 signed char sh,sl,th,tl;
2629 th=get_reg(i_regs->regmap,rt1[i]|64);
2630 tl=get_reg(i_regs->regmap,rt1[i]);
2631 sh=get_reg(i_regs->regmap,rs1[i]|64);
2632 sl=get_reg(i_regs->regmap,rs1[i]);
2637 if(th>=0) emit_zeroreg(th);
2644 if(opcode2[i]==0x38) // DSLL
2646 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2647 emit_shlimm(sl,imm[i],tl);
2649 if(opcode2[i]==0x3a) // DSRL
2651 emit_shrdimm(sl,sh,imm[i],tl);
2652 if(th>=0) emit_shrimm(sh,imm[i],th);
2654 if(opcode2[i]==0x3b) // DSRA
2656 emit_shrdimm(sl,sh,imm[i],tl);
2657 if(th>=0) emit_sarimm(sh,imm[i],th);
2661 if(sl!=tl) emit_mov(sl,tl);
2662 if(th>=0&&sh!=th) emit_mov(sh,th);
2668 if(opcode2[i]==0x3c) // DSLL32
2671 signed char sl,tl,th;
2672 tl=get_reg(i_regs->regmap,rt1[i]);
2673 th=get_reg(i_regs->regmap,rt1[i]|64);
2674 sl=get_reg(i_regs->regmap,rs1[i]);
2683 emit_shlimm(th,imm[i]&31,th);
2688 if(opcode2[i]==0x3e) // DSRL32
2691 signed char sh,tl,th;
2692 tl=get_reg(i_regs->regmap,rt1[i]);
2693 th=get_reg(i_regs->regmap,rt1[i]|64);
2694 sh=get_reg(i_regs->regmap,rs1[i]|64);
2698 if(th>=0) emit_zeroreg(th);
2701 emit_shrimm(tl,imm[i]&31,tl);
2706 if(opcode2[i]==0x3f) // DSRA32
2710 tl=get_reg(i_regs->regmap,rt1[i]);
2711 sh=get_reg(i_regs->regmap,rs1[i]|64);
2717 emit_sarimm(tl,imm[i]&31,tl);
2724 #ifndef shift_assemble
2725 void shift_assemble(int i,struct regstat *i_regs)
2727 printf("Need shift_assemble for this architecture.\n");
2732 void load_assemble(int i,struct regstat *i_regs)
2734 int s,th,tl,addr,map=-1;
2737 int memtarget=0,c=0;
2739 th=get_reg(i_regs->regmap,rt1[i]|64);
2740 tl=get_reg(i_regs->regmap,rt1[i]);
2741 s=get_reg(i_regs->regmap,rs1[i]);
2743 for(hr=0;hr<HOST_REGS;hr++) {
2744 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2746 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2748 c=(i_regs->wasconst>>s)&1;
2749 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2750 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2752 //printf("load_assemble: c=%d\n",c);
2753 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2754 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2757 if(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) {
2758 // could be FIFO, must perform the read
2759 assem_debug("(forced read)\n");
2760 tl=get_reg(i_regs->regmap,-1);
2764 if(offset||s<0||c) addr=tl;
2771 if(th>=0) reglist&=~(1<<th);
2774 //#define R29_HACK 1
2776 // Strmnnrmn's speed hack
2777 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2780 emit_cmpimm(addr,RAM_SIZE);
2782 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2783 // Hint to branch predictor that the branch is unlikely to be taken
2785 emit_jno_unlikely(0);
2793 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2794 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2795 map=get_reg(i_regs->regmap,TLREG);
2797 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2798 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2800 if (opcode[i]==0x20) { // LB
2802 #ifdef HOST_IMM_ADDR32
2804 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2808 //emit_xorimm(addr,3,tl);
2809 //gen_tlb_addr_r(tl,map);
2810 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2812 #ifdef BIG_ENDIAN_MIPS
2813 if(!c) emit_xorimm(addr,3,tl);
2814 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2816 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2817 else if (tl!=addr) emit_mov(addr,tl);
2819 emit_movsbl_indexed_tlb(x,tl,map,tl);
2822 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2825 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2827 if (opcode[i]==0x21) { // LH
2829 #ifdef HOST_IMM_ADDR32
2831 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2836 #ifdef BIG_ENDIAN_MIPS
2837 if(!c) emit_xorimm(addr,2,tl);
2838 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2840 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2841 else if (tl!=addr) emit_mov(addr,tl);
2844 //emit_movswl_indexed_tlb(x,tl,map,tl);
2847 gen_tlb_addr_r(tl,map);
2848 emit_movswl_indexed(x,tl,tl);
2850 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2853 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2856 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2858 if (opcode[i]==0x23) { // LW
2860 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2861 #ifdef HOST_IMM_ADDR32
2863 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2866 emit_readword_indexed_tlb(0,addr,map,tl);
2868 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2871 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2873 if (opcode[i]==0x24) { // LBU
2875 #ifdef HOST_IMM_ADDR32
2877 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2881 //emit_xorimm(addr,3,tl);
2882 //gen_tlb_addr_r(tl,map);
2883 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2885 #ifdef BIG_ENDIAN_MIPS
2886 if(!c) emit_xorimm(addr,3,tl);
2887 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2889 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2890 else if (tl!=addr) emit_mov(addr,tl);
2892 emit_movzbl_indexed_tlb(x,tl,map,tl);
2895 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2898 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2900 if (opcode[i]==0x25) { // LHU
2902 #ifdef HOST_IMM_ADDR32
2904 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2909 #ifdef BIG_ENDIAN_MIPS
2910 if(!c) emit_xorimm(addr,2,tl);
2911 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2913 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2914 else if (tl!=addr) emit_mov(addr,tl);
2917 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2920 gen_tlb_addr_r(tl,map);
2921 emit_movzwl_indexed(x,tl,tl);
2923 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2925 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2929 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2931 if (opcode[i]==0x27) { // LWU
2934 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2935 #ifdef HOST_IMM_ADDR32
2937 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2940 emit_readword_indexed_tlb(0,addr,map,tl);
2942 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2945 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2949 if (opcode[i]==0x37) { // LD
2951 //gen_tlb_addr_r(tl,map);
2952 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2953 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2954 #ifdef HOST_IMM_ADDR32
2956 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2959 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2961 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2964 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2966 //emit_storereg(rt1[i],tl); // DEBUG
2968 //if(opcode[i]==0x23)
2969 //if(opcode[i]==0x24)
2970 //if(opcode[i]==0x23||opcode[i]==0x24)
2971 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2975 emit_readword((int)&last_count,ECX);
2977 if(get_reg(i_regs->regmap,CCREG)<0)
2978 emit_loadreg(CCREG,HOST_CCREG);
2979 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2980 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2981 emit_writeword(HOST_CCREG,(int)&Count);
2984 if(get_reg(i_regs->regmap,CCREG)<0)
2985 emit_loadreg(CCREG,0);
2987 emit_mov(HOST_CCREG,0);
2989 emit_addimm(0,2*ccadj[i],0);
2990 emit_writeword(0,(int)&Count);
2992 emit_call((int)memdebug);
2994 restore_regs(0x100f);
2998 #ifndef loadlr_assemble
2999 void loadlr_assemble(int i,struct regstat *i_regs)
3001 printf("Need loadlr_assemble for this architecture.\n");
3006 void store_assemble(int i,struct regstat *i_regs)
3011 int jaddr=0,jaddr2,type;
3012 int memtarget=0,c=0;
3013 int agr=AGEN1+(i&1);
3015 th=get_reg(i_regs->regmap,rs2[i]|64);
3016 tl=get_reg(i_regs->regmap,rs2[i]);
3017 s=get_reg(i_regs->regmap,rs1[i]);
3018 temp=get_reg(i_regs->regmap,agr);
3019 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3022 c=(i_regs->wasconst>>s)&1;
3023 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3024 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3028 for(hr=0;hr<HOST_REGS;hr++) {
3029 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3031 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3032 if(offset||s<0||c) addr=temp;
3037 // Strmnnrmn's speed hack
3039 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3041 emit_cmpimm(addr,RAM_SIZE);
3042 #ifdef DESTRUCTIVE_SHIFT
3043 if(s==addr) emit_mov(s,temp);
3046 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3050 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3051 // Hint to branch predictor that the branch is unlikely to be taken
3053 emit_jno_unlikely(0);
3061 if (opcode[i]==0x28) x=3; // SB
3062 if (opcode[i]==0x29) x=2; // SH
3063 map=get_reg(i_regs->regmap,TLREG);
3065 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3066 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3069 if (opcode[i]==0x28) { // SB
3072 #ifdef BIG_ENDIAN_MIPS
3073 if(!c) emit_xorimm(addr,3,temp);
3074 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3076 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3077 else if (addr!=temp) emit_mov(addr,temp);
3079 //gen_tlb_addr_w(temp,map);
3080 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3081 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3085 if (opcode[i]==0x29) { // SH
3088 #ifdef BIG_ENDIAN_MIPS
3089 if(!c) emit_xorimm(addr,2,temp);
3090 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3092 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3093 else if (addr!=temp) emit_mov(addr,temp);
3096 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3099 gen_tlb_addr_w(temp,map);
3100 emit_writehword_indexed(tl,x,temp);
3102 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3106 if (opcode[i]==0x2B) { // SW
3108 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3109 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3112 if (opcode[i]==0x3F) { // SD
3116 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3117 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3118 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3121 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3122 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3123 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3128 if(!using_tlb&&(!c||memtarget))
3129 // addr could be a temp, make sure it survives STORE*_STUB
3132 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3133 } else if(!memtarget) {
3134 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3138 #ifdef DESTRUCTIVE_SHIFT
3139 // The x86 shift operation is 'destructive'; it overwrites the
3140 // source register, so we need to make a copy first and use that.
3143 #if defined(HOST_IMM8)
3144 int ir=get_reg(i_regs->regmap,INVCP);
3146 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3148 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3152 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3155 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3156 //if(opcode[i]==0x2B || opcode[i]==0x28)
3157 //if(opcode[i]==0x2B || opcode[i]==0x29)
3158 //if(opcode[i]==0x2B)
3159 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3163 emit_readword((int)&last_count,ECX);
3165 if(get_reg(i_regs->regmap,CCREG)<0)
3166 emit_loadreg(CCREG,HOST_CCREG);
3167 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3168 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3169 emit_writeword(HOST_CCREG,(int)&Count);
3172 if(get_reg(i_regs->regmap,CCREG)<0)
3173 emit_loadreg(CCREG,0);
3175 emit_mov(HOST_CCREG,0);
3177 emit_addimm(0,2*ccadj[i],0);
3178 emit_writeword(0,(int)&Count);
3180 emit_call((int)memdebug);
3182 restore_regs(0x100f);
3186 void storelr_assemble(int i,struct regstat *i_regs)
3193 int case1,case2,case3;
3194 int done0,done1,done2;
3196 int agr=AGEN1+(i&1);
3198 th=get_reg(i_regs->regmap,rs2[i]|64);
3199 tl=get_reg(i_regs->regmap,rs2[i]);
3200 s=get_reg(i_regs->regmap,rs1[i]);
3201 temp=get_reg(i_regs->regmap,agr);
3202 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3205 c=(i_regs->isconst>>s)&1;
3206 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3207 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3210 for(hr=0;hr<HOST_REGS;hr++) {
3211 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3217 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3218 if(!offset&&s!=temp) emit_mov(s,temp);
3224 if(!memtarget||!rs1[i]) {
3229 if((u_int)rdram!=0x80000000)
3230 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3232 int map=get_reg(i_regs->regmap,TLREG);
3234 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3235 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3236 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3237 if(!jaddr&&!memtarget) {
3241 gen_tlb_addr_w(temp,map);
3244 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3245 temp2=get_reg(i_regs->regmap,FTEMP);
3246 if(!rs2[i]) temp2=th=tl;
3249 #ifndef BIG_ENDIAN_MIPS
3250 emit_xorimm(temp,3,temp);
3252 emit_testimm(temp,2);
3255 emit_testimm(temp,1);
3259 if (opcode[i]==0x2A) { // SWL
3260 emit_writeword_indexed(tl,0,temp);
3262 if (opcode[i]==0x2E) { // SWR
3263 emit_writebyte_indexed(tl,3,temp);
3265 if (opcode[i]==0x2C) { // SDL
3266 emit_writeword_indexed(th,0,temp);
3267 if(rs2[i]) emit_mov(tl,temp2);
3269 if (opcode[i]==0x2D) { // SDR
3270 emit_writebyte_indexed(tl,3,temp);
3271 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3276 set_jump_target(case1,(int)out);
3277 if (opcode[i]==0x2A) { // SWL
3278 // Write 3 msb into three least significant bytes
3279 if(rs2[i]) emit_rorimm(tl,8,tl);
3280 emit_writehword_indexed(tl,-1,temp);
3281 if(rs2[i]) emit_rorimm(tl,16,tl);
3282 emit_writebyte_indexed(tl,1,temp);
3283 if(rs2[i]) emit_rorimm(tl,8,tl);
3285 if (opcode[i]==0x2E) { // SWR
3286 // Write two lsb into two most significant bytes
3287 emit_writehword_indexed(tl,1,temp);
3289 if (opcode[i]==0x2C) { // SDL
3290 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3291 // Write 3 msb into three least significant bytes
3292 if(rs2[i]) emit_rorimm(th,8,th);
3293 emit_writehword_indexed(th,-1,temp);
3294 if(rs2[i]) emit_rorimm(th,16,th);
3295 emit_writebyte_indexed(th,1,temp);
3296 if(rs2[i]) emit_rorimm(th,8,th);
3298 if (opcode[i]==0x2D) { // SDR
3299 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3300 // Write two lsb into two most significant bytes
3301 emit_writehword_indexed(tl,1,temp);
3306 set_jump_target(case2,(int)out);
3307 emit_testimm(temp,1);
3310 if (opcode[i]==0x2A) { // SWL
3311 // Write two msb into two least significant bytes
3312 if(rs2[i]) emit_rorimm(tl,16,tl);
3313 emit_writehword_indexed(tl,-2,temp);
3314 if(rs2[i]) emit_rorimm(tl,16,tl);
3316 if (opcode[i]==0x2E) { // SWR
3317 // Write 3 lsb into three most significant bytes
3318 emit_writebyte_indexed(tl,-1,temp);
3319 if(rs2[i]) emit_rorimm(tl,8,tl);
3320 emit_writehword_indexed(tl,0,temp);
3321 if(rs2[i]) emit_rorimm(tl,24,tl);
3323 if (opcode[i]==0x2C) { // SDL
3324 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3325 // Write two msb into two least significant bytes
3326 if(rs2[i]) emit_rorimm(th,16,th);
3327 emit_writehword_indexed(th,-2,temp);
3328 if(rs2[i]) emit_rorimm(th,16,th);
3330 if (opcode[i]==0x2D) { // SDR
3331 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3332 // Write 3 lsb into three most significant bytes
3333 emit_writebyte_indexed(tl,-1,temp);
3334 if(rs2[i]) emit_rorimm(tl,8,tl);
3335 emit_writehword_indexed(tl,0,temp);
3336 if(rs2[i]) emit_rorimm(tl,24,tl);
3341 set_jump_target(case3,(int)out);
3342 if (opcode[i]==0x2A) { // SWL
3343 // Write msb into least significant byte
3344 if(rs2[i]) emit_rorimm(tl,24,tl);
3345 emit_writebyte_indexed(tl,-3,temp);
3346 if(rs2[i]) emit_rorimm(tl,8,tl);
3348 if (opcode[i]==0x2E) { // SWR
3349 // Write entire word
3350 emit_writeword_indexed(tl,-3,temp);
3352 if (opcode[i]==0x2C) { // SDL
3353 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3354 // Write msb into least significant byte
3355 if(rs2[i]) emit_rorimm(th,24,th);
3356 emit_writebyte_indexed(th,-3,temp);
3357 if(rs2[i]) emit_rorimm(th,8,th);
3359 if (opcode[i]==0x2D) { // SDR
3360 if(rs2[i]) emit_mov(th,temp2);
3361 // Write entire word
3362 emit_writeword_indexed(tl,-3,temp);
3364 set_jump_target(done0,(int)out);
3365 set_jump_target(done1,(int)out);
3366 set_jump_target(done2,(int)out);
3367 if (opcode[i]==0x2C) { // SDL
3368 emit_testimm(temp,4);
3371 emit_andimm(temp,~3,temp);
3372 emit_writeword_indexed(temp2,4,temp);
3373 set_jump_target(done0,(int)out);
3375 if (opcode[i]==0x2D) { // SDR
3376 emit_testimm(temp,4);
3379 emit_andimm(temp,~3,temp);
3380 emit_writeword_indexed(temp2,-4,temp);
3381 set_jump_target(done0,(int)out);
3384 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3387 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3388 #if defined(HOST_IMM8)
3389 int ir=get_reg(i_regs->regmap,INVCP);
3391 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3393 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3397 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3401 //save_regs(0x100f);
3402 emit_readword((int)&last_count,ECX);
3403 if(get_reg(i_regs->regmap,CCREG)<0)
3404 emit_loadreg(CCREG,HOST_CCREG);
3405 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3406 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3407 emit_writeword(HOST_CCREG,(int)&Count);
3408 emit_call((int)memdebug);
3410 //restore_regs(0x100f);
3414 void c1ls_assemble(int i,struct regstat *i_regs)
3416 #ifndef DISABLE_COP1
3422 int jaddr,jaddr2=0,jaddr3,type;
3423 int agr=AGEN1+(i&1);
3425 th=get_reg(i_regs->regmap,FTEMP|64);
3426 tl=get_reg(i_regs->regmap,FTEMP);
3427 s=get_reg(i_regs->regmap,rs1[i]);
3428 temp=get_reg(i_regs->regmap,agr);
3429 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3434 for(hr=0;hr<HOST_REGS;hr++) {
3435 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3437 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3438 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3440 // Loads use a temporary register which we need to save
3443 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3447 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3448 //else c=(i_regs->wasconst>>s)&1;
3449 if(s>=0) c=(i_regs->wasconst>>s)&1;
3450 // Check cop1 unusable
3452 signed char rs=get_reg(i_regs->regmap,CSREG);
3454 emit_testimm(rs,0x20000000);
3457 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3460 if (opcode[i]==0x39) { // SWC1 (get float address)
3461 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3463 if (opcode[i]==0x3D) { // SDC1 (get double address)
3464 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3466 // Generate address + offset
3469 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3473 map=get_reg(i_regs->regmap,TLREG);
3475 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3476 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3478 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3479 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3482 if (opcode[i]==0x39) { // SWC1 (read float)
3483 emit_readword_indexed(0,tl,tl);
3485 if (opcode[i]==0x3D) { // SDC1 (read double)
3486 emit_readword_indexed(4,tl,th);
3487 emit_readword_indexed(0,tl,tl);
3489 if (opcode[i]==0x31) { // LWC1 (get target address)
3490 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3492 if (opcode[i]==0x35) { // LDC1 (get target address)
3493 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3500 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3502 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3504 #ifdef DESTRUCTIVE_SHIFT
3505 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3506 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3510 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3511 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3513 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3514 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3517 if (opcode[i]==0x31) { // LWC1
3518 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3519 //gen_tlb_addr_r(ar,map);
3520 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3521 #ifdef HOST_IMM_ADDR32
3522 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3525 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3528 if (opcode[i]==0x35) { // LDC1
3530 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3531 //gen_tlb_addr_r(ar,map);
3532 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3533 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3534 #ifdef HOST_IMM_ADDR32
3535 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3538 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3541 if (opcode[i]==0x39) { // SWC1
3542 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3543 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3546 if (opcode[i]==0x3D) { // SDC1
3548 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3549 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3550 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3554 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3555 #ifndef DESTRUCTIVE_SHIFT
3556 temp=offset||c||s<0?ar:s;
3558 #if defined(HOST_IMM8)
3559 int ir=get_reg(i_regs->regmap,INVCP);
3561 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3563 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3567 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3570 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3571 if (opcode[i]==0x31) { // LWC1 (write float)
3572 emit_writeword_indexed(tl,0,temp);
3574 if (opcode[i]==0x35) { // LDC1 (write double)
3575 emit_writeword_indexed(th,4,temp);
3576 emit_writeword_indexed(tl,0,temp);
3578 //if(opcode[i]==0x39)
3579 /*if(opcode[i]==0x39||opcode[i]==0x31)
3582 emit_readword((int)&last_count,ECX);
3583 if(get_reg(i_regs->regmap,CCREG)<0)
3584 emit_loadreg(CCREG,HOST_CCREG);
3585 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3586 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3587 emit_writeword(HOST_CCREG,(int)&Count);
3588 emit_call((int)memdebug);
3592 cop1_unusable(i, i_regs);
3596 void c2ls_assemble(int i,struct regstat *i_regs)
3601 int memtarget=0,c=0;
3602 int jaddr,jaddr2=0,jaddr3,type;
3603 int agr=AGEN1+(i&1);
3605 u_int copr=(source[i]>>16)&0x1f;
3606 s=get_reg(i_regs->regmap,rs1[i]);
3607 tl=get_reg(i_regs->regmap,FTEMP);
3613 for(hr=0;hr<HOST_REGS;hr++) {
3614 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3616 if(i_regs->regmap[HOST_CCREG]==CCREG)
3617 reglist&=~(1<<HOST_CCREG);
3620 if (opcode[i]==0x3a) { // SWC2
3621 ar=get_reg(i_regs->regmap,agr);
3622 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3627 if(s>=0) c=(i_regs->wasconst>>s)&1;
3628 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3629 if (!offset&&!c&&s>=0) ar=s;
3632 if (opcode[i]==0x3a) { // SWC2
3633 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3641 emit_jmp(0); // inline_readstub/inline_writestub?
3645 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3649 if (opcode[i]==0x32) { // LWC2
3650 #ifdef HOST_IMM_ADDR32
3651 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3654 emit_readword_indexed(0,ar,tl);
3656 if (opcode[i]==0x3a) { // SWC2
3657 #ifdef DESTRUCTIVE_SHIFT
3658 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3660 emit_writeword_indexed(tl,0,ar);
3664 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3665 if (opcode[i]==0x3a) { // SWC2
3666 #if defined(HOST_IMM8)
3667 int ir=get_reg(i_regs->regmap,INVCP);
3669 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3671 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3675 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3677 if (opcode[i]==0x32) { // LWC2
3678 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3682 #ifndef multdiv_assemble
3683 void multdiv_assemble(int i,struct regstat *i_regs)
3685 printf("Need multdiv_assemble for this architecture.\n");
3690 void mov_assemble(int i,struct regstat *i_regs)
3692 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3693 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3696 signed char sh,sl,th,tl;
3697 th=get_reg(i_regs->regmap,rt1[i]|64);
3698 tl=get_reg(i_regs->regmap,rt1[i]);
3701 sh=get_reg(i_regs->regmap,rs1[i]|64);
3702 sl=get_reg(i_regs->regmap,rs1[i]);
3703 if(sl>=0) emit_mov(sl,tl);
3704 else emit_loadreg(rs1[i],tl);
3706 if(sh>=0) emit_mov(sh,th);
3707 else emit_loadreg(rs1[i]|64,th);
3713 #ifndef fconv_assemble
3714 void fconv_assemble(int i,struct regstat *i_regs)
3716 printf("Need fconv_assemble for this architecture.\n");
3722 void float_assemble(int i,struct regstat *i_regs)
3724 printf("Need float_assemble for this architecture.\n");
3729 void syscall_assemble(int i,struct regstat *i_regs)
3731 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3732 assert(ccreg==HOST_CCREG);
3733 assert(!is_delayslot);
3734 emit_movimm(start+i*4,EAX); // Get PC
3735 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3736 emit_jmp((int)jump_syscall_hle); // XXX
3739 void hlecall_assemble(int i,struct regstat *i_regs)
3741 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3742 assert(ccreg==HOST_CCREG);
3743 assert(!is_delayslot);
3744 emit_movimm(start+i*4+4,0); // Get PC
3745 emit_movimm((int)psxHLEt[source[i]&7],1);
3746 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3747 emit_jmp((int)jump_hlecall);
3750 void ds_assemble(int i,struct regstat *i_regs)
3755 alu_assemble(i,i_regs);break;
3757 imm16_assemble(i,i_regs);break;
3759 shift_assemble(i,i_regs);break;
3761 shiftimm_assemble(i,i_regs);break;
3763 load_assemble(i,i_regs);break;
3765 loadlr_assemble(i,i_regs);break;
3767 store_assemble(i,i_regs);break;
3769 storelr_assemble(i,i_regs);break;
3771 cop0_assemble(i,i_regs);break;
3773 cop1_assemble(i,i_regs);break;
3775 c1ls_assemble(i,i_regs);break;
3777 cop2_assemble(i,i_regs);break;
3779 c2ls_assemble(i,i_regs);break;
3781 c2op_assemble(i,i_regs);break;
3783 fconv_assemble(i,i_regs);break;
3785 float_assemble(i,i_regs);break;
3787 fcomp_assemble(i,i_regs);break;
3789 multdiv_assemble(i,i_regs);break;
3791 mov_assemble(i,i_regs);break;
3800 printf("Jump in the delay slot. This is probably a bug.\n");
3805 // Is the branch target a valid internal jump?
3806 int internal_branch(uint64_t i_is32,int addr)
3808 if(addr&1) return 0; // Indirect (register) jump
3809 if(addr>=start && addr<start+slen*4-4)
3811 int t=(addr-start)>>2;
3812 // Delay slots are not valid branch targets
3813 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3814 // 64 -> 32 bit transition requires a recompile
3815 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3817 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3818 else printf("optimizable: yes\n");
3820 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3821 if(requires_32bit[t]&~i_is32) return 0;
3827 #ifndef wb_invalidate
3828 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3829 uint64_t u,uint64_t uu)
3832 for(hr=0;hr<HOST_REGS;hr++) {
3833 if(hr!=EXCLUDE_REG) {
3834 if(pre[hr]!=entry[hr]) {
3837 if(get_reg(entry,pre[hr])<0) {
3839 if(!((u>>pre[hr])&1)) {
3840 emit_storereg(pre[hr],hr);
3841 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3842 emit_sarimm(hr,31,hr);
3843 emit_storereg(pre[hr]|64,hr);
3847 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3848 emit_storereg(pre[hr],hr);
3857 // Move from one register to another (no writeback)
3858 for(hr=0;hr<HOST_REGS;hr++) {
3859 if(hr!=EXCLUDE_REG) {
3860 if(pre[hr]!=entry[hr]) {
3861 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3863 if((nr=get_reg(entry,pre[hr]))>=0) {
3873 // Load the specified registers
3874 // This only loads the registers given as arguments because
3875 // we don't want to load things that will be overwritten
3876 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3880 for(hr=0;hr<HOST_REGS;hr++) {
3881 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3882 if(entry[hr]!=regmap[hr]) {
3883 if(regmap[hr]==rs1||regmap[hr]==rs2)
3890 emit_loadreg(regmap[hr],hr);
3897 for(hr=0;hr<HOST_REGS;hr++) {
3898 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3899 if(entry[hr]!=regmap[hr]) {
3900 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3902 assert(regmap[hr]!=64);
3903 if((is32>>(regmap[hr]&63))&1) {
3904 int lr=get_reg(regmap,regmap[hr]-64);
3906 emit_sarimm(lr,31,hr);
3908 emit_loadreg(regmap[hr],hr);
3912 emit_loadreg(regmap[hr],hr);
3920 // Load registers prior to the start of a loop
3921 // so that they are not loaded within the loop
3922 static void loop_preload(signed char pre[],signed char entry[])
3925 for(hr=0;hr<HOST_REGS;hr++) {
3926 if(hr!=EXCLUDE_REG) {
3927 if(pre[hr]!=entry[hr]) {
3929 if(get_reg(pre,entry[hr])<0) {
3930 assem_debug("loop preload:\n");
3931 //printf("loop preload: %d\n",hr);
3935 else if(entry[hr]<TEMPREG)
3937 emit_loadreg(entry[hr],hr);
3939 else if(entry[hr]-64<TEMPREG)
3941 emit_loadreg(entry[hr],hr);
3950 // Generate address for load/store instruction
3951 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3952 void address_generation(int i,struct regstat *i_regs,signed char entry[])