1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
33 #include "new_dynarec_config.h"
34 #include "../psxhle.h"
35 #include "../psxinterpreter.h"
37 #include "emu_if.h" // emulator interface
39 #define noinline __attribute__((noinline,noclone))
41 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
44 #define min(a, b) ((b) < (a) ? (b) : (a))
47 #define max(a, b) ((b) > (a) ? (b) : (a))
52 //#define REG_ALLOC_PRINT
55 #define assem_debug printf
57 #define assem_debug(...)
59 //#define inv_debug printf
60 #define inv_debug(...)
63 #include "assem_x86.h"
66 #include "assem_x64.h"
69 #include "assem_arm.h"
72 #include "assem_arm64.h"
75 #define RAM_SIZE 0x200000
77 #define MAX_OUTPUT_BLOCK_SIZE 262144
80 // apparently Vita has a 16MB limit, so either we cut tc in half,
81 // or use this hack (it's a hack because tc size was designed to be power-of-2)
82 #define TC_REDUCE_BYTES 4096
84 #define TC_REDUCE_BYTES 0
89 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
92 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
93 const void *f[2048 / sizeof(void *)];
97 #ifdef BASE_ADDR_DYNAMIC
98 static struct ndrc_mem *ndrc;
100 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
101 static struct ndrc_mem *ndrc = &ndrc_;
122 // regmap_pre[i] - regs before [i] insn starts; dirty things here that
123 // don't match .regmap will be written back
124 // [i].regmap_entry - regs that must be set up if someone jumps here
125 // [i].regmap - regs [i] insn will read/(over)write
128 signed char regmap_entry[HOST_REGS];
129 signed char regmap[HOST_REGS];
133 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
134 u_int isconst; // ... but isconst is false when r2 is known
135 u_int loadedconst; // host regs that have constants loaded
136 u_int waswritten; // MIPS regs that were used as store base before
139 // note: asm depends on this layout
145 struct ll_entry *next;
173 static struct decoded_insn
194 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
195 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
196 struct ll_entry *jump_dirty[4096];
198 static struct ll_entry *jump_out[4096];
200 static u_int *source;
201 static char insn[MAXBLOCK][10];
202 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
203 static uint64_t gte_rt[MAXBLOCK];
204 static uint64_t gte_unneeded[MAXBLOCK];
205 static u_int smrv[32]; // speculated MIPS register values
206 static u_int smrv_strong; // mask or regs that are likely to have correct values
207 static u_int smrv_weak; // same, but somewhat less likely
208 static u_int smrv_strong_next; // same, but after current insn executes
209 static u_int smrv_weak_next;
210 static int imm[MAXBLOCK];
211 static u_int ba[MAXBLOCK];
212 static uint64_t unneeded_reg[MAXBLOCK];
213 static uint64_t branch_unneeded_reg[MAXBLOCK];
214 // see 'struct regstat' for a description
215 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
216 // contains 'real' consts at [i] insn, but may differ from what's actually
217 // loaded in host reg as 'final' value is always loaded, see get_final_value()
218 static uint32_t current_constmap[HOST_REGS];
219 static uint32_t constmap[MAXBLOCK][HOST_REGS];
220 static struct regstat regs[MAXBLOCK];
221 static struct regstat branch_regs[MAXBLOCK];
222 static signed char minimum_free_regs[MAXBLOCK];
223 static u_int needed_reg[MAXBLOCK];
224 static u_int wont_dirty[MAXBLOCK];
225 static u_int will_dirty[MAXBLOCK];
226 static int ccadj[MAXBLOCK];
228 static void *instr_addr[MAXBLOCK];
229 static struct link_entry link_addr[MAXBLOCK];
230 static int linkcount;
231 static struct code_stub stubs[MAXBLOCK*3];
232 static int stubcount;
233 static u_int literals[1024][2];
234 static int literalcount;
235 static int is_delayslot;
236 static char shadow[1048576] __attribute__((aligned(16)));
239 static u_int stop_after_jal;
240 static u_int f1_hack;
242 int new_dynarec_hacks;
243 int new_dynarec_hacks_pergame;
244 int new_dynarec_hacks_old;
245 int new_dynarec_did_compile;
247 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
249 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
250 extern int last_count; // last absolute target, often = next_interupt
252 extern int pending_exception;
253 extern int branch_target;
254 extern uintptr_t ram_offset;
255 extern uintptr_t mini_ht[32][2];
256 extern u_char restore_candidate[512];
258 /* registers that may be allocated */
260 #define LOREG 32 // lo
261 #define HIREG 33 // hi
262 //#define FSREG 34 // FPU status (FCSR)
263 #define CSREG 35 // Coprocessor status
264 #define CCREG 36 // Cycle count
265 #define INVCP 37 // Pointer to invalid_code
266 //#define MMREG 38 // Pointer to memory_map
267 #define ROREG 39 // ram offset (if rdram!=0x80000000)
269 #define FTEMP 40 // FPU temporary register
270 #define PTEMP 41 // Prefetch temporary register
271 //#define TLREG 42 // TLB mapping offset
272 #define RHASH 43 // Return address hash
273 #define RHTBL 44 // Return address hash table address
274 #define RTEMP 45 // JR/JALR address register
276 #define AGEN1 46 // Address generation temporary register
277 //#define AGEN2 47 // Address generation temporary register
278 //#define MGEN1 48 // Maptable address generation temporary register
279 //#define MGEN2 49 // Maptable address generation temporary register
280 #define BTREG 50 // Branch target temporary register
282 /* instruction types */
283 #define NOP 0 // No operation
284 #define LOAD 1 // Load
285 #define STORE 2 // Store
286 #define LOADLR 3 // Unaligned load
287 #define STORELR 4 // Unaligned store
288 #define MOV 5 // Move
289 #define ALU 6 // Arithmetic/logic
290 #define MULTDIV 7 // Multiply/divide
291 #define SHIFT 8 // Shift by register
292 #define SHIFTIMM 9// Shift by immediate
293 #define IMM16 10 // 16-bit immediate
294 #define RJUMP 11 // Unconditional jump to register
295 #define UJUMP 12 // Unconditional jump
296 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
297 #define SJUMP 14 // Conditional branch (regimm format)
298 #define COP0 15 // Coprocessor 0
299 #define COP1 16 // Coprocessor 1
300 #define C1LS 17 // Coprocessor 1 load/store
301 //#define FJUMP 18 // Conditional branch (floating point)
302 //#define FLOAT 19 // Floating point unit
303 //#define FCONV 20 // Convert integer to float
304 //#define FCOMP 21 // Floating point compare (sets FSREG)
305 #define SYSCALL 22// SYSCALL,BREAK
306 #define OTHER 23 // Other
307 #define SPAN 24 // Branch/delay slot spans 2 pages
308 #define NI 25 // Not implemented
309 #define HLECALL 26// PCSX fake opcodes for HLE
310 #define COP2 27 // Coprocessor 2 move
311 #define C2LS 28 // Coprocessor 2 load/store
312 #define C2OP 29 // Coprocessor 2 operation
313 #define INTCALL 30// Call interpreter to handle rare corner cases
320 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
321 #define DJT_2 (void *)2l
324 int new_recompile_block(u_int addr);
325 void *get_addr_ht(u_int vaddr);
326 void invalidate_block(u_int block);
327 void invalidate_addr(u_int addr);
328 void remove_hash(int vaddr);
330 void dyna_linker_ds();
332 void verify_code_ds();
335 void fp_exception_ds();
336 void jump_syscall (u_int u0, u_int u1, u_int pc);
337 void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
338 void jump_break (u_int u0, u_int u1, u_int pc);
339 void jump_break_ds(u_int u0, u_int u1, u_int pc);
340 void jump_to_new_pc();
341 void call_gteStall();
342 void new_dyna_leave();
344 // Needed by assembler
345 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
346 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
347 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
348 static void load_all_regs(const signed char i_regmap[]);
349 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
350 static void load_regs_entry(int t);
351 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
352 static u_int get_host_reglist(const signed char *regmap);
354 static int verify_dirty(const u_int *ptr);
355 static int get_final_value(int hr, int i, int *value);
356 static void add_stub(enum stub_type type, void *addr, void *retaddr,
357 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
358 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
359 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
360 static void add_to_linker(void *addr, u_int target, int ext);
361 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
362 int addr, int *offset_reg, int *addr_reg_override);
363 static void *get_direct_memhandler(void *table, u_int addr,
364 enum stub_type type, uintptr_t *addr_host);
365 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
366 static void pass_args(int a0, int a1);
367 static void emit_far_jump(const void *f);
368 static void emit_far_call(const void *f);
371 #include <psp2/kernel/sysmem.h>
373 // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
374 extern int getVMBlock();
375 int _newlib_vm_size_user = sizeof(*ndrc);
378 static void mprotect_w_x(void *start, void *end, int is_x)
382 // *Open* enables write on all memory that was
383 // allocated by sceKernelAllocMemBlockForVM()?
385 sceKernelCloseVMDomain();
387 sceKernelOpenVMDomain();
389 u_long mstart = (u_long)start & ~4095ul;
390 u_long mend = (u_long)end;
391 if (mprotect((void *)mstart, mend - mstart,
392 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
393 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
398 static void start_tcache_write(void *start, void *end)
400 mprotect_w_x(start, end, 0);
403 static void end_tcache_write(void *start, void *end)
405 #if defined(__arm__) || defined(__aarch64__)
406 size_t len = (char *)end - (char *)start;
407 #if defined(__BLACKBERRY_QNX__)
408 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
409 #elif defined(__MACH__)
410 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
412 sceKernelSyncVMDomain(sceBlock, start, len);
414 ctr_flush_invalidate_cache();
415 #elif defined(__aarch64__)
416 // as of 2021, __clear_cache() is still broken on arm64
417 // so here is a custom one :(
418 clear_cache_arm64(start, end);
420 __clear_cache(start, end);
425 mprotect_w_x(start, end, 1);
428 static void *start_block(void)
430 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
431 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
432 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
433 start_tcache_write(out, end);
437 static void end_block(void *start)
439 end_tcache_write(start, out);
442 // also takes care of w^x mappings when patching code
443 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
445 static void mark_clear_cache(void *target)
447 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
448 u_int mask = 1u << ((offset >> 12) & 31);
449 if (!(needs_clear_cache[offset >> 17] & mask)) {
450 char *start = (char *)((uintptr_t)target & ~4095l);
451 start_tcache_write(start, start + 4095);
452 needs_clear_cache[offset >> 17] |= mask;
456 // Clearing the cache is rather slow on ARM Linux, so mark the areas
457 // that need to be cleared, and then only clear these areas once.
458 static void do_clear_cache(void)
461 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
463 u_int bitmap = needs_clear_cache[i];
466 for (j = 0; j < 32; j++)
469 if (!(bitmap & (1<<j)))
472 start = ndrc->translation_cache + i*131072 + j*4096;
474 for (j++; j < 32; j++) {
475 if (!(bitmap & (1<<j)))
479 end_tcache_write(start, end);
481 needs_clear_cache[i] = 0;
485 //#define DEBUG_CYCLE_COUNT 1
487 #define NO_CYCLE_PENALTY_THR 12
489 int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
490 int cycle_multiplier_override;
491 int cycle_multiplier_old;
492 static int cycle_multiplier_active;
494 static int CLOCK_ADJUST(int x)
496 int m = cycle_multiplier_active;
497 int s = (x >> 31) | 1;
498 return (x * m + s * 50) / 100;
501 static int ds_writes_rjump_rs(int i)
503 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
506 static u_int get_page(u_int vaddr)
508 u_int page=vaddr&~0xe0000000;
509 if (page < 0x1000000)
510 page &= ~0x0e00000; // RAM mirrors
512 if(page>2048) page=2048+(page&2047);
516 // no virtual mem in PCSX
517 static u_int get_vpage(u_int vaddr)
519 return get_page(vaddr);
522 static struct ht_entry *hash_table_get(u_int vaddr)
524 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
527 static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
529 ht_bin->vaddr[1] = ht_bin->vaddr[0];
530 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
531 ht_bin->vaddr[0] = vaddr;
532 ht_bin->tcaddr[0] = tcaddr;
535 // some messy ari64's code, seems to rely on unsigned 32bit overflow
536 static int doesnt_expire_soon(void *tcaddr)
538 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
539 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
542 // Get address from virtual address
543 // This is called from the recompiled JR/JALR instructions
544 void noinline *get_addr(u_int vaddr)
546 u_int page=get_page(vaddr);
547 u_int vpage=get_vpage(vaddr);
548 struct ll_entry *head;
549 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
552 if(head->vaddr==vaddr) {
553 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
554 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
559 head=jump_dirty[vpage];
561 if(head->vaddr==vaddr) {
562 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
563 // Don't restore blocks which are about to expire from the cache
564 if (doesnt_expire_soon(head->addr))
565 if (verify_dirty(head->addr)) {
566 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
567 invalid_code[vaddr>>12]=0;
568 inv_code_start=inv_code_end=~0;
570 restore_candidate[vpage>>3]|=1<<(vpage&7);
572 else restore_candidate[page>>3]|=1<<(page&7);
573 struct ht_entry *ht_bin = hash_table_get(vaddr);
574 if (ht_bin->vaddr[0] == vaddr)
575 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
577 hash_table_add(ht_bin, vaddr, head->addr);
584 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
585 int r=new_recompile_block(vaddr);
586 if(r==0) return get_addr(vaddr);
587 // Execute in unmapped page, generate pagefault execption
589 Cause=(vaddr<<31)|0x8;
590 EPC=(vaddr&1)?vaddr-5:vaddr;
592 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
593 EntryHi=BadVAddr&0xFFFFE000;
594 return get_addr_ht(0x80000000);
596 // Look up address in hash table first
597 void *get_addr_ht(u_int vaddr)
599 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
600 const struct ht_entry *ht_bin = hash_table_get(vaddr);
601 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
602 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
603 return get_addr(vaddr);
606 static void clear_all_regs(signed char regmap[])
608 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
611 static signed char get_reg(const signed char regmap[],int r)
614 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
618 // Find a register that is available for two consecutive cycles
619 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
622 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
626 int count_free_regs(signed char regmap[])
630 for(hr=0;hr<HOST_REGS;hr++)
632 if(hr!=EXCLUDE_REG) {
633 if(regmap[hr]<0) count++;
639 void dirty_reg(struct regstat *cur,signed char reg)
643 for (hr=0;hr<HOST_REGS;hr++) {
644 if((cur->regmap[hr]&63)==reg) {
650 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
654 for (hr=0;hr<HOST_REGS;hr++) {
655 if(cur->regmap[hr]==reg) {
657 current_constmap[hr]=value;
662 static void clear_const(struct regstat *cur, signed char reg)
666 for (hr=0;hr<HOST_REGS;hr++) {
667 if((cur->regmap[hr]&63)==reg) {
668 cur->isconst&=~(1<<hr);
673 static int is_const(struct regstat *cur, signed char reg)
678 for (hr=0;hr<HOST_REGS;hr++) {
679 if((cur->regmap[hr]&63)==reg) {
680 return (cur->isconst>>hr)&1;
686 static uint32_t get_const(struct regstat *cur, signed char reg)
690 for (hr=0;hr<HOST_REGS;hr++) {
691 if(cur->regmap[hr]==reg) {
692 return current_constmap[hr];
695 SysPrintf("Unknown constant in r%d\n",reg);
699 // Least soon needed registers
700 // Look at the next ten instructions and see which registers
701 // will be used. Try not to reallocate these.
702 void lsn(u_char hsn[], int i, int *preferred_reg)
712 if (dops[i+j].is_ujump)
714 // Don't go past an unconditonal jump
721 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
722 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
723 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
724 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
725 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
726 // Stores can allocate zero
727 hsn[dops[i+j].rs1]=j;
728 hsn[dops[i+j].rs2]=j;
730 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
732 // On some architectures stores need invc_ptr
733 #if defined(HOST_IMM8)
734 if (dops[i+j].is_store)
737 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
745 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
747 // Follow first branch
748 int t=(ba[i+b]-start)>>2;
749 j=7-b;if(t+j>=slen) j=slen-t-1;
752 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
753 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
754 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
755 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
758 // TODO: preferred register based on backward branch
760 // Delay slot should preferably not overwrite branch conditions or cycle count
761 if (i > 0 && dops[i-1].is_jump) {
762 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
763 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
769 // Coprocessor load/store needs FTEMP, even if not declared
770 if(dops[i].itype==C2LS) {
773 // Load L/R also uses FTEMP as a temporary register
774 if(dops[i].itype==LOADLR) {
777 // Also SWL/SWR/SDL/SDR
778 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
781 // Don't remove the miniht registers
782 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
789 // We only want to allocate registers if we're going to use them again soon
790 int needed_again(int r, int i)
796 if (i > 0 && dops[i-1].is_ujump)
798 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
799 return 0; // Don't need any registers if exiting the block
807 if (dops[i+j].is_ujump)
809 // Don't go past an unconditonal jump
813 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
820 if(dops[i+j].rs1==r) rn=j;
821 if(dops[i+j].rs2==r) rn=j;
822 if((unneeded_reg[i+j]>>r)&1) rn=10;
823 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
833 // Try to match register allocations at the end of a loop with those
835 int loop_reg(int i, int r, int hr)
844 if (dops[i+j].is_ujump)
846 // Don't go past an unconditonal jump
853 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
859 if((unneeded_reg[i+k]>>r)&1) return hr;
860 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
862 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
864 int t=(ba[i+k]-start)>>2;
865 int reg=get_reg(regs[t].regmap_entry,r);
866 if(reg>=0) return reg;
867 //reg=get_reg(regs[t+1].regmap_entry,r);
868 //if(reg>=0) return reg;
876 // Allocate every register, preserving source/target regs
877 void alloc_all(struct regstat *cur,int i)
881 for(hr=0;hr<HOST_REGS;hr++) {
882 if(hr!=EXCLUDE_REG) {
883 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
884 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
887 cur->dirty&=~(1<<hr);
890 if((cur->regmap[hr]&63)==0)
893 cur->dirty&=~(1<<hr);
900 static int host_tempreg_in_use;
902 static void host_tempreg_acquire(void)
904 assert(!host_tempreg_in_use);
905 host_tempreg_in_use = 1;
908 static void host_tempreg_release(void)
910 host_tempreg_in_use = 0;
913 static void host_tempreg_acquire(void) {}
914 static void host_tempreg_release(void) {}
918 extern void gen_interupt();
919 extern void do_insn_cmp();
920 #define FUNCNAME(f) { f, " " #f }
921 static const struct {
924 } function_names[] = {
925 FUNCNAME(cc_interrupt),
926 FUNCNAME(gen_interupt),
927 FUNCNAME(get_addr_ht),
929 FUNCNAME(jump_handler_read8),
930 FUNCNAME(jump_handler_read16),
931 FUNCNAME(jump_handler_read32),
932 FUNCNAME(jump_handler_write8),
933 FUNCNAME(jump_handler_write16),
934 FUNCNAME(jump_handler_write32),
935 FUNCNAME(invalidate_addr),
936 FUNCNAME(jump_to_new_pc),
937 FUNCNAME(jump_break),
938 FUNCNAME(jump_break_ds),
939 FUNCNAME(jump_syscall),
940 FUNCNAME(jump_syscall_ds),
941 FUNCNAME(call_gteStall),
942 FUNCNAME(new_dyna_leave),
944 FUNCNAME(pcsx_mtc0_ds),
946 FUNCNAME(do_insn_cmp),
949 FUNCNAME(verify_code),
953 static const char *func_name(const void *a)
956 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
957 if (function_names[i].addr == a)
958 return function_names[i].name;
962 #define func_name(x) ""
966 #include "assem_x86.c"
969 #include "assem_x64.c"
972 #include "assem_arm.c"
975 #include "assem_arm64.c"
978 static void *get_trampoline(const void *f)
982 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
983 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
986 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
987 SysPrintf("trampoline table is full, last func %p\n", f);
990 if (ndrc->tramp.f[i] == NULL) {
991 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
992 ndrc->tramp.f[i] = f;
993 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
995 return &ndrc->tramp.ops[i];
998 static void emit_far_jump(const void *f)
1000 if (can_jump_or_call(f)) {
1005 f = get_trampoline(f);
1009 static void emit_far_call(const void *f)
1011 if (can_jump_or_call(f)) {
1016 f = get_trampoline(f);
1020 // Add virtual address mapping to linked list
1021 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1023 struct ll_entry *new_entry;
1024 new_entry=malloc(sizeof(struct ll_entry));
1025 assert(new_entry!=NULL);
1026 new_entry->vaddr=vaddr;
1027 new_entry->reg_sv_flags=0;
1028 new_entry->addr=addr;
1029 new_entry->next=*head;
1033 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
1035 ll_add(head,vaddr,addr);
1036 (*head)->reg_sv_flags=reg_sv_flags;
1039 // Check if an address is already compiled
1040 // but don't return addresses which are about to expire from the cache
1041 void *check_addr(u_int vaddr)
1043 struct ht_entry *ht_bin = hash_table_get(vaddr);
1045 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1046 if (ht_bin->vaddr[i] == vaddr)
1047 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1048 if (isclean(ht_bin->tcaddr[i]))
1049 return ht_bin->tcaddr[i];
1051 u_int page=get_page(vaddr);
1052 struct ll_entry *head;
1054 while (head != NULL) {
1055 if (head->vaddr == vaddr) {
1056 if (doesnt_expire_soon(head->addr)) {
1057 // Update existing entry with current address
1058 if (ht_bin->vaddr[0] == vaddr) {
1059 ht_bin->tcaddr[0] = head->addr;
1062 if (ht_bin->vaddr[1] == vaddr) {
1063 ht_bin->tcaddr[1] = head->addr;
1066 // Insert into hash table with low priority.
1067 // Don't evict existing entries, as they are probably
1068 // addresses that are being accessed frequently.
1069 if (ht_bin->vaddr[0] == -1) {
1070 ht_bin->vaddr[0] = vaddr;
1071 ht_bin->tcaddr[0] = head->addr;
1073 else if (ht_bin->vaddr[1] == -1) {
1074 ht_bin->vaddr[1] = vaddr;
1075 ht_bin->tcaddr[1] = head->addr;
1085 void remove_hash(int vaddr)
1087 //printf("remove hash: %x\n",vaddr);
1088 struct ht_entry *ht_bin = hash_table_get(vaddr);
1089 if (ht_bin->vaddr[1] == vaddr) {
1090 ht_bin->vaddr[1] = -1;
1091 ht_bin->tcaddr[1] = NULL;
1093 if (ht_bin->vaddr[0] == vaddr) {
1094 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1095 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1096 ht_bin->vaddr[1] = -1;
1097 ht_bin->tcaddr[1] = NULL;
1101 static void ll_remove_matching_addrs(struct ll_entry **head,
1102 uintptr_t base_offs_s, int shift)
1104 struct ll_entry *next;
1106 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1107 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1108 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1110 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
1111 remove_hash((*head)->vaddr);
1118 head=&((*head)->next);
1123 // Remove all entries from linked list
1124 void ll_clear(struct ll_entry **head)
1126 struct ll_entry *cur;
1127 struct ll_entry *next;
1138 // Dereference the pointers and remove if it matches
1139 static void ll_kill_pointers(struct ll_entry *head,
1140 uintptr_t base_offs_s, int shift)
1143 u_char *ptr = get_pointer(head->addr);
1144 uintptr_t o1 = ptr - ndrc->translation_cache;
1145 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1146 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1147 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1149 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
1150 void *host_addr=find_extjump_insn(head->addr);
1151 mark_clear_cache(host_addr);
1152 set_jump_target(host_addr, head->addr);
1158 // This is called when we write to a compiled block (see do_invstub)
1159 static void invalidate_page(u_int page)
1161 struct ll_entry *head;
1162 struct ll_entry *next;
1166 inv_debug("INVALIDATE: %x\n",head->vaddr);
1167 remove_hash(head->vaddr);
1172 head=jump_out[page];
1175 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
1176 void *host_addr=find_extjump_insn(head->addr);
1177 mark_clear_cache(host_addr);
1178 set_jump_target(host_addr, head->addr); // point back to dyna_linker
1185 static void invalidate_block_range(u_int block, u_int first, u_int last)
1187 u_int page=get_page(block<<12);
1188 //printf("first=%d last=%d\n",first,last);
1189 invalidate_page(page);
1190 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1191 assert(last<page+5);
1192 // Invalidate the adjacent pages if a block crosses a 4K boundary
1194 invalidate_page(first);
1197 for(first=page+1;first<last;first++) {
1198 invalidate_page(first);
1202 // Don't trap writes
1203 invalid_code[block]=1;
1206 memset(mini_ht,-1,sizeof(mini_ht));
1210 void invalidate_block(u_int block)
1212 u_int page=get_page(block<<12);
1213 u_int vpage=get_vpage(block<<12);
1214 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1215 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1218 struct ll_entry *head;
1219 head=jump_dirty[vpage];
1220 //printf("page=%d vpage=%d\n",page,vpage);
1222 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1223 u_char *start, *end;
1224 get_bounds(head->addr, &start, &end);
1225 //printf("start: %p end: %p\n", start, end);
1226 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1227 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1228 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1229 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
1235 invalidate_block_range(block,first,last);
1238 void invalidate_addr(u_int addr)
1241 // this check is done by the caller
1242 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1243 u_int page=get_vpage(addr);
1244 if(page<2048) { // RAM
1245 struct ll_entry *head;
1246 u_int addr_min=~0, addr_max=0;
1247 u_int mask=RAM_SIZE-1;
1248 u_int addr_main=0x80000000|(addr&mask);
1250 inv_code_start=addr_main&~0xfff;
1251 inv_code_end=addr_main|0xfff;
1254 // must check previous page too because of spans..
1256 inv_code_start-=0x1000;
1258 for(;pg1<=page;pg1++) {
1259 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1260 u_char *start_h, *end_h;
1262 get_bounds(head->addr, &start_h, &end_h);
1263 start = (uintptr_t)start_h - ram_offset;
1264 end = (uintptr_t)end_h - ram_offset;
1265 if(start<=addr_main&&addr_main<end) {
1266 if(start<addr_min) addr_min=start;
1267 if(end>addr_max) addr_max=end;
1269 else if(addr_main<start) {
1270 if(start<inv_code_end)
1271 inv_code_end=start-1;
1274 if(end>inv_code_start)
1280 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1281 inv_code_start=inv_code_end=~0;
1282 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1286 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1287 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1288 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1292 invalidate_block(addr>>12);
1295 // This is called when loading a save state.
1296 // Anything could have changed, so invalidate everything.
1297 void invalidate_all_pages(void)
1300 for(page=0;page<4096;page++)
1301 invalidate_page(page);
1302 for(page=0;page<1048576;page++)
1303 if(!invalid_code[page]) {
1304 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1305 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1308 memset(mini_ht,-1,sizeof(mini_ht));
1313 static void do_invstub(int n)
1316 u_int reglist=stubs[n].a;
1317 set_jump_target(stubs[n].addr, out);
1319 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1320 emit_far_call(invalidate_addr);
1321 restore_regs(reglist);
1322 emit_jmp(stubs[n].retaddr); // return address
1325 // Add an entry to jump_out after making a link
1326 // src should point to code by emit_extjump2()
1327 void add_jump_out(u_int vaddr,void *src)
1329 u_int page=get_page(vaddr);
1330 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
1331 check_extjump2(src);
1332 ll_add(jump_out+page,vaddr,src);
1333 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
1336 // If a code block was found to be unmodified (bit was set in
1337 // restore_candidate) and it remains unmodified (bit is clear
1338 // in invalid_code) then move the entries for that 4K page from
1339 // the dirty list to the clean list.
1340 void clean_blocks(u_int page)
1342 struct ll_entry *head;
1343 inv_debug("INV: clean_blocks page=%d\n",page);
1344 head=jump_dirty[page];
1346 if(!invalid_code[head->vaddr>>12]) {
1347 // Don't restore blocks which are about to expire from the cache
1348 if (doesnt_expire_soon(head->addr)) {
1349 if(verify_dirty(head->addr)) {
1350 u_char *start, *end;
1351 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
1354 get_bounds(head->addr, &start, &end);
1355 if (start - rdram < RAM_SIZE) {
1356 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
1357 inv|=invalid_code[i];
1360 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1364 void *clean_addr = get_clean_addr(head->addr);
1365 if (doesnt_expire_soon(clean_addr)) {
1367 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
1368 //printf("page=%x, addr=%x\n",page,head->vaddr);
1369 //assert(head->vaddr>>12==(page|0x80000));
1370 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1371 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1372 if (ht_bin->vaddr[0] == head->vaddr)
1373 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1374 if (ht_bin->vaddr[1] == head->vaddr)
1375 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1385 /* Register allocation */
1387 // Note: registers are allocated clean (unmodified state)
1388 // if you intend to modify the register, you must call dirty_reg().
1389 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1392 int preferred_reg = PREFERRED_REG_FIRST
1393 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1394 if (reg == CCREG) preferred_reg = HOST_CCREG;
1395 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1396 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1398 // Don't allocate unused registers
1399 if((cur->u>>reg)&1) return;
1401 // see if it's already allocated
1402 for(hr=0;hr<HOST_REGS;hr++)
1404 if(cur->regmap[hr]==reg) return;
1407 // Keep the same mapping if the register was already allocated in a loop
1408 preferred_reg = loop_reg(i,reg,preferred_reg);
1410 // Try to allocate the preferred register
1411 if(cur->regmap[preferred_reg]==-1) {
1412 cur->regmap[preferred_reg]=reg;
1413 cur->dirty&=~(1<<preferred_reg);
1414 cur->isconst&=~(1<<preferred_reg);
1417 r=cur->regmap[preferred_reg];
1420 cur->regmap[preferred_reg]=reg;
1421 cur->dirty&=~(1<<preferred_reg);
1422 cur->isconst&=~(1<<preferred_reg);
1426 // Clear any unneeded registers
1427 // We try to keep the mapping consistent, if possible, because it
1428 // makes branches easier (especially loops). So we try to allocate
1429 // first (see above) before removing old mappings. If this is not
1430 // possible then go ahead and clear out the registers that are no
1432 for(hr=0;hr<HOST_REGS;hr++)
1437 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1441 // Try to allocate any available register, but prefer
1442 // registers that have not been used recently.
1444 for (hr = PREFERRED_REG_FIRST; ; ) {
1445 if (cur->regmap[hr] < 0) {
1446 int oldreg = regs[i-1].regmap[hr];
1447 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1448 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1450 cur->regmap[hr]=reg;
1451 cur->dirty&=~(1<<hr);
1452 cur->isconst&=~(1<<hr);
1457 if (hr == EXCLUDE_REG)
1459 if (hr == HOST_REGS)
1461 if (hr == PREFERRED_REG_FIRST)
1466 // Try to allocate any available register
1467 for (hr = PREFERRED_REG_FIRST; ; ) {
1468 if (cur->regmap[hr] < 0) {
1469 cur->regmap[hr]=reg;
1470 cur->dirty&=~(1<<hr);
1471 cur->isconst&=~(1<<hr);
1475 if (hr == EXCLUDE_REG)
1477 if (hr == HOST_REGS)
1479 if (hr == PREFERRED_REG_FIRST)
1483 // Ok, now we have to evict someone
1484 // Pick a register we hopefully won't need soon
1485 u_char hsn[MAXREG+1];
1486 memset(hsn,10,sizeof(hsn));
1488 lsn(hsn,i,&preferred_reg);
1489 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1490 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1492 // Don't evict the cycle count at entry points, otherwise the entry
1493 // stub will have to write it.
1494 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1495 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1498 // Alloc preferred register if available
1499 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1500 for(hr=0;hr<HOST_REGS;hr++) {
1501 // Evict both parts of a 64-bit register
1502 if((cur->regmap[hr]&63)==r) {
1504 cur->dirty&=~(1<<hr);
1505 cur->isconst&=~(1<<hr);
1508 cur->regmap[preferred_reg]=reg;
1511 for(r=1;r<=MAXREG;r++)
1513 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1514 for(hr=0;hr<HOST_REGS;hr++) {
1515 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1516 if(cur->regmap[hr]==r) {
1517 cur->regmap[hr]=reg;
1518 cur->dirty&=~(1<<hr);
1519 cur->isconst&=~(1<<hr);
1530 for(r=1;r<=MAXREG;r++)
1533 for(hr=0;hr<HOST_REGS;hr++) {
1534 if(cur->regmap[hr]==r) {
1535 cur->regmap[hr]=reg;
1536 cur->dirty&=~(1<<hr);
1537 cur->isconst&=~(1<<hr);
1544 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1547 // Allocate a temporary register. This is done without regard to
1548 // dirty status or whether the register we request is on the unneeded list
1549 // Note: This will only allocate one register, even if called multiple times
1550 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1553 int preferred_reg = -1;
1555 // see if it's already allocated
1556 for(hr=0;hr<HOST_REGS;hr++)
1558 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1561 // Try to allocate any available register
1562 for(hr=HOST_REGS-1;hr>=0;hr--) {
1563 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1564 cur->regmap[hr]=reg;
1565 cur->dirty&=~(1<<hr);
1566 cur->isconst&=~(1<<hr);
1571 // Find an unneeded register
1572 for(hr=HOST_REGS-1;hr>=0;hr--)
1578 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1579 cur->regmap[hr]=reg;
1580 cur->dirty&=~(1<<hr);
1581 cur->isconst&=~(1<<hr);
1588 // Ok, now we have to evict someone
1589 // Pick a register we hopefully won't need soon
1590 // TODO: we might want to follow unconditional jumps here
1591 // TODO: get rid of dupe code and make this into a function
1592 u_char hsn[MAXREG+1];
1593 memset(hsn,10,sizeof(hsn));
1595 lsn(hsn,i,&preferred_reg);
1596 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1598 // Don't evict the cycle count at entry points, otherwise the entry
1599 // stub will have to write it.
1600 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1601 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1604 for(r=1;r<=MAXREG;r++)
1606 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1607 for(hr=0;hr<HOST_REGS;hr++) {
1608 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1609 if(cur->regmap[hr]==r) {
1610 cur->regmap[hr]=reg;
1611 cur->dirty&=~(1<<hr);
1612 cur->isconst&=~(1<<hr);
1623 for(r=1;r<=MAXREG;r++)
1626 for(hr=0;hr<HOST_REGS;hr++) {
1627 if(cur->regmap[hr]==r) {
1628 cur->regmap[hr]=reg;
1629 cur->dirty&=~(1<<hr);
1630 cur->isconst&=~(1<<hr);
1637 SysPrintf("This shouldn't happen");abort();
1640 static void mov_alloc(struct regstat *current,int i)
1642 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1643 alloc_cc(current,i); // for stalls
1644 dirty_reg(current,CCREG);
1647 // Note: Don't need to actually alloc the source registers
1648 //alloc_reg(current,i,dops[i].rs1);
1649 alloc_reg(current,i,dops[i].rt1);
1651 clear_const(current,dops[i].rs1);
1652 clear_const(current,dops[i].rt1);
1653 dirty_reg(current,dops[i].rt1);
1656 static void shiftimm_alloc(struct regstat *current,int i)
1658 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1661 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1662 else dops[i].lt1=dops[i].rs1;
1663 alloc_reg(current,i,dops[i].rt1);
1664 dirty_reg(current,dops[i].rt1);
1665 if(is_const(current,dops[i].rs1)) {
1666 int v=get_const(current,dops[i].rs1);
1667 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1668 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1669 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1671 else clear_const(current,dops[i].rt1);
1676 clear_const(current,dops[i].rs1);
1677 clear_const(current,dops[i].rt1);
1680 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1684 if(dops[i].opcode2==0x3c) // DSLL32
1688 if(dops[i].opcode2==0x3e) // DSRL32
1692 if(dops[i].opcode2==0x3f) // DSRA32
1698 static void shift_alloc(struct regstat *current,int i)
1701 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1703 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1704 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1705 alloc_reg(current,i,dops[i].rt1);
1706 if(dops[i].rt1==dops[i].rs2) {
1707 alloc_reg_temp(current,i,-1);
1708 minimum_free_regs[i]=1;
1710 } else { // DSLLV/DSRLV/DSRAV
1713 clear_const(current,dops[i].rs1);
1714 clear_const(current,dops[i].rs2);
1715 clear_const(current,dops[i].rt1);
1716 dirty_reg(current,dops[i].rt1);
1720 static void alu_alloc(struct regstat *current,int i)
1722 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1724 if(dops[i].rs1&&dops[i].rs2) {
1725 alloc_reg(current,i,dops[i].rs1);
1726 alloc_reg(current,i,dops[i].rs2);
1729 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1730 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1732 alloc_reg(current,i,dops[i].rt1);
1735 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1737 alloc_reg(current,i,dops[i].rs1);
1738 alloc_reg(current,i,dops[i].rs2);
1739 alloc_reg(current,i,dops[i].rt1);
1742 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1744 if(dops[i].rs1&&dops[i].rs2) {
1745 alloc_reg(current,i,dops[i].rs1);
1746 alloc_reg(current,i,dops[i].rs2);
1750 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1751 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1753 alloc_reg(current,i,dops[i].rt1);
1756 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1759 clear_const(current,dops[i].rs1);
1760 clear_const(current,dops[i].rs2);
1761 clear_const(current,dops[i].rt1);
1762 dirty_reg(current,dops[i].rt1);
1765 static void imm16_alloc(struct regstat *current,int i)
1767 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1768 else dops[i].lt1=dops[i].rs1;
1769 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1770 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1773 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1774 clear_const(current,dops[i].rs1);
1775 clear_const(current,dops[i].rt1);
1777 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1778 if(is_const(current,dops[i].rs1)) {
1779 int v=get_const(current,dops[i].rs1);
1780 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1781 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1782 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1784 else clear_const(current,dops[i].rt1);
1786 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1787 if(is_const(current,dops[i].rs1)) {
1788 int v=get_const(current,dops[i].rs1);
1789 set_const(current,dops[i].rt1,v+imm[i]);
1791 else clear_const(current,dops[i].rt1);
1794 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1796 dirty_reg(current,dops[i].rt1);
1799 static void load_alloc(struct regstat *current,int i)
1801 clear_const(current,dops[i].rt1);
1802 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1803 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1804 if (needed_again(dops[i].rs1, i))
1805 alloc_reg(current, i, dops[i].rs1);
1807 alloc_reg(current, i, ROREG);
1808 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1809 alloc_reg(current,i,dops[i].rt1);
1810 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1811 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1815 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1819 dirty_reg(current,dops[i].rt1);
1820 // LWL/LWR need a temporary register for the old value
1821 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1823 alloc_reg(current,i,FTEMP);
1824 alloc_reg_temp(current,i,-1);
1825 minimum_free_regs[i]=1;
1830 // Load to r0 or unneeded register (dummy load)
1831 // but we still need a register to calculate the address
1832 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1834 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1836 alloc_reg_temp(current,i,-1);
1837 minimum_free_regs[i]=1;
1838 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1845 void store_alloc(struct regstat *current,int i)
1847 clear_const(current,dops[i].rs2);
1848 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1849 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1850 alloc_reg(current,i,dops[i].rs2);
1851 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
1855 alloc_reg(current, i, ROREG);
1856 #if defined(HOST_IMM8)
1857 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1858 alloc_reg(current, i, INVCP);
1860 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
1861 alloc_reg(current,i,FTEMP);
1863 // We need a temporary register for address generation
1864 alloc_reg_temp(current,i,-1);
1865 minimum_free_regs[i]=1;
1868 void c1ls_alloc(struct regstat *current,int i)
1870 clear_const(current,dops[i].rt1);
1871 alloc_reg(current,i,CSREG); // Status
1874 void c2ls_alloc(struct regstat *current,int i)
1876 clear_const(current,dops[i].rt1);
1877 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1878 alloc_reg(current,i,FTEMP);
1880 alloc_reg(current, i, ROREG);
1881 #if defined(HOST_IMM8)
1882 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1883 if (dops[i].opcode == 0x3a) // SWC2
1884 alloc_reg(current,i,INVCP);
1886 // We need a temporary register for address generation
1887 alloc_reg_temp(current,i,-1);
1888 minimum_free_regs[i]=1;
1891 #ifndef multdiv_alloc
1892 void multdiv_alloc(struct regstat *current,int i)
1899 // case 0x1D: DMULTU
1902 clear_const(current,dops[i].rs1);
1903 clear_const(current,dops[i].rs2);
1904 alloc_cc(current,i); // for stalls
1905 if(dops[i].rs1&&dops[i].rs2)
1907 if((dops[i].opcode2&4)==0) // 32-bit
1909 current->u&=~(1LL<<HIREG);
1910 current->u&=~(1LL<<LOREG);
1911 alloc_reg(current,i,HIREG);
1912 alloc_reg(current,i,LOREG);
1913 alloc_reg(current,i,dops[i].rs1);
1914 alloc_reg(current,i,dops[i].rs2);
1915 dirty_reg(current,HIREG);
1916 dirty_reg(current,LOREG);
1925 // Multiply by zero is zero.
1926 // MIPS does not have a divide by zero exception.
1927 // The result is undefined, we return zero.
1928 alloc_reg(current,i,HIREG);
1929 alloc_reg(current,i,LOREG);
1930 dirty_reg(current,HIREG);
1931 dirty_reg(current,LOREG);
1936 void cop0_alloc(struct regstat *current,int i)
1938 if(dops[i].opcode2==0) // MFC0
1941 clear_const(current,dops[i].rt1);
1942 alloc_all(current,i);
1943 alloc_reg(current,i,dops[i].rt1);
1944 dirty_reg(current,dops[i].rt1);
1947 else if(dops[i].opcode2==4) // MTC0
1950 clear_const(current,dops[i].rs1);
1951 alloc_reg(current,i,dops[i].rs1);
1952 alloc_all(current,i);
1955 alloc_all(current,i); // FIXME: Keep r0
1957 alloc_reg(current,i,0);
1962 // TLBR/TLBWI/TLBWR/TLBP/ERET
1963 assert(dops[i].opcode2==0x10);
1964 alloc_all(current,i);
1966 minimum_free_regs[i]=HOST_REGS;
1969 static void cop2_alloc(struct regstat *current,int i)
1971 if (dops[i].opcode2 < 3) // MFC2/CFC2
1973 alloc_cc(current,i); // for stalls
1974 dirty_reg(current,CCREG);
1976 clear_const(current,dops[i].rt1);
1977 alloc_reg(current,i,dops[i].rt1);
1978 dirty_reg(current,dops[i].rt1);
1981 else if (dops[i].opcode2 > 3) // MTC2/CTC2
1984 clear_const(current,dops[i].rs1);
1985 alloc_reg(current,i,dops[i].rs1);
1989 alloc_reg(current,i,0);
1992 alloc_reg_temp(current,i,-1);
1993 minimum_free_regs[i]=1;
1996 void c2op_alloc(struct regstat *current,int i)
1998 alloc_cc(current,i); // for stalls
1999 dirty_reg(current,CCREG);
2000 alloc_reg_temp(current,i,-1);
2003 void syscall_alloc(struct regstat *current,int i)
2005 alloc_cc(current,i);
2006 dirty_reg(current,CCREG);
2007 alloc_all(current,i);
2008 minimum_free_regs[i]=HOST_REGS;
2012 void delayslot_alloc(struct regstat *current,int i)
2014 switch(dops[i].itype) {
2022 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
2023 SysPrintf("Disabled speculative precompilation\n");
2027 imm16_alloc(current,i);
2031 load_alloc(current,i);
2035 store_alloc(current,i);
2038 alu_alloc(current,i);
2041 shift_alloc(current,i);
2044 multdiv_alloc(current,i);
2047 shiftimm_alloc(current,i);
2050 mov_alloc(current,i);
2053 cop0_alloc(current,i);
2058 cop2_alloc(current,i);
2061 c1ls_alloc(current,i);
2064 c2ls_alloc(current,i);
2067 c2op_alloc(current,i);
2072 // Special case where a branch and delay slot span two pages in virtual memory
2073 static void pagespan_alloc(struct regstat *current,int i)
2076 current->wasconst=0;
2078 minimum_free_regs[i]=HOST_REGS;
2079 alloc_all(current,i);
2080 alloc_cc(current,i);
2081 dirty_reg(current,CCREG);
2082 if(dops[i].opcode==3) // JAL
2084 alloc_reg(current,i,31);
2085 dirty_reg(current,31);
2087 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
2089 alloc_reg(current,i,dops[i].rs1);
2090 if (dops[i].rt1!=0) {
2091 alloc_reg(current,i,dops[i].rt1);
2092 dirty_reg(current,dops[i].rt1);
2095 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2097 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2098 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
2101 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2103 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2108 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2109 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2111 assert(stubcount < ARRAY_SIZE(stubs));
2112 stubs[stubcount].type = type;
2113 stubs[stubcount].addr = addr;
2114 stubs[stubcount].retaddr = retaddr;
2115 stubs[stubcount].a = a;
2116 stubs[stubcount].b = b;
2117 stubs[stubcount].c = c;
2118 stubs[stubcount].d = d;
2119 stubs[stubcount].e = e;
2123 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2124 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2126 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2129 // Write out a single register
2130 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2133 for(hr=0;hr<HOST_REGS;hr++) {
2134 if(hr!=EXCLUDE_REG) {
2135 if((regmap[hr]&63)==r) {
2137 assert(regmap[hr]<64);
2138 emit_storereg(r,hr);
2145 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2147 //if(dirty_pre==dirty) return;
2149 for(hr=0;hr<HOST_REGS;hr++) {
2150 if(hr!=EXCLUDE_REG) {
2152 if(((~u)>>(reg&63))&1) {
2154 if(((dirty_pre&~dirty)>>hr)&1) {
2156 emit_storereg(reg,hr);
2169 static void pass_args(int a0, int a1)
2173 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2175 else if(a0!=0&&a1==0) {
2177 if (a0>=0) emit_mov(a0,0);
2180 if(a0>=0&&a0!=0) emit_mov(a0,0);
2181 if(a1>=0&&a1!=1) emit_mov(a1,1);
2185 static void alu_assemble(int i, const struct regstat *i_regs)
2187 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2189 signed char s1,s2,t;
2190 t=get_reg(i_regs->regmap,dops[i].rt1);
2192 s1=get_reg(i_regs->regmap,dops[i].rs1);
2193 s2=get_reg(i_regs->regmap,dops[i].rs2);
2194 if(dops[i].rs1&&dops[i].rs2) {
2197 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2198 else emit_add(s1,s2,t);
2200 else if(dops[i].rs1) {
2201 if(s1>=0) emit_mov(s1,t);
2202 else emit_loadreg(dops[i].rs1,t);
2204 else if(dops[i].rs2) {
2206 if(dops[i].opcode2&2) emit_neg(s2,t);
2207 else emit_mov(s2,t);
2210 emit_loadreg(dops[i].rs2,t);
2211 if(dops[i].opcode2&2) emit_neg(t,t);
2214 else emit_zeroreg(t);
2218 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2221 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2223 signed char s1l,s2l,t;
2225 t=get_reg(i_regs->regmap,dops[i].rt1);
2228 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2229 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2230 if(dops[i].rs2==0) // rx<r0
2232 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2234 emit_shrimm(s1l,31,t);
2236 else // SLTU (unsigned can not be less than zero, 0<0)
2239 else if(dops[i].rs1==0) // r0<rx
2242 if(dops[i].opcode2==0x2a) // SLT
2243 emit_set_gz32(s2l,t);
2244 else // SLTU (set if not zero)
2245 emit_set_nz32(s2l,t);
2248 assert(s1l>=0);assert(s2l>=0);
2249 if(dops[i].opcode2==0x2a) // SLT
2250 emit_set_if_less32(s1l,s2l,t);
2252 emit_set_if_carry32(s1l,s2l,t);
2258 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2260 signed char s1l,s2l,tl;
2261 tl=get_reg(i_regs->regmap,dops[i].rt1);
2264 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2265 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2266 if(dops[i].rs1&&dops[i].rs2) {
2269 if(dops[i].opcode2==0x24) { // AND
2270 emit_and(s1l,s2l,tl);
2272 if(dops[i].opcode2==0x25) { // OR
2273 emit_or(s1l,s2l,tl);
2275 if(dops[i].opcode2==0x26) { // XOR
2276 emit_xor(s1l,s2l,tl);
2278 if(dops[i].opcode2==0x27) { // NOR
2279 emit_or(s1l,s2l,tl);
2285 if(dops[i].opcode2==0x24) { // AND
2288 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2290 if(s1l>=0) emit_mov(s1l,tl);
2291 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2295 if(s2l>=0) emit_mov(s2l,tl);
2296 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2298 else emit_zeroreg(tl);
2300 if(dops[i].opcode2==0x27) { // NOR
2302 if(s1l>=0) emit_not(s1l,tl);
2304 emit_loadreg(dops[i].rs1,tl);
2310 if(s2l>=0) emit_not(s2l,tl);
2312 emit_loadreg(dops[i].rs2,tl);
2316 else emit_movimm(-1,tl);
2325 static void imm16_assemble(int i, const struct regstat *i_regs)
2327 if (dops[i].opcode==0x0f) { // LUI
2330 t=get_reg(i_regs->regmap,dops[i].rt1);
2333 if(!((i_regs->isconst>>t)&1))
2334 emit_movimm(imm[i]<<16,t);
2338 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2341 t=get_reg(i_regs->regmap,dops[i].rt1);
2342 s=get_reg(i_regs->regmap,dops[i].rs1);
2347 if(!((i_regs->isconst>>t)&1)) {
2349 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2350 emit_addimm(t,imm[i],t);
2352 if(!((i_regs->wasconst>>s)&1))
2353 emit_addimm(s,imm[i],t);
2355 emit_movimm(constmap[i][s]+imm[i],t);
2361 if(!((i_regs->isconst>>t)&1))
2362 emit_movimm(imm[i],t);
2367 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2370 tl=get_reg(i_regs->regmap,dops[i].rt1);
2371 sl=get_reg(i_regs->regmap,dops[i].rs1);
2375 emit_addimm(sl,imm[i],tl);
2377 emit_movimm(imm[i],tl);
2382 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2384 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2386 t=get_reg(i_regs->regmap,dops[i].rt1);
2387 sl=get_reg(i_regs->regmap,dops[i].rs1);
2391 if(dops[i].opcode==0x0a) { // SLTI
2393 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2394 emit_slti32(t,imm[i],t);
2396 emit_slti32(sl,imm[i],t);
2401 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2402 emit_sltiu32(t,imm[i],t);
2404 emit_sltiu32(sl,imm[i],t);
2408 // SLTI(U) with r0 is just stupid,
2409 // nonetheless examples can be found
2410 if(dops[i].opcode==0x0a) // SLTI
2411 if(0<imm[i]) emit_movimm(1,t);
2412 else emit_zeroreg(t);
2415 if(imm[i]) emit_movimm(1,t);
2416 else emit_zeroreg(t);
2422 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2425 tl=get_reg(i_regs->regmap,dops[i].rt1);
2426 sl=get_reg(i_regs->regmap,dops[i].rs1);
2427 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2428 if(dops[i].opcode==0x0c) //ANDI
2432 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2433 emit_andimm(tl,imm[i],tl);
2435 if(!((i_regs->wasconst>>sl)&1))
2436 emit_andimm(sl,imm[i],tl);
2438 emit_movimm(constmap[i][sl]&imm[i],tl);
2448 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2450 if(dops[i].opcode==0x0d) { // ORI
2452 emit_orimm(tl,imm[i],tl);
2454 if(!((i_regs->wasconst>>sl)&1))
2455 emit_orimm(sl,imm[i],tl);
2457 emit_movimm(constmap[i][sl]|imm[i],tl);
2460 if(dops[i].opcode==0x0e) { // XORI
2462 emit_xorimm(tl,imm[i],tl);
2464 if(!((i_regs->wasconst>>sl)&1))
2465 emit_xorimm(sl,imm[i],tl);
2467 emit_movimm(constmap[i][sl]^imm[i],tl);
2472 emit_movimm(imm[i],tl);
2480 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2482 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2486 t=get_reg(i_regs->regmap,dops[i].rt1);
2487 s=get_reg(i_regs->regmap,dops[i].rs1);
2489 if(t>=0&&!((i_regs->isconst>>t)&1)){
2496 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2498 if(dops[i].opcode2==0) // SLL
2500 emit_shlimm(s<0?t:s,imm[i],t);
2502 if(dops[i].opcode2==2) // SRL
2504 emit_shrimm(s<0?t:s,imm[i],t);
2506 if(dops[i].opcode2==3) // SRA
2508 emit_sarimm(s<0?t:s,imm[i],t);
2512 if(s>=0 && s!=t) emit_mov(s,t);
2516 //emit_storereg(dops[i].rt1,t); //DEBUG
2519 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2523 if(dops[i].opcode2==0x3c) // DSLL32
2527 if(dops[i].opcode2==0x3e) // DSRL32
2531 if(dops[i].opcode2==0x3f) // DSRA32
2537 #ifndef shift_assemble
2538 static void shift_assemble(int i, const struct regstat *i_regs)
2540 signed char s,t,shift;
2541 if (dops[i].rt1 == 0)
2543 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2544 t = get_reg(i_regs->regmap, dops[i].rt1);
2545 s = get_reg(i_regs->regmap, dops[i].rs1);
2546 shift = get_reg(i_regs->regmap, dops[i].rs2);
2552 else if(dops[i].rs2==0) {
2554 if(s!=t) emit_mov(s,t);
2557 host_tempreg_acquire();
2558 emit_andimm(shift,31,HOST_TEMPREG);
2559 switch(dops[i].opcode2) {
2561 emit_shl(s,HOST_TEMPREG,t);
2564 emit_shr(s,HOST_TEMPREG,t);
2567 emit_sar(s,HOST_TEMPREG,t);
2572 host_tempreg_release();
2586 static int get_ptr_mem_type(u_int a)
2588 if(a < 0x00200000) {
2589 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2590 // return wrong, must use memhandler for BIOS self-test to pass
2591 // 007 does similar stuff from a00 mirror, weird stuff
2595 if(0x1f800000 <= a && a < 0x1f801000)
2597 if(0x80200000 <= a && a < 0x80800000)
2599 if(0xa0000000 <= a && a < 0xa0200000)
2604 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2606 int r = get_reg(i_regs->regmap, ROREG);
2607 if (r < 0 && host_tempreg_free) {
2608 host_tempreg_acquire();
2609 emit_loadreg(ROREG, r = HOST_TEMPREG);
2616 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2617 int addr, int *offset_reg, int *addr_reg_override)
2621 int mr = dops[i].rs1;
2623 if(((smrv_strong|smrv_weak)>>mr)&1) {
2624 type=get_ptr_mem_type(smrv[mr]);
2625 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2628 // use the mirror we are running on
2629 type=get_ptr_mem_type(start);
2630 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2633 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2634 host_tempreg_acquire();
2635 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2636 addr=*addr_reg_override=HOST_TEMPREG;
2639 else if(type==MTYPE_0000) { // RAM 0 mirror
2640 host_tempreg_acquire();
2641 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2642 addr=*addr_reg_override=HOST_TEMPREG;
2645 else if(type==MTYPE_A000) { // RAM A mirror
2646 host_tempreg_acquire();
2647 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2648 addr=*addr_reg_override=HOST_TEMPREG;
2651 else if(type==MTYPE_1F80) { // scratchpad
2652 if (psxH == (void *)0x1f800000) {
2653 host_tempreg_acquire();
2654 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2655 emit_cmpimm(HOST_TEMPREG,0x1000);
2656 host_tempreg_release();
2661 // do the usual RAM check, jump will go to the right handler
2666 if (type == 0) // need ram check
2668 emit_cmpimm(addr,RAM_SIZE);
2670 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2671 // Hint to branch predictor that the branch is unlikely to be taken
2672 if (dops[i].rs1 >= 28)
2673 emit_jno_unlikely(0);
2677 if (ram_offset != 0)
2678 *offset_reg = get_ro_reg(i_regs, 0);
2684 // return memhandler, or get directly accessable address and return 0
2685 static void *get_direct_memhandler(void *table, u_int addr,
2686 enum stub_type type, uintptr_t *addr_host)
2688 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2689 uintptr_t l1, l2 = 0;
2690 l1 = ((uintptr_t *)table)[addr>>12];
2692 uintptr_t v = l1 << 1;
2693 *addr_host = v + addr;
2698 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2699 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2700 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2701 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2703 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2705 uintptr_t v = l2 << 1;
2706 *addr_host = v + (addr&0xfff);
2709 return (void *)(l2 << 1);
2713 static u_int get_host_reglist(const signed char *regmap)
2715 u_int reglist = 0, hr;
2716 for (hr = 0; hr < HOST_REGS; hr++) {
2717 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2723 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2726 reglist &= ~(1u << r1);
2728 reglist &= ~(1u << r2);
2732 // find a temp caller-saved register not in reglist (so assumed to be free)
2733 static int reglist_find_free(u_int reglist)
2735 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2738 return __builtin_ctz(free_regs);
2741 static void do_load_word(int a, int rt, int offset_reg)
2743 if (offset_reg >= 0)
2744 emit_ldr_dualindexed(offset_reg, a, rt);
2746 emit_readword_indexed(0, a, rt);
2749 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2751 if (offset_reg < 0) {
2752 emit_writeword_indexed(rt, ofs, a);
2756 emit_addimm(a, ofs, a);
2757 emit_str_dualindexed(offset_reg, a, rt);
2758 if (ofs != 0 && preseve_a)
2759 emit_addimm(a, -ofs, a);
2762 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2764 if (offset_reg < 0) {
2765 emit_writehword_indexed(rt, ofs, a);
2769 emit_addimm(a, ofs, a);
2770 emit_strh_dualindexed(offset_reg, a, rt);
2771 if (ofs != 0 && preseve_a)
2772 emit_addimm(a, -ofs, a);
2775 static void do_store_byte(int a, int rt, int offset_reg)
2777 if (offset_reg >= 0)
2778 emit_strb_dualindexed(offset_reg, a, rt);
2780 emit_writebyte_indexed(rt, 0, a);
2783 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2788 int memtarget=0,c=0;
2789 int offset_reg = -1;
2790 int fastio_reg_override = -1;
2791 u_int reglist=get_host_reglist(i_regs->regmap);
2792 tl=get_reg(i_regs->regmap,dops[i].rt1);
2793 s=get_reg(i_regs->regmap,dops[i].rs1);
2795 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2797 c=(i_regs->wasconst>>s)&1;
2799 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2802 //printf("load_assemble: c=%d\n",c);
2803 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2804 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2805 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2807 // could be FIFO, must perform the read
2809 assem_debug("(forced read)\n");
2810 tl=get_reg(i_regs->regmap,-1);
2813 if(offset||s<0||c) addr=tl;
2815 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2817 //printf("load_assemble: c=%d\n",c);
2818 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2819 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2823 // Strmnnrmn's speed hack
2824 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2827 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2828 &offset_reg, &fastio_reg_override);
2831 else if (ram_offset && memtarget) {
2832 offset_reg = get_ro_reg(i_regs, 0);
2834 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2835 switch (dops[i].opcode) {
2841 if (fastio_reg_override >= 0)
2842 a = fastio_reg_override;
2844 if (offset_reg >= 0)
2845 emit_ldrsb_dualindexed(offset_reg, a, tl);
2847 emit_movsbl_indexed(0, a, tl);
2850 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2853 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2860 if (fastio_reg_override >= 0)
2861 a = fastio_reg_override;
2862 if (offset_reg >= 0)
2863 emit_ldrsh_dualindexed(offset_reg, a, tl);
2865 emit_movswl_indexed(0, a, tl);
2868 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2871 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2877 if (fastio_reg_override >= 0)
2878 a = fastio_reg_override;
2879 do_load_word(a, tl, offset_reg);
2882 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2885 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2892 if (fastio_reg_override >= 0)
2893 a = fastio_reg_override;
2895 if (offset_reg >= 0)
2896 emit_ldrb_dualindexed(offset_reg, a, tl);
2898 emit_movzbl_indexed(0, a, tl);
2901 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2904 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2911 if (fastio_reg_override >= 0)
2912 a = fastio_reg_override;
2913 if (offset_reg >= 0)
2914 emit_ldrh_dualindexed(offset_reg, a, tl);
2916 emit_movzwl_indexed(0, a, tl);
2919 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2922 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2930 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2931 host_tempreg_release();
2934 #ifndef loadlr_assemble
2935 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
2937 int s,tl,temp,temp2,addr;
2940 int memtarget=0,c=0;
2941 int offset_reg = -1;
2942 int fastio_reg_override = -1;
2943 u_int reglist=get_host_reglist(i_regs->regmap);
2944 tl=get_reg(i_regs->regmap,dops[i].rt1);
2945 s=get_reg(i_regs->regmap,dops[i].rs1);
2946 temp=get_reg(i_regs->regmap,-1);
2947 temp2=get_reg(i_regs->regmap,FTEMP);
2948 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2952 if(offset||s<0||c) addr=temp2;
2955 c=(i_regs->wasconst>>s)&1;
2957 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2961 emit_shlimm(addr,3,temp);
2962 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2963 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2965 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2967 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2968 &offset_reg, &fastio_reg_override);
2971 if (ram_offset && memtarget) {
2972 offset_reg = get_ro_reg(i_regs, 0);
2974 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2975 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2977 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2980 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
2983 if (fastio_reg_override >= 0)
2984 a = fastio_reg_override;
2985 do_load_word(a, temp2, offset_reg);
2986 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2987 host_tempreg_release();
2988 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
2991 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
2994 emit_andimm(temp,24,temp);
2995 if (dops[i].opcode==0x22) // LWL
2996 emit_xorimm(temp,24,temp);
2997 host_tempreg_acquire();
2998 emit_movimm(-1,HOST_TEMPREG);
2999 if (dops[i].opcode==0x26) {
3000 emit_shr(temp2,temp,temp2);
3001 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3003 emit_shl(temp2,temp,temp2);
3004 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3006 host_tempreg_release();
3007 emit_or(temp2,tl,tl);
3009 //emit_storereg(dops[i].rt1,tl); // DEBUG
3011 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3017 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3023 enum stub_type type=0;
3024 int memtarget=0,c=0;
3025 int agr=AGEN1+(i&1);
3026 int offset_reg = -1;
3027 int fastio_reg_override = -1;
3028 u_int reglist=get_host_reglist(i_regs->regmap);
3029 tl=get_reg(i_regs->regmap,dops[i].rs2);
3030 s=get_reg(i_regs->regmap,dops[i].rs1);
3031 temp=get_reg(i_regs->regmap,agr);
3032 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3035 c=(i_regs->wasconst>>s)&1;
3037 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3042 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3043 if(offset||s<0||c) addr=temp;
3046 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3047 &offset_reg, &fastio_reg_override);
3049 else if (ram_offset && memtarget) {
3050 offset_reg = get_ro_reg(i_regs, 0);
3053 switch (dops[i].opcode) {
3058 if (fastio_reg_override >= 0)
3059 a = fastio_reg_override;
3060 do_store_byte(a, tl, offset_reg);
3068 if (fastio_reg_override >= 0)
3069 a = fastio_reg_override;
3070 do_store_hword(a, 0, tl, offset_reg, 1);
3077 if (fastio_reg_override >= 0)
3078 a = fastio_reg_override;
3079 do_store_word(a, 0, tl, offset_reg, 1);
3087 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3088 host_tempreg_release();
3090 // PCSX store handlers don't check invcode again
3092 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3095 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3097 #ifdef DESTRUCTIVE_SHIFT
3098 // The x86 shift operation is 'destructive'; it overwrites the
3099 // source register, so we need to make a copy first and use that.
3102 #if defined(HOST_IMM8)
3103 int ir=get_reg(i_regs->regmap,INVCP);
3105 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3107 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
3109 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3110 emit_callne(invalidate_addr_reg[addr]);
3114 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3118 u_int addr_val=constmap[i][s]+offset;
3120 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3121 } else if(c&&!memtarget) {
3122 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3124 // basic current block modification detection..
3125 // not looking back as that should be in mips cache already
3126 // (see Spyro2 title->attract mode)
3127 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3128 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3129 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3130 if(i_regs->regmap==regs[i].regmap) {
3131 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3132 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3133 emit_movimm(start+i*4+4,0);
3134 emit_writeword(0,&pcaddr);
3135 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3136 emit_far_call(get_addr_ht);
3142 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3148 void *case1, *case23, *case3;
3149 void *done0, *done1, *done2;
3150 int memtarget=0,c=0;
3151 int agr=AGEN1+(i&1);
3152 int offset_reg = -1;
3153 u_int reglist=get_host_reglist(i_regs->regmap);
3154 tl=get_reg(i_regs->regmap,dops[i].rs2);
3155 s=get_reg(i_regs->regmap,dops[i].rs1);
3156 temp=get_reg(i_regs->regmap,agr);
3157 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3160 c=(i_regs->isconst>>s)&1;
3162 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3168 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3169 if(!offset&&s!=temp) emit_mov(s,temp);
3175 if(!memtarget||!dops[i].rs1) {
3181 offset_reg = get_ro_reg(i_regs, 0);
3183 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3187 emit_testimm(temp,2);
3190 emit_testimm(temp,1);
3194 if (dops[i].opcode == 0x2A) { // SWL
3195 // Write msb into least significant byte
3196 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3197 do_store_byte(temp, tl, offset_reg);
3198 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3200 else if (dops[i].opcode == 0x2E) { // SWR
3201 // Write entire word
3202 do_store_word(temp, 0, tl, offset_reg, 1);
3207 set_jump_target(case1, out);
3208 if (dops[i].opcode == 0x2A) { // SWL
3209 // Write two msb into two least significant bytes
3210 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3211 do_store_hword(temp, -1, tl, offset_reg, 0);
3212 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3214 else if (dops[i].opcode == 0x2E) { // SWR
3215 // Write 3 lsb into three most significant bytes
3216 do_store_byte(temp, tl, offset_reg);
3217 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3218 do_store_hword(temp, 1, tl, offset_reg, 0);
3219 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3224 set_jump_target(case23, out);
3225 emit_testimm(temp,1);
3229 if (dops[i].opcode==0x2A) { // SWL
3230 // Write 3 msb into three least significant bytes
3231 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3232 do_store_hword(temp, -2, tl, offset_reg, 1);
3233 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3234 do_store_byte(temp, tl, offset_reg);
3235 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3237 else if (dops[i].opcode == 0x2E) { // SWR
3238 // Write two lsb into two most significant bytes
3239 do_store_hword(temp, 0, tl, offset_reg, 1);
3244 set_jump_target(case3, out);
3245 if (dops[i].opcode == 0x2A) { // SWL
3246 do_store_word(temp, -3, tl, offset_reg, 0);
3248 else if (dops[i].opcode == 0x2E) { // SWR
3249 do_store_byte(temp, tl, offset_reg);
3251 set_jump_target(done0, out);
3252 set_jump_target(done1, out);
3253 set_jump_target(done2, out);
3254 if (offset_reg == HOST_TEMPREG)
3255 host_tempreg_release();
3257 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
3258 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3259 #if defined(HOST_IMM8)
3260 int ir=get_reg(i_regs->regmap,INVCP);
3262 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3264 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3266 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3267 emit_callne(invalidate_addr_reg[temp]);
3271 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3276 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3278 if(dops[i].opcode2==0) // MFC0
3280 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3281 u_int copr=(source[i]>>11)&0x1f;
3282 //assert(t>=0); // Why does this happen? OOT is weird
3283 if(t>=0&&dops[i].rt1!=0) {
3284 emit_readword(®_cop0[copr],t);
3287 else if(dops[i].opcode2==4) // MTC0
3289 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3290 char copr=(source[i]>>11)&0x1f;
3292 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3293 if(copr==9||copr==11||copr==12||copr==13) {
3294 emit_readword(&last_count,HOST_TEMPREG);
3295 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3296 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3297 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3298 emit_writeword(HOST_CCREG,&Count);
3300 // What a mess. The status register (12) can enable interrupts,
3301 // so needs a special case to handle a pending interrupt.
3302 // The interrupt must be taken immediately, because a subsequent
3303 // instruction might disable interrupts again.
3304 if(copr==12||copr==13) {
3306 // burn cycles to cause cc_interrupt, which will
3307 // reschedule next_interupt. Relies on CCREG from above.
3308 assem_debug("MTC0 DS %d\n", copr);
3309 emit_writeword(HOST_CCREG,&last_count);
3310 emit_movimm(0,HOST_CCREG);
3311 emit_storereg(CCREG,HOST_CCREG);
3312 emit_loadreg(dops[i].rs1,1);
3313 emit_movimm(copr,0);
3314 emit_far_call(pcsx_mtc0_ds);
3315 emit_loadreg(dops[i].rs1,s);
3318 emit_movimm(start+i*4+4,HOST_TEMPREG);
3319 emit_writeword(HOST_TEMPREG,&pcaddr);
3320 emit_movimm(0,HOST_TEMPREG);
3321 emit_writeword(HOST_TEMPREG,&pending_exception);
3324 emit_loadreg(dops[i].rs1,1);
3327 emit_movimm(copr,0);
3328 emit_far_call(pcsx_mtc0);
3329 if(copr==9||copr==11||copr==12||copr==13) {
3330 emit_readword(&Count,HOST_CCREG);
3331 emit_readword(&next_interupt,HOST_TEMPREG);
3332 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
3333 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3334 emit_writeword(HOST_TEMPREG,&last_count);
3335 emit_storereg(CCREG,HOST_CCREG);
3337 if(copr==12||copr==13) {
3338 assert(!is_delayslot);
3339 emit_readword(&pending_exception,14);
3343 emit_readword(&pcaddr, 0);
3344 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3345 emit_far_call(get_addr_ht);
3347 set_jump_target(jaddr, out);
3349 emit_loadreg(dops[i].rs1,s);
3353 assert(dops[i].opcode2==0x10);
3354 //if((source[i]&0x3f)==0x10) // RFE
3356 emit_readword(&Status,0);
3357 emit_andimm(0,0x3c,1);
3358 emit_andimm(0,~0xf,0);
3359 emit_orrshr_imm(1,2,0);
3360 emit_writeword(0,&Status);
3365 static void cop1_unusable(int i, const struct regstat *i_regs)
3367 // XXX: should just just do the exception instead
3372 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3376 static void cop1_assemble(int i, const struct regstat *i_regs)
3378 cop1_unusable(i, i_regs);
3381 static void c1ls_assemble(int i, const struct regstat *i_regs)
3383 cop1_unusable(i, i_regs);
3387 static void do_cop1stub(int n)
3390 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3391 set_jump_target(stubs[n].addr, out);
3393 // int rs=stubs[n].b;
3394 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3397 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3398 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3400 //else {printf("fp exception in delay slot\n");}
3401 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3402 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3403 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3404 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3405 emit_far_jump(ds?fp_exception_ds:fp_exception);
3408 static int cop2_is_stalling_op(int i, int *cycles)
3410 if (dops[i].opcode == 0x3a) { // SWC2
3414 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3418 if (dops[i].itype == C2OP) {
3419 *cycles = gte_cycletab[source[i] & 0x3f];
3422 // ... what about MTC2/CTC2/LWC2?
3427 static void log_gte_stall(int stall, u_int cycle)
3429 if ((u_int)stall <= 44)
3430 printf("x stall %2d %u\n", stall, cycle + last_count);
3433 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3437 emit_movimm(stall, 0);
3439 emit_mov(HOST_TEMPREG, 0);
3440 emit_addimm(HOST_CCREG, ccadj[i], 1);
3441 emit_far_call(log_gte_stall);
3442 restore_regs(reglist);
3446 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3448 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3449 int rtmp = reglist_find_free(reglist);
3451 if (HACK_ENABLED(NDHACK_NO_STALLS))
3453 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3454 // happens occasionally... cc evicted? Don't bother then
3455 //printf("no cc %08x\n", start + i*4);
3459 for (j = i - 1; j >= 0; j--) {
3460 //if (dops[j].is_ds) break;
3461 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3463 if (j > 0 && ccadj[j - 1] > ccadj[j])
3468 cycles_passed = ccadj[i] - ccadj[j];
3469 if (other_gte_op_cycles >= 0)
3470 stall = other_gte_op_cycles - cycles_passed;
3471 else if (cycles_passed >= 44)
3472 stall = 0; // can't stall
3473 if (stall == -MAXBLOCK && rtmp >= 0) {
3474 // unknown stall, do the expensive runtime check
3475 assem_debug("; cop2_do_stall_check\n");
3478 emit_movimm(gte_cycletab[op], 0);
3479 emit_addimm(HOST_CCREG, ccadj[i], 1);
3480 emit_far_call(call_gteStall);
3481 restore_regs(reglist);
3483 host_tempreg_acquire();
3484 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3485 emit_addimm(rtmp, -ccadj[i], rtmp);
3486 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3487 emit_cmpimm(HOST_TEMPREG, 44);
3488 emit_cmovb_reg(rtmp, HOST_CCREG);
3489 //emit_log_gte_stall(i, 0, reglist);
3490 host_tempreg_release();
3493 else if (stall > 0) {
3494 //emit_log_gte_stall(i, stall, reglist);
3495 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3498 // save gteBusyCycle, if needed
3499 if (gte_cycletab[op] == 0)
3501 other_gte_op_cycles = -1;
3502 for (j = i + 1; j < slen; j++) {
3503 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3505 if (dops[j].is_jump) {
3507 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3512 if (other_gte_op_cycles >= 0)
3513 // will handle stall when assembling that op
3515 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
3516 if (cycles_passed >= 44)
3518 assem_debug("; save gteBusyCycle\n");
3519 host_tempreg_acquire();
3521 emit_readword(&last_count, HOST_TEMPREG);
3522 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3523 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
3524 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3525 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3527 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
3528 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3530 host_tempreg_release();
3533 static int is_mflohi(int i)
3535 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3538 static int check_multdiv(int i, int *cycles)
3540 if (dops[i].itype != MULTDIV)
3542 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3543 *cycles = 11; // approx from 7 11 14
3549 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3551 int j, found = 0, c = 0;
3552 if (HACK_ENABLED(NDHACK_NO_STALLS))
3554 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3555 // happens occasionally... cc evicted? Don't bother then
3558 for (j = i + 1; j < slen; j++) {
3561 if ((found = is_mflohi(j)))
3563 if (dops[j].is_jump) {
3565 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3571 // handle all in multdiv_do_stall()
3573 check_multdiv(i, &c);
3575 assem_debug("; muldiv prepare stall %d\n", c);
3576 host_tempreg_acquire();
3577 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3578 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3579 host_tempreg_release();
3582 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3584 int j, known_cycles = 0;
3585 u_int reglist = get_host_reglist(i_regs->regmap);
3586 int rtmp = get_reg(i_regs->regmap, -1);
3588 rtmp = reglist_find_free(reglist);
3589 if (HACK_ENABLED(NDHACK_NO_STALLS))
3591 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3592 // happens occasionally... cc evicted? Don't bother then
3593 //printf("no cc/rtmp %08x\n", start + i*4);
3597 for (j = i - 1; j >= 0; j--) {
3598 if (dops[j].is_ds) break;
3599 if (check_multdiv(j, &known_cycles))
3602 // already handled by this op
3604 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3609 if (known_cycles > 0) {
3610 known_cycles -= ccadj[i] - ccadj[j];
3611 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3612 if (known_cycles > 0)
3613 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3616 assem_debug("; muldiv stall unresolved\n");
3617 host_tempreg_acquire();
3618 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3619 emit_addimm(rtmp, -ccadj[i], rtmp);
3620 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3621 emit_cmpimm(HOST_TEMPREG, 37);
3622 emit_cmovb_reg(rtmp, HOST_CCREG);
3623 //emit_log_gte_stall(i, 0, reglist);
3624 host_tempreg_release();
3627 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3637 emit_readword(®_cop2d[copr],tl);
3638 emit_signextend16(tl,tl);
3639 emit_writeword(tl,®_cop2d[copr]); // hmh
3646 emit_readword(®_cop2d[copr],tl);
3647 emit_andimm(tl,0xffff,tl);
3648 emit_writeword(tl,®_cop2d[copr]);
3651 emit_readword(®_cop2d[14],tl); // SXY2
3652 emit_writeword(tl,®_cop2d[copr]);
3656 c2op_mfc2_29_assemble(tl,temp);
3659 emit_readword(®_cop2d[copr],tl);
3664 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3668 emit_readword(®_cop2d[13],temp); // SXY1
3669 emit_writeword(sl,®_cop2d[copr]);
3670 emit_writeword(temp,®_cop2d[12]); // SXY0
3671 emit_readword(®_cop2d[14],temp); // SXY2
3672 emit_writeword(sl,®_cop2d[14]);
3673 emit_writeword(temp,®_cop2d[13]); // SXY1
3676 emit_andimm(sl,0x001f,temp);
3677 emit_shlimm(temp,7,temp);
3678 emit_writeword(temp,®_cop2d[9]);
3679 emit_andimm(sl,0x03e0,temp);
3680 emit_shlimm(temp,2,temp);
3681 emit_writeword(temp,®_cop2d[10]);
3682 emit_andimm(sl,0x7c00,temp);
3683 emit_shrimm(temp,3,temp);
3684 emit_writeword(temp,®_cop2d[11]);
3685 emit_writeword(sl,®_cop2d[28]);
3688 emit_xorsar_imm(sl,sl,31,temp);
3689 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3690 emit_clz(temp,temp);
3692 emit_movs(temp,HOST_TEMPREG);
3693 emit_movimm(0,temp);
3694 emit_jeq((int)out+4*4);
3695 emit_addpl_imm(temp,1,temp);
3696 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3697 emit_jns((int)out-2*4);
3699 emit_writeword(sl,®_cop2d[30]);
3700 emit_writeword(temp,®_cop2d[31]);
3705 emit_writeword(sl,®_cop2d[copr]);
3710 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3715 int memtarget=0,c=0;
3717 enum stub_type type;
3718 int agr=AGEN1+(i&1);
3719 int offset_reg = -1;
3720 int fastio_reg_override = -1;
3721 u_int reglist=get_host_reglist(i_regs->regmap);
3722 u_int copr=(source[i]>>16)&0x1f;
3723 s=get_reg(i_regs->regmap,dops[i].rs1);
3724 tl=get_reg(i_regs->regmap,FTEMP);
3726 assert(dops[i].rs1>0);
3729 if(i_regs->regmap[HOST_CCREG]==CCREG)
3730 reglist&=~(1<<HOST_CCREG);
3733 if (dops[i].opcode==0x3a) { // SWC2
3734 ar=get_reg(i_regs->regmap,agr);
3735 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3740 if(s>=0) c=(i_regs->wasconst>>s)&1;
3741 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3742 if (!offset&&!c&&s>=0) ar=s;
3745 cop2_do_stall_check(0, i, i_regs, reglist);
3747 if (dops[i].opcode==0x3a) { // SWC2
3748 cop2_get_dreg(copr,tl,-1);
3756 emit_jmp(0); // inline_readstub/inline_writestub?
3760 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3761 &offset_reg, &fastio_reg_override);
3763 else if (ram_offset && memtarget) {
3764 offset_reg = get_ro_reg(i_regs, 0);
3766 switch (dops[i].opcode) {
3767 case 0x32: { // LWC2
3769 if (fastio_reg_override >= 0)
3770 a = fastio_reg_override;
3771 do_load_word(a, tl, offset_reg);
3774 case 0x3a: { // SWC2
3775 #ifdef DESTRUCTIVE_SHIFT
3776 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3779 if (fastio_reg_override >= 0)
3780 a = fastio_reg_override;
3781 do_store_word(a, 0, tl, offset_reg, 1);
3788 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3789 host_tempreg_release();
3791 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3792 if(dops[i].opcode==0x3a) // SWC2
3793 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3794 #if defined(HOST_IMM8)
3795 int ir=get_reg(i_regs->regmap,INVCP);
3797 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3799 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3801 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3802 emit_callne(invalidate_addr_reg[ar]);
3806 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3809 if (dops[i].opcode==0x32) { // LWC2
3810 host_tempreg_acquire();
3811 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3812 host_tempreg_release();
3816 static void cop2_assemble(int i, const struct regstat *i_regs)
3818 u_int copr = (source[i]>>11) & 0x1f;
3819 signed char temp = get_reg(i_regs->regmap, -1);
3821 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3822 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3823 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3824 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3825 reglist = reglist_exclude(reglist, tl, -1);
3827 cop2_do_stall_check(0, i, i_regs, reglist);
3829 if (dops[i].opcode2==0) { // MFC2
3830 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3831 if(tl>=0&&dops[i].rt1!=0)
3832 cop2_get_dreg(copr,tl,temp);
3834 else if (dops[i].opcode2==4) { // MTC2
3835 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3836 cop2_put_dreg(copr,sl,temp);
3838 else if (dops[i].opcode2==2) // CFC2
3840 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3841 if(tl>=0&&dops[i].rt1!=0)
3842 emit_readword(®_cop2c[copr],tl);
3844 else if (dops[i].opcode2==6) // CTC2
3846 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3855 emit_signextend16(sl,temp);
3858 c2op_ctc2_31_assemble(sl,temp);
3864 emit_writeword(temp,®_cop2c[copr]);
3869 static void do_unalignedwritestub(int n)
3871 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3873 set_jump_target(stubs[n].addr, out);
3876 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3877 int addr=stubs[n].b;
3878 u_int reglist=stubs[n].e;
3879 signed char *i_regmap=i_regs->regmap;
3880 int temp2=get_reg(i_regmap,FTEMP);
3882 rt=get_reg(i_regmap,dops[i].rs2);
3885 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3887 reglist&=~(1<<temp2);
3889 // don't bother with it and call write handler
3892 int cc=get_reg(i_regmap,CCREG);
3894 emit_loadreg(CCREG,2);
3895 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
3896 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
3897 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3899 emit_storereg(CCREG,2);
3900 restore_regs(reglist);
3901 emit_jmp(stubs[n].retaddr); // return address
3904 #ifndef multdiv_assemble
3905 void multdiv_assemble(int i,struct regstat *i_regs)
3907 printf("Need multdiv_assemble for this architecture.\n");
3912 static void mov_assemble(int i, const struct regstat *i_regs)
3914 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3915 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3918 tl=get_reg(i_regs->regmap,dops[i].rt1);
3921 sl=get_reg(i_regs->regmap,dops[i].rs1);
3922 if(sl>=0) emit_mov(sl,tl);
3923 else emit_loadreg(dops[i].rs1,tl);
3926 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
3927 multdiv_do_stall(i, i_regs);
3930 // call interpreter, exception handler, things that change pc/regs/cycles ...
3931 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
3933 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3934 assert(ccreg==HOST_CCREG);
3935 assert(!is_delayslot);
3938 emit_movimm(pc,3); // Get PC
3939 emit_readword(&last_count,2);
3940 emit_writeword(3,&psxRegs.pc);
3941 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3942 emit_add(2,HOST_CCREG,2);
3943 emit_writeword(2,&psxRegs.cycle);
3944 emit_far_call(func);
3945 emit_far_jump(jump_to_new_pc);
3948 static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3950 // 'break' tends to be littered around to catch things like
3951 // division by 0 and is almost never executed, so don't emit much code here
3952 void *func = (dops[i].opcode2 == 0x0C)
3953 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
3954 : (is_delayslot ? jump_break_ds : jump_break);
3955 signed char ccreg = get_reg(i_regs->regmap, CCREG);
3956 assert(ccreg == HOST_CCREG);
3957 emit_movimm(start + i*4, 2); // pc
3958 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
3959 emit_far_jump(func);
3962 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3964 void *hlefunc = psxNULL;
3965 uint32_t hleCode = source[i] & 0x03ffffff;
3966 if (hleCode < ARRAY_SIZE(psxHLEt))
3967 hlefunc = psxHLEt[hleCode];
3969 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
3972 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
3974 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
3977 static void speculate_mov(int rs,int rt)
3980 smrv_strong_next|=1<<rt;
3985 static void speculate_mov_weak(int rs,int rt)
3988 smrv_weak_next|=1<<rt;
3993 static void speculate_register_values(int i)
3996 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3997 // gp,sp are likely to stay the same throughout the block
3998 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3999 smrv_weak_next=~smrv_strong_next;
4000 //printf(" llr %08x\n", smrv[4]);
4002 smrv_strong=smrv_strong_next;
4003 smrv_weak=smrv_weak_next;
4004 switch(dops[i].itype) {
4006 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4007 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4008 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4009 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4011 smrv_strong_next&=~(1<<dops[i].rt1);
4012 smrv_weak_next&=~(1<<dops[i].rt1);
4016 smrv_strong_next&=~(1<<dops[i].rt1);
4017 smrv_weak_next&=~(1<<dops[i].rt1);
4020 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
4021 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
4023 if(get_final_value(hr,i,&value))
4024 smrv[dops[i].rt1]=value;
4025 else smrv[dops[i].rt1]=constmap[i][hr];
4026 smrv_strong_next|=1<<dops[i].rt1;
4030 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4031 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4035 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4036 // special case for BIOS
4037 smrv[dops[i].rt1]=0xa0000000;
4038 smrv_strong_next|=1<<dops[i].rt1;
4045 smrv_strong_next&=~(1<<dops[i].rt1);
4046 smrv_weak_next&=~(1<<dops[i].rt1);
4050 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4051 smrv_strong_next&=~(1<<dops[i].rt1);
4052 smrv_weak_next&=~(1<<dops[i].rt1);
4056 if (dops[i].opcode==0x32) { // LWC2
4057 smrv_strong_next&=~(1<<dops[i].rt1);
4058 smrv_weak_next&=~(1<<dops[i].rt1);
4064 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4065 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4069 static void ujump_assemble(int i, const struct regstat *i_regs);
4070 static void rjump_assemble(int i, const struct regstat *i_regs);
4071 static void cjump_assemble(int i, const struct regstat *i_regs);
4072 static void sjump_assemble(int i, const struct regstat *i_regs);
4073 static void pagespan_assemble(int i, const struct regstat *i_regs);
4075 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4078 switch (dops[i].itype) {
4080 alu_assemble(i, i_regs);
4083 imm16_assemble(i, i_regs);
4086 shift_assemble(i, i_regs);
4089 shiftimm_assemble(i, i_regs);
4092 load_assemble(i, i_regs, ccadj_);
4095 loadlr_assemble(i, i_regs, ccadj_);
4098 store_assemble(i, i_regs, ccadj_);
4101 storelr_assemble(i, i_regs, ccadj_);
4104 cop0_assemble(i, i_regs, ccadj_);
4107 cop1_assemble(i, i_regs);
4110 c1ls_assemble(i, i_regs);
4113 cop2_assemble(i, i_regs);
4116 c2ls_assemble(i, i_regs, ccadj_);
4119 c2op_assemble(i, i_regs);
4122 multdiv_assemble(i, i_regs);
4123 multdiv_prepare_stall(i, i_regs, ccadj_);
4126 mov_assemble(i, i_regs);
4129 syscall_assemble(i, i_regs, ccadj_);
4132 hlecall_assemble(i, i_regs, ccadj_);
4135 intcall_assemble(i, i_regs, ccadj_);
4138 ujump_assemble(i, i_regs);
4142 rjump_assemble(i, i_regs);
4146 cjump_assemble(i, i_regs);
4150 sjump_assemble(i, i_regs);
4154 pagespan_assemble(i, i_regs);
4159 // not handled, just skip
4167 static void ds_assemble(int i, const struct regstat *i_regs)
4169 speculate_register_values(i);
4171 switch (dops[i].itype) {
4180 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4183 assemble(i, i_regs, ccadj[i]);
4188 // Is the branch target a valid internal jump?
4189 static int internal_branch(int addr)
4191 if(addr&1) return 0; // Indirect (register) jump
4192 if(addr>=start && addr<start+slen*4-4)
4199 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4202 for(hr=0;hr<HOST_REGS;hr++) {
4203 if(hr!=EXCLUDE_REG) {
4204 if(pre[hr]!=entry[hr]) {
4207 if(get_reg(entry,pre[hr])<0) {
4209 if(!((u>>pre[hr])&1))
4210 emit_storereg(pre[hr],hr);
4217 // Move from one register to another (no writeback)
4218 for(hr=0;hr<HOST_REGS;hr++) {
4219 if(hr!=EXCLUDE_REG) {
4220 if(pre[hr]!=entry[hr]) {
4221 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4223 if((nr=get_reg(entry,pre[hr]))>=0) {
4232 // Load the specified registers
4233 // This only loads the registers given as arguments because
4234 // we don't want to load things that will be overwritten
4235 static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
4239 for(hr=0;hr<HOST_REGS;hr++) {
4240 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4241 if(entry[hr]!=regmap[hr]) {
4242 if(regmap[hr]==rs1||regmap[hr]==rs2)
4249 emit_loadreg(regmap[hr],hr);
4257 // Load registers prior to the start of a loop
4258 // so that they are not loaded within the loop
4259 static void loop_preload(signed char pre[],signed char entry[])
4262 for(hr=0;hr<HOST_REGS;hr++) {
4263 if(hr!=EXCLUDE_REG) {
4264 if(pre[hr]!=entry[hr]) {
4266 if(get_reg(pre,entry[hr])<0) {
4267 assem_debug("loop preload:\n");
4268 //printf("loop preload: %d\n",hr);
4272 else if(entry[hr]<TEMPREG)
4274 emit_loadreg(entry[hr],hr);
4276 else if(entry[hr]-64<TEMPREG)
4278 emit_loadreg(entry[hr],hr);
4287 // Generate address for load/store instruction
4288 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4289 void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4291 if (dops[i].is_load || dops[i].is_store) {
4293 int agr=AGEN1+(i&1);
4294 if(dops[i].itype==LOAD) {
4295 ra=get_reg(i_regs->regmap,dops[i].rt1);
4296 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4299 if(dops[i].itype==LOADLR) {
4300 ra=get_reg(i_regs->regmap,FTEMP);
4302 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4303 ra=get_reg(i_regs->regmap,agr);
4304 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4306 if(dops[i].itype==C2LS) {
4307 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4308 ra=get_reg(i_regs->regmap,FTEMP);
4309 else { // SWC1/SDC1/SWC2/SDC2
4310 ra=get_reg(i_regs->regmap,agr);
4311 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4314 int rs=get_reg(i_regs->regmap,dops[i].rs1);
4317 int c=(i_regs->wasconst>>rs)&1;
4318 if(dops[i].rs1==0) {
4319 // Using r0 as a base address
4320 if(!entry||entry[ra]!=agr) {
4321 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4322 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4323 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4324 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4326 emit_movimm(offset,ra);
4328 } // else did it in the previous cycle
4331 if(!entry||entry[ra]!=dops[i].rs1)
4332 emit_loadreg(dops[i].rs1,ra);
4333 //if(!entry||entry[ra]!=dops[i].rs1)
4334 // printf("poor load scheduling!\n");
4337 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4338 if(!entry||entry[ra]!=agr) {
4339 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4340 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4341 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4342 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4344 emit_movimm(constmap[i][rs]+offset,ra);
4345 regs[i].loadedconst|=1<<ra;
4347 } // else did it in the previous cycle
4348 } // else load_consts already did it
4350 if(offset&&!c&&dops[i].rs1) {
4352 emit_addimm(rs,offset,ra);
4354 emit_addimm(ra,offset,ra);
4359 // Preload constants for next instruction
4360 if (dops[i+1].is_load || dops[i+1].is_store) {
4363 agr=AGEN1+((i+1)&1);
4364 ra=get_reg(i_regs->regmap,agr);
4366 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4367 int offset=imm[i+1];
4368 int c=(regs[i+1].wasconst>>rs)&1;
4369 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4370 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4371 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4372 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4373 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4375 emit_movimm(constmap[i+1][rs]+offset,ra);
4376 regs[i+1].loadedconst|=1<<ra;
4379 else if(dops[i+1].rs1==0) {
4380 // Using r0 as a base address
4381 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4382 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4383 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4384 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4386 emit_movimm(offset,ra);
4393 static int get_final_value(int hr, int i, int *value)
4395 int reg=regs[i].regmap[hr];
4397 if(regs[i+1].regmap[hr]!=reg) break;
4398 if(!((regs[i+1].isconst>>hr)&1)) break;
4399 if(dops[i+1].bt) break;
4403 if (dops[i].is_jump) {
4404 *value=constmap[i][hr];
4408 if (dops[i+1].is_jump) {
4409 // Load in delay slot, out-of-order execution
4410 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4412 // Precompute load address
4413 *value=constmap[i][hr]+imm[i+2];
4417 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4419 // Precompute load address
4420 *value=constmap[i][hr]+imm[i+1];
4421 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4426 *value=constmap[i][hr];
4427 //printf("c=%lx\n",(long)constmap[i][hr]);
4428 if(i==slen-1) return 1;
4430 return !((unneeded_reg[i+1]>>reg)&1);
4433 // Load registers with known constants
4434 static void load_consts(signed char pre[],signed char regmap[],int i)
4437 // propagate loaded constant flags
4438 if(i==0||dops[i].bt)
4439 regs[i].loadedconst=0;
4441 for(hr=0;hr<HOST_REGS;hr++) {
4442 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4443 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4445 regs[i].loadedconst|=1<<hr;
4450 for(hr=0;hr<HOST_REGS;hr++) {
4451 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4452 //if(entry[hr]!=regmap[hr]) {
4453 if(!((regs[i].loadedconst>>hr)&1)) {
4454 assert(regmap[hr]<64);
4455 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4456 int value,similar=0;
4457 if(get_final_value(hr,i,&value)) {
4458 // see if some other register has similar value
4459 for(hr2=0;hr2<HOST_REGS;hr2++) {
4460 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4461 if(is_similar_value(value,constmap[i][hr2])) {
4469 if(get_final_value(hr2,i,&value2)) // is this needed?
4470 emit_movimm_from(value2,hr2,value,hr);
4472 emit_movimm(value,hr);
4478 emit_movimm(value,hr);
4481 regs[i].loadedconst|=1<<hr;
4488 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4492 for(hr=0;hr<HOST_REGS;hr++) {
4493 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4494 assert(regmap[hr] < 64);
4495 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4496 int value=constmap[i][hr];
4501 emit_movimm(value,hr);
4508 // Write out all dirty registers (except cycle count)
4509 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4512 for(hr=0;hr<HOST_REGS;hr++) {
4513 if(hr!=EXCLUDE_REG) {
4514 if(i_regmap[hr]>0) {
4515 if(i_regmap[hr]!=CCREG) {
4516 if((i_dirty>>hr)&1) {
4517 assert(i_regmap[hr]<64);
4518 emit_storereg(i_regmap[hr],hr);
4526 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4527 // This writes the registers not written by store_regs_bt
4528 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4531 int t=(addr-start)>>2;
4532 for(hr=0;hr<HOST_REGS;hr++) {
4533 if(hr!=EXCLUDE_REG) {
4534 if(i_regmap[hr]>0) {
4535 if(i_regmap[hr]!=CCREG) {
4536 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4537 if((i_dirty>>hr)&1) {
4538 assert(i_regmap[hr]<64);
4539 emit_storereg(i_regmap[hr],hr);
4548 // Load all registers (except cycle count)
4549 static void load_all_regs(const signed char i_regmap[])
4552 for(hr=0;hr<HOST_REGS;hr++) {
4553 if(hr!=EXCLUDE_REG) {
4554 if(i_regmap[hr]==0) {
4558 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4560 emit_loadreg(i_regmap[hr],hr);
4566 // Load all current registers also needed by next instruction
4567 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4570 for(hr=0;hr<HOST_REGS;hr++) {
4571 if(hr!=EXCLUDE_REG) {
4572 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4573 if(i_regmap[hr]==0) {
4577 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4579 emit_loadreg(i_regmap[hr],hr);
4586 // Load all regs, storing cycle count if necessary
4587 static void load_regs_entry(int t)
4590 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4591 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
4592 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4593 emit_storereg(CCREG,HOST_CCREG);
4596 for(hr=0;hr<HOST_REGS;hr++) {
4597 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4598 if(regs[t].regmap_entry[hr]==0) {
4601 else if(regs[t].regmap_entry[hr]!=CCREG)
4603 emit_loadreg(regs[t].regmap_entry[hr],hr);
4609 // Store dirty registers prior to branch
4610 void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4612 if(internal_branch(addr))
4614 int t=(addr-start)>>2;
4616 for(hr=0;hr<HOST_REGS;hr++) {
4617 if(hr!=EXCLUDE_REG) {
4618 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4619 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4620 if((i_dirty>>hr)&1) {
4621 assert(i_regmap[hr]<64);
4622 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4623 emit_storereg(i_regmap[hr],hr);
4632 // Branch out of this block, write out all dirty regs
4633 wb_dirtys(i_regmap,i_dirty);
4637 // Load all needed registers for branch target
4638 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4640 //if(addr>=start && addr<(start+slen*4))
4641 if(internal_branch(addr))
4643 int t=(addr-start)>>2;
4645 // Store the cycle count before loading something else
4646 if(i_regmap[HOST_CCREG]!=CCREG) {
4647 assert(i_regmap[HOST_CCREG]==-1);
4649 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4650 emit_storereg(CCREG,HOST_CCREG);
4653 for(hr=0;hr<HOST_REGS;hr++) {
4654 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4655 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4656 if(regs[t].regmap_entry[hr]==0) {
4659 else if(regs[t].regmap_entry[hr]!=CCREG)
4661 emit_loadreg(regs[t].regmap_entry[hr],hr);
4669 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4671 if(addr>=start && addr<start+slen*4-4)
4673 int t=(addr-start)>>2;
4675 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4676 for(hr=0;hr<HOST_REGS;hr++)
4680 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4682 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4689 if(i_regmap[hr]<TEMPREG)
4691 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4694 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4700 else // Same register but is it 32-bit or dirty?
4703 if(!((regs[t].dirty>>hr)&1))
4707 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4709 //printf("%x: dirty no match\n",addr);
4717 // Delay slots are not valid branch targets
4718 //if(t>0&&(dops[t-1].is_jump) return 0;
4719 // Delay slots require additional processing, so do not match
4720 if(dops[t].is_ds) return 0;
4725 for(hr=0;hr<HOST_REGS;hr++)
4731 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4746 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4748 extern void do_insn_cmp();
4750 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4752 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4754 // write out changed consts to match the interpreter
4755 if (i > 0 && !dops[i].bt) {
4756 for (hr = 0; hr < HOST_REGS; hr++) {
4757 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4758 if (hr == EXCLUDE_REG || reg < 0)
4760 if (!((regs[i-1].isconst >> hr) & 1))
4762 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4764 emit_movimm(constmap[i-1][hr],0);
4765 emit_storereg(reg, 0);
4768 emit_movimm(start+i*4,0);
4769 emit_writeword(0,&pcaddr);
4770 int cc = get_reg(regs[i].regmap_entry, CCREG);
4772 emit_loadreg(CCREG, cc = 0);
4773 emit_addimm(cc, ccadj_, 0);
4774 emit_writeword(0, &psxRegs.cycle);
4775 emit_far_call(do_insn_cmp);
4776 //emit_readword(&cycle,0);
4777 //emit_addimm(0,2,0);
4778 //emit_writeword(0,&cycle);
4780 restore_regs(reglist);
4781 assem_debug("\\\\do_insn_cmp\n");
4784 #define drc_dbg_emit_do_cmp(x,y)
4787 // Used when a branch jumps into the delay slot of another branch
4788 static void ds_assemble_entry(int i)
4790 int t = (ba[i] - start) >> 2;
4791 int ccadj_ = -CLOCK_ADJUST(1);
4793 instr_addr[t] = out;
4794 assem_debug("Assemble delay slot at %x\n",ba[i]);
4795 assem_debug("<->\n");
4796 drc_dbg_emit_do_cmp(t, ccadj_);
4797 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4798 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4799 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4800 address_generation(t,®s[t],regs[t].regmap_entry);
4801 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4802 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4803 if (dops[t].is_store)
4804 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
4806 switch (dops[t].itype) {
4815 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4818 assemble(t, ®s[t], ccadj_);
4820 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4821 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4822 if(internal_branch(ba[i]+4))
4823 assem_debug("branch: internal\n");
4825 assem_debug("branch: external\n");
4826 assert(internal_branch(ba[i]+4));
4827 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4831 static void emit_extjump(void *addr, u_int target)
4833 emit_extjump2(addr, target, dyna_linker);
4836 static void emit_extjump_ds(void *addr, u_int target)
4838 emit_extjump2(addr, target, dyna_linker_ds);
4841 // Load 2 immediates optimizing for small code size
4842 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4844 emit_movimm(imm1,rt1);
4845 emit_movimm_from(imm1,rt1,imm2,rt2);
4848 static void do_cc(int i, const signed char i_regmap[], int *adj,
4849 int addr, int taken, int invert)
4851 int count, count_plus2;
4855 if(dops[i].itype==RJUMP)
4859 //if(ba[i]>=start && ba[i]<(start+slen*4))
4860 if(internal_branch(ba[i]))
4863 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
4871 count_plus2 = count + CLOCK_ADJUST(2);
4872 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4874 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4876 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4877 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4881 else if(*adj==0||invert) {
4882 int cycles = count_plus2;
4887 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4888 cycles=*adj+count+2-*adj;
4891 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4897 emit_cmpimm(HOST_CCREG, -count_plus2);
4901 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
4904 static void do_ccstub(int n)
4907 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4908 set_jump_target(stubs[n].addr, out);
4910 if(stubs[n].d==NULLDS) {
4911 // Delay slot instruction is nullified ("likely" branch)
4912 wb_dirtys(regs[i].regmap,regs[i].dirty);
4914 else if(stubs[n].d!=TAKEN) {
4915 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4918 if(internal_branch(ba[i]))
4919 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4923 // Save PC as return address
4924 emit_movimm(stubs[n].c,EAX);
4925 emit_writeword(EAX,&pcaddr);
4929 // Return address depends on which way the branch goes
4930 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
4932 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4933 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4939 else if(dops[i].rs2==0)
4944 #ifdef DESTRUCTIVE_WRITEBACK
4946 if((branch_regs[i].dirty>>s1l)&&1)
4947 emit_loadreg(dops[i].rs1,s1l);
4950 if((branch_regs[i].dirty>>s1l)&1)
4951 emit_loadreg(dops[i].rs2,s1l);
4954 if((branch_regs[i].dirty>>s2l)&1)
4955 emit_loadreg(dops[i].rs2,s2l);
4958 int addr=-1,alt=-1,ntaddr=-1;
4961 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4962 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4963 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4971 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4972 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4973 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4979 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
4983 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4984 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4985 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4991 assert(hr<HOST_REGS);
4993 if((dops[i].opcode&0x2f)==4) // BEQ
4995 #ifdef HAVE_CMOV_IMM
4996 if(s2l>=0) emit_cmp(s1l,s2l);
4997 else emit_test(s1l,s1l);
4998 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5000 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5001 if(s2l>=0) emit_cmp(s1l,s2l);
5002 else emit_test(s1l,s1l);
5003 emit_cmovne_reg(alt,addr);
5006 if((dops[i].opcode&0x2f)==5) // BNE
5008 #ifdef HAVE_CMOV_IMM
5009 if(s2l>=0) emit_cmp(s1l,s2l);
5010 else emit_test(s1l,s1l);
5011 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5013 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5014 if(s2l>=0) emit_cmp(s1l,s2l);
5015 else emit_test(s1l,s1l);
5016 emit_cmovne_reg(alt,addr);
5019 if((dops[i].opcode&0x2f)==6) // BLEZ
5021 //emit_movimm(ba[i],alt);
5022 //emit_movimm(start+i*4+8,addr);
5023 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5025 emit_cmovl_reg(alt,addr);
5027 if((dops[i].opcode&0x2f)==7) // BGTZ
5029 //emit_movimm(ba[i],addr);
5030 //emit_movimm(start+i*4+8,ntaddr);
5031 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5033 emit_cmovl_reg(ntaddr,addr);
5035 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
5037 //emit_movimm(ba[i],alt);
5038 //emit_movimm(start+i*4+8,addr);
5039 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5041 emit_cmovs_reg(alt,addr);
5043 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
5045 //emit_movimm(ba[i],addr);
5046 //emit_movimm(start+i*4+8,alt);
5047 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5049 emit_cmovs_reg(alt,addr);
5051 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5052 if(source[i]&0x10000) // BC1T
5054 //emit_movimm(ba[i],alt);
5055 //emit_movimm(start+i*4+8,addr);
5056 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5057 emit_testimm(s1l,0x800000);
5058 emit_cmovne_reg(alt,addr);
5062 //emit_movimm(ba[i],addr);
5063 //emit_movimm(start+i*4+8,alt);
5064 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5065 emit_testimm(s1l,0x800000);
5066 emit_cmovne_reg(alt,addr);
5069 emit_writeword(addr,&pcaddr);
5072 if(dops[i].itype==RJUMP)
5074 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5075 if (ds_writes_rjump_rs(i)) {
5076 r=get_reg(branch_regs[i].regmap,RTEMP);
5078 emit_writeword(r,&pcaddr);
5080 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5082 // Update cycle count
5083 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5084 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5085 emit_far_call(cc_interrupt);
5086 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5087 if(stubs[n].d==TAKEN) {
5088 if(internal_branch(ba[i]))
5089 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5090 else if(dops[i].itype==RJUMP) {
5091 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5092 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5094 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5096 }else if(stubs[n].d==NOTTAKEN) {
5097 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5098 else load_all_regs(branch_regs[i].regmap);
5099 }else if(stubs[n].d==NULLDS) {
5100 // Delay slot instruction is nullified ("likely" branch)
5101 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5102 else load_all_regs(regs[i].regmap);
5104 load_all_regs(branch_regs[i].regmap);
5106 if (stubs[n].retaddr)
5107 emit_jmp(stubs[n].retaddr);
5109 do_jump_vaddr(stubs[n].e);
5112 static void add_to_linker(void *addr, u_int target, int ext)
5114 assert(linkcount < ARRAY_SIZE(link_addr));
5115 link_addr[linkcount].addr = addr;
5116 link_addr[linkcount].target = target;
5117 link_addr[linkcount].ext = ext;
5121 static void ujump_assemble_write_ra(int i)
5124 unsigned int return_address;
5125 rt=get_reg(branch_regs[i].regmap,31);
5126 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5128 return_address=start+i*4+8;
5131 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5132 int temp=-1; // note: must be ds-safe
5136 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5137 else emit_movimm(return_address,rt);
5145 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5148 emit_movimm(return_address,rt); // PC into link register
5150 emit_prefetch(hash_table_get(return_address));
5156 static void ujump_assemble(int i, const struct regstat *i_regs)
5159 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5160 address_generation(i+1,i_regs,regs[i].regmap_entry);
5162 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5163 if(dops[i].rt1==31&&temp>=0)
5165 signed char *i_regmap=i_regs->regmap;
5166 int return_address=start+i*4+8;
5167 if(get_reg(branch_regs[i].regmap,31)>0)
5168 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5171 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5172 ujump_assemble_write_ra(i); // writeback ra for DS
5175 ds_assemble(i+1,i_regs);
5176 uint64_t bc_unneeded=branch_regs[i].u;
5177 bc_unneeded|=1|(1LL<<dops[i].rt1);
5178 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5179 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5180 if(!ra_done&&dops[i].rt1==31)
5181 ujump_assemble_write_ra(i);
5183 cc=get_reg(branch_regs[i].regmap,CCREG);
5184 assert(cc==HOST_CCREG);
5185 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5187 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5189 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5190 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5191 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5192 if(internal_branch(ba[i]))
5193 assem_debug("branch: internal\n");
5195 assem_debug("branch: external\n");
5196 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5197 ds_assemble_entry(i);
5200 add_to_linker(out,ba[i],internal_branch(ba[i]));
5205 static void rjump_assemble_write_ra(int i)
5207 int rt,return_address;
5208 assert(dops[i+1].rt1!=dops[i].rt1);
5209 assert(dops[i+1].rt2!=dops[i].rt1);
5210 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5211 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5213 return_address=start+i*4+8;
5217 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5220 emit_movimm(return_address,rt); // PC into link register
5222 emit_prefetch(hash_table_get(return_address));
5226 static void rjump_assemble(int i, const struct regstat *i_regs)
5231 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5233 if (ds_writes_rjump_rs(i)) {
5234 // Delay slot abuse, make a copy of the branch address register
5235 temp=get_reg(branch_regs[i].regmap,RTEMP);
5237 assert(regs[i].regmap[temp]==RTEMP);
5241 address_generation(i+1,i_regs,regs[i].regmap_entry);
5245 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5246 signed char *i_regmap=i_regs->regmap;
5247 int return_address=start+i*4+8;
5248 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5253 if(dops[i].rs1==31) {
5254 int rh=get_reg(regs[i].regmap,RHASH);
5255 if(rh>=0) do_preload_rhash(rh);
5258 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5259 rjump_assemble_write_ra(i);
5262 ds_assemble(i+1,i_regs);
5263 uint64_t bc_unneeded=branch_regs[i].u;
5264 bc_unneeded|=1|(1LL<<dops[i].rt1);
5265 bc_unneeded&=~(1LL<<dops[i].rs1);
5266 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5267 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5268 if(!ra_done&&dops[i].rt1!=0)
5269 rjump_assemble_write_ra(i);
5270 cc=get_reg(branch_regs[i].regmap,CCREG);
5271 assert(cc==HOST_CCREG);
5274 int rh=get_reg(branch_regs[i].regmap,RHASH);
5275 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5276 if(dops[i].rs1==31) {
5277 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5278 do_preload_rhtbl(ht);
5282 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5283 #ifdef DESTRUCTIVE_WRITEBACK
5284 if((branch_regs[i].dirty>>rs)&1) {
5285 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5286 emit_loadreg(dops[i].rs1,rs);
5291 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5294 if(dops[i].rs1==31) {
5295 do_miniht_load(ht,rh);
5298 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5299 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5301 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5302 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5303 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
5304 // special case for RFE
5308 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5310 if(dops[i].rs1==31) {
5311 do_miniht_jump(rs,rh,ht);
5318 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5319 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5323 static void cjump_assemble(int i, const struct regstat *i_regs)
5325 const signed char *i_regmap = i_regs->regmap;
5328 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5329 assem_debug("match=%d\n",match);
5331 int unconditional=0,nop=0;
5333 int internal=internal_branch(ba[i]);
5334 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5335 if(!match) invert=1;
5336 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5337 if(i>(ba[i]-start)>>2) invert=1;
5340 invert=1; // because of near cond. branches
5344 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5345 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5348 s1l=get_reg(i_regmap,dops[i].rs1);
5349 s2l=get_reg(i_regmap,dops[i].rs2);
5351 if(dops[i].rs1==0&&dops[i].rs2==0)
5353 if(dops[i].opcode&1) nop=1;
5354 else unconditional=1;
5355 //assert(dops[i].opcode!=5);
5356 //assert(dops[i].opcode!=7);
5357 //assert(dops[i].opcode!=0x15);
5358 //assert(dops[i].opcode!=0x17);
5360 else if(dops[i].rs1==0)
5365 else if(dops[i].rs2==0)
5371 // Out of order execution (delay slot first)
5373 address_generation(i+1,i_regs,regs[i].regmap_entry);
5374 ds_assemble(i+1,i_regs);
5376 uint64_t bc_unneeded=branch_regs[i].u;
5377 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5379 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5380 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5381 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5382 cc=get_reg(branch_regs[i].regmap,CCREG);
5383 assert(cc==HOST_CCREG);
5385 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5386 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5387 //assem_debug("cycle count (adj)\n");
5389 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5390 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5391 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5392 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5394 assem_debug("branch: internal\n");
5396 assem_debug("branch: external\n");
5397 if (internal && dops[(ba[i]-start)>>2].is_ds) {
5398 ds_assemble_entry(i);
5401 add_to_linker(out,ba[i],internal);
5404 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5405 if(((u_int)out)&7) emit_addnop(0);
5410 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5413 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5416 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5417 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5418 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5420 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5422 if(dops[i].opcode==4) // BEQ
5424 if(s2l>=0) emit_cmp(s1l,s2l);
5425 else emit_test(s1l,s1l);
5430 add_to_linker(out,ba[i],internal);
5434 if(dops[i].opcode==5) // BNE
5436 if(s2l>=0) emit_cmp(s1l,s2l);
5437 else emit_test(s1l,s1l);
5442 add_to_linker(out,ba[i],internal);
5446 if(dops[i].opcode==6) // BLEZ
5453 add_to_linker(out,ba[i],internal);
5457 if(dops[i].opcode==7) // BGTZ
5464 add_to_linker(out,ba[i],internal);
5469 if(taken) set_jump_target(taken, out);
5470 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5471 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5473 emit_addimm(cc,-adj,cc);
5474 add_to_linker(out,ba[i],internal);
5477 add_to_linker(out,ba[i],internal*2);
5483 if(adj) emit_addimm(cc,-adj,cc);
5484 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5485 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5487 assem_debug("branch: internal\n");
5489 assem_debug("branch: external\n");
5490 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5491 ds_assemble_entry(i);
5494 add_to_linker(out,ba[i],internal);
5498 set_jump_target(nottaken, out);
5501 if(nottaken1) set_jump_target(nottaken1, out);
5503 if(!invert) emit_addimm(cc,adj,cc);
5505 } // (!unconditional)
5509 // In-order execution (branch first)
5510 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5511 if(!unconditional&&!nop) {
5512 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5514 if((dops[i].opcode&0x2f)==4) // BEQ
5516 if(s2l>=0) emit_cmp(s1l,s2l);
5517 else emit_test(s1l,s1l);
5521 if((dops[i].opcode&0x2f)==5) // BNE
5523 if(s2l>=0) emit_cmp(s1l,s2l);
5524 else emit_test(s1l,s1l);
5528 if((dops[i].opcode&0x2f)==6) // BLEZ
5534 if((dops[i].opcode&0x2f)==7) // BGTZ
5540 } // if(!unconditional)
5542 uint64_t ds_unneeded=branch_regs[i].u;
5543 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5547 if(taken) set_jump_target(taken, out);
5548 assem_debug("1:\n");
5549 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5551 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5552 address_generation(i+1,&branch_regs[i],0);
5554 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5555 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5556 ds_assemble(i+1,&branch_regs[i]);
5557 cc=get_reg(branch_regs[i].regmap,CCREG);
5559 emit_loadreg(CCREG,cc=HOST_CCREG);
5560 // CHECK: Is the following instruction (fall thru) allocated ok?
5562 assert(cc==HOST_CCREG);
5563 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5564 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5565 assem_debug("cycle count (adj)\n");
5566 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5567 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5569 assem_debug("branch: internal\n");
5571 assem_debug("branch: external\n");
5572 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5573 ds_assemble_entry(i);
5576 add_to_linker(out,ba[i],internal);
5581 if(!unconditional) {
5582 if(nottaken1) set_jump_target(nottaken1, out);
5583 set_jump_target(nottaken, out);
5584 assem_debug("2:\n");
5585 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5587 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5588 address_generation(i+1,&branch_regs[i],0);
5590 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5591 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5592 ds_assemble(i+1,&branch_regs[i]);
5593 cc=get_reg(branch_regs[i].regmap,CCREG);
5595 // Cycle count isn't in a register, temporarily load it then write it out
5596 emit_loadreg(CCREG,HOST_CCREG);
5597 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5600 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5601 emit_storereg(CCREG,HOST_CCREG);
5604 cc=get_reg(i_regmap,CCREG);
5605 assert(cc==HOST_CCREG);
5606 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5609 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5615 static void sjump_assemble(int i, const struct regstat *i_regs)
5617 const signed char *i_regmap = i_regs->regmap;
5620 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5621 assem_debug("smatch=%d\n",match);
5623 int unconditional=0,nevertaken=0;
5625 int internal=internal_branch(ba[i]);
5626 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5627 if(!match) invert=1;
5628 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5629 if(i>(ba[i]-start)>>2) invert=1;
5632 invert=1; // because of near cond. branches
5635 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5636 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5639 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5642 s1l=get_reg(i_regmap,dops[i].rs1);
5646 if(dops[i].opcode2&1) unconditional=1;
5648 // These are never taken (r0 is never less than zero)
5649 //assert(dops[i].opcode2!=0);
5650 //assert(dops[i].opcode2!=2);
5651 //assert(dops[i].opcode2!=0x10);
5652 //assert(dops[i].opcode2!=0x12);
5656 // Out of order execution (delay slot first)
5658 address_generation(i+1,i_regs,regs[i].regmap_entry);
5659 ds_assemble(i+1,i_regs);
5661 uint64_t bc_unneeded=branch_regs[i].u;
5662 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5664 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5665 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5666 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5667 if(dops[i].rt1==31) {
5668 int rt,return_address;
5669 rt=get_reg(branch_regs[i].regmap,31);
5670 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5672 // Save the PC even if the branch is not taken
5673 return_address=start+i*4+8;
5674 emit_movimm(return_address,rt); // PC into link register
5676 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5680 cc=get_reg(branch_regs[i].regmap,CCREG);
5681 assert(cc==HOST_CCREG);
5683 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5684 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5685 assem_debug("cycle count (adj)\n");
5687 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5688 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5689 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5690 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5692 assem_debug("branch: internal\n");
5694 assem_debug("branch: external\n");
5695 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5696 ds_assemble_entry(i);
5699 add_to_linker(out,ba[i],internal);
5702 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5703 if(((u_int)out)&7) emit_addnop(0);
5707 else if(nevertaken) {
5708 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5711 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5714 void *nottaken = NULL;
5715 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5716 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5719 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5726 add_to_linker(out,ba[i],internal);
5730 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5737 add_to_linker(out,ba[i],internal);
5744 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5745 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5747 emit_addimm(cc,-adj,cc);
5748 add_to_linker(out,ba[i],internal);
5751 add_to_linker(out,ba[i],internal*2);
5757 if(adj) emit_addimm(cc,-adj,cc);
5758 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5759 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5761 assem_debug("branch: internal\n");
5763 assem_debug("branch: external\n");
5764 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5765 ds_assemble_entry(i);
5768 add_to_linker(out,ba[i],internal);
5772 set_jump_target(nottaken, out);
5776 if(!invert) emit_addimm(cc,adj,cc);
5778 } // (!unconditional)
5782 // In-order execution (branch first)
5784 void *nottaken = NULL;
5785 if(dops[i].rt1==31) {
5786 int rt,return_address;
5787 rt=get_reg(branch_regs[i].regmap,31);
5789 // Save the PC even if the branch is not taken
5790 return_address=start+i*4+8;
5791 emit_movimm(return_address,rt); // PC into link register
5793 emit_prefetch(hash_table_get(return_address));
5797 if(!unconditional) {
5798 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5800 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5806 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5812 } // if(!unconditional)
5814 uint64_t ds_unneeded=branch_regs[i].u;
5815 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5819 //assem_debug("1:\n");
5820 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5822 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5823 address_generation(i+1,&branch_regs[i],0);
5825 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5826 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5827 ds_assemble(i+1,&branch_regs[i]);
5828 cc=get_reg(branch_regs[i].regmap,CCREG);
5830 emit_loadreg(CCREG,cc=HOST_CCREG);
5831 // CHECK: Is the following instruction (fall thru) allocated ok?
5833 assert(cc==HOST_CCREG);
5834 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5835 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5836 assem_debug("cycle count (adj)\n");
5837 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5838 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5840 assem_debug("branch: internal\n");
5842 assem_debug("branch: external\n");
5843 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5844 ds_assemble_entry(i);
5847 add_to_linker(out,ba[i],internal);
5852 if(!unconditional) {
5853 set_jump_target(nottaken, out);
5854 assem_debug("1:\n");
5855 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5856 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5857 address_generation(i+1,&branch_regs[i],0);
5858 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5859 ds_assemble(i+1,&branch_regs[i]);
5860 cc=get_reg(branch_regs[i].regmap,CCREG);
5862 // Cycle count isn't in a register, temporarily load it then write it out
5863 emit_loadreg(CCREG,HOST_CCREG);
5864 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5867 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5868 emit_storereg(CCREG,HOST_CCREG);
5871 cc=get_reg(i_regmap,CCREG);
5872 assert(cc==HOST_CCREG);
5873 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5876 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5882 static void pagespan_assemble(int i, const struct regstat *i_regs)
5884 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5885 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
5887 void *nottaken = NULL;
5888 int unconditional=0;
5894 else if(dops[i].rs2==0)
5899 int addr=-1,alt=-1,ntaddr=-1;
5900 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5904 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5905 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5906 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5915 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5916 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5917 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5923 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5927 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5928 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5929 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5936 assert(hr<HOST_REGS);
5937 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5938 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
5940 emit_addimm(HOST_CCREG, ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5941 if(dops[i].opcode==2) // J
5945 if(dops[i].opcode==3) // JAL
5948 int rt=get_reg(i_regs->regmap,31);
5949 emit_movimm(start+i*4+8,rt);
5952 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
5955 if(dops[i].opcode2==9) // JALR
5957 int rt=get_reg(i_regs->regmap,dops[i].rt1);
5958 emit_movimm(start+i*4+8,rt);
5961 if((dops[i].opcode&0x3f)==4) // BEQ
5963 if(dops[i].rs1==dops[i].rs2)
5968 #ifdef HAVE_CMOV_IMM
5970 if(s2l>=0) emit_cmp(s1l,s2l);
5971 else emit_test(s1l,s1l);
5972 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5978 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5979 if(s2l>=0) emit_cmp(s1l,s2l);
5980 else emit_test(s1l,s1l);
5981 emit_cmovne_reg(alt,addr);
5984 if((dops[i].opcode&0x3f)==5) // BNE
5986 #ifdef HAVE_CMOV_IMM
5987 if(s2l>=0) emit_cmp(s1l,s2l);
5988 else emit_test(s1l,s1l);
5989 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5992 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5993 if(s2l>=0) emit_cmp(s1l,s2l);
5994 else emit_test(s1l,s1l);
5995 emit_cmovne_reg(alt,addr);
5998 if((dops[i].opcode&0x3f)==0x14) // BEQL
6000 if(s2l>=0) emit_cmp(s1l,s2l);
6001 else emit_test(s1l,s1l);
6002 if(nottaken) set_jump_target(nottaken, out);
6006 if((dops[i].opcode&0x3f)==0x15) // BNEL
6008 if(s2l>=0) emit_cmp(s1l,s2l);
6009 else emit_test(s1l,s1l);
6012 if(taken) set_jump_target(taken, out);
6014 if((dops[i].opcode&0x3f)==6) // BLEZ
6016 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6018 emit_cmovl_reg(alt,addr);
6020 if((dops[i].opcode&0x3f)==7) // BGTZ
6022 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6024 emit_cmovl_reg(ntaddr,addr);
6026 if((dops[i].opcode&0x3f)==0x16) // BLEZL
6028 assert((dops[i].opcode&0x3f)!=0x16);
6030 if((dops[i].opcode&0x3f)==0x17) // BGTZL
6032 assert((dops[i].opcode&0x3f)!=0x17);
6034 assert(dops[i].opcode!=1); // BLTZ/BGEZ
6036 //FIXME: Check CSREG
6037 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
6038 if((source[i]&0x30000)==0) // BC1F
6040 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6041 emit_testimm(s1l,0x800000);
6042 emit_cmovne_reg(alt,addr);
6044 if((source[i]&0x30000)==0x10000) // BC1T
6046 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6047 emit_testimm(s1l,0x800000);
6048 emit_cmovne_reg(alt,addr);
6050 if((source[i]&0x30000)==0x20000) // BC1FL
6052 emit_testimm(s1l,0x800000);
6056 if((source[i]&0x30000)==0x30000) // BC1TL
6058 emit_testimm(s1l,0x800000);
6064 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6065 wb_dirtys(regs[i].regmap,regs[i].dirty);
6068 emit_movimm(ba[i],HOST_BTREG);
6070 else if(addr!=HOST_BTREG)
6072 emit_mov(addr,HOST_BTREG);
6074 void *branch_addr=out;
6076 int target_addr=start+i*4+5;
6078 void *compiled_target_addr=check_addr(target_addr);
6079 emit_extjump_ds(branch_addr, target_addr);
6080 if(compiled_target_addr) {
6081 set_jump_target(branch_addr, compiled_target_addr);
6082 add_jump_out(target_addr,stub);
6084 else set_jump_target(branch_addr, stub);
6087 // Assemble the delay slot for the above
6088 static void pagespan_ds()
6090 assem_debug("initial delay slot:\n");
6091 u_int vaddr=start+1;
6092 u_int page=get_page(vaddr);
6093 u_int vpage=get_vpage(vaddr);
6094 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6095 do_dirty_stub_ds(slen*4);
6096 ll_add(jump_in+page,vaddr,(void *)out);
6097 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6098 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6099 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
6100 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6101 emit_writeword(HOST_BTREG,&branch_target);
6102 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
6103 address_generation(0,®s[0],regs[0].regmap_entry);
6104 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6105 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6106 if (dops[0].is_store)
6107 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
6109 switch (dops[0].itype) {
6118 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
6121 assemble(0, ®s[0], 0);
6123 int btaddr=get_reg(regs[0].regmap,BTREG);
6125 btaddr=get_reg(regs[0].regmap,-1);
6126 emit_readword(&branch_target,btaddr);
6128 assert(btaddr!=HOST_CCREG);
6129 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6131 host_tempreg_acquire();
6132 emit_movimm(start+4,HOST_TEMPREG);
6133 emit_cmp(btaddr,HOST_TEMPREG);
6134 host_tempreg_release();
6136 emit_cmpimm(btaddr,start+4);
6140 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
6141 do_jump_vaddr(btaddr);
6142 set_jump_target(branch, out);
6143 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6144 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6147 // Basic liveness analysis for MIPS registers
6148 void unneeded_registers(int istart,int iend,int r)
6151 uint64_t u,gte_u,b,gte_b;
6152 uint64_t temp_u,temp_gte_u=0;
6153 uint64_t gte_u_unknown=0;
6154 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
6158 gte_u=gte_u_unknown;
6160 //u=unneeded_reg[iend+1];
6162 gte_u=gte_unneeded[iend+1];
6165 for (i=iend;i>=istart;i--)
6167 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6170 // If subroutine call, flag return address as a possible branch target
6171 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
6173 if(ba[i]<start || ba[i]>=(start+slen*4))
6175 // Branch out of this block, flush all regs
6177 gte_u=gte_u_unknown;
6178 branch_unneeded_reg[i]=u;
6179 // Merge in delay slot
6180 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6181 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6184 gte_u&=~gte_rs[i+1];
6188 // Internal branch, flag target
6189 dops[(ba[i]-start)>>2].bt=1;
6190 if(ba[i]<=start+i*4) {
6192 if(dops[i].is_ujump)
6194 // Unconditional branch
6198 // Conditional branch (not taken case)
6199 temp_u=unneeded_reg[i+2];
6200 temp_gte_u&=gte_unneeded[i+2];
6202 // Merge in delay slot
6203 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6204 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6206 temp_gte_u|=gte_rt[i+1];
6207 temp_gte_u&=~gte_rs[i+1];
6208 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6209 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
6211 temp_gte_u|=gte_rt[i];
6212 temp_gte_u&=~gte_rs[i];
6213 unneeded_reg[i]=temp_u;
6214 gte_unneeded[i]=temp_gte_u;
6215 // Only go three levels deep. This recursion can take an
6216 // excessive amount of time if there are a lot of nested loops.
6218 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6220 unneeded_reg[(ba[i]-start)>>2]=1;
6221 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6224 if (dops[i].is_ujump)
6226 // Unconditional branch
6227 u=unneeded_reg[(ba[i]-start)>>2];
6228 gte_u=gte_unneeded[(ba[i]-start)>>2];
6229 branch_unneeded_reg[i]=u;
6230 // Merge in delay slot
6231 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6232 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6235 gte_u&=~gte_rs[i+1];
6237 // Conditional branch
6238 b=unneeded_reg[(ba[i]-start)>>2];
6239 gte_b=gte_unneeded[(ba[i]-start)>>2];
6240 branch_unneeded_reg[i]=b;
6241 // Branch delay slot
6242 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6243 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6246 gte_b&=~gte_rs[i+1];
6250 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6252 branch_unneeded_reg[i]=1;
6258 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6260 // SYSCALL instruction (software interrupt)
6263 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6265 // ERET instruction (return from interrupt)
6269 // Written registers are unneeded
6270 u|=1LL<<dops[i].rt1;
6271 u|=1LL<<dops[i].rt2;
6273 // Accessed registers are needed
6274 u&=~(1LL<<dops[i].rs1);
6275 u&=~(1LL<<dops[i].rs2);
6277 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
6278 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
6279 // Source-target dependencies
6280 // R0 is always unneeded
6284 gte_unneeded[i]=gte_u;
6286 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6289 for(r=1;r<=CCREG;r++) {
6290 if((unneeded_reg[i]>>r)&1) {
6291 if(r==HIREG) printf(" HI");
6292 else if(r==LOREG) printf(" LO");
6293 else printf(" r%d",r);
6301 // Write back dirty registers as soon as we will no longer modify them,
6302 // so that we don't end up with lots of writes at the branches.
6303 void clean_registers(int istart,int iend,int wr)
6307 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6308 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6310 will_dirty_i=will_dirty_next=0;
6311 wont_dirty_i=wont_dirty_next=0;
6313 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6314 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6316 for (i=iend;i>=istart;i--)
6320 if(ba[i]<start || ba[i]>=(start+slen*4))
6322 // Branch out of this block, flush all regs
6323 if (dops[i].is_ujump)
6325 // Unconditional branch
6328 // Merge in delay slot (will dirty)
6329 for(r=0;r<HOST_REGS;r++) {
6330 if(r!=EXCLUDE_REG) {
6331 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6332 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6333 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6334 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6335 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6336 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6337 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6338 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6339 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6340 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6341 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6342 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6343 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6344 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6350 // Conditional branch
6352 wont_dirty_i=wont_dirty_next;
6353 // Merge in delay slot (will dirty)
6354 for(r=0;r<HOST_REGS;r++) {
6355 if(r!=EXCLUDE_REG) {
6356 if (1) { // !dops[i].likely) {
6357 // Might not dirty if likely branch is not taken
6358 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6359 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6360 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6361 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6362 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6363 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6364 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6365 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6366 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6367 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6368 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6369 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6370 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6371 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6376 // Merge in delay slot (wont dirty)
6377 for(r=0;r<HOST_REGS;r++) {
6378 if(r!=EXCLUDE_REG) {
6379 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6380 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6381 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6382 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6383 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6384 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6385 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6386 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6387 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6388 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6392 #ifndef DESTRUCTIVE_WRITEBACK
6393 branch_regs[i].dirty&=wont_dirty_i;
6395 branch_regs[i].dirty|=will_dirty_i;
6401 if(ba[i]<=start+i*4) {
6403 if (dops[i].is_ujump)
6405 // Unconditional branch
6408 // Merge in delay slot (will dirty)
6409 for(r=0;r<HOST_REGS;r++) {
6410 if(r!=EXCLUDE_REG) {
6411 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6412 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6413 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6414 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6415 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6416 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6417 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6418 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6419 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6420 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6421 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6422 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6423 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6424 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6428 // Conditional branch (not taken case)
6429 temp_will_dirty=will_dirty_next;
6430 temp_wont_dirty=wont_dirty_next;
6431 // Merge in delay slot (will dirty)
6432 for(r=0;r<HOST_REGS;r++) {
6433 if(r!=EXCLUDE_REG) {
6434 if (1) { // !dops[i].likely) {
6435 // Will not dirty if likely branch is not taken
6436 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6437 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6438 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6439 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6440 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6441 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6442 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6443 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6444 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6445 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6446 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6447 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6448 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6449 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6454 // Merge in delay slot (wont dirty)
6455 for(r=0;r<HOST_REGS;r++) {
6456 if(r!=EXCLUDE_REG) {
6457 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6458 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6459 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6460 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6461 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6462 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6463 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6464 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6465 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6466 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6469 // Deal with changed mappings
6471 for(r=0;r<HOST_REGS;r++) {
6472 if(r!=EXCLUDE_REG) {
6473 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6474 temp_will_dirty&=~(1<<r);
6475 temp_wont_dirty&=~(1<<r);
6476 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6477 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6478 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6480 temp_will_dirty|=1<<r;
6481 temp_wont_dirty|=1<<r;
6488 will_dirty[i]=temp_will_dirty;
6489 wont_dirty[i]=temp_wont_dirty;
6490 clean_registers((ba[i]-start)>>2,i-1,0);
6492 // Limit recursion. It can take an excessive amount
6493 // of time if there are a lot of nested loops.
6494 will_dirty[(ba[i]-start)>>2]=0;
6495 wont_dirty[(ba[i]-start)>>2]=-1;
6500 if (dops[i].is_ujump)
6502 // Unconditional branch
6505 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6506 for(r=0;r<HOST_REGS;r++) {
6507 if(r!=EXCLUDE_REG) {
6508 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6509 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6510 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6512 if(branch_regs[i].regmap[r]>=0) {
6513 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6514 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6519 // Merge in delay slot
6520 for(r=0;r<HOST_REGS;r++) {
6521 if(r!=EXCLUDE_REG) {
6522 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6523 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6524 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6525 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6526 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6527 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6528 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6529 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6530 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6531 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6532 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6533 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6534 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6535 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6539 // Conditional branch
6540 will_dirty_i=will_dirty_next;
6541 wont_dirty_i=wont_dirty_next;
6542 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6543 for(r=0;r<HOST_REGS;r++) {
6544 if(r!=EXCLUDE_REG) {
6545 signed char target_reg=branch_regs[i].regmap[r];
6546 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6547 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6548 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6550 else if(target_reg>=0) {
6551 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6552 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6557 // Merge in delay slot
6558 for(r=0;r<HOST_REGS;r++) {
6559 if(r!=EXCLUDE_REG) {
6560 if (1) { // !dops[i].likely) {
6561 // Might not dirty if likely branch is not taken
6562 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6563 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6564 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6565 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6566 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6567 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6568 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6569 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6570 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6571 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6572 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6573 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6574 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6575 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6580 // Merge in delay slot (won't dirty)
6581 for(r=0;r<HOST_REGS;r++) {
6582 if(r!=EXCLUDE_REG) {
6583 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6584 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6585 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6586 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6587 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6588 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6589 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6590 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6591 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6592 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6596 #ifndef DESTRUCTIVE_WRITEBACK
6597 branch_regs[i].dirty&=wont_dirty_i;
6599 branch_regs[i].dirty|=will_dirty_i;
6604 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6606 // SYSCALL instruction (software interrupt)
6610 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6612 // ERET instruction (return from interrupt)
6616 will_dirty_next=will_dirty_i;
6617 wont_dirty_next=wont_dirty_i;
6618 for(r=0;r<HOST_REGS;r++) {
6619 if(r!=EXCLUDE_REG) {
6620 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6621 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6622 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6623 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6624 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6625 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6626 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6627 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6629 if (!dops[i].is_jump)
6631 // Don't store a register immediately after writing it,
6632 // may prevent dual-issue.
6633 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6634 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
6640 will_dirty[i]=will_dirty_i;
6641 wont_dirty[i]=wont_dirty_i;
6642 // Mark registers that won't be dirtied as not dirty
6644 regs[i].dirty|=will_dirty_i;
6645 #ifndef DESTRUCTIVE_WRITEBACK
6646 regs[i].dirty&=wont_dirty_i;
6649 if (i < iend-1 && !dops[i].is_ujump) {
6650 for(r=0;r<HOST_REGS;r++) {
6651 if(r!=EXCLUDE_REG) {
6652 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6653 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6654 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6662 for(r=0;r<HOST_REGS;r++) {
6663 if(r!=EXCLUDE_REG) {
6664 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6665 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6666 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6674 // Deal with changed mappings
6675 temp_will_dirty=will_dirty_i;
6676 temp_wont_dirty=wont_dirty_i;
6677 for(r=0;r<HOST_REGS;r++) {
6678 if(r!=EXCLUDE_REG) {
6680 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6682 #ifndef DESTRUCTIVE_WRITEBACK
6683 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6685 regs[i].wasdirty|=will_dirty_i&(1<<r);
6688 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6689 // Register moved to a different register
6690 will_dirty_i&=~(1<<r);
6691 wont_dirty_i&=~(1<<r);
6692 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6693 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6695 #ifndef DESTRUCTIVE_WRITEBACK
6696 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6698 regs[i].wasdirty|=will_dirty_i&(1<<r);
6702 will_dirty_i&=~(1<<r);
6703 wont_dirty_i&=~(1<<r);
6704 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6705 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6706 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6709 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6719 void disassemble_inst(int i)
6721 if (dops[i].bt) printf("*"); else printf(" ");
6722 switch(dops[i].itype) {
6724 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6726 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6728 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6730 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6731 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6733 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6736 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
6738 if(dops[i].opcode==0xf) //LUI
6739 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
6741 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6745 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6749 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
6753 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6756 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6759 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6762 if((dops[i].opcode2&0x1d)==0x10)
6763 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6764 else if((dops[i].opcode2&0x1d)==0x11)
6765 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6767 printf (" %x: %s\n",start+i*4,insn[i]);
6770 if(dops[i].opcode2==0)
6771 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6772 else if(dops[i].opcode2==4)
6773 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6774 else printf (" %x: %s\n",start+i*4,insn[i]);
6777 if(dops[i].opcode2<3)
6778 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6779 else if(dops[i].opcode2>3)
6780 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6781 else printf (" %x: %s\n",start+i*4,insn[i]);
6784 if(dops[i].opcode2<3)
6785 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6786 else if(dops[i].opcode2>3)
6787 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6788 else printf (" %x: %s\n",start+i*4,insn[i]);
6791 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6794 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6797 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6800 //printf (" %s %8x\n",insn[i],source[i]);
6801 printf (" %x: %s\n",start+i*4,insn[i]);
6805 static void disassemble_inst(int i) {}
6808 #define DRC_TEST_VAL 0x74657374
6810 static void new_dynarec_test(void)
6812 int (*testfunc)(void);
6817 // check structure linkage
6818 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6820 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6823 SysPrintf("testing if we can run recompiled code @%p...\n", out);
6824 ((volatile u_int *)out)[0]++; // make cache dirty
6826 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6827 out = ndrc->translation_cache;
6828 beginning = start_block();
6829 emit_movimm(DRC_TEST_VAL + i, 0); // test
6832 end_block(beginning);
6833 testfunc = beginning;
6834 ret[i] = testfunc();
6837 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6838 SysPrintf("test passed.\n");
6840 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6841 out = ndrc->translation_cache;
6844 // clear the state completely, instead of just marking
6845 // things invalid like invalidate_all_pages() does
6846 void new_dynarec_clear_full(void)
6849 out = ndrc->translation_cache;
6850 memset(invalid_code,1,sizeof(invalid_code));
6851 memset(hash_table,0xff,sizeof(hash_table));
6852 memset(mini_ht,-1,sizeof(mini_ht));
6853 memset(restore_candidate,0,sizeof(restore_candidate));
6854 memset(shadow,0,sizeof(shadow));
6856 expirep=16384; // Expiry pointer, +2 blocks
6857 pending_exception=0;
6860 inv_code_start=inv_code_end=~0;
6864 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6865 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6866 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6868 cycle_multiplier_old = cycle_multiplier;
6869 new_dynarec_hacks_old = new_dynarec_hacks;
6872 void new_dynarec_init(void)
6874 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6879 #ifdef BASE_ADDR_DYNAMIC
6881 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6883 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6884 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6886 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6887 sceKernelOpenVMDomain();
6888 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6889 #elif defined(_MSC_VER)
6890 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6891 PAGE_EXECUTE_READWRITE);
6893 uintptr_t desired_addr = 0;
6896 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6898 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6899 PROT_READ | PROT_WRITE | PROT_EXEC,
6900 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6901 if (ndrc == MAP_FAILED) {
6902 SysPrintf("mmap() failed: %s\n", strerror(errno));
6907 #ifndef NO_WRITE_EXEC
6908 // not all systems allow execute in data segment by default
6909 // size must be 4K aligned for 3DS?
6910 if (mprotect(ndrc, sizeof(*ndrc),
6911 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6912 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6915 out = ndrc->translation_cache;
6916 cycle_multiplier=200;
6917 new_dynarec_clear_full();
6919 // Copy this into local area so we don't have to put it in every literal pool
6920 invc_ptr=invalid_code;
6924 ram_offset=(uintptr_t)rdram-0x80000000;
6926 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6929 void new_dynarec_cleanup(void)
6932 #ifdef BASE_ADDR_DYNAMIC
6934 // sceBlock is managed by retroarch's bootstrap code
6935 //sceKernelFreeMemBlock(sceBlock);
6938 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6939 SysPrintf("munmap() failed\n");
6942 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6943 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6944 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6946 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6950 static u_int *get_source_start(u_int addr, u_int *limit)
6952 if (addr < 0x00200000 ||
6953 (0xa0000000 <= addr && addr < 0xa0200000))
6955 // used for BIOS calls mostly?
6956 *limit = (addr&0xa0000000)|0x00200000;
6957 return (u_int *)(rdram + (addr&0x1fffff));
6959 else if (!Config.HLE && (
6960 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6961 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6963 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6964 // but timings in PCSX are too tied to the interpreter's BIAS
6965 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6966 cycle_multiplier_active = 200;
6968 *limit = (addr & 0xfff00000) | 0x80000;
6969 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6971 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6972 *limit = (addr & 0x80600000) + 0x00200000;
6973 return (u_int *)(rdram + (addr&0x1fffff));
6978 static u_int scan_for_ret(u_int addr)
6983 mem = get_source_start(addr, &limit);
6987 if (limit > addr + 0x1000)
6988 limit = addr + 0x1000;
6989 for (; addr < limit; addr += 4, mem++) {
6990 if (*mem == 0x03e00008) // jr $ra
6996 struct savestate_block {
7001 static int addr_cmp(const void *p1_, const void *p2_)
7003 const struct savestate_block *p1 = p1_, *p2 = p2_;
7004 return p1->addr - p2->addr;
7007 int new_dynarec_save_blocks(void *save, int size)
7009 struct savestate_block *blocks = save;
7010 int maxcount = size / sizeof(blocks[0]);
7011 struct savestate_block tmp_blocks[1024];
7012 struct ll_entry *head;
7013 int p, s, d, o, bcnt;
7017 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
7019 for (head = jump_in[p]; head != NULL; head = head->next) {
7020 tmp_blocks[bcnt].addr = head->vaddr;
7021 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7026 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7028 addr = tmp_blocks[0].addr;
7029 for (s = d = 0; s < bcnt; s++) {
7030 if (tmp_blocks[s].addr < addr)
7032 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7033 tmp_blocks[d++] = tmp_blocks[s];
7034 addr = scan_for_ret(tmp_blocks[s].addr);
7037 if (o + d > maxcount)
7039 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7043 return o * sizeof(blocks[0]);
7046 void new_dynarec_load_blocks(const void *save, int size)
7048 const struct savestate_block *blocks = save;
7049 int count = size / sizeof(blocks[0]);
7050 u_int regs_save[32];
7054 get_addr(psxRegs.pc);
7056 // change GPRs for speculation to at least partially work..
7057 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7058 for (i = 1; i < 32; i++)
7059 psxRegs.GPR.r[i] = 0x80000000;
7061 for (b = 0; b < count; b++) {
7062 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7064 psxRegs.GPR.r[i] = 0x1f800000;
7067 get_addr(blocks[b].addr);
7069 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7071 psxRegs.GPR.r[i] = 0x80000000;
7075 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7078 static int apply_hacks(void)
7081 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
7083 /* special hack(s) */
7084 for (i = 0; i < slen - 4; i++)
7086 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
7087 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
7088 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
7089 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
7091 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
7092 dops[i + 3].itype = NOP;
7096 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7097 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7098 && dops[i-7].itype == STORE)
7101 if (dops[i].itype == IMM16)
7103 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7104 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7105 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7107 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
7115 int new_recompile_block(u_int addr)
7117 u_int pagelimit = 0;
7118 u_int state_rflags = 0;
7121 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
7122 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7124 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7126 // this is just for speculation
7127 for (i = 1; i < 32; i++) {
7128 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7129 state_rflags |= 1 << i;
7132 start = (u_int)addr&~3;
7133 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
7134 new_dynarec_did_compile=1;
7135 if (Config.HLE && start == 0x80001000) // hlecall
7137 // XXX: is this enough? Maybe check hleSoftCall?
7138 void *beginning=start_block();
7139 u_int page=get_page(start);
7141 invalid_code[start>>12]=0;
7142 emit_movimm(start,0);
7143 emit_writeword(0,&pcaddr);
7144 emit_far_jump(new_dyna_leave);
7146 end_block(beginning);
7147 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7150 else if (f1_hack && hack_addr == 0) {
7151 void *beginning = start_block();
7152 u_int page = get_page(start);
7153 emit_movimm(start, 0);
7154 emit_writeword(0, &hack_addr);
7155 emit_readword(&psxRegs.GPR.n.sp, 0);
7156 emit_readptr(&mem_rtab, 1);
7157 emit_shrimm(0, 12, 2);
7158 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7159 emit_addimm(0, 0x18, 0);
7160 emit_adds_ptr(1, 1, 1);
7161 emit_ldr_dualindexed(1, 0, 0);
7162 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7163 emit_far_call(get_addr_ht);
7164 emit_jmpreg(0); // jr k0
7166 end_block(beginning);
7168 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7169 SysPrintf("F1 hack to %08x\n", start);
7173 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
7174 ? cycle_multiplier_override : cycle_multiplier;
7176 source = get_source_start(start, &pagelimit);
7177 if (source == NULL) {
7178 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7182 /* Pass 1: disassemble */
7183 /* Pass 2: register dependencies, branch targets */
7184 /* Pass 3: register allocation */
7185 /* Pass 4: branch dependencies */
7186 /* Pass 5: pre-alloc */
7187 /* Pass 6: optimize clean/dirty state */
7188 /* Pass 7: flag 32-bit registers */
7189 /* Pass 8: assembly */
7190 /* Pass 9: linker */
7191 /* Pass 10: garbage collection / free memory */
7195 unsigned int type,op,op2;
7197 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7199 /* Pass 1 disassembly */
7201 for (i = 0; !done; i++)
7203 memset(&dops[i], 0, sizeof(dops[i]));
7205 minimum_free_regs[i]=0;
7206 dops[i].opcode=op=source[i]>>26;
7209 case 0x00: strcpy(insn[i],"special"); type=NI;
7213 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7214 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7215 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7216 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7217 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7218 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7219 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7220 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7221 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7222 case 0x0D: strcpy(insn[i],"BREAK"); type=SYSCALL; break;
7223 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7224 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7225 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7226 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7227 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7228 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7229 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7230 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7231 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7232 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7233 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7234 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7235 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7236 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7237 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7238 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7239 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7240 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7241 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7242 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7243 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7244 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7245 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7246 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7247 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7249 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7250 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7251 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7252 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7253 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7254 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7255 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7256 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7257 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7258 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7259 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7260 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7261 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7262 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7263 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7264 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7265 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7269 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7270 op2=(source[i]>>16)&0x1f;
7273 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7274 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7275 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7276 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7277 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7278 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7279 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7280 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7281 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7282 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7283 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7284 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7285 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7286 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7289 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7290 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7291 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7292 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7293 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7294 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7295 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7296 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7297 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7298 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7299 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7300 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7301 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7302 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7303 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7304 op2=(source[i]>>21)&0x1f;
7307 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7308 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
7309 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7310 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7311 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7314 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
7315 op2=(source[i]>>21)&0x1f;
7318 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7319 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7320 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7321 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7322 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7323 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7324 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7325 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7327 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7328 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7329 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7330 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7331 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7332 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7333 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7335 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7337 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7338 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7339 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7340 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7342 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7343 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7345 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7346 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7347 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7348 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7350 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7351 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7352 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7354 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7355 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7357 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7358 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7359 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7361 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7362 op2=(source[i]>>21)&0x1f;
7364 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
7365 if (gte_handlers[source[i]&0x3f]!=NULL) {
7366 if (gte_regnames[source[i]&0x3f]!=NULL)
7367 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7369 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
7375 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7376 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7377 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7378 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
7381 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7382 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7383 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
7384 default: strcpy(insn[i],"???"); type=NI;
7385 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
7389 dops[i].opcode2=op2;
7390 /* Get registers/immediates */
7392 gte_rs[i]=gte_rt[i]=0;
7395 dops[i].rs1=(source[i]>>21)&0x1f;
7397 dops[i].rt1=(source[i]>>16)&0x1f;
7399 imm[i]=(short)source[i];
7403 dops[i].rs1=(source[i]>>21)&0x1f;
7404 dops[i].rs2=(source[i]>>16)&0x1f;
7407 imm[i]=(short)source[i];
7410 // LWL/LWR only load part of the register,
7411 // therefore the target register must be treated as a source too
7412 dops[i].rs1=(source[i]>>21)&0x1f;
7413 dops[i].rs2=(source[i]>>16)&0x1f;
7414 dops[i].rt1=(source[i]>>16)&0x1f;
7416 imm[i]=(short)source[i];
7419 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7420 else dops[i].rs1=(source[i]>>21)&0x1f;
7422 dops[i].rt1=(source[i]>>16)&0x1f;
7424 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7425 imm[i]=(unsigned short)source[i];
7427 imm[i]=(short)source[i];
7435 // The JAL instruction writes to r31.
7442 dops[i].rs1=(source[i]>>21)&0x1f;
7446 // The JALR instruction writes to rd.
7448 dops[i].rt1=(source[i]>>11)&0x1f;
7453 dops[i].rs1=(source[i]>>21)&0x1f;
7454 dops[i].rs2=(source[i]>>16)&0x1f;
7457 if(op&2) { // BGTZ/BLEZ
7462 dops[i].rs1=(source[i]>>21)&0x1f;
7466 if(op2&0x10) { // BxxAL
7468 // NOTE: If the branch is not taken, r31 is still overwritten
7472 dops[i].rs1=(source[i]>>21)&0x1f; // source
7473 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7474 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7478 dops[i].rs1=(source[i]>>21)&0x1f; // source
7479 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7488 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7489 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7490 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7491 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7492 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7493 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
7496 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7497 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7498 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7502 dops[i].rs1=(source[i]>>16)&0x1f;
7504 dops[i].rt1=(source[i]>>11)&0x1f;
7506 imm[i]=(source[i]>>6)&0x1f;
7507 // DSxx32 instructions
7508 if(op2>=0x3c) imm[i]|=0x20;
7515 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7516 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7517 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7518 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
7525 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7526 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7534 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7535 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7537 int gr=(source[i]>>11)&0x1F;
7540 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7541 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7542 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7543 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7547 dops[i].rs1=(source[i]>>21)&0x1F;
7551 imm[i]=(short)source[i];
7554 dops[i].rs1=(source[i]>>21)&0x1F;
7558 imm[i]=(short)source[i];
7559 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7560 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7567 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7568 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7569 gte_rt[i]|=1ll<<63; // every op changes flags
7570 if((source[i]&0x3f)==GTE_MVMVA) {
7571 int v = (source[i] >> 15) & 3;
7572 gte_rs[i]&=~0xe3fll;
7573 if(v==3) gte_rs[i]|=0xe00ll;
7574 else gte_rs[i]|=3ll<<(v*2);
7591 /* Calculate branch target addresses */
7593 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7594 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
7595 ba[i]=start+i*4+8; // Ignore never taken branch
7596 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
7597 ba[i]=start+i*4+8; // Ignore never taken branch
7598 else if(type==CJUMP||type==SJUMP)
7599 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7602 /* simplify always (not)taken branches */
7603 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7604 dops[i].rs1 = dops[i].rs2 = 0;
7606 dops[i].itype = type = UJUMP;
7607 dops[i].rs2 = CCREG;
7610 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7611 dops[i].itype = type = UJUMP;
7613 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7614 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
7615 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7616 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
7618 /* messy cases to just pass over to the interpreter */
7619 if (i > 0 && dops[i-1].is_jump) {
7621 // branch in delay slot?
7622 if (dops[i].is_jump) {
7623 // don't handle first branch and call interpreter if it's hit
7624 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7627 // basic load delay detection
7628 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
7629 int t=(ba[i-1]-start)/4;
7630 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
7631 // jump target wants DS result - potential load delay effect
7632 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7634 dops[t+1].bt=1; // expected return from interpreter
7636 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
7637 !(i>=3&&dops[i-3].is_jump)) {
7638 // v0 overwrite like this is a sign of trouble, bail out
7639 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7644 memset(&dops[i-1], 0, sizeof(dops[i-1]));
7645 dops[i-1].itype = INTCALL;
7646 dops[i-1].rs1 = CCREG;
7649 i--; // don't compile the DS
7653 /* Is this the end of the block? */
7654 if (i > 0 && dops[i-1].is_ujump) {
7655 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
7659 if(stop_after_jal) done=1;
7661 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7663 // Don't recompile stuff that's already compiled
7664 if(check_addr(start+i*4+4)) done=1;
7665 // Don't get too close to the limit
7666 if(i>MAXBLOCK/2) done=1;
7668 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
7669 done = stop_after_jal ? 1 : 2;
7671 // Does the block continue due to a branch?
7674 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7675 if(ba[j]==start+i*4+4) done=j=0;
7676 if(ba[j]==start+i*4+8) done=j=0;
7679 //assert(i<MAXBLOCK-1);
7680 if(start+i*4==pagelimit-4) done=1;
7681 assert(start+i*4<pagelimit);
7682 if (i==MAXBLOCK-1) done=1;
7683 // Stop if we're compiling junk
7684 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
7685 done=stop_after_jal=1;
7686 SysPrintf("Disabled speculative precompilation\n");
7690 if (dops[i-1].is_jump) {
7691 if(start+i*4==pagelimit) {
7692 dops[i-1].itype=SPAN;
7697 int clear_hack_addr = apply_hacks();
7699 /* Pass 2 - Register dependencies and branch targets */
7701 unneeded_registers(0,slen-1,0);
7703 /* Pass 3 - Register allocation */
7705 struct regstat current; // Current register allocations/status
7706 clear_all_regs(current.regmap_entry);
7707 clear_all_regs(current.regmap);
7708 current.wasdirty = current.dirty = 0;
7709 current.u = unneeded_reg[0];
7710 alloc_reg(¤t, 0, CCREG);
7711 dirty_reg(¤t, CCREG);
7712 current.wasconst = 0;
7713 current.isconst = 0;
7714 current.loadedconst = 0;
7715 current.waswritten = 0;
7721 // First instruction is delay slot
7726 current.regmap[HOST_BTREG]=BTREG;
7734 for(hr=0;hr<HOST_REGS;hr++)
7736 // Is this really necessary?
7737 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7740 current.waswritten=0;
7743 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7744 regs[i].wasconst=current.isconst;
7745 regs[i].wasdirty=current.dirty;
7749 regs[i].loadedconst=0;
7750 if (!dops[i].is_jump) {
7752 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7759 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7760 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7763 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7769 ds=0; // Skip delay slot, already allocated as part of branch
7770 // ...but we need to alloc it in case something jumps here
7772 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7774 current.u=branch_unneeded_reg[i-1];
7776 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7778 struct regstat temp;
7779 memcpy(&temp,¤t,sizeof(current));
7780 temp.wasdirty=temp.dirty;
7781 // TODO: Take into account unconditional branches, as below
7782 delayslot_alloc(&temp,i);
7783 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7784 regs[i].wasdirty=temp.wasdirty;
7785 regs[i].dirty=temp.dirty;
7789 // Create entry (branch target) regmap
7790 for(hr=0;hr<HOST_REGS;hr++)
7792 int r=temp.regmap[hr];
7794 if(r!=regmap_pre[i][hr]) {
7795 regs[i].regmap_entry[hr]=-1;
7800 if((current.u>>r)&1) {
7801 regs[i].regmap_entry[hr]=-1;
7802 regs[i].regmap[hr]=-1;
7803 //Don't clear regs in the delay slot as the branch might need them
7804 //current.regmap[hr]=-1;
7806 regs[i].regmap_entry[hr]=r;
7809 // First instruction expects CCREG to be allocated
7810 if(i==0&&hr==HOST_CCREG)
7811 regs[i].regmap_entry[hr]=CCREG;
7813 regs[i].regmap_entry[hr]=-1;
7817 else { // Not delay slot
7818 switch(dops[i].itype) {
7820 //current.isconst=0; // DEBUG
7821 //current.wasconst=0; // DEBUG
7822 //regs[i].wasconst=0; // DEBUG
7823 clear_const(¤t,dops[i].rt1);
7824 alloc_cc(¤t,i);
7825 dirty_reg(¤t,CCREG);
7826 if (dops[i].rt1==31) {
7827 alloc_reg(¤t,i,31);
7828 dirty_reg(¤t,31);
7829 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7830 //assert(dops[i+1].rt1!=dops[i].rt1);
7832 alloc_reg(¤t,i,PTEMP);
7836 delayslot_alloc(¤t,i+1);
7837 //current.isconst=0; // DEBUG
7839 //printf("i=%d, isconst=%x\n",i,current.isconst);
7842 //current.isconst=0;
7843 //current.wasconst=0;
7844 //regs[i].wasconst=0;
7845 clear_const(¤t,dops[i].rs1);
7846 clear_const(¤t,dops[i].rt1);
7847 alloc_cc(¤t,i);
7848 dirty_reg(¤t,CCREG);
7849 if (!ds_writes_rjump_rs(i)) {
7850 alloc_reg(¤t,i,dops[i].rs1);
7851 if (dops[i].rt1!=0) {
7852 alloc_reg(¤t,i,dops[i].rt1);
7853 dirty_reg(¤t,dops[i].rt1);
7854 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7855 assert(dops[i+1].rt1!=dops[i].rt1);
7857 alloc_reg(¤t,i,PTEMP);
7861 if(dops[i].rs1==31) { // JALR
7862 alloc_reg(¤t,i,RHASH);
7863 alloc_reg(¤t,i,RHTBL);
7866 delayslot_alloc(¤t,i+1);
7868 // The delay slot overwrites our source register,
7869 // allocate a temporary register to hold the old value.
7873 delayslot_alloc(¤t,i+1);
7875 alloc_reg(¤t,i,RTEMP);
7877 //current.isconst=0; // DEBUG
7882 //current.isconst=0;
7883 //current.wasconst=0;
7884 //regs[i].wasconst=0;
7885 clear_const(¤t,dops[i].rs1);
7886 clear_const(¤t,dops[i].rs2);
7887 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7889 alloc_cc(¤t,i);
7890 dirty_reg(¤t,CCREG);
7891 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7892 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7893 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7894 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7895 // The delay slot overwrites one of our conditions.
7896 // Allocate the branch condition registers instead.
7900 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7901 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7906 delayslot_alloc(¤t,i+1);
7910 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7912 alloc_cc(¤t,i);
7913 dirty_reg(¤t,CCREG);
7914 alloc_reg(¤t,i,dops[i].rs1);
7915 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7916 // The delay slot overwrites one of our conditions.
7917 // Allocate the branch condition registers instead.
7921 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7926 delayslot_alloc(¤t,i+1);
7930 // Don't alloc the delay slot yet because we might not execute it
7931 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7936 alloc_cc(¤t,i);
7937 dirty_reg(¤t,CCREG);
7938 alloc_reg(¤t,i,dops[i].rs1);
7939 alloc_reg(¤t,i,dops[i].rs2);
7942 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7947 alloc_cc(¤t,i);
7948 dirty_reg(¤t,CCREG);
7949 alloc_reg(¤t,i,dops[i].rs1);
7952 //current.isconst=0;
7955 //current.isconst=0;
7956 //current.wasconst=0;
7957 //regs[i].wasconst=0;
7958 clear_const(¤t,dops[i].rs1);
7959 clear_const(¤t,dops[i].rt1);
7960 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7961 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
7963 alloc_cc(¤t,i);
7964 dirty_reg(¤t,CCREG);
7965 alloc_reg(¤t,i,dops[i].rs1);
7966 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
7967 alloc_reg(¤t,i,31);
7968 dirty_reg(¤t,31);
7969 //#ifdef REG_PREFETCH
7970 //alloc_reg(¤t,i,PTEMP);
7973 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7974 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7975 // Allocate the branch condition registers instead.
7979 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7984 delayslot_alloc(¤t,i+1);
7988 // Don't alloc the delay slot yet because we might not execute it
7989 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
7994 alloc_cc(¤t,i);
7995 dirty_reg(¤t,CCREG);
7996 alloc_reg(¤t,i,dops[i].rs1);
7999 //current.isconst=0;
8002 imm16_alloc(¤t,i);
8006 load_alloc(¤t,i);
8010 store_alloc(¤t,i);
8013 alu_alloc(¤t,i);
8016 shift_alloc(¤t,i);
8019 multdiv_alloc(¤t,i);
8022 shiftimm_alloc(¤t,i);
8025 mov_alloc(¤t,i);
8028 cop0_alloc(¤t,i);
8033 cop2_alloc(¤t,i);
8036 c1ls_alloc(¤t,i);
8039 c2ls_alloc(¤t,i);
8042 c2op_alloc(¤t,i);
8047 syscall_alloc(¤t,i);
8050 pagespan_alloc(¤t,i);
8054 // Create entry (branch target) regmap
8055 for(hr=0;hr<HOST_REGS;hr++)
8058 r=current.regmap[hr];
8060 if(r!=regmap_pre[i][hr]) {
8061 // TODO: delay slot (?)
8062 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8063 if(or<0||(r&63)>=TEMPREG){
8064 regs[i].regmap_entry[hr]=-1;
8068 // Just move it to a different register
8069 regs[i].regmap_entry[hr]=r;
8070 // If it was dirty before, it's still dirty
8071 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
8078 regs[i].regmap_entry[hr]=0;
8083 if((current.u>>r)&1) {
8084 regs[i].regmap_entry[hr]=-1;
8085 //regs[i].regmap[hr]=-1;
8086 current.regmap[hr]=-1;
8088 regs[i].regmap_entry[hr]=r;
8092 // Branches expect CCREG to be allocated at the target
8093 if(regmap_pre[i][hr]==CCREG)
8094 regs[i].regmap_entry[hr]=CCREG;
8096 regs[i].regmap_entry[hr]=-1;
8099 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8102 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8103 current.waswritten|=1<<dops[i-1].rs1;
8104 current.waswritten&=~(1<<dops[i].rt1);
8105 current.waswritten&=~(1<<dops[i].rt2);
8106 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8107 current.waswritten&=~(1<<dops[i].rs1);
8109 /* Branch post-alloc */
8112 current.wasdirty=current.dirty;
8113 switch(dops[i-1].itype) {
8115 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8116 branch_regs[i-1].isconst=0;
8117 branch_regs[i-1].wasconst=0;
8118 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8119 alloc_cc(&branch_regs[i-1],i-1);
8120 dirty_reg(&branch_regs[i-1],CCREG);
8121 if(dops[i-1].rt1==31) { // JAL
8122 alloc_reg(&branch_regs[i-1],i-1,31);
8123 dirty_reg(&branch_regs[i-1],31);
8125 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8126 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8129 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8130 branch_regs[i-1].isconst=0;
8131 branch_regs[i-1].wasconst=0;
8132 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8133 alloc_cc(&branch_regs[i-1],i-1);
8134 dirty_reg(&branch_regs[i-1],CCREG);
8135 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8136 if(dops[i-1].rt1!=0) { // JALR
8137 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8138 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
8141 if(dops[i-1].rs1==31) { // JALR
8142 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8143 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8146 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8147 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8150 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
8152 alloc_cc(¤t,i-1);
8153 dirty_reg(¤t,CCREG);
8154 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8155 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
8156 // The delay slot overwrote one of our conditions
8157 // Delay slot goes after the test (in order)
8158 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8160 delayslot_alloc(¤t,i);
8165 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8166 // Alloc the branch condition registers
8167 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
8168 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
8170 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8171 branch_regs[i-1].isconst=0;
8172 branch_regs[i-1].wasconst=0;
8173 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8174 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8177 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
8179 alloc_cc(¤t,i-1);
8180 dirty_reg(¤t,CCREG);
8181 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8182 // The delay slot overwrote the branch condition
8183 // Delay slot goes after the test (in order)
8184 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8186 delayslot_alloc(¤t,i);
8191 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8192 // Alloc the branch condition register
8193 alloc_reg(¤t,i-1,dops[i-1].rs1);
8195 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8196 branch_regs[i-1].isconst=0;
8197 branch_regs[i-1].wasconst=0;
8198 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8199 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8202 // Alloc the delay slot in case the branch is taken
8203 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
8205 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8206 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8207 alloc_cc(&branch_regs[i-1],i);
8208 dirty_reg(&branch_regs[i-1],CCREG);
8209 delayslot_alloc(&branch_regs[i-1],i);
8210 branch_regs[i-1].isconst=0;
8211 alloc_reg(¤t,i,CCREG); // Not taken path
8212 dirty_reg(¤t,CCREG);
8213 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8216 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
8218 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8219 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8220 alloc_cc(&branch_regs[i-1],i);
8221 dirty_reg(&branch_regs[i-1],CCREG);
8222 delayslot_alloc(&branch_regs[i-1],i);
8223 branch_regs[i-1].isconst=0;
8224 alloc_reg(¤t,i,CCREG); // Not taken path
8225 dirty_reg(¤t,CCREG);
8226 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8230 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8231 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
8233 alloc_cc(¤t,i-1);
8234 dirty_reg(¤t,CCREG);
8235 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8236 // The delay slot overwrote the branch condition
8237 // Delay slot goes after the test (in order)
8238 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8240 delayslot_alloc(¤t,i);
8245 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8246 // Alloc the branch condition register
8247 alloc_reg(¤t,i-1,dops[i-1].rs1);
8249 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8250 branch_regs[i-1].isconst=0;
8251 branch_regs[i-1].wasconst=0;
8252 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8253 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8256 // Alloc the delay slot in case the branch is taken
8257 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
8259 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8260 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8261 alloc_cc(&branch_regs[i-1],i);
8262 dirty_reg(&branch_regs[i-1],CCREG);
8263 delayslot_alloc(&branch_regs[i-1],i);
8264 branch_regs[i-1].isconst=0;
8265 alloc_reg(¤t,i,CCREG); // Not taken path
8266 dirty_reg(¤t,CCREG);
8267 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8269 // FIXME: BLTZAL/BGEZAL
8270 if(dops[i-1].opcode2&0x10) { // BxxZAL
8271 alloc_reg(&branch_regs[i-1],i-1,31);
8272 dirty_reg(&branch_regs[i-1],31);
8277 if (dops[i-1].is_ujump)
8279 if(dops[i-1].rt1==31) // JAL/JALR
8281 // Subroutine call will return here, don't alloc any registers
8283 clear_all_regs(current.regmap);
8284 alloc_reg(¤t,i,CCREG);
8285 dirty_reg(¤t,CCREG);
8289 // Internal branch will jump here, match registers to caller
8291 clear_all_regs(current.regmap);
8292 alloc_reg(¤t,i,CCREG);
8293 dirty_reg(¤t,CCREG);
8296 if(ba[j]==start+i*4+4) {
8297 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8298 current.dirty=branch_regs[j].dirty;
8303 if(ba[j]==start+i*4+4) {
8304 for(hr=0;hr<HOST_REGS;hr++) {
8305 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8306 current.regmap[hr]=-1;
8308 current.dirty&=branch_regs[j].dirty;
8317 // Count cycles in between branches
8318 ccadj[i] = CLOCK_ADJUST(cc);
8319 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
8323 #if !defined(DRC_DBG)
8324 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
8326 // this should really be removed since the real stalls have been implemented,
8327 // but doing so causes sizeable perf regression against the older version
8328 u_int gtec = gte_cycletab[source[i] & 0x3f];
8329 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
8331 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
8335 else if(dops[i].itype==C2LS)
8337 // same as with C2OP
8338 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
8346 if(!dops[i].is_ds) {
8347 regs[i].dirty=current.dirty;
8348 regs[i].isconst=current.isconst;
8349 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
8351 for(hr=0;hr<HOST_REGS;hr++) {
8352 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
8353 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8354 regs[i].wasconst&=~(1<<hr);
8358 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
8359 regs[i].waswritten=current.waswritten;
8362 /* Pass 4 - Cull unused host registers */
8366 for (i=slen-1;i>=0;i--)
8371 if(ba[i]<start || ba[i]>=(start+slen*4))
8373 // Branch out of this block, don't need anything
8379 // Need whatever matches the target
8381 int t=(ba[i]-start)>>2;
8382 for(hr=0;hr<HOST_REGS;hr++)
8384 if(regs[i].regmap_entry[hr]>=0) {
8385 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8389 // Conditional branch may need registers for following instructions
8390 if (!dops[i].is_ujump)
8393 nr|=needed_reg[i+2];
8394 for(hr=0;hr<HOST_REGS;hr++)
8396 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8397 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8401 // Don't need stuff which is overwritten
8402 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8403 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8404 // Merge in delay slot
8405 for(hr=0;hr<HOST_REGS;hr++)
8407 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8408 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8409 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8410 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8411 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8412 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8413 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8414 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8415 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8417 if(dops[i+1].is_store) {
8418 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8419 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8423 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8425 // SYSCALL instruction (software interrupt)
8428 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8430 // ERET instruction (return from interrupt)
8436 for(hr=0;hr<HOST_REGS;hr++) {
8437 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8438 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8439 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8440 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8444 for(hr=0;hr<HOST_REGS;hr++)
8446 // Overwritten registers are not needed
8447 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8448 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8449 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8450 // Source registers are needed
8451 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8452 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8453 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8454 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8455 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8456 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8457 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8459 if(dops[i].is_store) {
8460 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8461 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8463 // Don't store a register immediately after writing it,
8464 // may prevent dual-issue.
8465 // But do so if this is a branch target, otherwise we
8466 // might have to load the register before the branch.
8467 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
8468 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
8469 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8470 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8472 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
8473 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8474 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8478 // Cycle count is needed at branches. Assume it is needed at the target too.
8479 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
8480 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8481 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8486 // Deallocate unneeded registers
8487 for(hr=0;hr<HOST_REGS;hr++)
8490 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8493 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8494 if (dops[i+1].is_load || dops[i+1].is_store)
8496 if (dops[i+1].is_store)
8498 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8500 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8501 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8502 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8503 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
8504 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8505 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8506 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8507 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
8509 regs[i].regmap[hr]=-1;
8510 regs[i].isconst&=~(1<<hr);
8511 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8512 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8513 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8514 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
8515 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8516 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8517 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8518 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
8520 branch_regs[i].regmap[hr]=-1;
8521 branch_regs[i].regmap_entry[hr]=-1;
8522 if (!dops[i].is_ujump)
8525 regmap_pre[i+2][hr]=-1;
8526 regs[i+2].wasconst&=~(1<<hr);
8537 int map1 = -1, map2 = -1, temp=-1;
8538 if (dops[i].is_load || dops[i].is_store)
8540 if (dops[i].is_store)
8542 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8544 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8545 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8546 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8547 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8548 regs[i].regmap[hr] != CCREG)
8550 if(i<slen-1&&!dops[i].is_ds) {
8551 assert(regs[i].regmap[hr]<64);
8552 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8553 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8555 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8556 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8558 regmap_pre[i+1][hr]=-1;
8559 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8560 regs[i+1].wasconst&=~(1<<hr);
8562 regs[i].regmap[hr]=-1;
8563 regs[i].isconst&=~(1<<hr);
8571 /* Pass 5 - Pre-allocate registers */
8573 // If a register is allocated during a loop, try to allocate it for the
8574 // entire loop, if possible. This avoids loading/storing registers
8575 // inside of the loop.
8577 signed char f_regmap[HOST_REGS];
8578 clear_all_regs(f_regmap);
8579 for(i=0;i<slen-1;i++)
8581 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8583 if(ba[i]>=start && ba[i]<(start+i*4))
8584 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8585 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8586 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8587 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8588 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8590 int t=(ba[i]-start)>>2;
8591 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8592 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8593 for(hr=0;hr<HOST_REGS;hr++)
8595 if(regs[i].regmap[hr]>=0) {
8596 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8597 // dealloc old register
8599 for(n=0;n<HOST_REGS;n++)
8601 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8603 // and alloc new one
8604 f_regmap[hr]=regs[i].regmap[hr];
8607 if(branch_regs[i].regmap[hr]>=0) {
8608 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8609 // dealloc old register
8611 for(n=0;n<HOST_REGS;n++)
8613 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8615 // and alloc new one
8616 f_regmap[hr]=branch_regs[i].regmap[hr];
8620 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8621 f_regmap[hr]=branch_regs[i].regmap[hr];
8623 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8624 f_regmap[hr]=branch_regs[i].regmap[hr];
8626 // Avoid dirty->clean transition
8627 #ifdef DESTRUCTIVE_WRITEBACK
8628 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8630 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8631 // case above, however it's always a good idea. We can't hoist the
8632 // load if the register was already allocated, so there's no point
8633 // wasting time analyzing most of these cases. It only "succeeds"
8634 // when the mapping was different and the load can be replaced with
8635 // a mov, which is of negligible benefit. So such cases are
8637 if(f_regmap[hr]>0) {
8638 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8642 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8643 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8645 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8646 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8648 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8649 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8651 if(get_reg(regs[i].regmap,r&63)<0) break;
8652 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8655 while(k>1&®s[k-1].regmap[hr]==-1) {
8656 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8657 //printf("no free regs for store %x\n",start+(k-1)*4);
8660 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8661 //printf("no-match due to different register\n");
8664 if (dops[k-2].is_jump) {
8665 //printf("no-match due to branch\n");
8668 // call/ret fast path assumes no registers allocated
8669 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8675 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8676 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8678 regs[k].regmap_entry[hr]=f_regmap[hr];
8679 regs[k].regmap[hr]=f_regmap[hr];
8680 regmap_pre[k+1][hr]=f_regmap[hr];
8681 regs[k].wasdirty&=~(1<<hr);
8682 regs[k].dirty&=~(1<<hr);
8683 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8684 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8685 regs[k].wasconst&=~(1<<hr);
8686 regs[k].isconst&=~(1<<hr);
8691 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8694 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8695 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8696 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8697 regs[i].regmap_entry[hr]=f_regmap[hr];
8698 regs[i].regmap[hr]=f_regmap[hr];
8699 regs[i].wasdirty&=~(1<<hr);
8700 regs[i].dirty&=~(1<<hr);
8701 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8702 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8703 regs[i].wasconst&=~(1<<hr);
8704 regs[i].isconst&=~(1<<hr);
8705 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8706 branch_regs[i].wasdirty&=~(1<<hr);
8707 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8708 branch_regs[i].regmap[hr]=f_regmap[hr];
8709 branch_regs[i].dirty&=~(1<<hr);
8710 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8711 branch_regs[i].wasconst&=~(1<<hr);
8712 branch_regs[i].isconst&=~(1<<hr);
8713 if (!dops[i].is_ujump) {
8714 regmap_pre[i+2][hr]=f_regmap[hr];
8715 regs[i+2].wasdirty&=~(1<<hr);
8716 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8721 // Alloc register clean at beginning of loop,
8722 // but may dirty it in pass 6
8723 regs[k].regmap_entry[hr]=f_regmap[hr];
8724 regs[k].regmap[hr]=f_regmap[hr];
8725 regs[k].dirty&=~(1<<hr);
8726 regs[k].wasconst&=~(1<<hr);
8727 regs[k].isconst&=~(1<<hr);
8728 if (dops[k].is_jump) {
8729 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8730 branch_regs[k].regmap[hr]=f_regmap[hr];
8731 branch_regs[k].dirty&=~(1<<hr);
8732 branch_regs[k].wasconst&=~(1<<hr);
8733 branch_regs[k].isconst&=~(1<<hr);
8734 if (!dops[k].is_ujump) {
8735 regmap_pre[k+2][hr]=f_regmap[hr];
8736 regs[k+2].wasdirty&=~(1<<hr);
8741 regmap_pre[k+1][hr]=f_regmap[hr];
8742 regs[k+1].wasdirty&=~(1<<hr);
8745 if(regs[j].regmap[hr]==f_regmap[hr])
8746 regs[j].regmap_entry[hr]=f_regmap[hr];
8750 if(regs[j].regmap[hr]>=0)
8752 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8753 //printf("no-match due to different register\n");
8756 if (dops[j].is_ujump)
8758 // Stop on unconditional branch
8761 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8764 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8767 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8770 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8771 //printf("no-match due to different register (branch)\n");
8775 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8776 //printf("No free regs for store %x\n",start+j*4);
8779 assert(f_regmap[hr]<64);
8786 // Non branch or undetermined branch target
8787 for(hr=0;hr<HOST_REGS;hr++)
8789 if(hr!=EXCLUDE_REG) {
8790 if(regs[i].regmap[hr]>=0) {
8791 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8792 // dealloc old register
8794 for(n=0;n<HOST_REGS;n++)
8796 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8798 // and alloc new one
8799 f_regmap[hr]=regs[i].regmap[hr];
8804 // Try to restore cycle count at branch targets
8806 for(j=i;j<slen-1;j++) {
8807 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8808 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8809 //printf("no free regs for store %x\n",start+j*4);
8813 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8815 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8817 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8818 regs[k].regmap[HOST_CCREG]=CCREG;
8819 regmap_pre[k+1][HOST_CCREG]=CCREG;
8820 regs[k+1].wasdirty|=1<<HOST_CCREG;
8821 regs[k].dirty|=1<<HOST_CCREG;
8822 regs[k].wasconst&=~(1<<HOST_CCREG);
8823 regs[k].isconst&=~(1<<HOST_CCREG);
8826 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8828 // Work backwards from the branch target
8829 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8831 //printf("Extend backwards\n");
8834 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8835 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8836 //printf("no free regs for store %x\n",start+(k-1)*4);
8841 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8842 //printf("Extend CC, %x ->\n",start+k*4);
8844 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8845 regs[k].regmap[HOST_CCREG]=CCREG;
8846 regmap_pre[k+1][HOST_CCREG]=CCREG;
8847 regs[k+1].wasdirty|=1<<HOST_CCREG;
8848 regs[k].dirty|=1<<HOST_CCREG;
8849 regs[k].wasconst&=~(1<<HOST_CCREG);
8850 regs[k].isconst&=~(1<<HOST_CCREG);
8855 //printf("Fail Extend CC, %x ->\n",start+k*4);
8859 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8860 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8861 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8863 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8868 // This allocates registers (if possible) one instruction prior
8869 // to use, which can avoid a load-use penalty on certain CPUs.
8870 for(i=0;i<slen-1;i++)
8872 if (!i || !dops[i-1].is_jump)
8876 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8877 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8880 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8882 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8884 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8885 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8886 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8887 regs[i].isconst&=~(1<<hr);
8888 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8889 constmap[i][hr]=constmap[i+1][hr];
8890 regs[i+1].wasdirty&=~(1<<hr);
8891 regs[i].dirty&=~(1<<hr);
8896 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8898 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8900 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8901 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8902 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8903 regs[i].isconst&=~(1<<hr);
8904 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8905 constmap[i][hr]=constmap[i+1][hr];
8906 regs[i+1].wasdirty&=~(1<<hr);
8907 regs[i].dirty&=~(1<<hr);
8911 // Preload target address for load instruction (non-constant)
8912 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8913 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8915 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8917 regs[i].regmap[hr]=dops[i+1].rs1;
8918 regmap_pre[i+1][hr]=dops[i+1].rs1;
8919 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8920 regs[i].isconst&=~(1<<hr);
8921 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8922 constmap[i][hr]=constmap[i+1][hr];
8923 regs[i+1].wasdirty&=~(1<<hr);
8924 regs[i].dirty&=~(1<<hr);
8928 // Load source into target register
8929 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8930 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8932 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8934 regs[i].regmap[hr]=dops[i+1].rs1;
8935 regmap_pre[i+1][hr]=dops[i+1].rs1;
8936 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8937 regs[i].isconst&=~(1<<hr);
8938 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8939 constmap[i][hr]=constmap[i+1][hr];
8940 regs[i+1].wasdirty&=~(1<<hr);
8941 regs[i].dirty&=~(1<<hr);
8945 // Address for store instruction (non-constant)
8946 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8947 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8948 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8949 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8950 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8952 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8953 regs[i+1].isconst&=~(1<<hr);
8956 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8958 regs[i].regmap[hr]=dops[i+1].rs1;
8959 regmap_pre[i+1][hr]=dops[i+1].rs1;
8960 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8961 regs[i].isconst&=~(1<<hr);
8962 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8963 constmap[i][hr]=constmap[i+1][hr];
8964 regs[i+1].wasdirty&=~(1<<hr);
8965 regs[i].dirty&=~(1<<hr);
8969 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8970 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8972 hr=get_reg(regs[i+1].regmap,FTEMP);
8974 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8976 regs[i].regmap[hr]=dops[i+1].rs1;
8977 regmap_pre[i+1][hr]=dops[i+1].rs1;
8978 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8979 regs[i].isconst&=~(1<<hr);
8980 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8981 constmap[i][hr]=constmap[i+1][hr];
8982 regs[i+1].wasdirty&=~(1<<hr);
8983 regs[i].dirty&=~(1<<hr);
8985 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8987 // move it to another register
8988 regs[i+1].regmap[hr]=-1;
8989 regmap_pre[i+2][hr]=-1;
8990 regs[i+1].regmap[nr]=FTEMP;
8991 regmap_pre[i+2][nr]=FTEMP;
8992 regs[i].regmap[nr]=dops[i+1].rs1;
8993 regmap_pre[i+1][nr]=dops[i+1].rs1;
8994 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8995 regs[i].isconst&=~(1<<nr);
8996 regs[i+1].isconst&=~(1<<nr);
8997 regs[i].dirty&=~(1<<nr);
8998 regs[i+1].wasdirty&=~(1<<nr);
8999 regs[i+1].dirty&=~(1<<nr);
9000 regs[i+2].wasdirty&=~(1<<nr);
9004 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
9005 if(dops[i+1].itype==LOAD)
9006 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
9007 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
9008 hr=get_reg(regs[i+1].regmap,FTEMP);
9009 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
9010 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9011 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9013 if(hr>=0&®s[i].regmap[hr]<0) {
9014 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
9015 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9016 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9017 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9018 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9019 regs[i].isconst&=~(1<<hr);
9020 regs[i+1].wasdirty&=~(1<<hr);
9021 regs[i].dirty&=~(1<<hr);
9030 /* Pass 6 - Optimize clean/dirty state */
9031 clean_registers(0,slen-1,1);
9033 /* Pass 7 - Identify 32-bit registers */
9034 for (i=slen-1;i>=0;i--)
9036 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
9038 // Conditional branch
9039 if((source[i]>>16)!=0x1000&&i<slen-2) {
9040 // Mark this address as a branch target since it may be called
9041 // upon return from interrupt
9047 if(dops[slen-1].itype==SPAN) {
9048 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
9051 #ifdef REG_ALLOC_PRINT
9052 /* Debug/disassembly */
9057 for(r=1;r<=CCREG;r++) {
9058 if((unneeded_reg[i]>>r)&1) {
9059 if(r==HIREG) printf(" HI");
9060 else if(r==LOREG) printf(" LO");
9061 else printf(" r%d",r);
9065 #if defined(__i386__) || defined(__x86_64__)
9066 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9069 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9071 #if defined(__i386__) || defined(__x86_64__)
9073 if(needed_reg[i]&1) printf("eax ");
9074 if((needed_reg[i]>>1)&1) printf("ecx ");
9075 if((needed_reg[i]>>2)&1) printf("edx ");
9076 if((needed_reg[i]>>3)&1) printf("ebx ");
9077 if((needed_reg[i]>>5)&1) printf("ebp ");
9078 if((needed_reg[i]>>6)&1) printf("esi ");
9079 if((needed_reg[i]>>7)&1) printf("edi ");
9081 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9083 if(regs[i].wasdirty&1) printf("eax ");
9084 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9085 if((regs[i].wasdirty>>2)&1) printf("edx ");
9086 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9087 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9088 if((regs[i].wasdirty>>6)&1) printf("esi ");
9089 if((regs[i].wasdirty>>7)&1) printf("edi ");
9092 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9094 if(regs[i].wasdirty&1) printf("r0 ");
9095 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9096 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9097 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9098 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9099 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9100 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9101 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9102 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9103 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9104 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9105 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9108 disassemble_inst(i);
9109 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9110 #if defined(__i386__) || defined(__x86_64__)
9111 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9112 if(regs[i].dirty&1) printf("eax ");
9113 if((regs[i].dirty>>1)&1) printf("ecx ");
9114 if((regs[i].dirty>>2)&1) printf("edx ");
9115 if((regs[i].dirty>>3)&1) printf("ebx ");
9116 if((regs[i].dirty>>5)&1) printf("ebp ");
9117 if((regs[i].dirty>>6)&1) printf("esi ");
9118 if((regs[i].dirty>>7)&1) printf("edi ");
9121 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9122 if(regs[i].dirty&1) printf("r0 ");
9123 if((regs[i].dirty>>1)&1) printf("r1 ");
9124 if((regs[i].dirty>>2)&1) printf("r2 ");
9125 if((regs[i].dirty>>3)&1) printf("r3 ");
9126 if((regs[i].dirty>>4)&1) printf("r4 ");
9127 if((regs[i].dirty>>5)&1) printf("r5 ");
9128 if((regs[i].dirty>>6)&1) printf("r6 ");
9129 if((regs[i].dirty>>7)&1) printf("r7 ");
9130 if((regs[i].dirty>>8)&1) printf("r8 ");
9131 if((regs[i].dirty>>9)&1) printf("r9 ");
9132 if((regs[i].dirty>>10)&1) printf("r10 ");
9133 if((regs[i].dirty>>12)&1) printf("r12 ");
9136 if(regs[i].isconst) {
9137 printf("constants: ");
9138 #if defined(__i386__) || defined(__x86_64__)
9139 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9140 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9141 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9142 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9143 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9144 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9145 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
9147 #if defined(__arm__) || defined(__aarch64__)
9149 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9150 if ((regs[i].isconst >> r) & 1)
9151 printf(" r%d=%x", r, (u_int)constmap[i][r]);
9155 if(dops[i].is_jump) {
9156 #if defined(__i386__) || defined(__x86_64__)
9157 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9158 if(branch_regs[i].dirty&1) printf("eax ");
9159 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9160 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9161 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9162 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9163 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9164 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9167 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9168 if(branch_regs[i].dirty&1) printf("r0 ");
9169 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9170 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9171 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9172 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9173 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9174 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9175 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9176 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9177 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9178 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9179 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9183 #endif // REG_ALLOC_PRINT
9185 /* Pass 8 - Assembly */
9186 linkcount=0;stubcount=0;
9187 ds=0;is_delayslot=0;
9189 void *beginning=start_block();
9194 void *instr_addr0_override = NULL;
9196 if (start == 0x80030000) {
9197 // nasty hack for the fastbios thing
9198 // override block entry to this code
9199 instr_addr0_override = out;
9200 emit_movimm(start,0);
9201 // abuse io address var as a flag that we
9202 // have already returned here once
9203 emit_readword(&address,1);
9204 emit_writeword(0,&pcaddr);
9205 emit_writeword(0,&address);
9208 emit_jeq(out + 4*2);
9209 emit_far_jump(new_dyna_leave);
9211 emit_jne(new_dyna_leave);
9216 //if(ds) printf("ds: ");
9217 disassemble_inst(i);
9219 ds=0; // Skip delay slot
9220 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9221 instr_addr[i] = NULL;
9223 speculate_register_values(i);
9224 #ifndef DESTRUCTIVE_WRITEBACK
9225 if (i < 2 || !dops[i-2].is_ujump)
9227 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9229 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9230 dirty_pre=branch_regs[i].dirty;
9232 dirty_pre=regs[i].dirty;
9236 if (i < 2 || !dops[i-2].is_ujump)
9238 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9239 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9241 // branch target entry point
9242 instr_addr[i] = out;
9243 assem_debug("<->\n");
9244 drc_dbg_emit_do_cmp(i, ccadj[i]);
9245 if (clear_hack_addr) {
9247 emit_writeword(0, &hack_addr);
9248 clear_hack_addr = 0;
9252 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9253 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9254 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9255 address_generation(i,®s[i],regs[i].regmap_entry);
9256 load_consts(regmap_pre[i],regs[i].regmap,i);
9259 // Load the delay slot registers if necessary
9260 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9261 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9262 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9263 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9264 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9265 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9266 if (dops[i+1].is_store)
9267 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9271 // Preload registers for following instruction
9272 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9273 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9274 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9275 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9276 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9277 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9279 // TODO: if(is_ooo(i)) address_generation(i+1);
9280 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9281 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
9282 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9283 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9284 if (dops[i].is_store)
9285 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9287 ds = assemble(i, ®s[i], ccadj[i]);
9289 if (dops[i].is_ujump)
9292 literal_pool_jumpover(256);
9297 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9298 // no ending needed for this block since INTCALL never returns
9300 // If the block did not end with an unconditional branch,
9301 // add a jump to the next instruction.
9303 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9304 assert(!dops[i-1].is_jump);
9306 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9307 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9308 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9309 emit_loadreg(CCREG,HOST_CCREG);
9310 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9314 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9315 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9317 add_to_linker(out,start+i*4,0);
9324 assert(!dops[i-1].is_jump);
9325 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9326 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9327 emit_loadreg(CCREG,HOST_CCREG);
9328 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9329 add_to_linker(out,start+i*4,0);
9333 // TODO: delay slot stubs?
9335 for(i=0;i<stubcount;i++)
9337 switch(stubs[i].type)
9345 do_readstub(i);break;
9350 do_writestub(i);break;
9354 do_invstub(i);break;
9356 do_cop1stub(i);break;
9358 do_unalignedwritestub(i);break;
9362 if (instr_addr0_override)
9363 instr_addr[0] = instr_addr0_override;
9365 /* Pass 9 - Linker */
9366 for(i=0;i<linkcount;i++)
9368 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9370 if (!link_addr[i].ext)
9373 void *addr = check_addr(link_addr[i].target);
9374 emit_extjump(link_addr[i].addr, link_addr[i].target);
9376 set_jump_target(link_addr[i].addr, addr);
9377 add_jump_out(link_addr[i].target,stub);
9380 set_jump_target(link_addr[i].addr, stub);
9385 int target=(link_addr[i].target-start)>>2;
9386 assert(target>=0&&target<slen);
9387 assert(instr_addr[target]);
9388 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9389 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9391 set_jump_target(link_addr[i].addr, instr_addr[target]);
9396 u_int source_len = slen*4;
9397 if (dops[slen-1].itype == INTCALL && source_len > 4)
9398 // no need to treat the last instruction as compiled
9399 // as interpreter fully handles it
9402 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9405 // External Branch Targets (jump_in)
9408 if(dops[i].bt||i==0)
9410 if(instr_addr[i]) // TODO - delay slots (=null)
9412 u_int vaddr=start+i*4;
9413 u_int page=get_page(vaddr);
9414 u_int vpage=get_vpage(vaddr);
9417 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
9418 assem_debug("jump_in: %x\n",start+i*4);
9419 ll_add(jump_dirty+vpage,vaddr,out);
9420 void *entry_point = do_dirty_stub(i, source_len);
9421 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
9422 // If there was an existing entry in the hash table,
9423 // replace it with the new address.
9424 // Don't add new entries. We'll insert the
9425 // ones that actually get used in check_addr().
9426 struct ht_entry *ht_bin = hash_table_get(vaddr);
9427 if (ht_bin->vaddr[0] == vaddr)
9428 ht_bin->tcaddr[0] = entry_point;
9429 if (ht_bin->vaddr[1] == vaddr)
9430 ht_bin->tcaddr[1] = entry_point;
9435 // Write out the literal pool if necessary
9437 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9439 if(((u_int)out)&7) emit_addnop(13);
9441 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9442 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9443 memcpy(copy, source, source_len);
9446 end_block(beginning);
9448 // If we're within 256K of the end of the buffer,
9449 // start over from the beginning. (Is 256K enough?)
9450 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9451 out = ndrc->translation_cache;
9453 // Trap writes to any of the pages we compiled
9454 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9457 inv_code_start=inv_code_end=~0;
9459 // for PCSX we need to mark all mirrors too
9460 if(get_page(start)<(RAM_SIZE>>12))
9461 for(i=start>>12;i<=(start+slen*4)>>12;i++)
9462 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9463 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9464 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9466 /* Pass 10 - Free memory by expiring oldest blocks */
9468 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
9471 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
9472 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9473 uintptr_t base_offs_s = base_offs >> shift;
9474 inv_debug("EXP: Phase %d\n",expirep);
9475 switch((expirep>>11)&3)
9478 // Clear jump_in and jump_dirty
9479 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9480 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9481 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9482 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
9486 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9487 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
9492 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9493 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9494 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9495 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9496 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9497 ht_bin->vaddr[1] = -1;
9498 ht_bin->tcaddr[1] = NULL;
9500 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9501 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9502 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9503 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9504 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9505 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9506 ht_bin->vaddr[1] = -1;
9507 ht_bin->tcaddr[1] = NULL;
9513 if((expirep&2047)==0)
9515 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9516 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
9519 expirep=(expirep+1)&65535;
9527 // vim:shiftwidth=2:expandtab