libpcsxcore/psxhw.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 /*
  21 * Functions for PSX hardware control.
  22 */
  23
  24 #include "psxhw.h"
  25 #include "psxevents.h"
  26 #include "mdec.h"
  27 #include "cdrom.h"
  28 #include "gpu.h"
  29
  30 static u32 (*psxHwReadGpuSRptr)(void) = psxHwReadGpuSR;
  31
  32 void psxHwReset() {
  33         memset(psxH, 0, 0x10000);
  34
  35         mdecInit(); // initialize mdec decoder
  36         cdrReset();
  37         psxRcntInit();
  38         HW_GPU_STATUS = SWAP32(0x10802000);
  39         psxHwReadGpuSRptr = Config.hacks.gpu_busy
  40                 ? psxHwReadGpuSRbusyHack : psxHwReadGpuSR;
  41 }
  42
  43 void psxHwWriteIstat(u32 value)
  44 {
  45         u32 stat = psxHu16(0x1070) & value;
  46         psxHu16ref(0x1070) = SWAPu16(stat);
  47
  48         psxRegs.CP0.n.Cause &= ~0x400;
  49         if (stat & psxHu16(0x1074))
  50                 psxRegs.CP0.n.Cause |= 0x400;
  51 }
  52
  53 void psxHwWriteImask(u32 value)
  54 {
  55         u32 stat = psxHu16(0x1070);
  56         psxHu16ref(0x1074) = SWAPu16(value);
  57         if (stat & value) {
  58                 //if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
  59                 //      log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
  60                 set_event(PSXINT_NEWDRC_CHECK, 1);
  61         }
  62         psxRegs.CP0.n.Cause &= ~0x400;
  63         if (stat & value)
  64                 psxRegs.CP0.n.Cause |= 0x400;
  65 }
  66
  67 #define make_dma_func(n) \
  68 void psxHwWriteChcr##n(u32 value) \
  69 { \
  70         if (value & SWAPu32(HW_DMA##n##_CHCR) & 0x01000000) \
  71                 log_unhandled("dma" #n " %08x -> %08x\n", HW_DMA##n##_CHCR, value); \
  72         HW_DMA##n##_CHCR = SWAPu32(value); \
  73         if (value & 0x01000000 && SWAPu32(HW_DMA_PCR) & (8u << (n * 4))) \
  74                 psxDma##n(SWAPu32(HW_DMA##n##_MADR), SWAPu32(HW_DMA##n##_BCR), value); \
  75 }
  76
  77 make_dma_func(0)
  78 make_dma_func(1)
  79 make_dma_func(2)
  80 make_dma_func(3)
  81 make_dma_func(4)
  82 make_dma_func(6)
  83
  84 void psxHwWriteDmaIcr32(u32 value)
  85 {
  86         u32 tmp = value & 0x00ff803f;
  87         tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
  88         if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
  89             || tmp & HW_DMA_ICR_BUS_ERROR) {
  90                 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
  91                         psxHu32ref(0x1070) |= SWAP32(8);
  92                 tmp |= HW_DMA_ICR_IRQ_SENT;
  93         }
  94         HW_DMA_ICR = SWAPu32(tmp);
  95 }
  96
  97 void psxHwWriteGpuSR(u32 value)
  98 {
  99         u32 old_sr = HW_GPU_STATUS, new_sr;
 100         GPU_writeStatus(value);
 101         gpuSyncPluginSR();
 102         new_sr = HW_GPU_STATUS;
 103         // "The Next Tetris" seems to rely on the field order after enable
 104         if ((old_sr ^ new_sr) & new_sr & SWAP32(PSXGPU_ILACE))
 105                 frame_counter |= 1;
 106 }
 107
 108 u32 psxHwReadGpuSR(void)
 109 {
 110         u32 v, c = psxRegs.cycle;
 111
 112         // meh2, syncing for img bit, might want to avoid it..
 113         gpuSyncPluginSR();
 114         v = SWAP32(HW_GPU_STATUS);
 115         v |= ((s32)(psxRegs.gpuIdleAfter - c) >> 31) & PSXGPU_nBUSY;
 116
 117         // XXX: because of large timeslices can't use hSyncCount, using rough
 118         // approximization instead. Perhaps better use hcounter code here or something.
 119         if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
 120                 v |= PSXGPU_LCF & (c << 20);
 121         return v;
 122 }
 123
 124 // a hack due to poor timing of gpu idle bit
 125 // to get rid of this, GPU draw times, DMAs, cpu timing has to fall within
 126 // certain timing window or else games like "ToHeart" softlock
 127 u32 psxHwReadGpuSRbusyHack(void)
 128 {
 129         u32 v = psxHwReadGpuSR();
 130         static u32 hack;
 131         if (!(hack++ & 3))
 132                 v &= ~PSXGPU_nBUSY;
 133         return v;
 134 }
 135
 136 u8 psxHwRead8(u32 add) {
 137         u8 hard;
 138
 139         switch (add & 0xffff) {
 140         case 0x1040: hard = sioRead8(); break;
 141         case 0x1800: hard = cdrRead0(); break;
 142         case 0x1801: hard = cdrRead1(); break;
 143         case 0x1802: hard = cdrRead2(); break;
 144         case 0x1803: hard = cdrRead3(); break;
 145
 146         case 0x1041: case 0x1042: case 0x1043:
 147         case 0x1044: case 0x1045:
 148         case 0x1046: case 0x1047:
 149         case 0x1048: case 0x1049:
 150         case 0x104a: case 0x104b:
 151         case 0x104c: case 0x104d:
 152         case 0x104e: case 0x104f:
 153         case 0x1050: case 0x1051:
 154         case 0x1054: case 0x1055:
 155         case 0x1058: case 0x1059:
 156         case 0x105a: case 0x105b:
 157         case 0x105c: case 0x105d:
 158         case 0x1100: case 0x1101:
 159         case 0x1104: case 0x1105:
 160         case 0x1108: case 0x1109:
 161         case 0x1110: case 0x1111:
 162         case 0x1114: case 0x1115:
 163         case 0x1118: case 0x1119:
 164         case 0x1120: case 0x1121:
 165         case 0x1124: case 0x1125:
 166         case 0x1128: case 0x1129:
 167         case 0x1810: case 0x1811:
 168         case 0x1812: case 0x1813:
 169         case 0x1814: case 0x1815:
 170         case 0x1816: case 0x1817:
 171         case 0x1820: case 0x1821:
 172         case 0x1822: case 0x1823:
 173         case 0x1824: case 0x1825:
 174         case 0x1826: case 0x1827:
 175                 log_unhandled("unhandled r8  %08x @%08x\n", add, psxRegs.pc);
 176                 // falthrough
 177         default:
 178                 if (0x1f801c00 <= add && add < 0x1f802000) {
 179                         u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
 180                         hard = (add & 1) ? val >> 8 : val;
 181                         break;
 182                 }
 183                 hard = psxHu8(add);
 184         }
 185
 186         //printf("r8  %08x       %02x @%08x\n", add, hard, psxRegs.pc);
 187         return hard;
 188 }
 189
 190 u16 psxHwRead16(u32 add) {
 191         unsigned short hard;
 192
 193         switch (add & 0xffff) {
 194         case 0x1040: hard = sioRead8(); break;
 195         case 0x1044: hard = sioReadStat16(); break;
 196         case 0x1048: hard = sioReadMode16(); break;
 197         case 0x104a: hard = sioReadCtrl16(); break;
 198         case 0x104e: hard = sioReadBaud16(); break;
 199         case 0x1054: hard = 0x80; break; // Armored Core Link cable misdetection
 200         case 0x1100: hard = psxRcntRcount0(); break;
 201         case 0x1104: hard = psxRcntRmode(0); break;
 202         case 0x1108: hard = psxRcntRtarget(0); break;
 203         case 0x1110: hard = psxRcntRcount1(); break;
 204         case 0x1114: hard = psxRcntRmode(1); break;
 205         case 0x1118: hard = psxRcntRtarget(1); break;
 206         case 0x1120: hard = psxRcntRcount2(); break;
 207         case 0x1124: hard = psxRcntRmode(2); break;
 208         case 0x1128: hard = psxRcntRtarget(2); break;
 209
 210         case 0x1042:
 211         case 0x1046:
 212         case 0x104c:
 213         case 0x1050:
 214         case 0x1058:
 215         case 0x105a:
 216         case 0x105c:
 217         case 0x1800:
 218         case 0x1802:
 219         case 0x1810:
 220         case 0x1812:
 221         case 0x1814:
 222         case 0x1816:
 223         case 0x1820:
 224         case 0x1822:
 225         case 0x1824:
 226         case 0x1826:
 227                 log_unhandled("unhandled r16 %08x @%08x\n", add, psxRegs.pc);
 228                 // falthrough
 229         default:
 230                 if (0x1f801c00 <= add && add < 0x1f802000) {
 231                         hard = SPU_readRegister(add, psxRegs.cycle);
 232                         break;
 233                 }
 234                 hard = psxHu16(add);
 235         }
 236
 237         //printf("r16 %08x     %04x @%08x\n", add, hard, psxRegs.pc);
 238         return hard;
 239 }
 240
 241 u32 psxHwRead32(u32 add) {
 242         u32 hard;
 243
 244         switch (add & 0xffff) {
 245         case 0x1040: hard = sioRead8(); break;
 246         case 0x1044: hard = sioReadStat16(); break;
 247         case 0x1100: hard = psxRcntRcount0(); break;
 248         case 0x1104: hard = psxRcntRmode(0); break;
 249         case 0x1108: hard = psxRcntRtarget(0); break;
 250         case 0x1110: hard = psxRcntRcount1(); break;
 251         case 0x1114: hard = psxRcntRmode(1); break;
 252         case 0x1118: hard = psxRcntRtarget(1); break;
 253         case 0x1120: hard = psxRcntRcount2(); break;
 254         case 0x1124: hard = psxRcntRmode(2); break;
 255         case 0x1128: hard = psxRcntRtarget(2); break;
 256         case 0x1810: hard = GPU_readData(); break;
 257         case 0x1814: hard = psxHwReadGpuSRptr(); break;
 258         case 0x1820: hard = mdecRead0(); break;
 259         case 0x1824: hard = mdecRead1(); break;
 260
 261         case 0x1048:
 262         case 0x104c:
 263         case 0x1050:
 264         case 0x1054:
 265         case 0x1058:
 266         case 0x105c:
 267         case 0x1800:
 268                 log_unhandled("unhandled r32 %08x @%08x\n", add, psxRegs.pc);
 269                 // falthrough
 270         default:
 271                 if (0x1f801c00 <= add && add < 0x1f802000) {
 272                         hard = SPU_readRegister(add, psxRegs.cycle);
 273                         hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
 274                         break;
 275                 }
 276                 hard = psxHu32(add);
 277         }
 278         //printf("r32 %08x %08x @%08x\n", add, hard, psxRegs.pc);
 279         return hard;
 280 }
 281
 282 void psxHwWrite8(u32 add, u32 value) {
 283         switch (add & 0xffff) {
 284         case 0x1040: sioWrite8(value); return;
 285         case 0x10f6:
 286                 // nocash documents it as forced w32, but still games use this?
 287                 break;
 288         case 0x1800: cdrWrite0(value); return;
 289         case 0x1801: cdrWrite1(value); return;
 290         case 0x1802: cdrWrite2(value); return;
 291         case 0x1803: cdrWrite3(value); return;
 292         case 0x2041: break; // "POST (external 7 segment display)"
 293
 294         default:
 295                 if (0x1f801c00 <= add && add < 0x1f802000) {
 296                         log_unhandled("spu w8 %02x @%08x\n", value, psxRegs.pc);
 297                         if (!(add & 1))
 298                                 SPU_writeRegister(add, value, psxRegs.cycle);
 299                         return;
 300                 }
 301                 else
 302                         log_unhandled("unhandled w8  %08x %08x @%08x\n",
 303                                 add, value, psxRegs.pc);
 304         }
 305         psxHu8(add) = value;
 306 }
 307
 308 void psxHwWrite16(u32 add, u32 value) {
 309         switch (add & 0xffff) {
 310         case 0x1040: sioWrite8(value); return;
 311         case 0x1044: sioWriteStat16(value); return;
 312         case 0x1048: sioWriteMode16(value); return;
 313         case 0x104a: sioWriteCtrl16(value); return;
 314         case 0x104e: sioWriteBaud16(value); return;
 315         case 0x1070: psxHwWriteIstat(value); return;
 316         case 0x1074: psxHwWriteImask(value); return;
 317         case 0x1100: psxRcntWcount(0, value); return;
 318         case 0x1104: psxRcntWmode(0, value); return;
 319         case 0x1108: psxRcntWtarget(0, value); return;
 320         case 0x1110: psxRcntWcount(1, value); return;
 321         case 0x1114: psxRcntWmode(1, value); return;
 322         case 0x1118: psxRcntWtarget(1, value); return;
 323         case 0x1120: psxRcntWcount(2, value); return;
 324         case 0x1124: psxRcntWmode(2, value); return;
 325         case 0x1128: psxRcntWtarget(2, value); return;
 326
 327         // forced write32:
 328         case 0x1088: // DMA0 chcr (MDEC in DMA)
 329         case 0x108c: psxHwWriteChcr0(value); return;
 330         case 0x1098: // DMA1 chcr (MDEC out DMA)
 331         case 0x109c: psxHwWriteChcr1(value); return;
 332         case 0x10a8: // DMA2 chcr (GPU DMA)
 333         case 0x10ac: psxHwWriteChcr2(value); return;
 334         case 0x10b8: // DMA3 chcr (CDROM DMA)
 335         case 0x10bc: psxHwWriteChcr3(value); return;
 336         case 0x10c8: // DMA4 chcr (SPU DMA)
 337         case 0x10cc: psxHwWriteChcr4(value); return;
 338         case 0x10e8: // DMA6 chcr (OT clear)
 339         case 0x10ec: psxHwWriteChcr6(value); return;
 340         case 0x10f4: psxHwWriteDmaIcr32(value); return;
 341
 342         // forced write32 with no immediate effect:
 343         case 0x1014:
 344         case 0x1060:
 345         case 0x1080:
 346         case 0x1090:
 347         case 0x10a0:
 348         case 0x10b0:
 349         case 0x10c0:
 350         case 0x10d0:
 351         case 0x10e0:
 352         case 0x10f0:
 353                 psxHu32ref(add) = SWAPu32(value);
 354                 return;
 355
 356         case 0x1800:
 357         case 0x1802:
 358         case 0x1810:
 359         case 0x1812:
 360         case 0x1814:
 361         case 0x1816:
 362         case 0x1820:
 363         case 0x1822:
 364         case 0x1824:
 365         case 0x1826:
 366                 log_unhandled("unhandled w16 %08x @%08x\n", add, psxRegs.pc);
 367                 break;
 368
 369         default:
 370                 if (0x1f801c00 <= add && add < 0x1f802000) {
 371                         SPU_writeRegister(add, value, psxRegs.cycle);
 372                         return;
 373                 }
 374                 else if (0x1f801000 <= add && add < 0x1f801800)
 375                         log_unhandled("unhandled w16 %08x %08x @%08x\n",
 376                                 add, value, psxRegs.pc);
 377         }
 378         psxHu16ref(add) = SWAPu16(value);
 379 }
 380
 381 void psxHwWrite32(u32 add, u32 value) {
 382         switch (add & 0xffff) {
 383         case 0x1040: sioWrite8(value); return;
 384         case 0x1070: psxHwWriteIstat(value); return;
 385         case 0x1074: psxHwWriteImask(value); return;
 386         case 0x1088: // DMA0 chcr (MDEC in DMA)
 387         case 0x108c: psxHwWriteChcr0(value); return;
 388         case 0x1098: // DMA1 chcr (MDEC out DMA)
 389         case 0x109c: psxHwWriteChcr1(value); return;
 390         case 0x10a8: // DMA2 chcr (GPU DMA)
 391         case 0x10ac: psxHwWriteChcr2(value); return;
 392         case 0x10b8: // DMA3 chcr (CDROM DMA)
 393         case 0x10bc: psxHwWriteChcr3(value); return;
 394         case 0x10c8: // DMA4 chcr (SPU DMA)
 395         case 0x10cc: psxHwWriteChcr4(value); return;
 396         case 0x10e8: // DMA6 chcr (OT clear)
 397         case 0x10ec: psxHwWriteChcr6(value); return;
 398         case 0x10f4: psxHwWriteDmaIcr32(value); return;
 399
 400         case 0x1810: GPU_writeData(value); return;
 401         case 0x1814: psxHwWriteGpuSR(value); return;
 402         case 0x1820: mdecWrite0(value); break;
 403         case 0x1824: mdecWrite1(value); break;
 404
 405         case 0x1100: psxRcntWcount(0, value & 0xffff); return;
 406         case 0x1104: psxRcntWmode(0, value); return;
 407         case 0x1108: psxRcntWtarget(0, value & 0xffff); return;
 408         case 0x1110: psxRcntWcount(1, value & 0xffff); return;
 409         case 0x1114: psxRcntWmode(1, value); return;
 410         case 0x1118: psxRcntWtarget(1, value & 0xffff); return;
 411         case 0x1120: psxRcntWcount(2, value & 0xffff); return;
 412         case 0x1124: psxRcntWmode(2, value); return;
 413         case 0x1128: psxRcntWtarget(2, value & 0xffff); return;
 414
 415         case 0x1044:
 416         case 0x1048:
 417         case 0x104c:
 418         case 0x1050:
 419         case 0x1054:
 420         case 0x1058:
 421         case 0x105c:
 422         case 0x1800:
 423                 log_unhandled("unhandled w32 %08x %08x @%08x\n", add, value, psxRegs.pc);
 424                 break;
 425
 426         default:
 427                 if (0x1f801c00 <= add && add < 0x1f802000) {
 428                         SPU_writeRegister(add, value&0xffff, psxRegs.cycle);
 429                         SPU_writeRegister(add + 2, value>>16, psxRegs.cycle);
 430                         return;
 431                 }
 432         }
 433         psxHu32ref(add) = SWAPu32(value);
 434 }
 435
 436 int psxHwFreeze(void *f, int Mode) {
 437         return 0;
 438 }