libpcsxcore/r3000a.h

   1 /***************************************************************************
   2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
  18  ***************************************************************************/
  19
  20 #ifndef __R3000A_H__
  21 #define __R3000A_H__
  22
  23 #ifdef __cplusplus
  24 extern "C" {
  25 #endif
  26
  27 #include "psxcommon.h"
  28 #include "psxmem.h"
  29 #include "psxcounters.h"
  30 #include "psxbios.h"
  31
  32 #ifdef ICACHE_EMULATION
  33 enum {
  34         R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
  35         R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
  36         R3000ACPU_NOTIFY_DMA3_EXE_LOAD = 2
  37 };
  38 extern uint32_t *Read_ICache(uint32_t pc);
  39 #endif
  40
  41 typedef struct {
  42         int  (*Init)();
  43         void (*Reset)();
  44         void (*Execute)();              /* executes up to a break */
  45         void (*ExecuteBlock)(); /* executes up to a jump */
  46         void (*Clear)(u32 Addr, u32 Size);
  47 #ifdef ICACHE_EMULATION
  48         void (*Notify)(int note, void *data);
  49 #endif
  50         void (*ApplyConfig)();
  51         void (*Shutdown)();
  52 } R3000Acpu;
  53
  54 extern R3000Acpu *psxCpu;
  55 extern R3000Acpu psxInt;
  56 extern R3000Acpu psxRec;
  57
  58 typedef union {
  59 #if defined(__BIGENDIAN__)
  60         struct { u8 h3, h2, h, l; } b;
  61         struct { s8 h3, h2, h, l; } sb;
  62         struct { u16 h, l; } w;
  63         struct { s16 h, l; } sw;
  64 #else
  65         struct { u8 l, h, h2, h3; } b;
  66         struct { u16 l, h; } w;
  67         struct { s8 l, h, h2, h3; } sb;
  68         struct { s16 l, h; } sw;
  69 #endif
  70 } PAIR;
  71
  72 typedef union {
  73         struct {
  74                 u32   r0, at, v0, v1, a0, a1, a2, a3,
  75                                                 t0, t1, t2, t3, t4, t5, t6, t7,
  76                                                 s0, s1, s2, s3, s4, s5, s6, s7,
  77                                                 t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
  78         } n;
  79         u32 r[34]; /* Lo, Hi in r[32] and r[33] */
  80         PAIR p[34];
  81 } psxGPRRegs;
  82
  83 typedef union {
  84         struct {
  85                 u32     Index,     Random,    EntryLo0,  EntryLo1,
  86                                                 Context,   PageMask,  Wired,     Reserved0,
  87                                                 BadVAddr,  Count,     EntryHi,   Compare,
  88                                                 Status,    Cause,     EPC,       PRid,
  89                                                 Config,    LLAddr,    WatchLO,   WatchHI,
  90                                                 XContext,  Reserved1, Reserved2, Reserved3,
  91                                                 Reserved4, Reserved5, ECC,       CacheErr,
  92                                                 TagLo,     TagHi,     ErrorEPC,  Reserved6;
  93         } n;
  94         u32 r[32];
  95         PAIR p[32];
  96 } psxCP0Regs;
  97
  98 typedef struct {
  99         short x, y;
 100 } SVector2D;
 101
 102 typedef struct {
 103         short z, pad;
 104 } SVector2Dz;
 105
 106 typedef struct {
 107         short x, y, z, pad;
 108 } SVector3D;
 109
 110 typedef struct {
 111         short x, y, z, pad;
 112 } LVector3D;
 113
 114 typedef struct {
 115         unsigned char r, g, b, c;
 116 } CBGR;
 117
 118 typedef struct {
 119         short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
 120 } SMatrix3D;
 121
 122 typedef union {
 123         struct {
 124                 SVector3D     v0, v1, v2;
 125                 CBGR          rgb;
 126                 s32          otz;
 127                 s32          ir0, ir1, ir2, ir3;
 128                 SVector2D     sxy0, sxy1, sxy2, sxyp;
 129                 SVector2Dz    sz0, sz1, sz2, sz3;
 130                 CBGR          rgb0, rgb1, rgb2;
 131                 s32          reserved;
 132                 s32          mac0, mac1, mac2, mac3;
 133                 u32 irgb, orgb;
 134                 s32          lzcs, lzcr;
 135         } n;
 136         u32 r[32];
 137         PAIR p[32];
 138 } psxCP2Data;
 139
 140 typedef union {
 141         struct {
 142                 SMatrix3D rMatrix;
 143                 s32      trX, trY, trZ;
 144                 SMatrix3D lMatrix;
 145                 s32      rbk, gbk, bbk;
 146                 SMatrix3D cMatrix;
 147                 s32      rfc, gfc, bfc;
 148                 s32      ofx, ofy;
 149                 s32      h;
 150                 s32      dqa, dqb;
 151                 s32      zsf3, zsf4;
 152                 s32      flag;
 153         } n;
 154         u32 r[32];
 155         PAIR p[32];
 156 } psxCP2Ctrl;
 157
 158 enum {
 159         PSXINT_SIO = 0,
 160         PSXINT_CDR,
 161         PSXINT_CDREAD,
 162         PSXINT_GPUDMA,
 163         PSXINT_MDECOUTDMA,
 164         PSXINT_SPUDMA,
 165         PSXINT_GPUBUSY,
 166         PSXINT_MDECINDMA,
 167         PSXINT_GPUOTCDMA,
 168         PSXINT_CDRDMA,
 169         PSXINT_NEWDRC_CHECK,
 170         PSXINT_RCNT,
 171         PSXINT_CDRLID,
 172         PSXINT_CDRPLAY,
 173         PSXINT_SPU_UPDATE,
 174         PSXINT_COUNT
 175 };
 176
 177 typedef struct psxCP2Regs {
 178         psxCP2Data CP2D;        /* Cop2 data registers */
 179         psxCP2Ctrl CP2C;        /* Cop2 control registers */
 180 } psxCP2Regs;
 181
 182 typedef struct {
 183         psxGPRRegs GPR;         /* General Purpose Registers */
 184         psxCP0Regs CP0;         /* Coprocessor0 Registers */
 185         union {
 186                 struct {
 187                         psxCP2Data CP2D;        /* Cop2 data registers */
 188                         psxCP2Ctrl CP2C;        /* Cop2 control registers */
 189                 };
 190                 psxCP2Regs CP2;
 191         };
 192     u32 pc;                             /* Program counter */
 193     u32 code;                   /* The instruction */
 194         u32 cycle;
 195         u32 interrupt;
 196         struct { u32 sCycle, cycle; } intCycle[32];
 197         u32 gteBusyCycle;
 198         u32 muldivBusyCycle;
 199         // warning: changing anything in psxRegisters requires update of all
 200         // asm in libpcsxcore/new_dynarec/, but this member can be replaced
 201         u32 reserved[2];
 202 } psxRegisters;
 203
 204 extern psxRegisters psxRegs;
 205
 206 /* new_dynarec stuff */
 207 extern u32 event_cycles[PSXINT_COUNT];
 208 extern u32 next_interupt;
 209
 210 void new_dyna_before_save(void);
 211 void new_dyna_after_save(void);
 212 void new_dyna_freeze(void *f, int mode);
 213
 214 #define new_dyna_set_event(e, c) { \
 215         s32 c_ = c; \
 216         u32 abs_ = psxRegs.cycle + c_; \
 217         s32 odi_ = next_interupt - psxRegs.cycle; \
 218         event_cycles[e] = abs_; \
 219         if (c_ < odi_) { \
 220                 /*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
 221                 next_interupt = abs_; \
 222         } \
 223 }
 224
 225 #if defined(__BIGENDIAN__)
 226
 227 #define _i32(x) *(s32 *)&x
 228 #define _u32(x) x
 229
 230 #define _i16(x) (((short *)&x)[1])
 231 #define _u16(x) (((unsigned short *)&x)[1])
 232
 233 #define _i8(x) (((char *)&x)[3])
 234 #define _u8(x) (((unsigned char *)&x)[3])
 235
 236 #else
 237
 238 #define _i32(x) *(s32 *)&x
 239 #define _u32(x) x
 240
 241 #define _i16(x) *(short *)&x
 242 #define _u16(x) *(unsigned short *)&x
 243
 244 #define _i8(x) *(char *)&x
 245 #define _u8(x) *(unsigned char *)&x
 246
 247 #endif
 248
 249 /**** R3000A Instruction Macros ****/
 250 #define _PC_       psxRegs.pc       // The next PC to be executed
 251
 252 #define _fOp_(code)             ((code >> 26)       )  // The opcode part of the instruction register
 253 #define _fFunct_(code)  ((code      ) & 0x3F)  // The funct part of the instruction register
 254 #define _fRd_(code)             ((code >> 11) & 0x1F)  // The rd part of the instruction register
 255 #define _fRt_(code)             ((code >> 16) & 0x1F)  // The rt part of the instruction register
 256 #define _fRs_(code)             ((code >> 21) & 0x1F)  // The rs part of the instruction register
 257 #define _fSa_(code)             ((code >>  6) & 0x1F)  // The sa part of the instruction register
 258 #define _fIm_(code)             ((u16)code)            // The immediate part of the instruction register
 259 #define _fTarget_(code) (code & 0x03ffffff)    // The target part of the instruction register
 260
 261 #define _fImm_(code)    ((s16)code)            // sign-extended immediate
 262 #define _fImmU_(code)   (code&0xffff)          // zero-extended immediate
 263
 264 #define _Op_     _fOp_(psxRegs.code)
 265 #define _Funct_  _fFunct_(psxRegs.code)
 266 #define _Rd_     _fRd_(psxRegs.code)
 267 #define _Rt_     _fRt_(psxRegs.code)
 268 #define _Rs_     _fRs_(psxRegs.code)
 269 #define _Sa_     _fSa_(psxRegs.code)
 270 #define _Im_     _fIm_(psxRegs.code)
 271 #define _Target_ _fTarget_(psxRegs.code)
 272
 273 #define _Imm_    _fImm_(psxRegs.code)
 274 #define _ImmU_   _fImmU_(psxRegs.code)
 275
 276 #define _rRs_   psxRegs.GPR.r[_Rs_]   // Rs register
 277 #define _rRt_   psxRegs.GPR.r[_Rt_]   // Rt register
 278 #define _rRd_   psxRegs.GPR.r[_Rd_]   // Rd register
 279 #define _rSa_   psxRegs.GPR.r[_Sa_]   // Sa register
 280 #define _rFs_   psxRegs.CP0.r[_Rd_]   // Fs register
 281
 282 #define _c2dRs_ psxRegs.CP2D.r[_Rs_]  // Rs cop2 data register
 283 #define _c2dRt_ psxRegs.CP2D.r[_Rt_]  // Rt cop2 data register
 284 #define _c2dRd_ psxRegs.CP2D.r[_Rd_]  // Rd cop2 data register
 285 #define _c2dSa_ psxRegs.CP2D.r[_Sa_]  // Sa cop2 data register
 286
 287 #define _rHi_   psxRegs.GPR.n.hi   // The HI register
 288 #define _rLo_   psxRegs.GPR.n.lo   // The LO register
 289
 290 #define _JumpTarget_    ((_Target_ * 4) + (_PC_ & 0xf0000000))   // Calculates the target during a jump instruction
 291 #define _BranchTarget_  ((s16)_Im_ * 4 + _PC_)                 // Calculates the target during a branch instruction
 292
 293 #define _SetLink(x)     psxRegs.GPR.r[x] = _PC_ + 4;       // Sets the return address in the link register
 294
 295 int  psxInit();
 296 void psxReset();
 297 void psxShutdown();
 298 void psxException(u32 code, u32 bd);
 299 void psxBranchTest();
 300 void psxExecuteBios();
 301 int  psxTestLoadDelay(int reg, u32 tmp);
 302 void psxDelayTest(int reg, u32 bpc);
 303 void psxTestSWInts();
 304 void psxJumpTest();
 305
 306 #ifdef __cplusplus
 307 }
 308 #endif
 309 #endif