extern int pending_exception;
extern int branch_target;
extern uint64_t readmem_dword;
+#ifdef MUPEN64
extern precomp_instr fake_pc;
+#endif
extern void *dynarec_local;
extern u_int memory_map[1048576];
extern u_int mini_ht[32][2];
literalcount++;
}
-void kill_pointer(void *stub)
+void *kill_pointer(void *stub)
{
int *ptr=(int *)(stub+4);
assert((*ptr&0x0ff00000)==0x05900000);
int **l_ptr=(void *)ptr+offset+8;
int *i_ptr=*l_ptr;
set_jump_target((int)i_ptr,(int)stub);
+ return i_ptr;
}
int get_pointer(void *stub)
#endif
if((*ptr&0xFF000000)!=0xeb000000) ptr++;
assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
- u_int verifier=(int)ptr+((*ptr<<8)>>6)+8; // get target of bl
+ u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
unsigned int page=source>>12;
unsigned int map_value=memory_map[page];
#endif
if((*ptr&0xFF000000)!=0xeb000000) ptr++;
assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
- u_int verifier=(int)ptr+((*ptr<<8)>>6)+8; // get target of bl
+ u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
if(memory_map[source>>12]>=0x80000000) source = 0;
else source = source+(memory_map[source>>12]<<2);
u_int genjmp(u_int addr)
{
int offset=addr-(int)out-8;
- if(offset<-33554432||offset>=33554432) return 0;
+ if(offset<-33554432||offset>=33554432) {
+ if (addr>2) {
+ printf("genjmp: out of range: %08x\n", offset);
+ exit(1);
+ }
+ return 0;
+ }
return ((u_int)offset>>2)&0xffffff;
}
void emit_loadreg(int r, int hr)
{
+#ifdef FORCE32
+ if(r&64) {
+ printf("64bit load in 32bit mode!\n");
+ exit(1);
+ }
+#endif
if((r&63)==0)
emit_zeroreg(hr);
else {
- int addr=((int)reg)+((r&63)<<3)+((r&64)>>4);
+ int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
if(r==CCREG) addr=(int)&cycle_count;
}
void emit_storereg(int r, int hr)
{
- int addr=((int)reg)+((r&63)<<3)+((r&64)>>4);
+#ifdef FORCE32
+ if(r&64) {
+ printf("64bit store in 32bit mode!\n");
+ exit(1);
+ }
+#endif
+ int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
if(r==CCREG) addr=(int)&cycle_count;
output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
}
+void emit_testeqimm(int rs,int imm)
+{
+ u_int armval;
+ assem_debug("tsteq %s,$%d\n",regname[rs],imm);
+ assert(genimm(imm,&armval));
+ output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
+}
+
void emit_not(int rs,int rt)
{
assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
}
+void emit_mvnmi(int rs,int rt)
+{
+ assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
+ output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
+}
+
void emit_and(u_int rs1,u_int rs2,u_int rt)
{
assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
void emit_xorimm(int rs,int imm,int rt)
{
- assert(imm>0&&imm<65536);
u_int armval;
if(genimm(imm,&armval)) {
assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
}else{
- assert(imm>0);
+ assert(imm>0&&imm<65536);
assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
}
+void emit_signextend16(int rs,int rt)
+{
+ #ifdef ARMv5_ONLY
+ emit_shlimm(rs,16,rt);
+ emit_sarimm(rt,16,rt);
+ #else
+ assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
+ output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
+ #endif
+}
+
void emit_shl(u_int rs,u_int shift,u_int rt)
{
assert(rs<16);
output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
}
+void emit_orrne_imm(int rs,int imm,int rt)
+{
+ u_int armval;
+ assert(genimm(imm,&armval));
+ assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
+ output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
+}
+
+void emit_andne_imm(int rs,int imm,int rt)
+{
+ u_int armval;
+ assert(genimm(imm,&armval));
+ assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
+ output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
+}
+
void emit_jno_unlikely(int a)
{
//emit_jno(a);
emit_movimm(value,HOST_TEMPREG);
}
emit_storereg(i_regmap[hr],HOST_TEMPREG);
+#ifndef FORCE32
if((i_is32>>i_regmap[hr])&1) {
if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
}
+#endif
}
}
}
assert((ptr[3]&0x0e)==0xa);
emit_loadlp(target,0);
emit_loadlp(addr,1);
- assert(addr>=0x7000000&&addr<0x7FFFFFF);
+ assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
//assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
//DEBUG >
#ifdef DEBUG_CYCLE_COUNT
int addr=get_reg(i_regmap,AGEN1+(i&1));
int rth,rt;
int ds;
- if(itype[i]==C1LS||itype[i]==LOADLR) {
+ if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
rth=get_reg(i_regmap,FTEMP|64);
rt=get_reg(i_regmap,FTEMP);
}else{
rth=get_reg(i_regmap,rt1[i]|64);
rt=get_reg(i_regmap,rt1[i]);
}
+#ifdef PCSX
+ if(rt<0)
+ // assume forced dummy read
+ rt=get_reg(i_regmap,-1);
+#endif
assert(rs>=0);
assert(rt>=0);
if(addr<0) addr=rt;
ftable=(int)readmemh;
if(type==LOADW_STUB)
ftable=(int)readmem;
+#ifndef FORCE32
if(type==LOADD_STUB)
ftable=(int)readmemd;
+#endif
+ assert(ftable!=0);
emit_writeword(rs,(int)&address);
//emit_pusha();
save_regs(reglist);
ftable=(int)readmemh;
if(type==LOADW_STUB)
ftable=(int)readmem;
+#ifndef FORCE32
if(type==LOADD_STUB)
ftable=(int)readmemd;
+#endif
+ assert(ftable!=0);
emit_writeword(rs,(int)&address);
//emit_pusha();
save_regs(reglist);
int addr=get_reg(i_regmap,AGEN1+(i&1));
int rth,rt,r;
int ds;
- if(itype[i]==C1LS) {
+ if(itype[i]==C1LS||itype[i]==C2LS) {
rth=get_reg(i_regmap,FTEMP|64);
rt=get_reg(i_regmap,r=FTEMP);
}else{
ftable=(int)writememh;
if(type==STOREW_STUB)
ftable=(int)writemem;
+#ifndef FORCE32
if(type==STORED_STUB)
ftable=(int)writememd;
+#endif
+ assert(ftable!=0);
emit_writeword(rs,(int)&address);
//emit_shrimm(rs,16,rs);
//emit_movmem_indexedx4(ftable,rs,rs);
if(type==STOREW_STUB)
emit_writeword(rt,(int)&word);
if(type==STORED_STUB) {
+#ifndef FORCE32
emit_writeword(rt,(int)&dword);
emit_writeword(r?rth:rt,(int)&dword+4);
+#else
+ printf("STORED_STUB\n");
+#endif
}
//emit_pusha();
save_regs(reglist);
ftable=(int)writememh;
if(type==STOREW_STUB)
ftable=(int)writemem;
+#ifndef FORCE32
if(type==STORED_STUB)
ftable=(int)writememd;
+#endif
+ assert(ftable!=0);
emit_writeword(rs,(int)&address);
//emit_shrimm(rs,16,rs);
//emit_movmem_indexedx4(ftable,rs,rs);
if(type==STOREW_STUB)
emit_writeword(rt,(int)&word);
if(type==STORED_STUB) {
+#ifndef FORCE32
emit_writeword(rt,(int)&dword);
emit_writeword(target?rth:rt,(int)&dword+4);
+#else
+ printf("STORED_STUB\n");
+#endif
}
//emit_pusha();
save_regs(reglist);
assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
set_jump_target(stubs[n][1],(int)out);
int i=stubs[n][3];
- int rs=stubs[n][4];
+// int rs=stubs[n][4];
struct regstat *i_regs=(struct regstat *)stubs[n][5];
int ds=stubs[n][6];
if(!ds) {
else
inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
emit_andimm(temp,24,temp);
- if (opcode[i]==0x26) emit_xorimm(temp,24,temp); // LWR
+#ifdef BIG_ENDIAN_MIPS
+ if (opcode[i]==0x26) // LWR
+#else
+ if (opcode[i]==0x22) // LWL
+#endif
+ emit_xorimm(temp,24,temp);
emit_movimm(-1,HOST_TEMPREG);
if (opcode[i]==0x26) {
emit_shr(temp2,temp,temp2);
//emit_storereg(rt1[i],tl); // DEBUG
}
if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
+ // FIXME: little endian
int temp2h=get_reg(i_regs->regmap,FTEMP|64);
if(!c||memtarget) {
//if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
char copr=(source[i]>>11)&0x1f;
//assert(t>=0); // Why does this happen? OOT is weird
if(t>=0) {
+#ifdef MUPEN64
emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
emit_movimm((source[i]>>11)&0x1f,1);
emit_writeword(0,(int)&PC);
}
emit_call((int)MFC0);
emit_readword((int)&readmem_dword,t);
+#else
+ emit_readword((int)®_cop0+copr*4,t);
+#endif
}
}
else if(opcode2[i]==4) // MTC0
assert(s>=0);
emit_writeword(s,(int)&readmem_dword);
wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
+#ifdef MUPEN64 /// FIXME
emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
emit_movimm((source[i]>>11)&0x1f,1);
emit_writeword(0,(int)&PC);
emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
- if(copr==9||copr==11||copr==12) {
+#endif
+#ifdef PCSX
+ emit_movimm(source[i],0);
+ emit_writeword(0,(int)&psxRegs.code);
+#endif
+ if(copr==9||copr==11||copr==12||copr==13) {
emit_readword((int)&last_count,ECX);
emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
emit_add(HOST_CCREG,ECX,HOST_CCREG);
// so needs a special case to handle a pending interrupt.
// The interrupt must be taken immediately, because a subsequent
// instruction might disable interrupts again.
- if(copr==12&&!is_delayslot) {
+ if(copr==12||copr==13) {
emit_movimm(start+i*4+4,0);
emit_movimm(0,1);
emit_writeword(0,(int)&pcaddr);
//else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
//else
emit_call((int)MTC0);
- if(copr==9||copr==11||copr==12) {
+ if(copr==9||copr==11||copr==12||copr==13) {
emit_readword((int)&Count,HOST_CCREG);
emit_readword((int)&next_interupt,ECX);
emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
emit_writeword(ECX,(int)&last_count);
emit_storereg(CCREG,HOST_CCREG);
}
- if(copr==12) {
+ if(copr==12||copr==13) {
assert(!is_delayslot);
emit_readword((int)&pending_exception,14);
}
emit_loadreg(rs1[i],s);
if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
- if(copr==12) {
+ if(copr==12||copr==13) {
emit_test(14,14);
emit_jne((int)&do_interrupt);
}
else
{
assert(opcode2[i]==0x10);
+#ifndef DISABLE_TLB
if((source[i]&0x3f)==0x01) // TLBR
emit_call((int)TLBR);
if((source[i]&0x3f)==0x02) // TLBWI
}
if((source[i]&0x3f)==0x08) // TLBP
emit_call((int)TLBP);
+#endif
if((source[i]&0x3f)==0x18) // ERET
{
int count=ccadj[i];
}
}
+static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
+{
+ switch (copr) {
+ case 1:
+ case 3:
+ case 5:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ emit_readword((int)®_cop2d[copr],tl);
+ emit_signextend16(tl,tl);
+ emit_writeword(tl,(int)®_cop2d[copr]); // hmh
+ break;
+ case 7:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ emit_readword((int)®_cop2d[copr],tl);
+ emit_andimm(tl,0xffff,tl);
+ emit_writeword(tl,(int)®_cop2d[copr]);
+ break;
+ case 15:
+ emit_readword((int)®_cop2d[14],tl); // SXY2
+ emit_writeword(tl,(int)®_cop2d[copr]);
+ break;
+ case 28:
+ case 30:
+ emit_movimm(0,tl);
+ break;
+ case 29:
+ emit_readword((int)®_cop2d[9],temp);
+ emit_testimm(temp,0x8000); // do we need this?
+ emit_andimm(temp,0xf80,temp);
+ emit_andne_imm(temp,0,temp);
+ emit_shr(temp,7,tl);
+ emit_readword((int)®_cop2d[10],temp);
+ emit_testimm(temp,0x8000);
+ emit_andimm(temp,0xf80,temp);
+ emit_andne_imm(temp,0,temp);
+ emit_orrshr(temp,2,tl);
+ emit_readword((int)®_cop2d[11],temp);
+ emit_testimm(temp,0x8000);
+ emit_andimm(temp,0xf80,temp);
+ emit_andne_imm(temp,0,temp);
+ emit_orrshl(temp,3,tl);
+ emit_writeword(tl,(int)®_cop2d[copr]);
+ break;
+ default:
+ emit_readword((int)®_cop2d[copr],tl);
+ break;
+ }
+}
+
+static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
+{
+ switch (copr) {
+ case 15:
+ emit_readword((int)®_cop2d[13],temp); // SXY1
+ emit_writeword(sl,(int)®_cop2d[copr]);
+ emit_writeword(temp,(int)®_cop2d[12]); // SXY0
+ emit_readword((int)®_cop2d[14],temp); // SXY2
+ emit_writeword(sl,(int)®_cop2d[14]);
+ emit_writeword(temp,(int)®_cop2d[13]); // SXY1
+ break;
+ case 28:
+ emit_andimm(sl,0x001f,temp);
+ emit_shl(temp,7,temp);
+ emit_writeword(temp,(int)®_cop2d[9]);
+ emit_andimm(sl,0x03e0,temp);
+ emit_shl(temp,2,temp);
+ emit_writeword(temp,(int)®_cop2d[10]);
+ emit_andimm(sl,0x7c00,temp);
+ emit_shr(temp,3,temp);
+ emit_writeword(temp,(int)®_cop2d[11]);
+ emit_writeword(sl,(int)®_cop2d[28]);
+ break;
+ case 30:
+ emit_movs(sl,temp);
+ emit_mvnmi(temp,temp);
+ emit_clz(temp,temp);
+ emit_writeword(sl,(int)®_cop2d[30]);
+ emit_writeword(temp,(int)®_cop2d[31]);
+ break;
+ case 7:
+ case 29:
+ case 31:
+ break;
+ default:
+ emit_writeword(sl,(int)®_cop2d[copr]);
+ break;
+ }
+}
+
+void cop2_assemble(int i,struct regstat *i_regs)
+{
+ u_int copr=(source[i]>>11)&0x1f;
+ signed char temp=get_reg(i_regs->regmap,-1);
+ if (opcode2[i]==0) { // MFC2
+ signed char tl=get_reg(i_regs->regmap,rt1[i]);
+ if(tl>=0)
+ cop2_get_dreg(copr,tl,temp);
+ }
+ else if (opcode2[i]==4) { // MTC2
+ signed char sl=get_reg(i_regs->regmap,rs1[i]);
+ cop2_put_dreg(copr,sl,temp);
+ }
+ else if (opcode2[i]==2) // CFC2
+ {
+ signed char tl=get_reg(i_regs->regmap,rt1[i]);
+ if(tl>=0)
+ emit_readword((int)®_cop2c[copr],tl);
+ }
+ else if (opcode2[i]==6) // CTC2
+ {
+ signed char sl=get_reg(i_regs->regmap,rs1[i]);
+ switch(copr) {
+ case 4:
+ case 12:
+ case 20:
+ case 26:
+ case 27:
+ case 29:
+ case 30:
+ emit_signextend16(sl,temp);
+ break;
+ case 31:
+ //value = value & 0x7ffff000;
+ //if (value & 0x7f87e000) value |= 0x80000000;
+ emit_shrimm(sl,12,temp);
+ emit_shlimm(temp,12,temp);
+ emit_testimm(temp,0x7f000000);
+ emit_testeqimm(temp,0x00870000);
+ emit_testeqimm(temp,0x0000e000);
+ emit_orrne_imm(temp,0x80000000,temp);
+ break;
+ default:
+ temp=sl;
+ break;
+ }
+ emit_writeword(temp,(int)®_cop2c[copr]);
+ assert(sl>=0);
+ }
+}
+
+void c2op_assemble(int i,struct regstat *i_regs)
+{
+ signed char temp=get_reg(i_regs->regmap,-1);
+ u_int c2op=source[i]&0x3f;
+ u_int hr,reglist=0;
+ for(hr=0;hr<HOST_REGS;hr++) {
+ if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
+ }
+ if(i==0||itype[i-1]!=C2OP)
+ save_regs(reglist);
+
+ if (gte_handlers[c2op]!=NULL) {
+ int cc=get_reg(i_regs->regmap,CCREG);
+ emit_movimm(source[i],temp); // opcode
+ if (cc>=0&>e_cycletab[c2op])
+ emit_addimm(cc,gte_cycletab[c2op]/2,cc); // XXX: cound just adjust ccadj?
+ emit_writeword(temp,(int)&psxRegs.code);
+ emit_call((int)gte_handlers[c2op]);
+ }
+
+ if(i>=slen-1||itype[i+1]!=C2OP)
+ restore_regs(reglist);
+}
+
+void cop1_unusable(int i,struct regstat *i_regs)
+{
+ // XXX: should just just do the exception instead
+ if(!cop1_usable) {
+ int jaddr=(int)out;
+ emit_jmp(0);
+ add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
+ cop1_usable=1;
+ }
+}
+
void cop1_assemble(int i,struct regstat *i_regs)
{
+#ifndef DISABLE_COP1
// Check cop1 unusable
if(!cop1_usable) {
signed char rs=get_reg(i_regs->regmap,CSREG);
//emit_fldcw_indexed((int)&rounding_modes,temp);
}
}
+#else
+ cop1_unusable(i, i_regs);
+#endif
}
void fconv_assemble_arm(int i,struct regstat *i_regs)
{
+#ifndef DISABLE_COP1
signed char temp=get_reg(i_regs->regmap,-1);
assert(temp>=0);
// Check cop1 unusable
}
restore_regs(reglist);
+#else
+ cop1_unusable(i, i_regs);
+#endif
}
#define fconv_assemble fconv_assemble_arm
void fcomp_assemble(int i,struct regstat *i_regs)
{
+#ifndef DISABLE_COP1
signed char fs=get_reg(i_regs->regmap,FSREG);
signed char temp=get_reg(i_regs->regmap,-1);
assert(temp>=0);
}
restore_regs(reglist);
emit_loadreg(FSREG,fs);
+#else
+ cop1_unusable(i, i_regs);
+#endif
}
void float_assemble(int i,struct regstat *i_regs)
{
+#ifndef DISABLE_COP1
signed char temp=get_reg(i_regs->regmap,-1);
assert(temp>=0);
// Check cop1 unusable
}
restore_regs(reglist);
}
+#else
+ cop1_unusable(i, i_regs);
+#endif
}
void multdiv_assemble_arm(int i,struct regstat *i_regs)
// as a 64-bit value later.
void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
{
+#ifndef FORCE32
if(is32_pre==is32) return;
int hr,reg;
for(hr=0;hr<HOST_REGS;hr++) {
//}
}
}
+#endif
}
void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
// CPU-architecture-specific initialization
void arch_init() {
+#ifndef DISABLE_COP1
rounding_modes[0]=0x0<<22; // round
rounding_modes[1]=0x3<<22; // trunc
rounding_modes[2]=0x1<<22; // ceil
rounding_modes[3]=0x2<<22; // floor
+#endif
}
+
+// vim:shiftwidth=2:expandtab
notaz.gp2x.de / pcsx_rearmed.git / blobdiff