drc: try even more to not compile code as 64bit

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.c

diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index bc9e5cd..41d2e71 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -1002,7 +1002,8 @@ void emit_loadreg(int r, int hr)
 #ifdef FORCE32
   if(r&64) {
     printf("64bit load in 32bit mode!\n");
-    exit(1);
+    assert(0);
+    return;
   }
 #endif
   if((r&63)==0)
@@ -1026,7 +1027,8 @@ void emit_storereg(int r, int hr)
 #ifdef FORCE32
   if(r&64) {
     printf("64bit store in 32bit mode!\n");
-    exit(1);
+    assert(0);
+    return;
   }
 #endif
   int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
@@ -3328,7 +3330,7 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs)
   int s,th,tl,temp,temp2,addr,map=-1;
   int offset;
   int jaddr=0;
-  int memtarget,c=0;
+  int memtarget=0,c=0;
   u_int hr,reglist=0;
   th=get_reg(i_regs->regmap,rt1[i]|64);
   tl=get_reg(i_regs->regmap,rt1[i]);
@@ -3346,8 +3348,10 @@ void loadlr_assemble_arm(int i,struct regstat *i_regs)
   else addr=s;
   if(s>=0) {
     c=(i_regs->wasconst>>s)&1;
-    memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
-    if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+    if(c) {
+      memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+      if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+    }
   }
   if(!using_tlb) {
     if(!c) {