drc: handle MTC0 in delay slot

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.c

diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index b6b856a..56b0c1a 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -824,6 +824,11 @@ u_int genimm(u_int imm,u_int *encoded)
   }
   return 0;
 }
+void genimm_checked(u_int imm,u_int *encoded)
+{
+  u_int ret=genimm(imm,encoded);
+  assert(ret);
+}
 u_int genjmp(u_int addr)
 {
   int offset=addr-(int)out-8;
@@ -962,7 +967,7 @@ void emit_testimm(int rs,int imm)
 {
   u_int armval;
   assem_debug("tst %s,$%d\n",regname[rs],imm);
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
 }
 
@@ -970,7 +975,7 @@ void emit_testeqimm(int rs,int imm)
 {
   u_int armval;
   assem_debug("tsteq %s,$%d\n",regname[rs],imm);
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
 }
 
@@ -1133,14 +1138,14 @@ void emit_addnop(u_int r)
 void emit_adcimm(u_int rs,int imm,u_int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
 }
 /*void emit_sbcimm(int imm,u_int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
   output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
 }*/
@@ -1164,7 +1169,7 @@ void emit_rscimm(int rs,int imm,u_int rt)
 {
   assert(0);
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -1434,28 +1439,28 @@ void emit_cmovne_imm(int imm,int rt)
 {
   assem_debug("movne %s,#%d\n",regname[rt],imm);
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
 }
 void emit_cmovl_imm(int imm,int rt)
 {
   assem_debug("movlt %s,#%d\n",regname[rt],imm);
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
 }
 void emit_cmovb_imm(int imm,int rt)
 {
   assem_debug("movcc %s,#%d\n",regname[rt],imm);
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
 }
 void emit_cmovs_imm(int imm,int rt)
 {
   assem_debug("movmi %s,#%d\n",regname[rt],imm);
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
 }
 void emit_cmove_reg(int rs,int rt)
@@ -2095,7 +2100,7 @@ void emit_teq(int rs, int rt)
 void emit_rsbimm(int rs, int imm, int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -2361,7 +2366,7 @@ void emit_fmstat()
 void emit_bicne_imm(int rs,int imm,int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -2369,7 +2374,7 @@ void emit_bicne_imm(int rs,int imm,int rt)
 void emit_biccs_imm(int rs,int imm,int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -2377,7 +2382,7 @@ void emit_biccs_imm(int rs,int imm,int rt)
 void emit_bicvc_imm(int rs,int imm,int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -2385,7 +2390,7 @@ void emit_bicvc_imm(int rs,int imm,int rt)
 void emit_bichi_imm(int rs,int imm,int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -2393,7 +2398,7 @@ void emit_bichi_imm(int rs,int imm,int rt)
 void emit_orrvs_imm(int rs,int imm,int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -2401,7 +2406,7 @@ void emit_orrvs_imm(int rs,int imm,int rt)
 void emit_orrne_imm(int rs,int imm,int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -2409,7 +2414,7 @@ void emit_orrne_imm(int rs,int imm,int rt)
 void emit_andne_imm(int rs,int imm,int rt)
 {
   u_int armval;
-  assert(genimm(imm,&armval));
+  genimm_checked(imm,&armval);
   assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
   output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
 }
@@ -3373,7 +3378,7 @@ void cop0_assemble(int i,struct regstat *i_regs)
     signed char t=get_reg(i_regs->regmap,rt1[i]);
     char copr=(source[i]>>11)&0x1f;
     //assert(t>=0); // Why does this happen?  OOT is weird
-    if(t>=0) {
+    if(t>=0&&rt1[i]!=0) {
 #ifdef MUPEN64
       emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
       emit_movimm((source[i]>>11)&0x1f,1);
@@ -3400,15 +3405,11 @@ void cop0_assemble(int i,struct regstat *i_regs)
     assert(s>=0);
     emit_writeword(s,(int)&readmem_dword);
     wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
-#ifdef MUPEN64 /// FIXME
+#ifdef MUPEN64
     emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
     emit_movimm((source[i]>>11)&0x1f,1);
     emit_writeword(0,(int)&PC);
     emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
-#endif
-#ifdef PCSX
-    emit_movimm(source[i],0);
-    emit_writeword(0,(int)&psxRegs.code);
 #endif
     if(copr==9||copr==11||copr==12||copr==13) {
       emit_readword((int)&last_count,ECX);
@@ -3422,6 +3423,19 @@ void cop0_assemble(int i,struct regstat *i_regs)
     // The interrupt must be taken immediately, because a subsequent
     // instruction might disable interrupts again.
     if(copr==12||copr==13) {
+#ifdef PCSX
+      if (is_delayslot) {
+        // burn cycles to cause cc_interrupt, which will
+        // reschedule next_interupt. Relies on CCREG from above.
+        assem_debug("MTC0 DS %d\n", copr);
+        emit_writeword(HOST_CCREG,(int)&last_count);
+        emit_movimm(0,HOST_CCREG);
+        emit_storereg(CCREG,HOST_CCREG);
+        emit_movimm(copr,0);
+        emit_call((int)pcsx_mtc0_ds);
+        return;
+      }
+#endif
       emit_movimm(start+i*4+4,0);
       emit_movimm(0,1);
       emit_writeword(0,(int)&pcaddr);
@@ -3429,7 +3443,12 @@ void cop0_assemble(int i,struct regstat *i_regs)
     }
     //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
     //else
+#ifdef PCSX
+    emit_movimm(copr,0);
+    emit_call((int)pcsx_mtc0);
+#else
     emit_call((int)MTC0);
+#endif
     if(copr==9||copr==11||copr==12||copr==13) {
       emit_readword((int)&Count,HOST_CCREG);
       emit_readword((int)&next_interupt,ECX);
@@ -3594,7 +3613,7 @@ void cop2_assemble(int i,struct regstat *i_regs)
   signed char temp=get_reg(i_regs->regmap,-1);
   if (opcode2[i]==0) { // MFC2
     signed char tl=get_reg(i_regs->regmap,rt1[i]);
-    if(tl>=0)
+    if(tl>=0&&rt1[i]!=0)
       cop2_get_dreg(copr,tl,temp);
   }
   else if (opcode2[i]==4) { // MTC2
@@ -3604,7 +3623,7 @@ void cop2_assemble(int i,struct regstat *i_regs)
   else if (opcode2[i]==2) // CFC2
   {
     signed char tl=get_reg(i_regs->regmap,rt1[i]);
-    if(tl>=0)
+    if(tl>=0&&rt1[i]!=0)
       emit_readword((int)&reg_cop2c[copr],tl);
   }
   else if (opcode2[i]==6) // CTC2