drc: don't delay block restoration

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.c

diff --git a/libpcsxcore/new_dynarec/assem_arm.c b/libpcsxcore/new_dynarec/assem_arm.c
index c5c2c66..b9dd3cf 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.c
+++ b/libpcsxcore/new_dynarec/assem_arm.c
@@ -101,8 +101,6 @@ const u_int invalidate_addr_reg[16] = {
   0,
   0};
 
-static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
-
 /* Linker */
 
 static void set_jump_target(void *addr, void *target_)
@@ -473,6 +471,7 @@ static void emit_loadlp(u_int imm,u_int rt)
   output_w32(0xe5900000|rd_rn_rm(rt,15,0));
 }
 
+#ifdef HAVE_ARMV7
 static void emit_movw(u_int imm,u_int rt)
 {
   assert(imm<65536);
@@ -485,6 +484,7 @@ static void emit_movt(u_int imm,u_int rt)
   assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
   output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
 }
+#endif
 
 static void emit_movimm(u_int imm,u_int rt)
 {
@@ -522,38 +522,33 @@ static void emit_pcreladdr(u_int rt)
 
 static void emit_loadreg(int r, int hr)
 {
-  if(r&64) {
-    SysPrintf("64bit load in 32bit mode!\n");
-    assert(0);
-    return;
-  }
-  if((r&63)==0)
+  assert(hr != EXCLUDE_REG);
+  if (r == 0)
     emit_zeroreg(hr);
   else {
-    int addr = (int)&psxRegs.GPR.r[r];
+    void *addr;
     switch (r) {
     //case HIREG: addr = &hi; break;
     //case LOREG: addr = &lo; break;
-    case CCREG: addr = (int)&cycle_count; break;
-    case CSREG: addr = (int)&Status; break;
-    case INVCP: addr = (int)&invc_ptr; break;
-    case ROREG: addr = (int)&ram_offset; break;
-    default: assert(r < 34); break;
+    case CCREG: addr = &cycle_count; break;
+    case CSREG: addr = &Status; break;
+    case INVCP: addr = &invc_ptr; break;
+    case ROREG: addr = &ram_offset; break;
+    default:
+      assert(r < 34);
+      addr = &psxRegs.GPR.r[r];
+      break;
     }
-    u_int offset = addr-(u_int)&dynarec_local;
+    u_int offset = (u_char *)addr - (u_char *)&dynarec_local;
     assert(offset<4096);
-    assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
+    assem_debug("ldr %s,fp+%d # r%d\n",regname[hr],offset,r);
     output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
   }
 }
 
 static void emit_storereg(int r, int hr)
 {
-  if(r&64) {
-    SysPrintf("64bit store in 32bit mode!\n");
-    assert(0);
-    return;
-  }
+  assert(hr != EXCLUDE_REG);
   int addr = (int)&psxRegs.GPR.r[r];
   switch (r) {
   //case HIREG: addr = &hi; break;
@@ -563,7 +558,7 @@ static void emit_storereg(int r, int hr)
   }
   u_int offset = addr-(u_int)&dynarec_local;
   assert(offset<4096);
-  assem_debug("str %s,fp+%d\n",regname[hr],offset);
+  assem_debug("str %s,fp+%d # r%d\n",regname[hr],offset,r);
   output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
 }
 
@@ -949,6 +944,14 @@ static void emit_cmovae_imm(int imm,int rt)
   output_w32(0x23a00000|rd_rn_rm(rt,0,0)|armval);
 }
 
+static void emit_cmovs_imm(int imm,int rt)
+{
+  assem_debug("movmi %s,#%d\n",regname[rt],imm);
+  u_int armval;
+  genimm_checked(imm,&armval);
+  output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
+}
+
 static void emit_cmovne_reg(int rs,int rt)
 {
   assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
@@ -1521,14 +1524,6 @@ static void emit_orrne_imm(int rs,int imm,int rt)
   output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
 }
 
-static void emit_andne_imm(int rs,int imm,int rt)
-{
-  u_int armval;
-  genimm_checked(imm,&armval);
-  assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
-  output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
-}
-
 static unused void emit_addpl_imm(int rs,int imm,int rt)
 {
   u_int armval;
@@ -1637,7 +1632,8 @@ static void emit_extjump2(u_char *addr, u_int target, void *linker)
 
   emit_loadlp(target,0);
   emit_loadlp((u_int)addr,1);
-  assert(addr>=ndrc->translation_cache&&addr<(ndrc->translation_cache+(1<<TARGET_SIZE_2)));
+  assert(ndrc->translation_cache <= addr &&
+         addr < ndrc->translation_cache + sizeof(ndrc->translation_cache));
   //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
 //DEBUG >
 #ifdef DEBUG_CYCLE_COUNT
@@ -1804,7 +1800,7 @@ static void inline_readstub(enum stub_type type, int i, u_int addr,
 {
   int rs=get_reg(regmap,target);
   int rt=get_reg(regmap,target);
-  if(rs<0) rs=get_reg(regmap,-1);
+  if(rs<0) rs=get_reg_temp(regmap);
   assert(rs>=0);
   u_int is_dynamic;
   uintptr_t host_addr = 0;
@@ -1958,7 +1954,7 @@ static void do_writestub(int n)
 static void inline_writestub(enum stub_type type, int i, u_int addr,
   const signed char regmap[], int target, int adj, u_int reglist)
 {
-  int rs=get_reg(regmap,-1);
+  int rs=get_reg_temp(regmap);
   int rt=get_reg(regmap,target);
   assert(rs>=0);
   assert(rt>=0);
@@ -2119,10 +2115,10 @@ static void c2op_assemble(int i, const struct regstat *i_regs)
         }
 #else
         if(cv==3&&shift)
-          emit_far_call((int)gteMVMVA_part_cv3sh12_arm);
+          emit_far_call(gteMVMVA_part_cv3sh12_arm);
         else {
           emit_movimm(shift,1);
-          emit_far_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
+          emit_far_call(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm);
         }
         if(need_flags||need_ir)
           c2op_call_MACtoIR(lm,need_flags);
@@ -2200,11 +2196,11 @@ static void c2op_ctc2_31_assemble(signed char sl, signed char temp)
 static void do_mfc2_31_one(u_int copr,signed char temp)
 {
   emit_readword(&reg_cop2d[copr],temp);
-  emit_testimm(temp,0x8000); // do we need this?
-  emit_andne_imm(temp,0,temp);
-  emit_cmpimm(temp,0xf80);
-  emit_andimm(temp,0xf80,temp);
-  emit_cmovae_imm(0xf80,temp);
+  emit_lsls_imm(temp,16,temp);
+  emit_cmovs_imm(0,temp);
+  emit_cmpimm(temp,0xf80<<16);
+  emit_andimm(temp,0xf80<<16,temp);
+  emit_cmovae_imm(0xf80<<16,temp);
 }
 
 static void c2op_mfc2_29_assemble(signed char tl, signed char temp)
@@ -2214,11 +2210,11 @@ static void c2op_mfc2_29_assemble(signed char tl, signed char temp)
     temp = HOST_TEMPREG;
   }
   do_mfc2_31_one(9,temp);
-  emit_shrimm(temp,7,tl);
+  emit_shrimm(temp,7+16,tl);
   do_mfc2_31_one(10,temp);
-  emit_orrshr_imm(temp,2,tl);
+  emit_orrshr_imm(temp,2+16,tl);
   do_mfc2_31_one(11,temp);
-  emit_orrshl_imm(temp,3,tl);
+  emit_orrshr_imm(temp,-3+16,tl);
   emit_writeword(tl,&reg_cop2d[29]);
   if (temp == HOST_TEMPREG)
     host_tempreg_release();