spu: rework synchronization

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.h

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index 7ed8caf..2254638 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -17,13 +17,12 @@
 #define RAM_SIZE 0x200000
 
 #ifndef __ARM_ARCH_7A__
-#define ARMv5_ONLY
 //#undef CORTEX_A8_BRANCH_PREDICTION_HACK
 //#undef USE_MINI_HT
 #endif
 
-#ifndef __ANDROID__
-#define BASE_ADDR_FIXED 1
+#ifndef BASE_ADDR_FIXED
+#define BASE_ADDR_FIXED 0
 #endif
 
 #ifdef FORCE32
@@ -61,13 +60,10 @@ extern char *invc_ptr;
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
 // Code generator target address
-#ifdef BASE_ADDR_FIXED
+#if BASE_ADDR_FIXED
 // "round" address helpful for debug
 #define BASE_ADDR 0x1000000
 #else
 extern char translation_cache[1 << TARGET_SIZE_2];
-#define BASE_ADDR translation_cache
+#define BASE_ADDR (u_int)translation_cache
 #endif
-
-// This is defined in linkage_arm.s, but gcc -O3 likes this better
-#define rdram ((unsigned int *)0x80000000)