drc/gte: add some stall handling

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.h

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index bbaf5b9..9b3a1e1 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -6,7 +6,6 @@
 #define HOST_IMM8 1
 #define HAVE_CMOV_IMM 1
 #define HAVE_CONDITIONAL_CALL 1
-#define RAM_SIZE 0x200000
 
 /* ARM calling convention:
    r0-r3, r12: caller-save
@@ -31,18 +30,8 @@ extern char *invc_ptr;
 
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
-// Code generator target address
-#if   defined(BASE_ADDR_FIXED)
-  // "round" address helpful for debug
-  // this produces best code, but not many platforms allow it,
-  // only use if you are sure this range is always free
-  #define BASE_ADDR_ 0x1000000
-  #define translation_cache (u_char *)BASE_ADDR_
-#elif defined(BASE_ADDR_DYNAMIC)
-  // for platforms that can't just use .bss buffer, like vita
-  // otherwise better to use the next option for closer branches
-  extern u_char *translation_cache;
-#else
-  // using a static buffer in .bss
-  extern u_char translation_cache[1 << TARGET_SIZE_2];
-#endif
+struct tramp_insns
+{
+  u_int ldrpc;
+};
+