drc: some more general cleanup

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.h

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index bb6114c..bbaf5b9 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -8,17 +8,10 @@
 #define HAVE_CONDITIONAL_CALL 1
 #define RAM_SIZE 0x200000
 
-#define REG_SHIFT 2
-
 /* ARM calling convention:
    r0-r3, r12: caller-save
    r4-r11: callee-save */
 
-#define ARG1_REG 0
-#define ARG2_REG 1
-#define ARG3_REG 2
-#define ARG4_REG 3
-
 /* GCC register naming convention:
    r10 = sl (base)
    r11 = fp (frame pointer)
@@ -43,15 +36,13 @@ extern char *invc_ptr;
   // "round" address helpful for debug
   // this produces best code, but not many platforms allow it,
   // only use if you are sure this range is always free
-  #define BASE_ADDR 0x1000000
-  #define translation_cache (char *)BASE_ADDR
+  #define BASE_ADDR_ 0x1000000
+  #define translation_cache (u_char *)BASE_ADDR_
 #elif defined(BASE_ADDR_DYNAMIC)
   // for platforms that can't just use .bss buffer, like vita
   // otherwise better to use the next option for closer branches
-  extern char *translation_cache;
-  #define BASE_ADDR (u_int)translation_cache
+  extern u_char *translation_cache;
 #else
   // using a static buffer in .bss
-  extern char translation_cache[1 << TARGET_SIZE_2];
-  #define BASE_ADDR (u_int)translation_cache
+  extern u_char translation_cache[1 << TARGET_SIZE_2];
 #endif