drc: update according to interpreter

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm64.c

diff --git a/libpcsxcore/new_dynarec/assem_arm64.c b/libpcsxcore/new_dynarec/assem_arm64.c
index 6f9c91d..d35ad45 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm64.c
+++ b/libpcsxcore/new_dynarec/assem_arm64.c
@@ -302,6 +302,12 @@ static void emit_add(u_int rs1, u_int rs2, u_int rt)
   output_w32(0x0b000000 | rm_rn_rd(rs2, rs1, rt));
 }
 
+static void emit_adds(u_int rs1, u_int rs2, u_int rt)
+{
+  assem_debug("adds %s,%s,%s\n", regname[rt], regname[rs1], regname[rs2]);
+  output_w32(0x2b000000 | rm_rn_rd(rs2, rs1, rt));
+}
+
 static void emit_add64(u_int rs1, u_int rs2, u_int rt)
 {
   assem_debug("add %s,%s,%s\n", regname64[rt], regname64[rs1], regname64[rs2]);
@@ -315,19 +321,37 @@ static void emit_adds64(u_int rs1, u_int rs2, u_int rt)
 }
 #define emit_adds_ptr emit_adds64
 
+static void emit_add_lsrimm(u_int rs1, u_int rs2, u_int shift, u_int rt)
+{
+  assem_debug("add %s,%s,%s,lsr #%u\n",regname[rt],regname[rs1],regname[rs2],shift);
+  output_w32(0x0b400000 | rm_imm6_rn_rd(rs2, shift, rs1, rt));
+}
+
 static void emit_neg(u_int rs, u_int rt)
 {
   assem_debug("neg %s,%s\n",regname[rt],regname[rs]);
   output_w32(0x4b000000 | rm_rn_rd(rs, WZR, rt));
 }
 
+static void emit_negs(u_int rs, u_int rt)
+{
+  assem_debug("negs %s,%s\n",regname[rt],regname[rs]);
+  output_w32(0x6b000000 | rm_rn_rd(rs, WZR, rt));
+}
+
 static void emit_sub(u_int rs1, u_int rs2, u_int rt)
 {
   assem_debug("sub %s,%s,%s\n", regname[rt], regname[rs1], regname[rs2]);
   output_w32(0x4b000000 | rm_imm6_rn_rd(rs2, 0, rs1, rt));
 }
 
-static void emit_sub_asrimm(u_int rs1, u_int rs2, u_int shift, u_int rt)
+static void emit_subs(u_int rs1, u_int rs2, u_int rt)
+{
+  assem_debug("subs %s,%s,%s\n", regname[rt], regname[rs1], regname[rs2]);
+  output_w32(0x6b000000 | rm_imm6_rn_rd(rs2, 0, rs1, rt));
+}
+
+static unused void emit_sub_asrimm(u_int rs1, u_int rs2, u_int shift, u_int rt)
 {
   assem_debug("sub %s,%s,%s,asr #%u\n",regname[rt],regname[rs1],regname[rs2],shift);
   output_w32(0x4b800000 | rm_imm6_rn_rd(rs2, shift, rs1, rt));
@@ -422,7 +446,7 @@ static void emit_readword(void *addr, u_int rt)
 {
   uintptr_t offset = (u_char *)addr - (u_char *)&dynarec_local;
   if (!(offset & 3) && offset <= 16380) {
-    assem_debug("ldr %s,[x%d+%#lx]\n", regname[rt], FP, offset);
+    assem_debug("ldr %s,[x%d+%#lx]%s\n", regname[rt], FP, offset, fpofs_name(offset));
     output_w32(0xb9400000 | imm12_rn_rd(offset >> 2, FP, rt));
   }
   else
@@ -433,7 +457,7 @@ static void emit_readdword(void *addr, u_int rt)
 {
   uintptr_t offset = (u_char *)addr - (u_char *)&dynarec_local;
   if (!(offset & 7) && offset <= 32760) {
-    assem_debug("ldr %s,[x%d+%#lx]\n", regname64[rt], FP, offset);
+    assem_debug("ldr %s,[x%d+%#lx]%s\n", regname64[rt], FP, offset, fpofs_name(offset));
     output_w32(0xf9400000 | imm12_rn_rd(offset >> 3, FP, rt));
   }
   else
@@ -482,7 +506,7 @@ static void emit_writeword(u_int rt, void *addr)
 {
   uintptr_t offset = (u_char *)addr - (u_char *)&dynarec_local;
   if (!(offset & 3) && offset <= 16380) {
-    assem_debug("str %s,[x%d+%#lx]\n", regname[rt], FP, offset);
+    assem_debug("str %s,[x%d+%#lx]%s\n", regname[rt], FP, offset, fpofs_name(offset));
     output_w32(0xb9000000 | imm12_rn_rd(offset >> 2, FP, rt));
   }
   else
@@ -493,7 +517,7 @@ static void emit_writedword(u_int rt, void *addr)
 {
   uintptr_t offset = (u_char *)addr - (u_char *)&dynarec_local;
   if (!(offset & 7) && offset <= 32760) {
-    assem_debug("str %s,[x%d+%#lx]\n", regname64[rt], FP, offset);
+    assem_debug("str %s,[x%d+%#lx]%s\n", regname64[rt], FP, offset, fpofs_name(offset));
     output_w32(0xf9000000 | imm12_rn_rd(offset >> 3, FP, rt));
   }
   else
@@ -564,6 +588,12 @@ static void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
   output_w32(0x2a400000 | rm_imm6_rn_rd(rs, imm, rt, rt));
 }
 
+static void emit_orn_asrimm(u_int rs1, u_int rs2, u_int shift, u_int rt)
+{
+  assem_debug("orn %s,%s,%s,asr #%u\n",regname[rt],regname[rs1],regname[rs2],shift);
+  output_w32(0x2aa00000 | rm_imm6_rn_rd(rs2, shift, rs1, rt));
+}
+
 static void emit_bicsar_imm(u_int rs,u_int imm,u_int rt)
 {
   assem_debug("bic %s,%s,%s,asr #%d\n",regname[rt],regname[rt],regname[rs],imm);
@@ -595,24 +625,35 @@ static void emit_addimm_s(u_int s, u_int is64, u_int rs, uintptr_t imm, u_int rt
     assem_debug("sub%s %s,%s,%#lx\n", st, regname[rt], regname[rs], -imm);
     output_w32(0x51000000 | is64 | s | imm12_rn_rd(-imm, rs, rt));
   }
-  else if (imm < 16777216) {
-    assem_debug("add %s,%s,#%#lx\n",regname[rt],regname[rt],imm&0xfff000);
-    output_w32(0x11400000 | is64 | imm12_rn_rd(imm >> 12, rs, rt));
-    if ((imm & 0xfff) || s) {
-      assem_debug("add%s %s,%s,#%#lx\n",st,regname[rt],regname[rs],imm&0xfff);
-      output_w32(0x11000000 | is64 | s | imm12_rn_rd(imm & 0xfff, rt, rt));
+  else if (imm < 16777216 && (!(imm & 0xfff) || !s)) {
+    assem_debug("add%s %s,%s,#%#lx\n", st, regname[rt], regname[rs], imm&0xfff000);
+    output_w32(0x11400000 | is64 | s | imm12_rn_rd(imm >> 12, rs, rt));
+    if (imm & 0xfff) {
+      assem_debug("add %s,%s,#%#lx\n", regname[rt], regname[rt], imm&0xfff);
+      output_w32(0x11000000 | is64 | imm12_rn_rd(imm & 0xfff, rt, rt));
     }
   }
-  else if (-imm < 16777216) {
-    assem_debug("sub %s,%s,#%#lx\n",regname[rt],regname[rt],-imm&0xfff000);
-    output_w32(0x51400000 | is64 | imm12_rn_rd(-imm >> 12, rs, rt));
-    if ((imm & 0xfff) || s) {
-      assem_debug("sub%s %s,%s,#%#lx\n",st,regname[rt],regname[rs],-imm&0xfff);
-      output_w32(0x51000000 | is64 | s | imm12_rn_rd(-imm & 0xfff, rt, rt));
+  else if (-imm < 16777216 && (!(-imm & 0xfff) || !s)) {
+    assem_debug("sub%s %s,%s,#%#lx\n", st, regname[rt], regname[rs], -imm&0xfff000);
+    output_w32(0x51400000 | is64 | s | imm12_rn_rd(-imm >> 12, rs, rt));
+    if (-imm & 0xfff) {
+      assem_debug("sub %s,%s,#%#lx\n", regname[rt], regname[rt], -imm&0xfff);
+      output_w32(0x51000000 | is64 | imm12_rn_rd(-imm & 0xfff, rt, rt));
     }
   }
-  else
-    abort();
+  else {
+    u_int tmp = rt;
+    assert(!is64);
+    if (rs == rt) {
+      host_tempreg_acquire();
+      tmp = HOST_TEMPREG;
+    }
+    emit_movimm(imm, tmp);
+    assem_debug("add%s %s,%s,%s\n", st, regname[rt], regname[rs], regname[tmp]);
+    output_w32(0x0b000000 | s | rm_rn_rd(rs, tmp, rt));
+    if (tmp == HOST_TEMPREG)
+      host_tempreg_release();
+  }
 }
 
 static void emit_addimm(u_int rs, uintptr_t imm, u_int rt)
@@ -639,6 +680,11 @@ static void emit_addimm_and_set_flags(int imm, u_int rt)
   emit_addimm_s(1, 0, rt, imm, rt);
 }
 
+static void emit_addimm_and_set_flags3(u_int rs, int imm, u_int rt)
+{
+  emit_addimm_s(1, 0, rs, imm, rt);
+}
+
 static void emit_logicop_imm(u_int op, u_int rs, u_int imm, u_int rt)
 {
   const char *names[] = { "and", "orr", "eor", "ands" };
@@ -844,6 +890,12 @@ static void emit_csinvle_reg(u_int rs1,u_int rs2,u_int rt)
   output_w32(0x5a800000 | (COND_LE << 12) | rm_rn_rd(rs2, rs1, rt));
 }
 
+static void emit_csinvne_reg(u_int rs1,u_int rs2,u_int rt)
+{
+  assem_debug("csinv %s,%s,%s,ne\n",regname[rt],regname[rs1],regname[rs2]);
+  output_w32(0x5a800000 | (COND_NE << 12) | rm_rn_rd(rs2, rs1, rt));
+}
+
 static void emit_slti32(u_int rs,int imm,u_int rt)
 {
   if(rs!=rt) emit_zeroreg(rt);
@@ -972,6 +1024,13 @@ static void emit_jge(const void *a)
   output_w32(0x54000000 | (offset << 5) | COND_GE);
 }
 
+static void emit_jo(const void *a)
+{
+  assem_debug("bvs %p\n", a);
+  u_int offset = genjmpcc(a);
+  output_w32(0x54000000 | (offset << 5) | COND_VS);
+}
+
 static void emit_jno(const void *a)
 {
   assem_debug("bvc %p\n", a);
@@ -1405,7 +1464,7 @@ static void do_readstub(int n)
   u_int reglist = stubs[n].e;
   const signed char *i_regmap = i_regs->regmap;
   int rt;
-  if(dops[i].itype==C1LS||dops[i].itype==C2LS||dops[i].itype==LOADLR) {
+  if(dops[i].itype==C2LS||dops[i].itype==LOADLR) {
     rt=get_reg(i_regmap,FTEMP);
   }else{
     rt=get_reg(i_regmap,dops[i].rt1);
@@ -1435,7 +1494,7 @@ static void do_readstub(int n)
   emit_adds64(temp2,temp2,temp2);
   handler_jump=out;
   emit_jc(0);
-  if(dops[i].itype==C1LS||dops[i].itype==C2LS||(rt>=0&&dops[i].rt1!=0)) {
+  if(dops[i].itype==C2LS||(rt>=0&&dops[i].rt1!=0)) {
     switch(type) {
       case LOADB_STUB:  emit_ldrsb_dualindexed(temp2,rs,rt); break;
       case LOADBU_STUB: emit_ldrb_dualindexed(temp2,rs,rt); break;
@@ -1470,7 +1529,7 @@ static void do_readstub(int n)
   emit_addimm(cc<0?2:cc,(int)stubs[n].d,2);
   emit_far_call(handler);
   // (no cycle reload after read)
-  if(dops[i].itype==C1LS||dops[i].itype==C2LS||(rt>=0&&dops[i].rt1!=0)) {
+  if(dops[i].itype==C2LS||(rt>=0&&dops[i].rt1!=0)) {
     loadstore_extend(type,0,rt);
   }
   if(restore_jump)
@@ -1561,7 +1620,7 @@ static void do_writestub(int n)
   u_int reglist=stubs[n].e;
   signed char *i_regmap=i_regs->regmap;
   int rt,r;
-  if(dops[i].itype==C1LS||dops[i].itype==C2LS) {
+  if(dops[i].itype==C2LS) {
     rt=get_reg(i_regmap,r=FTEMP);
   }else{
     rt=get_reg(i_regmap,r=dops[i].rs2);
@@ -1827,8 +1886,10 @@ static void multdiv_assemble_arm64(int i, const struct regstat *i_regs)
 
         // div 0 quotient (remainder is already correct)
         host_tempreg_acquire();
-        if (dops[i].opcode2 == 0x1A) // DIV
-          emit_sub_asrimm(0,numerator,31,HOST_TEMPREG);
+        if (dops[i].opcode2 == 0x1A) { // DIV
+          emit_add_lsrimm(WZR,numerator,31,HOST_TEMPREG);
+          emit_orn_asrimm(HOST_TEMPREG,numerator,31,HOST_TEMPREG);
+        }
         else
           emit_movimm(~0,HOST_TEMPREG);
         emit_test(denominator,denominator);
@@ -1852,8 +1913,10 @@ static void multdiv_assemble_arm64(int i, const struct regstat *i_regs)
         if (hr >= 0)
           emit_mov(numerator,hr);
         if (lr >= 0) {
-          if (dops[i].opcode2 == 0x1A) // DIV
-            emit_sub_asrimm(0,numerator,31,lr);
+          if (dops[i].opcode2 == 0x1A) { // DIV
+            emit_add_lsrimm(WZR,numerator,31,lr);
+            emit_orn_asrimm(lr,numerator,31,lr);
+          }
           else
             emit_movimm(~0,lr);
         }
@@ -1863,6 +1926,17 @@ static void multdiv_assemble_arm64(int i, const struct regstat *i_regs)
         if (lr >= 0) emit_movimm(~0,lr);
       }
     }
+    else if ((dops[i].opcode2==0x1A || dops[i].opcode2==0x1B) && dops[i].rs1==0)
+    {
+      signed char denominator = get_reg(i_regs->regmap, dops[i].rs2);
+      assert(denominator >= 0);
+      if (hr >= 0) emit_zeroreg(hr);
+      if (lr >= 0) {
+        emit_zeroreg(lr);
+        emit_test(denominator, denominator);
+        emit_csinvne_reg(lr, lr, lr);
+      }
+    }
     else
     {
       // Multiply by zero is zero.