drc: prefer callee-saved regs on alloc

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm64.h

diff --git a/libpcsxcore/new_dynarec/assem_arm64.h b/libpcsxcore/new_dynarec/assem_arm64.h
index 6789f17..c5fcadf 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm64.h
+++ b/libpcsxcore/new_dynarec/assem_arm64.h
@@ -1,23 +1,16 @@
-#define HOST_REGS 29
-#define HOST_BTREG 27
-#define EXCLUDE_REG -1
-
 #define HOST_IMM8 1
-#define HAVE_CMOV_IMM 1
-#define RAM_SIZE 0x200000
-
-//#define REG_SHIFT 2
 
 /* calling convention:
    r0 -r17: caller-save
    r19-r29: callee-save */
 
-#define ARG1_REG 0
-#define ARG2_REG 1
-#define ARG3_REG 2
-#define ARG4_REG 3
+#define HOST_REGS 29
+#define HOST_BTREG 27
+#define EXCLUDE_REG -1
 
-#define SP 30
+#define SP 31
+#define WZR SP
+#define XZR SP
 
 #define LR 30
 #define HOST_TEMPREG LR
@@ -30,24 +23,27 @@
 #define HOST_CCREG 28
 #define rCC w28
 
+#define CALLER_SAVE_REGS 0x0007ffff
+#define PREFERRED_REG_FIRST 19
+#define PREFERRED_REG_LAST  27
+
 // stack space
 #define SSP_CALLEE_REGS (8*12)
 #define SSP_CALLER_REGS (8*20)
 #define SSP_ALL (SSP_CALLEE_REGS+SSP_CALLER_REGS)
 
+#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
+
 #ifndef __ASSEMBLER__
 
 extern char *invc_ptr;
 
-#define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
+struct tramp_insns
+{
+  u_int ldr;
+  u_int br;
+};
 
-// Code generator target address
-#if defined(BASE_ADDR_DYNAMIC)
-  // for platforms that can't just use .bss buffer (are there any on arm64?)
-  extern u_char *translation_cache;
-#else
-  // using a static buffer in .bss
-  extern u_char translation_cache[1 << TARGET_SIZE_2];
-#endif
+static void clear_cache_arm64(char *start, char *end);
 
 #endif // !__ASSEMBLY__