drc: arm64 wip

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm64.h

diff --git a/libpcsxcore/new_dynarec/assem_arm64.h b/libpcsxcore/new_dynarec/assem_arm64.h
index 8ba17ed..fe12ad7 100644 (file)
--- a/libpcsxcore/new_dynarec/assem_arm64.h
+++ b/libpcsxcore/new_dynarec/assem_arm64.h
@@ -3,19 +3,15 @@
 #define EXCLUDE_REG -1
 
 #define HOST_IMM8 1
-#define HAVE_CMOV_IMM 1
 #define RAM_SIZE 0x200000
 
-//#define REG_SHIFT 2
-
 /* calling convention:
    r0 -r17: caller-save
    r19-r29: callee-save */
 
-#define ARG1_REG 0
-#define ARG2_REG 1
-#define ARG3_REG 2
-#define ARG4_REG 3
+#define SP 31
+#define WZR SP
+#define XZR SP
 
 #define LR 30
 #define HOST_TEMPREG LR
@@ -28,6 +24,11 @@
 #define HOST_CCREG 28
 #define rCC w28
 
+// stack space
+#define SSP_CALLEE_REGS (8*12)
+#define SSP_CALLER_REGS (8*20)
+#define SSP_ALL (SSP_CALLEE_REGS+SSP_CALLER_REGS)
+
 #ifndef __ASSEMBLER__
 
 extern char *invc_ptr;