new ability to adjust psx cpu clock

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.c

diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index f65e5bd..66afe12 100644 (file)
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -116,17 +116,17 @@ void gen_interupt()
 // from interpreter
 extern void MTC0(int reg, u32 val);
 
-void pcsx_mtc0(u32 reg)
+void pcsx_mtc0(u32 reg, u32 val)
 {
-       evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
-       MTC0(reg, readmem_word);
+       evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
+       MTC0(reg, val);
        gen_interupt();
 }
 
-void pcsx_mtc0_ds(u32 reg)
+void pcsx_mtc0_ds(u32 reg, u32 val)
 {
-       evprintf("MTC0 %d #%x @%08x %u\n", reg, readmem_word, psxRegs.pc, psxRegs.cycle);
-       MTC0(reg, readmem_word);
+       evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
+       MTC0(reg, val);
 }
 
 void new_dyna_save(void)
@@ -190,13 +190,19 @@ static int ari64_init()
 #if !defined(DRC_DBG) && !defined(PCNT)
 #ifdef __arm__
        gte_handlers[0x06] = gteNCLIP_arm;
+       gte_handlers_nf[0x01] = gteRTPS_nf_arm;
+       gte_handlers_nf[0x30] = gteRTPT_nf_arm;
 #endif
 #ifdef __ARM_NEON__
        // compiler's _nf version is still a lot slower then neon
+       // _nf_arm RTPS is roughly the same, RTPT slower
        gte_handlers[0x01] = gte_handlers_nf[0x01] = gteRTPS_neon;
        gte_handlers[0x30] = gte_handlers_nf[0x30] = gteRTPT_neon;
        gte_handlers[0x12] = gte_handlers_nf[0x12] = gteMVMVA_neon;
 #endif
+#endif
+#ifdef DRC_DBG
+       memcpy(gte_handlers_nf, gte_handlers, sizeof(gte_handlers_nf));
 #endif
        psxH_ptr = psxH;
 
@@ -294,6 +300,8 @@ unsigned short hword;
 unsigned char byte;
 int pending_exception, stop;
 unsigned int next_interupt;
+int new_dynarec_did_compile;
+int cycle_multiplier;
 void *psxH_ptr;
 void new_dynarec_init() {}
 void new_dyna_start() {}