DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
-DRC_VAR(invc_ptr, 4)
+DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
+@DRC_VAR(align0, 4) /* unused/alignment */
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
/* psxRegs */
-DRC_VAR(reg, 128)
+@DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
@DRC_VAR(intCycle, 256)
DRC_VAR(rcnts, 7*4*4)
+DRC_VAR(inv_code_start, 4)
+DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 4)
DRC_VAR(mem_wtab, 4)
DRC_VAR(psxH_ptr, 4)
DRC_VAR(zeromem_ptr, 4)
-DRC_VAR(inv_code_start, 4)
-DRC_VAR(inv_code_end, 4)
-DRC_VAR(branch_target, 4)
+DRC_VAR(invc_ptr, 4)
DRC_VAR(scratch_buf_ptr, 4)
-@DRC_VAR(align0, 12) /* unused/alignment */
+@DRC_VAR(align1, 8) /* unused/alignment */
DRC_VAR(mini_ht, 256)
DRC_VAR(restore_candidate, 512)
-/* unused */
-DRC_VAR(FCR0, 4)
-DRC_VAR(FCR31, 4)
#ifdef TEXRELS_FORBIDDEN
.data
FUNCTION(verify_code_ds):
str r8, [fp, #LO_branch_target]
-FUNCTION(verify_code_vm):
FUNCTION(verify_code):
/* r1 = source */
/* r2 = target */
bl get_addr
mov pc, r0
.size verify_code, .-verify_code
- .size verify_code_vm, .-verify_code_vm
+ .size verify_code_ds, .-verify_code_ds
.align 2
FUNCTION(cc_interrupt):
FUNCTION(new_dyna_start):
/* ip is stored to conform EABI alignment */
stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
- load_varadr fp, dynarec_local
+ mov fp, r0 /* dynarec_local */
ldr r0, [fp, #LO_pcaddr]
bl get_addr_ht
ldr r1, [fp, #LO_next_interupt]
blx r3
ldr r0, [fp, #LO_next_interupt]
- pop {r2, r3}
+ pop {r2, lr}
str r0, [fp, #LO_last_count]
sub r0, r2, r0
- bx r3
+ bx lr
.endm
FUNCTION(jump_handler_write8):
blx r3
ldr r0, [fp, #LO_next_interupt]
- pop {r2, r3}
+ pop {r2, lr}
str r0, [fp, #LO_last_count]
sub r0, r2, r0
- bx r3
+ bx lr
FUNCTION(jump_handle_swl):
/* r0 = address, r1 = data, r2 = cycles */