/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* linkage_arm.s for PCSX *
- * Copyright (C) 2009-2010 Ari64 *
+ * Copyright (C) 2009-2011 Ari64 *
* Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
* *
* This program is free software; you can redistribute it and/or modify *
.size memory_map, 4194304
dynarec_local_end = memory_map + 4194304
+.macro load_var_adr reg var
+.if HAVE_ARMV7
+ movw \reg, #:lower16:\var
+ movt \reg, #:upper16:\var
+.else
+ ldr \reg, =\var
+.endif
+.endm
+
.text
.align 2
.global dyna_linker
dyna_linker:
/* r0 = virtual target address */
/* r1 = instruction to patch */
- mov r12, r0
- mov r6, #4096
- mov r2, #0x80000
ldr r3, .jiptr
+ /* get_page */
+ lsr r2, r0, #12
+ mov r6, #4096
+ bic r2, r2, #0xe0000
sub r6, r6, #1
+ cmp r2, #0x1000
ldr r7, [r1]
- eor r2, r2, r12, lsr #12
- and r6, r6, r12, lsr #12
+ biclt r2, #0x0e00
+ and r6, r6, r2
cmp r2, #2048
add r12, r7, #2
orrcs r2, r6, #2048
dyna_linker_ds:
/* r0 = virtual target address */
/* r1 = instruction to patch */
- mov r12, r0
- mov r6, #4096
- mov r2, #0x80000
ldr r3, .jiptr
+ /* get_page */
+ lsr r2, r0, #12
+ mov r6, #4096
+ bic r2, r2, #0xe0000
sub r6, r6, #1
+ cmp r2, #0x1000
ldr r7, [r1]
- eor r2, r2, r12, lsr #12
- and r6, r6, r12, lsr #12
+ biclt r2, #0x0e00
+ and r6, r6, r2
cmp r2, #2048
add r12, r7, #2
orrcs r2, r6, #2048
.size indirect_jump, .-indirect_jump
.size indirect_jump_indexed, .-indirect_jump_indexed
+ .align 2
+ .global invalidate_addr_r0
+ .type invalidate_addr_r0, %function
+invalidate_addr_r0:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r0, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r0, .-invalidate_addr_r0
+ .align 2
+ .global invalidate_addr_r1
+ .type invalidate_addr_r1, %function
+invalidate_addr_r1:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r1, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r1, .-invalidate_addr_r1
+ .align 2
+ .global invalidate_addr_r2
+ .type invalidate_addr_r2, %function
+invalidate_addr_r2:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r2, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r2, .-invalidate_addr_r2
+ .align 2
+ .global invalidate_addr_r3
+ .type invalidate_addr_r3, %function
+invalidate_addr_r3:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r3, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r3, .-invalidate_addr_r3
+ .align 2
+ .global invalidate_addr_r4
+ .type invalidate_addr_r4, %function
+invalidate_addr_r4:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r4, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r4, .-invalidate_addr_r4
+ .align 2
+ .global invalidate_addr_r5
+ .type invalidate_addr_r5, %function
+invalidate_addr_r5:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r5, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r5, .-invalidate_addr_r5
+ .align 2
+ .global invalidate_addr_r6
+ .type invalidate_addr_r6, %function
+invalidate_addr_r6:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r6, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r6, .-invalidate_addr_r6
+ .align 2
+ .global invalidate_addr_r7
+ .type invalidate_addr_r7, %function
+invalidate_addr_r7:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r7, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r7, .-invalidate_addr_r7
+ .align 2
+ .global invalidate_addr_r8
+ .type invalidate_addr_r8, %function
+invalidate_addr_r8:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r8, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r8, .-invalidate_addr_r8
+ .align 2
+ .global invalidate_addr_r9
+ .type invalidate_addr_r9, %function
+invalidate_addr_r9:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r9, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r9, .-invalidate_addr_r9
+ .align 2
+ .global invalidate_addr_r10
+ .type invalidate_addr_r10, %function
+invalidate_addr_r10:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r10, #12
+ b invalidate_addr_call
+ .size invalidate_addr_r10, .-invalidate_addr_r10
+ .align 2
+ .global invalidate_addr_r12
+ .type invalidate_addr_r12, %function
+invalidate_addr_r12:
+ stmia fp, {r0, r1, r2, r3, r12, lr}
+ lsr r0, r12, #12
+ .size invalidate_addr_r12, .-invalidate_addr_r12
+ .align 2
+ .global invalidate_addr_call
+ .type invalidate_addr_call, %function
+invalidate_addr_call:
+ bl invalidate_block
+ ldmia fp, {r0, r1, r2, r3, r12, pc}
+ .size invalidate_addr_call, .-invalidate_addr_call
+
.align 2
.global new_dyna_start
.type new_dyna_start, %function
new_dyna_start:
/* ip is stored to conform EABI alignment */
stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
-.if HAVE_ARMV7
- movw fp, #:lower16:dynarec_local
- movt fp, #:upper16:dynarec_local
-.else
- ldr fp, .dlptr
-.endif
+ load_var_adr fp, dynarec_local
ldr r0, [fp, #pcaddr-dynarec_local]
bl get_addr_ht
ldr r1, [fp, #next_interupt-dynarec_local]
str r1, [fp, #last_count-dynarec_local]
sub r10, r10, r1
mov pc, r0
-.dlptr:
- .word dynarec_local
.size new_dyna_start, .-new_dyna_start
/* --------------------------------------- */
.global ari_write_ram_mirror8
.global ari_write_ram_mirror16
.global ari_write_ram_mirror32
+.global ari_write_ram_mirror_ro32
.global ari_read_bios8
.global ari_read_bios16
.global ari_read_bios32
ari_write_ram_mirror32:
ari_write_ram_mirror (3<<11), word,
+ari_write_ram_mirror_ro32:
+ load_var_adr r0, pcsx_ram_is_ro
+ ldr r0, [r0]
+ tst r0, r0
+ movne pc, lr
+ nop
+ b ari_write_ram_mirror32
+
.macro ari_read_bios_mirror bic_const op
ldr r0, [fp, #address-dynarec_local]
notaz.gp2x.de / pcsx_rearmed.git / blobdiff