drc: reapply some libretro changes

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c

diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index 77fc357..15b9383 100644 (file)
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -121,8 +121,8 @@ struct regstat
   uint64_t wasdirty;
   uint64_t dirty;
   uint64_t u;
-  u_int wasconst;
-  u_int isconst;
+  u_int wasconst;                // before; for example 'lw r2, (r2)' wasconst is true
+  u_int isconst;                 //  ... but isconst is false when r2 is known
   u_int loadedconst;             // host regs that have constants loaded
   u_int waswritten;              // MIPS regs that were used as store base before
 };
@@ -468,12 +468,12 @@ static void do_clear_cache(void)
 int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
 int cycle_multiplier_override;
 int cycle_multiplier_old;
+static int cycle_multiplier_active;
 
 static int CLOCK_ADJUST(int x)
 {
-  int m = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
-        ? cycle_multiplier_override : cycle_multiplier;
-  int s=(x>>31)|1;
+  int m = cycle_multiplier_active;
+  int s = (x >> 31) | 1;
   return (x * m + s * 50) / 100;
 }
 
@@ -1616,9 +1616,8 @@ static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
 static void mov_alloc(struct regstat *current,int i)
 {
   if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
-    // logically this is needed but just won't work, no idea why
-    //alloc_cc(current,i); // for stalls
-    //dirty_reg(current,CCREG);
+    alloc_cc(current,i); // for stalls
+    dirty_reg(current,CCREG);
   }
 
   // Note: Don't need to actually alloc the source registers
@@ -4123,6 +4122,7 @@ static int assemble(int i, const struct regstat *i_regs, int ccadj_)
     case SPAN:
       pagespan_assemble(i, i_regs);
       break;
+    case NOP:
     case OTHER:
     case NI:
       // not handled, just skip
@@ -6841,14 +6841,22 @@ void new_dynarec_init(void)
 {
   SysPrintf("Init new dynarec\n");
 
+#ifdef _3DS
+  check_rosalina();
+#endif
 #ifdef BASE_ADDR_DYNAMIC
   #ifdef VITA
-  sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
+  sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
   if (sceBlock < 0)
     SysPrintf("sceKernelAllocMemBlockForVM failed\n");
   int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
   if (ret < 0)
     SysPrintf("sceKernelGetMemBlockBase failed\n");
+  sceKernelOpenVMDomain();
+  sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
+  #elif defined(_MSC_VER)
+  ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
+    PAGE_EXECUTE_READWRITE);
   #else
   uintptr_t desired_addr = 0;
   #ifdef __ELF__
@@ -6907,9 +6915,6 @@ void new_dynarec_cleanup(void)
 
 static u_int *get_source_start(u_int addr, u_int *limit)
 {
-  if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
-    cycle_multiplier_override = 0;
-
   if (addr < 0x00200000 ||
     (0xa0000000 <= addr && addr < 0xa0200000))
   {
@@ -6924,7 +6929,7 @@ static u_int *get_source_start(u_int addr, u_int *limit)
     // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
     // but timings in PCSX are too tied to the interpreter's BIAS
     if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
-      cycle_multiplier_override = 200;
+      cycle_multiplier_active = 200;
 
     *limit = (addr & 0xfff00000) | 0x80000;
     return (u_int *)((u_char *)psxR + (addr&0x7ffff));
@@ -7036,6 +7041,42 @@ void new_dynarec_load_blocks(const void *save, int size)
   memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
 }
 
+static void apply_hacks(void)
+{
+  int i;
+  if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
+    return;
+  /* special hack(s) */
+  for (i = 0; i < slen - 4; i++)
+  {
+    // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
+    if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
+        && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
+        && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
+    {
+      SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
+      dops[i + 3].itype = NOP;
+    }
+  }
+  i = slen;
+  if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
+      && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
+      && dops[i-7].itype == STORE)
+  {
+    i = i-8;
+    if (dops[i].itype == IMM16)
+      i--;
+    // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
+    if (dops[i].itype == STORELR && dops[i].rs1 == 6
+      && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
+    {
+      SysPrintf("F1 hack from %08x\n", start);
+      if (f1_hack == 0)
+        f1_hack = ~0u;
+    }
+  }
+}
+
 int new_recompile_block(u_int addr)
 {
   u_int pagelimit = 0;
@@ -7093,6 +7134,9 @@ int new_recompile_block(u_int addr)
     return 0;
   }
 
+  cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
+    ? cycle_multiplier_override : cycle_multiplier;
+
   source = get_source_start(start, &pagelimit);
   if (source == NULL) {
     SysPrintf("Compile at bogus memory address: %08x\n", addr);
@@ -7614,23 +7658,7 @@ int new_recompile_block(u_int addr)
   }
   assert(slen>0);
 
-  /* spacial hack(s) */
-  if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
-      && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
-      && dops[i-7].itype == STORE)
-  {
-    i = i-8;
-    if (dops[i].itype == IMM16)
-      i--;
-    // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
-    if (dops[i].itype == STORELR && dops[i].rs1 == 6
-      && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
-    {
-      SysPrintf("F1 hack from %08x\n", start);
-      if (f1_hack == 0)
-        f1_hack = ~0u;
-    }
-  }
+  apply_hacks();
 
   /* Pass 2 - Register dependencies and branch targets */
 
@@ -9197,7 +9225,7 @@ int new_recompile_block(u_int addr)
             load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
       }
       // TODO: if(is_ooo(i)) address_generation(i+1);
-      if (dops[i].itype == CJUMP)
+      if (!dops[i].is_jump || dops[i].itype == CJUMP)
         load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
       if (ram_offset && (dops[i].is_load || dops[i].is_store))
         load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);