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drc: use print wrapper to output errors
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
new_dynarec.c
diff --git
a/libpcsxcore/new_dynarec/new_dynarec.c
b/libpcsxcore/new_dynarec/new_dynarec.c
index
b6af4c4
..
4255917
100644
(file)
--- a/
libpcsxcore/new_dynarec/new_dynarec.c
+++ b/
libpcsxcore/new_dynarec/new_dynarec.c
@@
-41,6
+41,11
@@
#include "assem_arm.h"
#endif
#include "assem_arm.h"
#endif
+#ifdef __BLACKBERRY_QNX__
+#undef __clear_cache
+#define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
+#endif
+
#define MAXBLOCK 4096
#define MAX_OUTPUT_BLOCK_SIZE 262144
#define MAXBLOCK 4096
#define MAX_OUTPUT_BLOCK_SIZE 262144
@@
-141,6
+146,11
@@
struct ll_entry
int new_dynarec_did_compile;
int new_dynarec_hacks;
u_int stop_after_jal;
int new_dynarec_did_compile;
int new_dynarec_hacks;
u_int stop_after_jal;
+#ifndef RAM_FIXED
+ static u_int ram_offset;
+#else
+ static const u_int ram_offset=0;
+#endif
extern u_char restore_candidate[512];
extern int cycle_count;
extern u_char restore_candidate[512];
extern int cycle_count;
@@
-274,6
+284,8
@@
int tracedebug=0;
//#define DEBUG_CYCLE_COUNT 1
//#define DEBUG_CYCLE_COUNT 1
+#define NO_CYCLE_PENALTY_THR 12
+
int cycle_multiplier; // 100 for 1.0
static int CLOCK_ADJUST(int x)
int cycle_multiplier; // 100 for 1.0
static int CLOCK_ADJUST(int x)
@@
-644,7
+656,7
@@
uint64_t get_const(struct regstat *cur,signed char reg)
return current_constmap[hr];
}
}
return current_constmap[hr];
}
}
-
p
rintf("Unknown constant in r%d\n",reg);
+
SysP
rintf("Unknown constant in r%d\n",reg);
exit(1);
}
exit(1);
}
@@
-1211,7
+1223,7
@@
void invalidate_block(u_int block)
if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
get_bounds((int)head->addr,&start,&end);
//printf("start: %x end: %x\n",start,end);
if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
get_bounds((int)head->addr,&start,&end);
//printf("start: %x end: %x\n",start,end);
- if(page<2048&&start>=
0x80000000&&end<0x80000000
+RAM_SIZE) {
+ if(page<2048&&start>=
(u_int)rdram&&end<(u_int)rdram
+RAM_SIZE) {
if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
@@
-1241,10
+1253,11
@@
void invalidate_addr(u_int addr)
if(page<2048) { // RAM
struct ll_entry *head;
u_int addr_min=~0, addr_max=0;
if(page<2048) { // RAM
struct ll_entry *head;
u_int addr_min=~0, addr_max=0;
- int mask=RAM_SIZE-1;
+ u_int mask=RAM_SIZE-1;
+ u_int addr_main=0x80000000|(addr&mask);
int pg1;
int pg1;
- inv_code_start=addr&~0xfff;
- inv_code_end=addr|0xfff;
+ inv_code_start=addr
_main
&~0xfff;
+ inv_code_end=addr
_main
|0xfff;
pg1=page;
if (pg1>0) {
// must check previous page too because of spans..
pg1=page;
if (pg1>0) {
// must check previous page too because of spans..
@@
-1255,11
+1268,15
@@
void invalidate_addr(u_int addr)
for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
u_int start,end;
get_bounds((int)head->addr,&start,&end);
for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
u_int start,end;
get_bounds((int)head->addr,&start,&end);
- if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
+ if(ram_offset) {
+ start-=ram_offset;
+ end-=ram_offset;
+ }
+ if(start<=addr_main&&addr_main<end) {
if(start<addr_min) addr_min=start;
if(end>addr_max) addr_max=end;
}
if(start<addr_min) addr_min=start;
if(end>addr_max) addr_max=end;
}
- else if(addr<start) {
+ else if(addr
_main
<start) {
if(start<inv_code_end)
inv_code_end=start-1;
}
if(start<inv_code_end)
inv_code_end=start-1;
}
@@
-1276,6
+1293,8
@@
void invalidate_addr(u_int addr)
return;
}
else {
return;
}
else {
+ inv_code_start=(addr&~mask)|(inv_code_start&mask);
+ inv_code_end=(addr&~mask)|(inv_code_end&mask);
inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
return;
}
inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
return;
}
@@
-1978,7
+1997,7
@@
void delayslot_alloc(struct regstat *current,int i)
case HLECALL:
case SPAN:
assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
case HLECALL:
case SPAN:
assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
-
p
rintf("Disabled speculative precompilation\n");
+
SysP
rintf("Disabled speculative precompilation\n");
stop_after_jal=1;
break;
case IMM16:
stop_after_jal=1;
break;
case IMM16:
@@
-2917,6
+2936,10
@@
void load_assemble(int i,struct regstat *i_regs)
jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
}
}
jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
}
}
+ else if(ram_offset&&memtarget) {
+ emit_addimm(addr,ram_offset,HOST_TEMPREG);
+ fastload_reg_override=HOST_TEMPREG;
+ }
}else{ // using tlb
int x=0;
if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
}else{ // using tlb
int x=0;
if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
@@
-2982,7
+3005,7
@@
void load_assemble(int i,struct regstat *i_regs)
gen_tlb_addr_r(a,map);
emit_movswl_indexed(x,a,tl);
}else{
gen_tlb_addr_r(a,map);
emit_movswl_indexed(x,a,tl);
}else{
- #ifdef RAM_OFFSET
+ #if
1 //
def RAM_OFFSET
emit_movswl_indexed(x,a,tl);
#else
emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
emit_movswl_indexed(x,a,tl);
#else
emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
@@
-3069,7
+3092,7
@@
void load_assemble(int i,struct regstat *i_regs)
gen_tlb_addr_r(a,map);
emit_movzwl_indexed(x,a,tl);
}else{
gen_tlb_addr_r(a,map);
emit_movzwl_indexed(x,a,tl);
}else{
- #ifdef RAM_OFFSET
+ #if
1 //
def RAM_OFFSET
emit_movzwl_indexed(x,a,tl);
#else
emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
emit_movzwl_indexed(x,a,tl);
#else
emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
@@
-3226,6
+3249,10
@@
void store_assemble(int i,struct regstat *i_regs)
jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
#endif
}
jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
#endif
}
+ else if(ram_offset&&memtarget) {
+ emit_addimm(addr,ram_offset,HOST_TEMPREG);
+ faststore_reg_override=HOST_TEMPREG;
+ }
}else{ // using tlb
int x=0;
if (opcode[i]==0x28) x=3; // SB
}else{ // using tlb
int x=0;
if (opcode[i]==0x28) x=3; // SB
@@
-3270,7
+3297,8
@@
void store_assemble(int i,struct regstat *i_regs)
gen_tlb_addr_w(a,map);
emit_writehword_indexed(tl,x,a);
}else
gen_tlb_addr_w(a,map);
emit_writehword_indexed(tl,x,a);
}else
- emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
+ //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
+ emit_writehword_indexed(tl,x,a);
}
type=STOREH_STUB;
}
}
type=STOREH_STUB;
}
@@
-3341,7
+3369,7
@@
void store_assemble(int i,struct regstat *i_regs)
// basic current block modification detection..
// not looking back as that should be in mips cache already
if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
// basic current block modification detection..
// not looking back as that should be in mips cache already
if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
-
p
rintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
+
SysP
rintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
assert(i_regs->regmap==regs[i].regmap); // not delay slot
if(i_regs->regmap==regs[i].regmap) {
load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
assert(i_regs->regmap==regs[i].regmap); // not delay slot
if(i_regs->regmap==regs[i].regmap) {
load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
@@
-3874,6
+3902,10
@@
void c2ls_assemble(int i,struct regstat *i_regs)
if(!c) {
jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
}
if(!c) {
jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
}
+ else if(ram_offset&&memtarget) {
+ emit_addimm(ar,ram_offset,HOST_TEMPREG);
+ fastio_reg_override=HOST_TEMPREG;
+ }
if (opcode[i]==0x32) { // LWC2
#ifdef HOST_IMM_ADDR32
if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
if (opcode[i]==0x32) { // LWC2
#ifdef HOST_IMM_ADDR32
if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
@@
-4045,7
+4077,7
@@
void ds_assemble(int i,struct regstat *i_regs)
case CJUMP:
case SJUMP:
case FJUMP:
case CJUMP:
case SJUMP:
case FJUMP:
-
p
rintf("Jump in the delay slot. This is probably a bug.\n");
+
SysP
rintf("Jump in the delay slot. This is probably a bug.\n");
}
is_delayslot=0;
}
}
is_delayslot=0;
}
@@
-4938,7
+4970,7
@@
void ds_assemble_entry(int i)
case CJUMP:
case SJUMP:
case FJUMP:
case CJUMP:
case SJUMP:
case FJUMP:
-
p
rintf("Jump in the delay slot. This is probably a bug.\n");
+
SysP
rintf("Jump in the delay slot. This is probably a bug.\n");
}
store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
}
store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
@@
-4956,6
+4988,7
@@
void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
int count;
int jaddr;
int idle=0;
int count;
int jaddr;
int idle=0;
+ int t=0;
if(itype[i]==RJUMP)
{
*adj=0;
if(itype[i]==RJUMP)
{
*adj=0;
@@
-4963,7
+4996,7
@@
void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
//if(ba[i]>=start && ba[i]<(start+slen*4))
if(internal_branch(branch_regs[i].is32,ba[i]))
{
//if(ba[i]>=start && ba[i]<(start+slen*4))
if(internal_branch(branch_regs[i].is32,ba[i]))
{
-
int
t=(ba[i]-start)>>2;
+ t=(ba[i]-start)>>2;
if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
else *adj=ccadj[t];
}
if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
else *adj=ccadj[t];
}
@@
-4982,7
+5015,14
@@
void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
emit_jmp(0);
}
else if(*adj==0||invert) {
emit_jmp(0);
}
else if(*adj==0||invert) {
- emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
+ int cycles=CLOCK_ADJUST(count+2);
+ // faster loop HACK
+ if (t&&*adj) {
+ int rel=t-i;
+ if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
+ cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
+ }
+ emit_addimm_and_set_flags(cycles,HOST_CCREG);
jaddr=(int)out;
emit_jns(0);
}
jaddr=(int)out;
emit_jns(0);
}
@@
-5208,7
+5248,7
@@
void do_ccstub(int n)
}
emit_writeword(r,(int)&pcaddr);
}
}
emit_writeword(r,(int)&pcaddr);
}
- else {
p
rintf("Unknown branch type in do_ccstub\n");exit(1);}
+ else {
SysP
rintf("Unknown branch type in do_ccstub\n");exit(1);}
}
// Update cycle count
assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
}
// Update cycle count
assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
@@
-6765,7
+6805,7
@@
static void pagespan_ds()
case CJUMP:
case SJUMP:
case FJUMP:
case CJUMP:
case SJUMP:
case FJUMP:
-
p
rintf("Jump in the delay slot. This is probably a bug.\n");
+
SysP
rintf("Jump in the delay slot. This is probably a bug.\n");
}
int btaddr=get_reg(regs[0].regmap,BTREG);
if(btaddr<0) {
}
int btaddr=get_reg(regs[0].regmap,BTREG);
if(btaddr<0) {
@@
-7993,10
+8033,16
@@
void new_dynarec_init()
{
printf("Init new dynarec\n");
out=(u_char *)BASE_ADDR;
{
printf("Init new dynarec\n");
out=(u_char *)BASE_ADDR;
+#if BASE_ADDR_FIXED
if (mmap (out, 1<<TARGET_SIZE_2,
PROT_READ | PROT_WRITE | PROT_EXEC,
MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
if (mmap (out, 1<<TARGET_SIZE_2,
PROT_READ | PROT_WRITE | PROT_EXEC,
MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
- -1, 0) <= 0) {printf("mmap() failed\n");}
+ -1, 0) <= 0) {SysPrintf("mmap() failed\n");}
+#else
+ // not all systems allow execute in data segment by default
+ if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
+ SysPrintf("mprotect() failed\n");
+#endif
#ifdef MUPEN64
rdword=&readmem_dword;
fake_pc.f.r.rs=&readmem_dword;
#ifdef MUPEN64
rdword=&readmem_dword;
fake_pc.f.r.rs=&readmem_dword;
@@
-8050,17
+8096,24
@@
void new_dynarec_init()
#endif
tlb_hacks();
arch_init();
#endif
tlb_hacks();
arch_init();
+#ifndef RAM_FIXED
+ ram_offset=(u_int)rdram-0x80000000;
+#endif
+ if (ram_offset!=0)
+ SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
}
void new_dynarec_cleanup()
{
int n;
}
void new_dynarec_cleanup()
{
int n;
- if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
+ #if BASE_ADDR_FIXED
+ if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
+ #endif
for(n=0;n<4096;n++) ll_clear(jump_in+n);
for(n=0;n<4096;n++) ll_clear(jump_out+n);
for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
#ifdef ROM_COPY
for(n=0;n<4096;n++) ll_clear(jump_in+n);
for(n=0;n<4096;n++) ll_clear(jump_out+n);
for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
#ifdef ROM_COPY
- if (munmap (ROM_COPY, 67108864) < 0) {
p
rintf("munmap() failed\n");}
+ if (munmap (ROM_COPY, 67108864) < 0) {
SysP
rintf("munmap() failed\n");}
#endif
}
#endif
}
@@
-8157,7
+8210,7
@@
int new_recompile_block(int addr)
}
#endif
else {
}
#endif
else {
-
p
rintf("Compile at bogus memory address: %x \n", (int)addr);
+
SysP
rintf("Compile at bogus memory address: %x \n", (int)addr);
exit(1);
}
exit(1);
}
@@
-8486,7
+8539,7
@@
int new_recompile_block(int addr)
case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
#endif
default: strcpy(insn[i],"???"); type=NI;
case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
#endif
default: strcpy(insn[i],"???"); type=NI;
-
p
rintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
+
SysP
rintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
break;
}
itype[i]=type;
break;
}
itype[i]=type;
@@
-8761,7
+8814,7
@@
int new_recompile_block(int addr)
// branch in delay slot?
if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
// don't handle first branch and call interpreter if it's hit
// branch in delay slot?
if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
// don't handle first branch and call interpreter if it's hit
-
p
rintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
+
SysP
rintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
}
// basic load delay detection
do_in_intrp=1;
}
// basic load delay detection
@@
-8769,14
+8822,14
@@
int new_recompile_block(int addr)
int t=(ba[i-1]-start)/4;
if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
// jump target wants DS result - potential load delay effect
int t=(ba[i-1]-start)/4;
if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
// jump target wants DS result - potential load delay effect
-
p
rintf("load delay @%08x (%08x)\n", addr + i*4, addr);
+
SysP
rintf("load delay @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
bt[t+1]=1; // expected return from interpreter
}
else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
!(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
// v0 overwrite like this is a sign of trouble, bail out
do_in_intrp=1;
bt[t+1]=1; // expected return from interpreter
}
else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
!(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
// v0 overwrite like this is a sign of trouble, bail out
-
p
rintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
+
SysP
rintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
}
}
do_in_intrp=1;
}
}
@@
-8823,7
+8876,7
@@
int new_recompile_block(int addr)
// Stop if we're compiling junk
if(itype[i]==NI&&opcode[i]==0x11) {
done=stop_after_jal=1;
// Stop if we're compiling junk
if(itype[i]==NI&&opcode[i]==0x11) {
done=stop_after_jal=1;
-
p
rintf("Disabled speculative precompilation\n");
+
SysP
rintf("Disabled speculative precompilation\n");
}
}
slen=i;
}
}
slen=i;
@@
-9040,7
+9093,7
@@
int new_recompile_block(int addr)
current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
current.u|=1;
current.uu|=1;
current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
current.u|=1;
current.uu|=1;
- } else {
p
rintf("oops, branch at end of block with no delay slot\n");exit(1); }
+ } else {
SysP
rintf("oops, branch at end of block with no delay slot\n");exit(1); }
}
is_ds[i]=ds;
if(ds) {
}
is_ds[i]=ds;
if(ds) {
@@
-9815,7
+9868,7
@@
int new_recompile_block(int addr)
// GTE runs in parallel until accessed, divide by 2 for a rough guess
cc+=gte_cycletab[source[i]&0x3f]/2;
}
// GTE runs in parallel until accessed, divide by 2 for a rough guess
cc+=gte_cycletab[source[i]&0x3f]/2;
}
- else if(/*itype[i]==LOAD||
*/itype[i]==STORE||itype[i]==C1LS) // load
causes weird timing issues
+ else if(/*itype[i]==LOAD||
itype[i]==STORE||*/itype[i]==C1LS) // load,store
causes weird timing issues
{
cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
}
{
cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
}
@@
-10106,7
+10159,7
@@
int new_recompile_block(int addr)
if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
{
if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
{
-
p
rintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
+
SysP
rintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
}
regmap_pre[i+1][hr]=-1;
assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
}
regmap_pre[i+1][hr]=-1;
@@
-11543,7
+11596,7
@@
int new_recompile_block(int addr)
// If we're within 256K of the end of the buffer,
// start over from the beginning. (Is 256K enough?)
// If we're within 256K of the end of the buffer,
// start over from the beginning. (Is 256K enough?)
- if((
int)out>
BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
+ if((
u_int)out>(u_int)
BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
// Trap writes to any of the pages we compiled
for(i=start>>12;i<=(start+slen*4)>>12;i++) {
// Trap writes to any of the pages we compiled
for(i=start>>12;i<=(start+slen*4)>>12;i++) {
@@
-11571,11
+11624,11
@@
int new_recompile_block(int addr)
/* Pass 10 - Free memory by expiring oldest blocks */
/* Pass 10 - Free memory by expiring oldest blocks */
- int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
+ int end=((((int)out-
(int)
BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
while(expirep!=end)
{
int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
while(expirep!=end)
{
int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
- int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
+ int base=
(int)
BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
inv_debug("EXP: Phase %d\n",expirep);
switch((expirep>>11)&3)
{
inv_debug("EXP: Phase %d\n",expirep);
switch((expirep>>11)&3)
{