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drc: update invalid_code for RAM when mirrors are touched
[pcsx_rearmed.git]
/
libpcsxcore
/
new_dynarec
/
new_dynarec.c
diff --git
a/libpcsxcore/new_dynarec/new_dynarec.c
b/libpcsxcore/new_dynarec/new_dynarec.c
index
72af92d
..
6f5ca8f
100644
(file)
--- a/
libpcsxcore/new_dynarec/new_dynarec.c
+++ b/
libpcsxcore/new_dynarec/new_dynarec.c
@@
-121,7
+121,11
@@
struct ll_entry
char shadow[1048576] __attribute__((aligned(16)));
void *copy;
int expirep;
char shadow[1048576] __attribute__((aligned(16)));
void *copy;
int expirep;
+#ifndef PCSX
u_int using_tlb;
u_int using_tlb;
+#else
+ static const u_int using_tlb=0;
+#endif
u_int stop_after_jal;
extern u_char restore_candidate[512];
extern int cycle_count;
u_int stop_after_jal;
extern u_char restore_candidate[512];
extern int cycle_count;
@@
-1182,6
+1186,9
@@
void invalidate_block(u_int block)
// Don't trap writes
invalid_code[block]=1;
// Don't trap writes
invalid_code[block]=1;
+#ifdef PCSX
+ invalid_code[((u_int)0x80000000>>12)|page]=1;
+#endif
#ifndef DISABLE_TLB
// If there is a valid TLB entry for this page, remove write protect
if(tlb_LUT_w[block]) {
#ifndef DISABLE_TLB
// If there is a valid TLB entry for this page, remove write protect
if(tlb_LUT_w[block]) {
@@
-2780,8
+2787,10
@@
void load_assemble(int i,struct regstat *i_regs)
if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
- if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+ if (c) {
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+ if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+ }
}
//printf("load_assemble: c=%d\n",c);
//if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
}
//printf("load_assemble: c=%d\n",c);
//if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
@@
-3081,8
+3090,10
@@
void store_assemble(int i,struct regstat *i_regs)
offset=imm[i];
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
offset=imm[i];
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
- if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+ if(c) {
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+ if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+ }
}
assert(tl>=0);
assert(temp>=0);
}
assert(tl>=0);
assert(temp>=0);
@@
-3129,38
+3140,36
@@
void store_assemble(int i,struct regstat *i_regs)
if (opcode[i]==0x28) { // SB
if(!c||memtarget) {
if (opcode[i]==0x28) { // SB
if(!c||memtarget) {
- int x=0;
+ int x=0
,a=temp
;
#ifdef BIG_ENDIAN_MIPS
if(!c) emit_xorimm(addr,3,temp);
else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
#else
#ifdef BIG_ENDIAN_MIPS
if(!c) emit_xorimm(addr,3,temp);
else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
#else
- if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
- else if (addr!=temp) emit_mov(addr,temp);
+ if(!c) a=addr;
#endif
//gen_tlb_addr_w(temp,map);
//emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
#endif
//gen_tlb_addr_w(temp,map);
//emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
- emit_writebyte_indexed_tlb(tl,x,
temp,map,temp
);
+ emit_writebyte_indexed_tlb(tl,x,
a,map,a
);
}
type=STOREB_STUB;
}
if (opcode[i]==0x29) { // SH
if(!c||memtarget) {
}
type=STOREB_STUB;
}
if (opcode[i]==0x29) { // SH
if(!c||memtarget) {
- int x=0;
+ int x=0
,a=temp
;
#ifdef BIG_ENDIAN_MIPS
if(!c) emit_xorimm(addr,2,temp);
else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
#else
#ifdef BIG_ENDIAN_MIPS
if(!c) emit_xorimm(addr,2,temp);
else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
#else
- if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
- else if (addr!=temp) emit_mov(addr,temp);
+ if(!c) a=addr;
#endif
//#ifdef
//emit_writehword_indexed_tlb(tl,x,temp,map,temp);
//#else
if(map>=0) {
#endif
//#ifdef
//emit_writehword_indexed_tlb(tl,x,temp,map,temp);
//#else
if(map>=0) {
- gen_tlb_addr_w(
temp
,map);
- emit_writehword_indexed(tl,x,
temp
);
+ gen_tlb_addr_w(
a
,map);
+ emit_writehword_indexed(tl,x,
a
);
}else
}else
- emit_writehword_indexed(tl,(int)rdram-0x80000000+x,
temp
);
+ emit_writehword_indexed(tl,(int)rdram-0x80000000+x,
a
);
}
type=STOREH_STUB;
}
}
type=STOREH_STUB;
}
@@
-3254,7
+3263,7
@@
void storelr_assemble(int i,struct regstat *i_regs)
int jaddr=0,jaddr2;
int case1,case2,case3;
int done0,done1,done2;
int jaddr=0,jaddr2;
int case1,case2,case3;
int done0,done1,done2;
- int memtarget,c=0;
+ int memtarget
=0
,c=0;
int agr=AGEN1+(i&1);
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rs2[i]|64);
int agr=AGEN1+(i&1);
u_int hr,reglist=0;
th=get_reg(i_regs->regmap,rs2[i]|64);
@@
-3265,8
+3274,10
@@
void storelr_assemble(int i,struct regstat *i_regs)
offset=imm[i];
if(s>=0) {
c=(i_regs->isconst>>s)&1;
offset=imm[i];
if(s>=0) {
c=(i_regs->isconst>>s)&1;
- memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
- if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+ if(c) {
+ memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
+ if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
+ }
}
assert(tl>=0);
for(hr=0;hr<HOST_REGS;hr++) {
}
assert(tl>=0);
for(hr=0;hr<HOST_REGS;hr++) {
@@
-7727,7
+7738,9
@@
void new_dynarec_clear_full()
literalcount=0;
stop_after_jal=0;
// TLB
literalcount=0;
stop_after_jal=0;
// TLB
+#ifndef DISABLE_TLB
using_tlb=0;
using_tlb=0;
+#endif
for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
memory_map[n]=-1;
for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
memory_map[n]=-1;
for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
@@
-11022,6
+11035,12
@@
int new_recompile_block(int addr)
}
#endif
}
}
#endif
}
+#ifdef PCSX
+ // PCSX maps all RAM mirror invalid_code tests to 0x80000000..0x80000000+RAM_SIZE
+ if(get_page(start)<(RAM_SIZE>>12))
+ for(i=start>>12;i<=(start+slen*4)>>12;i++)
+ invalid_code[((u_int)0x80000000>>12)|i]=0;
+#endif
/* Pass 10 - Free memory by expiring oldest blocks */
/* Pass 10 - Free memory by expiring oldest blocks */