+static void vsync_hack_assemble(int i, int ld_ofs, int cc)
+{
+ int sp = get_reg(branch_regs[i].regmap, 29);
+ int ro = get_reg(branch_regs[i].regmap, ROREG);
+ int cycles = CLOCK_ADJUST(9+5) * 16;
+ void *t_exit[3], *loop_target, *t_loop_break;
+ int j;
+ if (sp < 0 || (ram_offset && ro < 0))
+ return;
+ assem_debug("; vsync hack\n");
+ host_tempreg_acquire();
+ emit_cmpimm(cc, -cycles);
+ t_exit[0] = out;
+ emit_jge(0);
+ emit_cmpimm(sp, RAM_SIZE);
+ t_exit[1] = out;
+ emit_jno(0);
+ if (ro >= 0) {
+ emit_addimm(sp, ld_ofs, HOST_TEMPREG);
+ emit_ldr_dualindexed(ro, HOST_TEMPREG, HOST_TEMPREG);
+ }
+ else
+ emit_readword_indexed(ld_ofs, sp, HOST_TEMPREG);
+ emit_cmpimm(HOST_TEMPREG, 17);
+ t_exit[2] = out;
+ emit_jl(0);
+
+ assem_debug("1:\n");
+ loop_target = out;
+ emit_addimm(HOST_TEMPREG, -16, HOST_TEMPREG);
+ emit_addimm(cc, cycles, cc);
+ emit_cmpimm(HOST_TEMPREG, 17);
+ t_loop_break = out;
+ emit_jl(DJT_2);
+ emit_cmpimm(cc, -cycles);
+ emit_jl(loop_target);
+
+ assem_debug("2:\n");
+ set_jump_target(t_loop_break, out);
+ do_store_word(sp, ld_ofs, HOST_TEMPREG, ro, 1);
+
+ for (j = 0; j < ARRAY_SIZE(t_exit); j++)
+ set_jump_target(t_exit[j], out);
+ host_tempreg_release();
+}
+