#include "new_dynarec_config.h"
#include "../psxhle.h"
#include "../psxinterpreter.h"
-#include "emu_if.h" //emulator interface
+#include "../gte.h"
+#include "emu_if.h" // emulator interface
#define noinline __attribute__((noinline,noclone))
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#endif
+#ifndef min
+#define min(a, b) ((b) < (a) ? (b) : (a))
+#endif
//#define DISASM
//#define assem_debug printf
#include "assem_arm64.h"
#endif
+#define RAM_SIZE 0x200000
#define MAXBLOCK 4096
#define MAX_OUTPUT_BLOCK_SIZE 262144
#endif
int new_dynarec_hacks;
+ int new_dynarec_hacks_pergame;
int new_dynarec_did_compile;
+ #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
+
extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
extern int last_count; // last absolute target, often = next_interupt
extern int pcaddr;
void fp_exception();
void fp_exception_ds();
void jump_to_new_pc();
+void call_gteStall();
void new_dyna_leave();
// Needed by assembler
static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
static void load_regs_entry(int t);
static void load_all_consts(signed char regmap[],u_int dirty,int i);
+static u_int get_host_reglist(const signed char *regmap);
static int verify_dirty(const u_int *ptr);
static int get_final_value(int hr, int i, int *value);
static void add_stub(enum stub_type type, void *addr, void *retaddr,
u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
- int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist);
+ int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
static void add_to_linker(void *addr, u_int target, int ext);
static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override);
static void *get_direct_memhandler(void *table, u_int addr,
enum stub_type type, uintptr_t *addr_host);
+static void cop2_call_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
static void pass_args(int a0, int a1);
static void emit_far_jump(const void *f);
static void emit_far_call(const void *f);
return (x * m + s * 50) / 100;
}
+// is the op an unconditional jump?
+static int is_ujump(int i)
+{
+ return itype[i] == UJUMP || itype[i] == RJUMP
+ || (source[i] >> 16) == 0x1000; // beq r0, r0, offset // b offset
+}
+
+static int is_jump(int i)
+{
+ return itype[i] == RJUMP || itype[i] == UJUMP || itype[i] == CJUMP || itype[i] == SJUMP;
+}
+
static u_int get_page(u_int vaddr)
{
u_int page=vaddr&~0xe0000000;
j=slen-i-1;
break;
}
- if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
+ if (is_ujump(i+j))
{
// Don't go past an unconditonal jump
j++;
// TODO: preferred register based on backward branch
}
// Delay slot should preferably not overwrite branch conditions or cycle count
- if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) {
+ if (i > 0 && is_jump(i-1)) {
if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
hsn[CCREG]=1;
int b=-1;
int rn=10;
- if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
+ if (i > 0 && is_ujump(i-1))
{
if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
return 0; // Don't need any registers if exiting the block
j=slen-i-1;
break;
}
- if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
+ if (is_ujump(i+j))
{
// Don't go past an unconditonal jump
j++;
j=slen-i-1;
break;
}
- if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
+ if (is_ujump(i+j))
{
// Don't go past an unconditonal jump
j++;
FUNCNAME(jump_handler_write32),
FUNCNAME(invalidate_addr),
FUNCNAME(jump_to_new_pc),
+ FUNCNAME(call_gteStall),
FUNCNAME(new_dyna_leave),
FUNCNAME(pcsx_mtc0),
FUNCNAME(pcsx_mtc0_ds),
minimum_free_regs[i]=HOST_REGS;
}
-static void cop12_alloc(struct regstat *current,int i)
+static void cop2_alloc(struct regstat *current,int i)
{
- alloc_reg(current,i,CSREG); // Load status
- if(opcode2[i]<3) // MFC1/CFC1
+ if (opcode2[i] < 3) // MFC2/CFC2
{
+ alloc_cc(current,i); // for stalls
+ dirty_reg(current,CCREG);
if(rt1[i]){
clear_const(current,rt1[i]);
alloc_reg(current,i,rt1[i]);
dirty_reg(current,rt1[i]);
}
- alloc_reg_temp(current,i,-1);
}
- else if(opcode2[i]>3) // MTC1/CTC1
+ else if (opcode2[i] > 3) // MTC2/CTC2
{
if(rs1[i]){
clear_const(current,rs1[i]);
current->u&=~1LL;
alloc_reg(current,i,0);
}
- alloc_reg_temp(current,i,-1);
}
+ alloc_reg_temp(current,i,-1);
minimum_free_regs[i]=1;
}
void c2op_alloc(struct regstat *current,int i)
{
+ alloc_cc(current,i); // for stalls
+ dirty_reg(current,CCREG);
alloc_reg_temp(current,i,-1);
}
cop0_alloc(current,i);
break;
case COP1:
+ break;
case COP2:
- cop12_alloc(current,i);
+ cop2_alloc(current,i);
break;
case C1LS:
c1ls_alloc(current,i);
}
static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
- int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist)
+ int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
{
add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
}
}
}
-static void load_assemble(int i,struct regstat *i_regs)
+static u_int get_host_reglist(const signed char *regmap)
+{
+ u_int reglist = 0, hr;
+ for (hr = 0; hr < HOST_REGS; hr++) {
+ if (hr != EXCLUDE_REG && regmap[hr] >= 0)
+ reglist |= 1 << hr;
+ }
+ return reglist;
+}
+
+static u_int reglist_exclude(u_int reglist, int r1, int r2)
+{
+ if (r1 >= 0)
+ reglist &= ~(1u << r1);
+ if (r2 >= 0)
+ reglist &= ~(1u << r2);
+ return reglist;
+}
+
+// find a temp caller-saved register not in reglist (so assumed to be free)
+static int reglist_find_free(u_int reglist)
+{
+ u_int free_regs = ~reglist & CALLER_SAVE_REGS;
+ if (free_regs == 0)
+ return -1;
+ return __builtin_ctz(free_regs);
+}
+
+static void load_assemble(int i, const struct regstat *i_regs)
{
int s,tl,addr;
int offset;
void *jaddr=0;
int memtarget=0,c=0;
int fastio_reg_override=-1;
- u_int hr,reglist=0;
+ u_int reglist=get_host_reglist(i_regs->regmap);
tl=get_reg(i_regs->regmap,rt1[i]);
s=get_reg(i_regs->regmap,rs1[i]);
offset=imm[i];
- for(hr=0;hr<HOST_REGS;hr++) {
- if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
- }
if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
if(s>=0) {
c=(i_regs->wasconst>>s)&1;
}
#ifndef loadlr_assemble
-static void loadlr_assemble(int i,struct regstat *i_regs)
+static void loadlr_assemble(int i, const struct regstat *i_regs)
{
int s,tl,temp,temp2,addr;
int offset;
void *jaddr=0;
int memtarget=0,c=0;
int fastio_reg_override=-1;
- u_int hr,reglist=0;
+ u_int reglist=get_host_reglist(i_regs->regmap);
tl=get_reg(i_regs->regmap,rt1[i]);
s=get_reg(i_regs->regmap,rs1[i]);
temp=get_reg(i_regs->regmap,-1);
addr=get_reg(i_regs->regmap,AGEN1+(i&1));
assert(addr<0);
offset=imm[i];
- for(hr=0;hr<HOST_REGS;hr++) {
- if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
- }
reglist|=1<<temp;
if(offset||s<0||c) addr=temp2;
else addr=s;
}
#endif
-void store_assemble(int i,struct regstat *i_regs)
+void store_assemble(int i, const struct regstat *i_regs)
{
int s,tl;
int addr,temp;
int memtarget=0,c=0;
int agr=AGEN1+(i&1);
int fastio_reg_override=-1;
- u_int hr,reglist=0;
+ u_int reglist=get_host_reglist(i_regs->regmap);
tl=get_reg(i_regs->regmap,rs2[i]);
s=get_reg(i_regs->regmap,rs1[i]);
temp=get_reg(i_regs->regmap,agr);
}
assert(tl>=0);
assert(temp>=0);
- for(hr=0;hr<HOST_REGS;hr++) {
- if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
- }
if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
if(offset||s<0||c) addr=temp;
else addr=s;
add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
jaddr=0;
}
- if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
+ if(!(i_regs->waswritten&(1<<rs1[i])) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
if(!c||memtarget) {
#ifdef DESTRUCTIVE_SHIFT
// The x86 shift operation is 'destructive'; it overwrites the
}
}
-static void storelr_assemble(int i,struct regstat *i_regs)
+static void storelr_assemble(int i, const struct regstat *i_regs)
{
int s,tl;
int temp;
void *done0, *done1, *done2;
int memtarget=0,c=0;
int agr=AGEN1+(i&1);
- u_int hr,reglist=0;
+ u_int reglist=get_host_reglist(i_regs->regmap);
tl=get_reg(i_regs->regmap,rs2[i]);
s=get_reg(i_regs->regmap,rs1[i]);
temp=get_reg(i_regs->regmap,agr);
}
}
assert(tl>=0);
- for(hr=0;hr<HOST_REGS;hr++) {
- if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
- }
assert(temp>=0);
if(!c) {
emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
set_jump_target(done2, out);
if(!c||!memtarget)
add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
- if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
+ if(!(i_regs->waswritten&(1<<rs1[i])) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
emit_addimm_no_flags(-ram_offset,temp);
#if defined(HOST_IMM8)
int ir=get_reg(i_regs->regmap,INVCP);
emit_far_jump(ds?fp_exception_ds:fp_exception);
}
+static int cop2_is_stalling_op(int i, int *cycles)
+{
+ if (opcode[i] == 0x3a) { // SWC2
+ *cycles = 0;
+ return 1;
+ }
+ if (itype[i] == COP2 && (opcode2[i] == 0 || opcode2[i] == 2)) { // MFC2/CFC2
+ *cycles = 0;
+ return 1;
+ }
+ if (itype[i] == C2OP) {
+ *cycles = gte_cycletab[source[i] & 0x3f];
+ return 1;
+ }
+ // ... what about MTC2/CTC2/LWC2?
+ return 0;
+}
+
+#if 0
+static void log_gte_stall(int stall, u_int cycle)
+{
+ if ((u_int)stall <= 44)
+ printf("x stall %2d %u\n", stall, cycle + last_count);
+ if (cycle + last_count > 1215348544) exit(1);
+}
+
+static void emit_log_gte_stall(int i, int stall, u_int reglist)
+{
+ save_regs(reglist);
+ if (stall > 0)
+ emit_movimm(stall, 0);
+ else
+ emit_mov(HOST_TEMPREG, 0);
+ emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1);
+ emit_far_call(log_gte_stall);
+ restore_regs(reglist);
+}
+#endif
+
+static void cop2_call_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
+{
+ int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
+ int rtmp = reglist_find_free(reglist);
+
+ if (HACK_ENABLED(NDHACK_GTE_NO_STALL))
+ return;
+ //assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
+ if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
+ // happens occasionally... cc evicted? Don't bother then
+ //printf("no cc %08x\n", start + i*4);
+ return;
+ }
+ if (!bt[i]) {
+ for (j = i - 1; j >= 0; j--) {
+ //if (is_ds[j]) break;
+ if (cop2_is_stalling_op(j, &other_gte_op_cycles) || bt[j])
+ break;
+ }
+ }
+ cycles_passed = CLOCK_ADJUST(ccadj[i] - ccadj[j]);
+ if (other_gte_op_cycles >= 0)
+ stall = other_gte_op_cycles - cycles_passed;
+ else if (cycles_passed >= 44)
+ stall = 0; // can't stall
+ if (stall == -MAXBLOCK && rtmp >= 0) {
+ // unknown stall, do the expensive runtime check
+ assem_debug("; cop2_call_stall_check\n");
+#if 0 // too slow
+ save_regs(reglist);
+ emit_movimm(gte_cycletab[op], 0);
+ emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1);
+ emit_far_call(call_gteStall);
+ restore_regs(reglist);
+#else
+ host_tempreg_acquire();
+ emit_readword(&psxRegs.gteBusyCycle, rtmp);
+ emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp);
+ emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
+ emit_cmpimm(HOST_TEMPREG, 44);
+ emit_cmovb_reg(rtmp, HOST_CCREG);
+ //emit_log_gte_stall(i, 0, reglist);
+ host_tempreg_release();
+#endif
+ }
+ else if (stall > 0) {
+ //emit_log_gte_stall(i, stall, reglist);
+ emit_addimm(HOST_CCREG, stall, HOST_CCREG);
+ }
+
+ // save gteBusyCycle, if needed
+ if (gte_cycletab[op] == 0)
+ return;
+ other_gte_op_cycles = -1;
+ for (j = i + 1; j < slen; j++) {
+ if (cop2_is_stalling_op(j, &other_gte_op_cycles))
+ break;
+ if (is_jump(j)) {
+ // check ds
+ if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
+ j++;
+ break;
+ }
+ }
+ if (other_gte_op_cycles >= 0)
+ // will handle stall when assembling that op
+ return;
+ cycles_passed = CLOCK_ADJUST(ccadj[min(j, slen -1)] - ccadj[i]);
+ if (cycles_passed >= 44)
+ return;
+ assem_debug("; save gteBusyCycle\n");
+ host_tempreg_acquire();
+#if 0
+ emit_readword(&last_count, HOST_TEMPREG);
+ emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
+ emit_addimm(HOST_TEMPREG, CLOCK_ADJUST(ccadj[i]), HOST_TEMPREG);
+ emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
+ emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
+#else
+ emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + gte_cycletab[op], HOST_TEMPREG);
+ emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
+#endif
+ host_tempreg_release();
+}
+
static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
{
switch (copr) {
}
}
-static void c2ls_assemble(int i,struct regstat *i_regs)
+static void c2ls_assemble(int i, const struct regstat *i_regs)
{
int s,tl;
int ar;
enum stub_type type;
int agr=AGEN1+(i&1);
int fastio_reg_override=-1;
- u_int hr,reglist=0;
+ u_int reglist=get_host_reglist(i_regs->regmap);
u_int copr=(source[i]>>16)&0x1f;
s=get_reg(i_regs->regmap,rs1[i]);
tl=get_reg(i_regs->regmap,FTEMP);
assert(rs1[i]>0);
assert(tl>=0);
- for(hr=0;hr<HOST_REGS;hr++) {
- if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
- }
if(i_regs->regmap[HOST_CCREG]==CCREG)
reglist&=~(1<<HOST_CCREG);
assert(ar>=0);
if (opcode[i]==0x3a) { // SWC2
+ cop2_call_stall_check(0, i, i_regs, reglist_exclude(reglist, tl, -1));
cop2_get_dreg(copr,tl,-1);
type=STOREW_STUB;
}
if(jaddr2)
add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
if(opcode[i]==0x3a) // SWC2
- if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
+ if(!(i_regs->waswritten&(1<<rs1[i])) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
#if defined(HOST_IMM8)
int ir=get_reg(i_regs->regmap,INVCP);
assert(ir>=0);
}
}
-static void cop2_assemble(int i,struct regstat *i_regs)
+static void cop2_assemble(int i, const struct regstat *i_regs)
{
- u_int copr=(source[i]>>11)&0x1f;
- signed char temp=get_reg(i_regs->regmap,-1);
+ u_int copr = (source[i]>>11) & 0x1f;
+ signed char temp = get_reg(i_regs->regmap, -1);
+
+ if (opcode2[i] == 0 || opcode2[i] == 2) { // MFC2/CFC2
+ if (!HACK_ENABLED(NDHACK_GTE_NO_STALL)) {
+ signed char tl = get_reg(i_regs->regmap, rt1[i]);
+ u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), tl, temp);
+ cop2_call_stall_check(0, i, i_regs, reglist);
+ }
+ }
if (opcode2[i]==0) { // MFC2
signed char tl=get_reg(i_regs->regmap,rt1[i]);
if(tl>=0&&rt1[i]!=0)
{
extern void do_insn_cmp();
//extern int cycle;
- u_int hr,reglist=0;
+ u_int hr, reglist = get_host_reglist(regs[i].regmap);
assem_debug("//do_insn_cmp %08x\n", start+i*4);
- for (hr = 0; hr < HOST_REGS; hr++)
- if(regs[i].regmap[hr]>=0) reglist|=1<<hr;
save_regs(reglist);
// write out changed consts to match the interpreter
if (i > 0 && !bt[i]) {
uint64_t u,gte_u,b,gte_b;
uint64_t temp_u,temp_gte_u=0;
uint64_t gte_u_unknown=0;
- if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
+ if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
gte_u_unknown=~0ll;
if(iend==slen-1) {
u=1;
bt[(ba[i]-start)>>2]=1;
if(ba[i]<=start+i*4) {
// Backward branch
- if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
+ if(is_ujump(i))
{
// Unconditional branch
temp_u=1;
gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
}
} /*else*/ if(1) {
- if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
+ if (is_ujump(i))
{
// Unconditional branch
u=unneeded_reg[(ba[i]-start)>>2];
if(ba[i]<start || ba[i]>=(start+slen*4))
{
// Branch out of this block, flush all regs
- if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
+ if (is_ujump(i))
{
// Unconditional branch
will_dirty_i=0;
// Internal branch
if(ba[i]<=start+i*4) {
// Backward branch
- if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
+ if (is_ujump(i))
{
// Unconditional branch
temp_will_dirty=0;
}
/*else*/ if(1)
{
- if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
+ if (is_ujump(i))
{
// Unconditional branch
will_dirty_i=0;
regs[i].dirty&=wont_dirty_i;
if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP)
{
- if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
+ if (i < iend-1 && !is_ujump(i)) {
for(r=0;r<HOST_REGS;r++) {
if(r!=EXCLUDE_REG) {
if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
static u_int *get_source_start(u_int addr, u_int *limit)
{
- if (!(new_dynarec_hacks & NDHACK_OVERRIDE_CYCLE_M))
+ if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
cycle_multiplier_override = 0;
if (addr < 0x00200000 ||
{
// BIOS. The multiplier should be much higher as it's uncached 8bit mem,
// but timings in PCSX are too tied to the interpreter's BIAS
- if (!(new_dynarec_hacks & NDHACK_OVERRIDE_CYCLE_M))
+ if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
cycle_multiplier_override = 200;
*limit = (addr & 0xfff00000) | 0x80000;
else if(type==CJUMP||type==SJUMP)
ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
else ba[i]=-1;
- if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP)) {
+ if (i > 0 && is_jump(i-1)) {
int do_in_intrp=0;
// branch in delay slot?
if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP) {
bt[t+1]=1; // expected return from interpreter
}
else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
- !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
+ !(i>=3&&is_jump(i-3))) {
// v0 overwrite like this is a sign of trouble, bail out
SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
do_in_intrp=1;
}
}
/* Is this the end of the block? */
- if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
+ if (i > 0 && is_ujump(i-1)) {
if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
done=2;
}
cop0_alloc(¤t,i);
break;
case COP1:
+ break;
case COP2:
- cop12_alloc(¤t,i);
+ cop2_alloc(¤t,i);
break;
case C1LS:
c1ls_alloc(¤t,i);
break;
}
- if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
+ if (is_ujump(i-1))
{
if(rt1[i-1]==31) // JAL/JALR
{
#if !defined(DRC_DBG)
else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
{
- // GTE runs in parallel until accessed, divide by 2 for a rough guess
- cc+=gte_cycletab[source[i]&0x3f]/2;
- }
- else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
- {
- cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
+ // this should really be removed since the real stalls have been implemented,
+ // but doing so causes sizeable perf regression against the older version
+ u_int gtec = gte_cycletab[source[i] & 0x3f];
+ cc += HACK_ENABLED(NDHACK_GTE_NO_STALL) ? gtec/2 : 2;
}
else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
{
}
else if(itype[i]==C2LS)
{
- cc+=4;
+ // same as with C2OP
+ cc += HACK_ENABLED(NDHACK_GTE_NO_STALL) ? 4 : 2;
}
#endif
else
}
}
// Conditional branch may need registers for following instructions
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
+ if (!is_ujump(i))
{
if(i<slen-2) {
nr|=needed_reg[i+2];
(regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
(regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
{
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
+ if (!is_ujump(i))
{
if(likely[i]) {
regs[i].regmap[hr]=-1;
{
branch_regs[i].regmap[hr]=-1;
branch_regs[i].regmap_entry[hr]=-1;
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
+ if (!is_ujump(i))
{
if(!likely[i]&&i<slen-2) {
regmap_pre[i+2][hr]=-1;
branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
branch_regs[i].wasconst&=~(1<<hr);
branch_regs[i].isconst&=~(1<<hr);
- if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
+ if (!is_ujump(i)) {
regmap_pre[i+2][hr]=f_regmap[hr];
regs[i+2].wasdirty&=~(1<<hr);
regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
branch_regs[k].dirty&=~(1<<hr);
branch_regs[k].wasconst&=~(1<<hr);
branch_regs[k].isconst&=~(1<<hr);
- if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
+ if (!is_ujump(k)) {
regmap_pre[k+2][hr]=f_regmap[hr];
regs[k+2].wasdirty&=~(1<<hr);
}
//printf("no-match due to different register\n");
break;
}
- if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
+ if (is_ujump(j))
{
// Stop on unconditional branch
break;
} else {
speculate_register_values(i);
#ifndef DESTRUCTIVE_WRITEBACK
- if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
+ if (i < 2 || !is_ujump(i-2))
{
wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
}
}
#endif
// write back
- if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
+ if (i < 2 || !is_ujump(i-2))
{
wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
loop_preload(regmap_pre[i],regs[i].regmap_entry);
case SPAN:
pagespan_assemble(i,®s[i]);break;
}
- if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
+ if (is_ujump(i))
literal_pool(1024);
else
literal_pool_jumpover(256);
}
}
- //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
+ //assert(is_ujump(i-2));
// If the block did not end with an unconditional branch,
// add a jump to the next instruction.
if(i>1) {
- if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
+ if(!is_ujump(i-2)&&itype[i-1]!=SPAN) {
assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP);
assert(i==slen);
if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP) {
notaz.gp2x.de / pcsx_rearmed.git / blobdiff