drc: adjust constants, 32bit is enough

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / patches / trace_intr

diff --git a/libpcsxcore/new_dynarec/patches/trace_intr b/libpcsxcore/new_dynarec/patches/trace_intr
index 57ce9c6..e4f790b 100644 (file)
--- a/libpcsxcore/new_dynarec/patches/trace_intr
+++ b/libpcsxcore/new_dynarec/patches/trace_intr
@@ -1,5 +1,17 @@
+diff --git a/Makefile b/Makefile
+index 0db94f7..e4fe560 100644
+--- a/Makefile
++++ b/Makefile
+@@ -26,6 +26,7 @@ endif
+ else # NO_CONFIG_MAK
+ config.mak:
+ endif
++CFLAGS += -UICACHE_EMULATION
+ 
+ -include Makefile.local
+ 
 diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
-index 2c82f58..8572981 100644
+index 2df259b..2a15e6e 100644
 --- a/libpcsxcore/new_dynarec/emu_if.c
 +++ b/libpcsxcore/new_dynarec/emu_if.c
 @@ -417,13 +417,17 @@ static void ari64_shutdown()
@@ -80,10 +92,10 @@ index dbcb989..0716f5e 100644
  #ifdef PSXHW_LOG
                        PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
 diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
-index 02e00a9..a007dc5 100644
+index 61c60ed..0fa5283 100644
 --- a/libpcsxcore/psxinterpreter.c
 +++ b/libpcsxcore/psxinterpreter.c
-@@ -512,8 +512,9 @@ static void doBranch(u32 tar) {
+@@ -511,8 +511,9 @@ static void doBranch(u32 tar) {
        debugI();
  
        psxRegs.pc += 4;
@@ -94,7 +106,7 @@ index 02e00a9..a007dc5 100644
        // check for load delay
        tmp = psxRegs.code >> 26;
        switch (tmp) {
-@@ -547,13 +548,15 @@ static void doBranch(u32 tar) {
+@@ -546,13 +547,15 @@ static void doBranch(u32 tar) {
                        }
                        break;
        }
@@ -111,7 +123,7 @@ index 02e00a9..a007dc5 100644
  }
  
  /*********************************************************
-@@ -636,12 +639,13 @@ void psxMULTU() {
+@@ -635,12 +638,13 @@ void psxMULTU() {
        psxRegs.GPR.n.hi = (u32)((res >> 32) & 0xffffffff);
  }
  
@@ -127,7 +139,7 @@ index 02e00a9..a007dc5 100644
  
  void psxBGEZ()   { RepZBranchi32(>=) }      // Branch if Rs >= 0
  void psxBGEZAL() { RepZBranchLinki32(>=) }  // Branch if Rs >= 0 and link
-@@ -711,7 +715,7 @@ void psxRFE() {
+@@ -710,7 +714,7 @@ void psxRFE() {
  * Register branch logic                                  *
  * Format:  OP rs, rt, offset                             *
  *********************************************************/
@@ -136,7 +148,7 @@ index 02e00a9..a007dc5 100644
  
  void psxBEQ() {       RepBranchi32(==) }  // Branch if Rs == Rt
  void psxBNE() {       RepBranchi32(!=) }  // Branch if Rs != Rt
-@@ -895,6 +899,9 @@ void MTC0(int reg, u32 val) {
+@@ -894,6 +898,9 @@ void MTC0(int reg, u32 val) {
                case 12: // Status
                        psxRegs.CP0.r[12] = val;
                        psxTestSWInts();
@@ -146,7 +158,7 @@ index 02e00a9..a007dc5 100644
                        break;
  
                case 13: // Cause
-@@ -1057,6 +1064,23 @@ void intExecuteBlock() {
+@@ -1056,6 +1063,23 @@ void intExecuteBlock() {
        while (!branch2) execI();
  }