drc: starting arm64 support

[pcsx_rearmed.git] / libpcsxcore / new_dynarec / pcsxmem.c

diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index 90f7765..bb471b6 100644 (file)
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -22,22 +22,27 @@
 //#define memprintf printf
 #define memprintf(...)
 
-static u32 *mem_readtab;
-static u32 *mem_writetab;
-static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
-static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
-static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
-//static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
-static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
-
-static void map_item(u32 *out, const void *h, u32 flag)
+static uintptr_t *mem_readtab;
+static uintptr_t *mem_writetab;
+static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
+static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
+static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
+//static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
+static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
+
+static
+#ifdef __clang__
+// When this is called in a loop, and 'h' is a function pointer, clang will crash.
+__attribute__ ((noinline))
+#endif
+void map_item(uintptr_t *out, const void *h, uintptr_t flag)
 {
-       u32 hv = (u32)h;
+       uintptr_t hv = (uintptr_t)h;
        if (hv & 1) {
                SysPrintf("FATAL: %p has LSB set\n", h);
                abort();
        }
-       *out = (hv >> 1) | (flag << 31);
+       *out = (hv >> 1) | (flag << (sizeof(hv) * 8 - 1));
 }
 
 // size must be power of 2, at least 4k
@@ -85,7 +90,7 @@ static void io_write_sio32(u32 value)
        sioWrite8((unsigned char)(value >> 24));
 }
 
-#ifndef DRC_DBG
+#if !defined(DRC_DBG) && defined(__arm__)
 
 static void map_rcnt_rcount0(u32 mode)
 {
@@ -147,9 +152,9 @@ make_rcnt_funcs(2)
 
 static void io_write_ireg16(u32 value)
 {
-       if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
+       //if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
        if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
-       psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
+       psxHu16ref(0x1070) &= value;
 }
 
 static void io_write_imask16(u32 value)
@@ -161,9 +166,9 @@ static void io_write_imask16(u32 value)
 
 static void io_write_ireg32(u32 value)
 {
-       if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
+       //if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
        if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
-       psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
+       psxHu32ref(0x1070) &= value;
 }
 
 static void io_write_imask32(u32 value)
@@ -205,7 +210,7 @@ make_dma_func(6)
 static void io_spu_write16(u32 value)
 {
        // meh
-       SPU_writeRegister(address, value);
+       SPU_writeRegister(address, value, psxRegs.cycle);
 }
 
 static void io_spu_write32(u32 value)
@@ -213,8 +218,8 @@ static void io_spu_write32(u32 value)
        SPUwriteRegister wfunc = SPU_writeRegister;
        u32 a = address;
 
-       wfunc(a, value & 0xffff);
-       wfunc(a + 2, value >> 16);
+       wfunc(a, value & 0xffff, psxRegs.cycle);
+       wfunc(a + 2, value >> 16, psxRegs.cycle);
 }
 
 static u32 io_gpu_read_status(void)
@@ -287,7 +292,7 @@ void new_dyna_pcsx_mem_load_state(void)
        map_rcnt_rcount2(rcnts[2].mode);
 }
 
-int pcsxmem_is_handler_dynamic(u_int addr)
+int pcsxmem_is_handler_dynamic(unsigned int addr)
 {
        if ((addr & 0xfffff000) != 0x1f801000)
                return 0;
@@ -301,7 +306,7 @@ void new_dyna_pcsx_mem_init(void)
        int i;
 
        // have to map these further to keep tcache close to .text
-       mem_readtab = psxMap(0x08000000, 0x200000 * 4, 0, MAP_TAG_LUTS);
+       mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
        if (mem_readtab == NULL) {
                SysPrintf("failed to map mem tables\n");
                exit(1);
@@ -338,11 +343,17 @@ void new_dyna_pcsx_mem_init(void)
 
        // scratchpad
        map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
+       map_l1_mem(mem_readtab, 0, 0x9f800000, 0x1000, psxH);
        map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
+       map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
 
        // I/O
        map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
+       map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1);
+       map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1);
        map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
+       map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1);
+       map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1);
 
        // L2
        // unmapped tables
@@ -475,3 +486,9 @@ void new_dyna_pcsx_mem_reset(void)
 
        map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
 }
+
+void new_dyna_pcsx_mem_shutdown(void)
+{
+       psxUnmap(mem_readtab, 0x200000 * 4, MAP_TAG_LUTS);
+       mem_writetab = mem_readtab = NULL;
+}