#include "psxhle.h"
#include "psxinterpreter.h"
#include "psxevents.h"
+#include "cdrom.h"
+#include <stdarg.h>
#include <zlib.h>
#ifndef PSXBIOS_LOG
//#define PSXBIOS_LOG printf
#define PSXBIOS_LOG(...)
#endif
+#ifndef PSXBIOS_EV_LOG
+//#define PSXBIOS_EV_LOG printf
+#define PSXBIOS_EV_LOG(...)
+#endif
#define PTR_1 (void *)(size_t)1
"dev_card_close", "dev_card_firstfile", "dev_card_nextfile","dev_card_erase",
"dev_card_undelete","dev_card_format", "dev_card_rename", "dev_card_6f",
// 0x70
- "_bu_init", "_96_init", "CdRemove", "sys_a0_73",
+ "_bu_init", "CdInit", "CdRemove", "sys_a0_73",
"sys_a0_74", "sys_a0_75", "sys_a0_76", "sys_a0_77",
"_96_CdSeekL", "sys_a0_79", "sys_a0_7a", "sys_a0_7b",
"_96_CdGetStatus", "sys_a0_7d", "_96_CdRead", "sys_a0_7f",
"sys_a0_8c", "sys_a0_8d", "sys_a0_8e", "sys_a0_8f",
// 0x90
"sys_a0_90", "sys_a0_91", "sys_a0_92", "sys_a0_93",
- "sys_a0_94", "sys_a0_95", "AddCDROMDevice", "AddMemCardDevide",
+ "sys_a0_94", "CdReset", "AddCDROMDevice", "AddMemCardDevide",
"DisableKernelIORedirection", "EnableKernelIORedirection", "sys_a0_9a", "sys_a0_9b",
"SetConf", "GetConf", "sys_a0_9e", "SetMem",
// 0xa0
"SysMalloc", "sys_b0_01", "sys_b0_02", "sys_b0_03",
"sys_b0_04", "sys_b0_05", "sys_b0_06", "DeliverEvent",
"OpenEvent", "CloseEvent", "WaitEvent", "TestEvent",
- "EnableEvent", "DisableEvent", "OpenTh", "CloseTh",
+ "EnableEvent", "DisableEvent", "OpenTh", "CloseTh",
// 0x10
- "ChangeTh", "sys_b0_11", "InitPAD", "StartPAD",
- "StopPAD", "PAD_init", "PAD_dr", "ReturnFromExecption",
+ "ChangeTh", "sys_b0_11", "InitPAD", "StartPAD",
+ "StopPAD", "PAD_init", "PAD_dr", "ReturnFromException",
"ResetEntryInt", "HookEntryInt", "sys_b0_1a", "sys_b0_1b",
"sys_b0_1c", "sys_b0_1d", "sys_b0_1e", "sys_b0_1f",
// 0x20
static int nfile;
static char cdir[8*8+8];
static u32 floodchk;
+static int card_io_delay;
// fixed RAM offsets, SCPH1001 compatible
#define A_TT_ExCB 0x0100
#define A_EXCEPTION 0x0c80
#define A_EXC_SP 0x6cf0
#define A_EEXIT_DEF 0x6cf4
+#define A_CARD_ISLOT 0x7264 // 0 or 1, toggled by card vint handler
#define A_KMALLOC_PTR 0x7460
#define A_KMALLOC_SIZE 0x7464
#define A_KMALLOC_END 0x7468
#define A_PAD_IN_LEN 0x74d8
#define A_PAD_OUT_LEN 0x74e0
#define A_PAD_DR_DST 0x74c4
-#define A_CARD_CHAN1 0x7500
+#define A_CARD_ACHAN 0x7500 // currently active port in 0xPortSlot format
+#define A_CARD_HANDLER 0x7528 // ptr to irq handler
+#define A_CARD_STATUS1 0x7568
+#define A_CARD_STATUS2 0x7569
#define A_PAD_DR_BUF1 0x7570
#define A_PAD_DR_BUF2 0x7598
#define A_EEXIT_PTR 0x75d0
#define A_C0_TRAPS 0x3010
#define A_B0_5B_TRAP 0x43d0
+#define CARD_HARDLER_WRITE 0x51F4
+#define CARD_HARDLER_WRITEM 0x51F5 // fake, for psxBios_write()
+#define CARD_HARDLER_READ 0x5688
+#define CARD_HARDLER_READM 0x5689 // fake, for psxBios_read()
+#define CARD_HARDLER_INFO 0x5B64
+
#define HLEOP(n) SWAPu32((0x3b << 26) | (n));
static u8 loadRam8(u32 addr)
ra = sra;
}
-static u32 OpenEvent(u32 class, u32 spec, u32 mode, u32 func);
-static u32 DeliverEvent(u32 class, u32 spec);
-static u32 UnDeliverEvent(u32 class, u32 spec);
+static u32 OpenEvent(u32 class, u32 spec, u32 mode, u32 func);
+static void EnableEvent(u32 ev, int do_log);
+static u32 DeliverEvent(u32 class, u32 spec);
+static u32 UnDeliverEvent(u32 class, u32 spec);
static void CloseEvent(u32 ev);
+static int card_buf_io(int is_write, int port, void *buf, u32 size)
+{
+ char *mcdptr = port ? Mcd2Data : Mcd1Data;
+ FileDesc *desc = &FDesc[2 + port];
+ u32 offset = 8192 * desc->mcfile + desc->offset;
+
+ PSXBIOS_LOG("card_%s_buf %d,%d: ofs=%x(%x) sz=%x (%s)\n",
+ is_write ? "write" : "read", port, desc->mcfile,
+ desc->offset, offset, size, mcdptr + 128 * desc->mcfile + 0xa);
+ if (!(loadRam8(A_CARD_STATUS1 + port) & 1)) {
+ PSXBIOS_LOG(" ...busy %x\n", loadRam8(A_CARD_STATUS1 + port));
+ return -1;
+ }
+ UnDeliverEvent(0xf4000001, 0x0004);
+ UnDeliverEvent(0xf4000001, 0x8000);
+ UnDeliverEvent(0xf4000001, 0x2000);
+ UnDeliverEvent(0xf4000001, 0x0100);
+
+ if (offset >= 128*1024u) {
+ log_unhandled("card offs %x(%x)\n", desc->offset, offset);
+ DeliverEvent(0xf4000001, 0x8000); // ?
+ return -1;
+ }
+ if (offset + size >= 128*1024u) {
+ log_unhandled("card offs+size %x+%x\n", offset, size);
+ size = 128*1024 - offset;
+ }
+ if (is_write) {
+ memcpy(mcdptr + offset, buf, size);
+ if (port == 0)
+ SaveMcd(Config.Mcd1, Mcd1Data, offset, size);
+ else
+ SaveMcd(Config.Mcd2, Mcd2Data, offset, size);
+ }
+ else {
+ size_t ram_offset = (s8 *)buf - psxM;
+ memcpy(buf, mcdptr + offset, size);
+ if (ram_offset < 0x200000)
+ psxCpu->Clear(ram_offset, (size + 3) / 4);
+ }
+ desc->offset += size;
+ if (desc->mode & 0x8000) { // async
+ storeRam8(A_CARD_STATUS1 + port, is_write ? 4 : 2); // busy
+ storeRam32(A_CARD_HANDLER,
+ is_write ? CARD_HARDLER_WRITEM : CARD_HARDLER_READM);
+ card_io_delay = 2 + size / 1024; // hack
+ return 0;
+ }
+ return size;
+}
+
/* *
// *
// *
// System calls A0 */
-
-#define buread(Ra1, mcd, length) { \
- PSXBIOS_LOG("read %d: %x,%x (%s)\n", FDesc[1 + mcd].mcfile, FDesc[1 + mcd].offset, a2, Mcd##mcd##Data + 128 * FDesc[1 + mcd].mcfile + 0xa); \
- ptr = Mcd##mcd##Data + 8192 * FDesc[1 + mcd].mcfile + FDesc[1 + mcd].offset; \
- memcpy(Ra1, ptr, length); \
- psxCpu->Clear(a1, (length + 3) / 4); \
- if (FDesc[1 + mcd].mode & 0x8000) { \
- DeliverEvent(0xf0000011, 0x0004); \
- DeliverEvent(0xf4000001, 0x0004); \
- v0 = 0; } \
- else v0 = length; \
- FDesc[1 + mcd].offset += v0; \
-}
-
-#define buwrite(Ra1, mcd, length) { \
- u32 offset = + 8192 * FDesc[1 + mcd].mcfile + FDesc[1 + mcd].offset; \
- PSXBIOS_LOG("write %d: %x,%x\n", FDesc[1 + mcd].mcfile, FDesc[1 + mcd].offset, a2); \
- ptr = Mcd##mcd##Data + offset; \
- memcpy(ptr, Ra1, length); \
- FDesc[1 + mcd].offset += length; \
- SaveMcd(Config.Mcd##mcd, Mcd##mcd##Data, offset, length); \
- if (FDesc[1 + mcd].mode & 0x8000) { \
- DeliverEvent(0xf0000011, 0x0004); \
- DeliverEvent(0xf4000001, 0x0004); \
- v0 = 0; } \
- else v0 = length; \
-}
-
/* Internally redirects to "FileRead(fd,tempbuf,1)".*/
/* For some strange reason, the returned character is sign-expanded; */
/* So if a return value of FFFFFFFFh could mean either character FFh, or error. */
-/* TODO FIX ME : Properly implement this behaviour */
-void psxBios_getc(void) // 0x03, 0x35
+static void psxBios_getc(void) // 0x03, 0x35
{
- char *ptr;
- void *pa1 = Ra1;
-#ifdef PSXBIOS_LOG
- PSXBIOS_LOG("psxBios_%s\n", biosA0n[0x03]);
-#endif
- v0 = -1;
+ s8 buf[1] = { -1 };
+ int ret = -1;
- if (pa1 != INVALID_PTR) {
- switch (a0) {
- case 2: buread(pa1, 1, 1); break;
- case 3: buread(pa1, 2, 1); break;
- }
+ PSXBIOS_LOG("psxBios_%s %d\n", biosA0n[0x03], a0);
+
+ if (a0 == 1)
+ ret = -1;
+ else if (a0 == 2 || a0 == 3) {
+ card_buf_io(0, a0 - 2, buf, 1);
+ ret = buf[0];
}
- pc0 = ra;
+ mips_return_c(ret, 100);
}
/* Copy of psxBios_write, except size is 1. */
-void psxBios_putc(void) // 0x09, 0x3B
+static void psxBios_putc(void) // 0x09, 0x3B
{
- char *ptr;
- void *pa1 = Ra1;
-#ifdef PSXBIOS_LOG
- PSXBIOS_LOG("psxBios_%s\n", biosA0n[0x09]);
-#endif
- v0 = -1;
- if (pa1 == INVALID_PTR) {
- pc0 = ra;
- return;
- }
+ u8 buf[1] = { (u8)a0 };
+ int ret = -1;
- if (a0 == 1) { // stdout
- char *ptr = (char *)pa1;
+ if (a1 != 1) // not stdout
+ PSXBIOS_LOG("psxBios_%s '%c' %d\n", biosA0n[0x09], (char)a0, a1);
- v0 = a2;
- while (a2 > 0) {
- printf("%c", *ptr++); a2--;
- }
- pc0 = ra; return;
+ if (a1 == 1) { // stdout
+ if (Config.PsxOut) printf("%c", (char)a0);
}
-
- switch (a0) {
- case 2: buwrite(pa1, 1, 1); break;
- case 3: buwrite(pa1, 2, 1); break;
+ else if (a1 == 2 || a1 == 3) {
+ ret = card_buf_io(1, a1 - 2, buf, 1);
}
- pc0 = ra;
+ mips_return_c(ret, 100);
}
static u32 do_todigit(u32 c)
heap_addr = loadRam32(A_HEAP_BASE);
heap_end = loadRam32(A_HEAP_END);
- heap_addr_new = heap_addr + 4 + size;
+ heap_addr_new = heap_addr + size + 4;
if (heap_addr_new >= heap_end)
return -1;
storeRam32(A_HEAP_BASE, heap_addr_new);
break;
}
// chunk too small
+ if (next_chunk_hdr == ~1) {
+ // rm useless last free block
+ storeRam32(A_HEAP_BASE, chunk + 4);
+ storeRam32(chunk, ~1);
+ continue;
+ }
if (next_chunk_hdr & 1) {
// merge
u32 msize = (chunk_hdr & ~3) + 4 + (next_chunk_hdr & ~3);
}
}
- if (i == limit)
+ if (i == limit) {
+ PSXBIOS_LOG("malloc: limit OOM\n");
ret = 0;
- else if (tries == 0 && malloc_heap_grow(size))
+ }
+ else if (tries == 0 && malloc_heap_grow(size)) {
+ PSXBIOS_LOG("malloc: grow OOM s=%d end=%08x/%08x\n",
+ size, loadRam32(A_HEAP_BASE), loadRam32(A_HEAP_END));
ret = 0;
+ }
else {
u32 chunk = loadRam32(A_HEAP_CURCHNK);
storeRam32(chunk, loadRam32(chunk) & ~3);
void psxBios_realloc() { // 0x38
u32 block = a0;
u32 size = a1;
-#ifdef PSXBIOS_LOG
- PSXBIOS_LOG("psxBios_%s\n", biosA0n[0x38]);
-#endif
+
+ PSXBIOS_LOG("psxBios_%s %08x %d\n", biosA0n[0x38], a0, a1);
a0 = block;
/* If "old_buf" is zero, executes malloc(new_size), and returns r2=new_buf (or 0=failed). */
use_cycles(500);
}
+// you likely want to mask irqs before calling these
+static u8 cdrom_sync(int do_ack)
+{
+ u8 r = 0;
+ if (psxRegs.interrupt & (1u << PSXINT_CDR)) {
+ if ((s32)(psxRegs.cycle - event_cycles[PSXINT_CDR]) < 0)
+ psxRegs.cycle = event_cycles[PSXINT_CDR] + 1;
+ irq_test(&psxRegs.CP0);
+ }
+ if (do_ack) {
+ cdrWrite0(1);
+ r = cdrRead3() & 0x1f;
+ cdrWrite3(0x5f); // ack; clear params
+ }
+ return r;
+}
+
+static void cdrom_cmd_and_wait(u8 cmd, int arg_cnt, int resp_cnt, ...)
+{
+ va_list ap;
+
+ cdrom_sync(0);
+ cdrWrite0(0);
+ va_start(ap, resp_cnt);
+ while (arg_cnt-- > 0)
+ cdrWrite2(va_arg(ap, u32));
+ va_end(ap);
+ cdrWrite1(cmd);
+
+ if (resp_cnt > 0) {
+ u8 r = cdrom_sync(1);
+ assert(r == 3); (void)r;
+ cdrRead1();
+ }
+ if (resp_cnt > 1) {
+ u8 r = cdrom_sync(1);
+ assert(r == 2); (void)r;
+ cdrRead1();
+ }
+}
+
/*
* long Load(char *name, struct EXEC *header);
*/
void psxBios_Load() { // 0x42
+ u8 time[3] = { 2, 0, 0x16 };
EXE_HEADER eheader;
char path[256];
char *pa0, *p;
else
snprintf(path, sizeof(path), "%s", (char *)pa0);
- if (LoadCdromFile(path, &eheader) == 0) {
+ if (LoadCdromFile(path, &eheader, time) == 0) {
memcpy(pa1, ((char*)&eheader)+16, sizeof(EXEC));
psxCpu->Clear(a1, sizeof(EXEC) / 4);
FlushCache();
PSXBIOS_LOG(" -> %d\n", v0);
pc0 = ra;
+
+ // set the cdrom to a state of just after exe read
+ psxRegs.CP0.n.SR &= ~0x404;
+ cdrom_sync(1);
+ cdrWrite0(1);
+ cdrWrite2(0x1f); // unmask
+ cdrom_cmd_and_wait(0x0e, 1, 1, 0x80u); // CdlSetmode
+ cdrom_cmd_and_wait(0x02, 3, 1, time[0], time[1], time[2]); // CdlSetloc
+ cdrom_cmd_and_wait(0x15, 0, 2); // CdlSeekL
+ psxHwWrite16(0x1f801070, ~4);
+ MTC0(&psxRegs, 12, psxRegs.CP0.n.SR | 0x404);
}
/*
pc0 = ra;
}
+static void gpu_sync() {
+ // not implemented...
+ // might be problematic to do because of Config.GpuListWalking
+ if (psxRegs.interrupt & (1u << PSXINT_GPUDMA))
+ log_unhandled("gpu_sync with active dma\n");
+ mips_return_c(0, 21);
+}
+
void psxBios_mem2vram() { // 0x47
int size;
gpuSyncPluginSR(); // flush
void psxBios_GPU_cw() { // 0x49
GPU_writeData(a0);
gpuSyncPluginSR();
- v0 = HW_GPU_STATUS;
- pc0 = ra;
+ use_cycles(13);
+ gpu_sync();
}
void psxBios_GPU_cwb() { // 0x4a
psxBios_Exec();
}
-void psxBios__bu_init() { // 70
-#ifdef PSXBIOS_LOG
+static void psxBios__bu_init() { // 70
PSXBIOS_LOG("psxBios_%s\n", biosA0n[0x70]);
-#endif
DeliverEvent(0xf0000011, 0x0004);
DeliverEvent(0xf4000001, 0x0004);
pc0 = ra;
}
-void psxBios__96_init() { // 71
-#ifdef PSXBIOS_LOG
- PSXBIOS_LOG("psxBios_%s\n", biosA0n[0x71]);
-#endif
-
- pc0 = ra;
-}
-
static void write_chain(u32 *d, u32 next, u32 handler1, u32 handler2);
static void psxBios_SysEnqIntRP_(u32 priority, u32 chain_eptr);
static void psxBios_SysDeqIntRP_(u32 priority, u32 chain_rm_eptr);
+static void psxBios_EnqueueCdIntr_(void)
+{
+ u32 *ram32 = (u32 *)psxM;
+
+ // traps should already be installed by write_chain()
+ ram32[0x91d0/4] = 0;
+ ram32[0x91d4/4] = SWAP32(0xbfc0506c);
+ ram32[0x91d8/4] = SWAP32(0xbfc04dec);
+ psxBios_SysEnqIntRP_(0, 0x91d0);
+ ram32[0x91e0/4] = 0;
+ ram32[0x91e4/4] = SWAP32(0xbfc050a4);
+ ram32[0x91e8/4] = SWAP32(0xbfc04fbc);
+ psxBios_SysEnqIntRP_(0, 0x91e0);
+ use_cycles(31);
+}
+
+static void setup_cd_irq_and_events(void)
+{
+ u16 specs[] = { 0x10, 0x20, 0x40, 0x80, 0x8000 };
+ size_t i;
+
+ psxBios_EnqueueCdIntr_();
+
+ for (i = 0; i < sizeof(specs) / sizeof(specs[0]); i++) {
+ u32 h = OpenEvent(0xf0000003, specs[i], EvMdMARK, 0);
+ // no error checks
+ storeRam32(A_CD_EVENTS + i * 4, h);
+ EnableEvent(h, 0);
+ }
+}
+
+static void psxBios_CdReset_() {
+ psxRegs.CP0.n.SR &= ~0x404; // disable interrupts
+
+ cdrom_sync(1);
+ cdrWrite0(1);
+ cdrWrite2(0x1f); // unmask
+ cdrom_cmd_and_wait(0x0a, 0, 2); // CdlReset
+ cdrom_cmd_and_wait(0x0e, 1, 1, 0x80u); // CdlSetmode
+
+ // todo(?): should read something (iso root directory?)
+ // from { 0, 2, 16 } to somewhere and pause
+
+ mips_return(1);
+ psxHwWrite16(0x1f801070, ~4);
+ MTC0(&psxRegs, 12, psxRegs.CP0.n.SR | 0x404);
+ DeliverEvent(0xf0000003, 0x0020);
+}
+
+static void psxBios_CdInit() { // 54, 71
+ PSXBIOS_LOG("psxBios_%s\n", biosA0n[0x71]);
+ setup_cd_irq_and_events();
+
+ psxBios_CdReset_();
+
+ // this function takes pretty much forever
+ mips_return_c(0, 50000*11);
+}
+
static void psxBios_DequeueCdIntr_() {
psxBios_SysDeqIntRP_(0, 0x91d0);
psxBios_SysDeqIntRP_(0, 0x91e0);
use_cycles(16);
}
+static void psxBios_CdReset() { // 95
+ PSXBIOS_LOG("psxBios_%s\n", biosA0n[0x95]);
+ psxBios_CdReset_();
+}
+
+static void psxBios_EnqueueCdIntr() { // a2
+ PSXBIOS_LOG("psxBios_%s\n", biosA0n[0xa2]);
+ psxBios_EnqueueCdIntr_();
+ // return value comes from SysEnqIntRP() insternal call
+}
+
static void psxBios_DequeueCdIntr() { // a3
PSXBIOS_LOG("psxBios_%s\n", biosA0n[0xa3]);
psxBios_DequeueCdIntr_();
pc0 = ra;
}
-static void psxBios__card_info() { // ab
- PSXBIOS_LOG("psxBios_%s: %x\n", biosA0n[0xab], a0);
- u32 ret, port;
- storeRam32(A_CARD_CHAN1, a0);
- port = a0 >> 4;
-
- switch (port) {
- case 0x0:
- case 0x1:
- ret = 0x0004;
- if (McdDisable[port & 1])
- ret = 0x0100;
- break;
- default:
- PSXBIOS_LOG("psxBios_%s: UNKNOWN PORT 0x%x\n", biosA0n[0xab], a0);
- ret = 0x0302;
- break;
- }
-
- if (McdDisable[0] && McdDisable[1])
- ret = 0x0100;
-
- DeliverEvent(0xf0000011, 0x0004);
-// DeliverEvent(0xf4000001, 0x0004);
- DeliverEvent(0xf4000001, ret);
- v0 = 1; pc0 = ra;
-}
-
-void psxBios__card_load() { // ac
-#ifdef PSXBIOS_LOG
- PSXBIOS_LOG("psxBios_%s: %x\n", biosA0n[0xac], a0);
-#endif
-
- storeRam32(A_CARD_CHAN1, a0);
-
-// DeliverEvent(0xf0000011, 0x0004);
- DeliverEvent(0xf4000001, 0x0004);
-
- v0 = 1; pc0 = ra;
-}
-
static void psxBios_GetSystemInfo() { // b4
u32 ret = 0;
//PSXBIOS_LOG("psxBios_%s %x\n", biosA0n[0xb4], a0);
}
static u32 DeliverEvent(u32 class, u32 spec) {
- EvCB *ev = (EvCB *)loadRam32ptr(A_TT_EvCB);
+ EvCB *ev, *ev_first = (EvCB *)loadRam32ptr(A_TT_EvCB);
u32 evcb_len = loadRam32(A_TT_EvCB + 4);
u32 ret = loadRam32(A_TT_EvCB) + evcb_len;
u32 i, lim = evcb_len / 0x1c;
//printf("%s %08x %x\n", __func__, class, spec);
- for (i = 0; i < lim; i++, ev++) {
+ for (i = 0, ev = ev_first; i < lim; i++, ev++) {
use_cycles(8);
if (SWAP32(ev->status) != EvStACTIVE)
continue;
use_cycles(6);
ret = SWAP32(ev->mode);
if (ret == EvMdMARK) {
+ if (ev->status != SWAP32(EvStALREADY))
+ PSXBIOS_EV_LOG("DeliverEvent %08x %x (%08zx) set\n",
+ class, spec, (ev - ev_first) | 0xf1000000u);
ev->status = SWAP32(EvStALREADY);
continue;
}
use_cycles(8);
if (ret == EvMdCALL) {
ret = SWAP32(ev->fhandler);
+ PSXBIOS_EV_LOG("DeliverEvent %08x %x (%08zx) cb %x\n",
+ class, spec, (ev - ev_first) | 0xf1000000u, ret);
if (ret) {
v0 = ret;
softCall(ret);
mips_return_c(ret, 15);
}
-static void psxBios_EnableEvent() { // 0c
+static void EnableEvent(u32 ev, int do_log) {
u32 base = loadRam32(A_TT_EvCB);
- u32 status = loadRam32(base + (a0 & 0xffff) * sizeof(EvCB) + 4);
- PSXBIOS_LOG("psxBios_%s %x (%x)\n", biosB0n[0x0c], a0, status);
+ u32 status = loadRam32(base + (ev & 0xffff) * sizeof(EvCB) + 4);
+ if (do_log)
+ PSXBIOS_LOG("psxBios_%s %x (%x)\n", biosB0n[0x0c], ev, status);
if (status != EvStUNUSED)
- storeRam32(base + (a0 & 0xffff) * sizeof(EvCB) + 4, EvStACTIVE);
+ storeRam32(base + (ev & 0xffff) * sizeof(EvCB) + 4, EvStACTIVE);
+}
+static void psxBios_EnableEvent() { // 0c
+ EnableEvent(a0, 1);
mips_return_c(1, 15);
}
if ((*fptr & 0xF0) != 0x50) continue;
if (strcmp(FDesc[1 + mcd].name, fptr+0xa)) continue;
FDesc[1 + mcd].mcfile = i;
- PSXBIOS_LOG("open %s\n", fptr+0xa);
v0 = 1 + mcd;
+ PSXBIOS_LOG("open %s -> %d\n", fptr+0xa, v0);
break;
}
if (a1 & 0x200 && v0 == -1) { /* FCREAT */
void psxBios_open() { // 0x32
void *pa0 = Ra0;
- PSXBIOS_LOG("psxBios_%s %s %x\n", biosB0n[0x32], Ra0, a1);
+ PSXBIOS_LOG("psxBios_%s %s(%x) %x\n", biosB0n[0x32], Ra0, a0, a1);
v0 = -1;
* int read(int fd , void *buf , int nbytes);
*/
-void psxBios_read() { // 0x34
- char *ptr;
+static void psxBios_read() { // 0x34
void *pa1 = Ra1;
+ int ret = -1;
-#ifdef PSXBIOS_LOG
PSXBIOS_LOG("psxBios_%s: %x, %x, %x\n", biosB0n[0x34], a0, a1, a2);
-#endif
- v0 = -1;
-
- if (pa1 != INVALID_PTR) {
- switch (a0) {
- case 2: buread(pa1, 1, a2); break;
- case 3: buread(pa1, 2, a2); break;
- }
- }
+ if (pa1 == INVALID_PTR)
+ ;
+ else if (a0 == 2 || a0 == 3)
+ ret = card_buf_io(0, a0 - 2, pa1, a2);
- pc0 = ra;
+ mips_return_c(ret, 100);
}
/*
* int write(int fd , void *buf , int nbytes);
*/
-void psxBios_write() { // 0x35/0x03
- char *ptr;
+static void psxBios_write() { // 0x35/0x03
void *pa1 = Ra1;
+ int ret = -1;
- if (a0 != 1) // stdout
+ if (a0 != 1) // not stdout
PSXBIOS_LOG("psxBios_%s: %x,%x,%x\n", biosB0n[0x35], a0, a1, a2);
- v0 = -1;
- if (pa1 == INVALID_PTR) {
- pc0 = ra;
- return;
- }
-
- if (a0 == 1) { // stdout
+ if (pa1 == INVALID_PTR)
+ ;
+ else if (a0 == 1) { // stdout
char *ptr = pa1;
v0 = a2;
}
pc0 = ra; return;
}
+ else if (a0 == 2 || a0 == 3)
+ ret = card_buf_io(1, a0 - 2, pa1, a2);
- switch (a0) {
- case 2: buwrite(pa1, 1, a2); break;
- case 3: buwrite(pa1, 2, a2); break;
- }
-
- pc0 = ra;
+ mips_return_c(ret, 100);
}
static void psxBios_write_psxout() {
}
void psxBios_InitCARD() { // 4a
+ u8 *ram8 = (u8 *)psxM;
u32 *ram32 = (u32 *)psxM;
PSXBIOS_LOG("psxBios_%s: %x\n", biosB0n[0x4a], a0);
write_chain(ram32 + A_PADCRD_CHN_E/4, 0, 0x49bc, 0x4a4c);
+ //card_error = 0;
+ ram8[A_CARD_ISLOT] = 0;
+ ram8[A_CARD_STATUS1] = 1;
+ ram8[A_CARD_STATUS2] = 1;
// (maybe) todo: early_card_irq, etc
ram32[A_PAD_IRQR_ENA/4] = SWAP32(a0);
void *pa2 = Ra2;
int port;
-#ifdef PSXBIOS_LOG
- PSXBIOS_LOG("psxBios_%s: %x,%x,%x\n", biosB0n[0x4e], a0, a1, a2);
-#endif
- /*
- Function also accepts sector 400h (a bug).
- But notaz said we shouldn't allow sector 400h because it can corrupt the emulator.
- */
- if (!(a1 <= 0x3FF))
+ PSXBIOS_LOG("psxBios_%s %02x,%x,%x\n", biosB0n[0x4e], a0, a1, a2);
+ // function also accepts sector 400h (a bug),
+ // but what actually happens then?
+ if (a1 > 0x400)
{
/* Invalid sectors */
v0 = 0; pc0 = ra;
return;
}
- storeRam32(A_CARD_CHAN1, a0);
+ storeRam32(A_CARD_ACHAN, a0);
port = a0 >> 4;
- if (pa2 != INVALID_PTR) {
+ if (pa2 != INVALID_PTR && a1 < 0x400) {
if (port == 0) {
memcpy(Mcd1Data + a1 * 128, pa2, 128);
SaveMcd(Config.Mcd1, Mcd1Data, a1 * 128, 128);
}
}
- DeliverEvent(0xf0000011, 0x0004);
-// DeliverEvent(0xf4000001, 0x0004);
+ storeRam8(A_CARD_STATUS1 + port, 4); // busy/write
+ storeRam32(A_CARD_HANDLER, CARD_HARDLER_WRITE);
v0 = 1; pc0 = ra;
}
-void psxBios__card_read() { // 0x4f
+static void psxBios__card_read() { // 0x4f
void *pa2 = Ra2;
int port;
-#ifdef PSXBIOS_LOG
- PSXBIOS_LOG("psxBios_%s\n", biosB0n[0x4f]);
-#endif
- /*
- Function also accepts sector 400h (a bug).
- But notaz said we shouldn't allow sector 400h because it can corrupt the emulator.
- */
- if (!(a1 <= 0x3FF))
+ PSXBIOS_LOG("psxBios_%s %x,%x,%x\n", biosB0n[0x4f], a0, a1, a2);
+ if (a1 > 0x400)
{
/* Invalid sectors */
v0 = 0; pc0 = ra;
return;
}
- storeRam32(A_CARD_CHAN1, a0);
+ storeRam32(A_CARD_ACHAN, a0);
port = a0 >> 4;
- if (pa2 != INVALID_PTR) {
+ if (pa2 != INVALID_PTR && a1 < 0x400) {
if (port == 0) {
memcpy(pa2, Mcd1Data + a1 * 128, 128);
} else {
}
}
- DeliverEvent(0xf0000011, 0x0004);
-// DeliverEvent(0xf4000001, 0x0004);
+ storeRam8(A_CARD_STATUS1 + port, 2); // busy/read
+ storeRam32(A_CARD_HANDLER, CARD_HARDLER_READ);
v0 = 1; pc0 = ra;
}
}
static void psxBios__card_chan() { // 0x58
- u32 ret;
- PSXBIOS_LOG("psxBios_%s\n", biosB0n[0x58]);
-
- // todo: should return active slot chan
+ // todo: should return active slot channel
// (active - which was last processed by irq code)
- ret = loadRam32(A_CARD_CHAN1);
+ u32 ret = loadRam32(A_CARD_ACHAN);
+ PSXBIOS_LOG("psxBios_%s -> %02x\n", biosB0n[0x58], ret);
+
mips_return_c(ret, 8);
}
}
static void psxBios__card_status() { // 5c
- PSXBIOS_LOG("psxBios_%s %x\n", biosB0n[0x5c], a0);
+ u8 s = loadRam8(A_CARD_STATUS1 + a0);
+ PSXBIOS_LOG("psxBios_%s %x -> %x\n", biosB0n[0x5c], a0, s);
- v0 = 1; // ready
- pc0 = ra;
+ mips_return_c(s, 5);
}
static void psxBios__card_wait() { // 5d
- PSXBIOS_LOG("psxBios_%s %x\n", biosB0n[0x5d], a0);
+ u8 s = loadRam8(A_CARD_STATUS1 + a0);
+ PSXBIOS_LOG("psxBios_%s %x -> %x\n", biosB0n[0x5d], a0, s);
- v0 = 1; // ready
- pc0 = ra;
+ // todo
+ if (!(s & 1))
+ log_unhandled("%s %x\n", __func__, s);
+
+ mips_return_c(s, 11);
+}
+
+static void psxBios__card_info() { // A ab
+ PSXBIOS_LOG("psxBios_%s %02x\n", biosA0n[0xab], a0);
+ u32 ret, port;
+ storeRam32(A_CARD_ACHAN, a0);
+ port = a0 >> 4;
+
+ switch (port) {
+ case 0x0:
+ case 0x1:
+ ret = 0x0004;
+ if (McdDisable[port & 1])
+ ret = 0x0100;
+ break;
+ default:
+ PSXBIOS_LOG("psxBios_%s: UNKNOWN PORT 0x%x\n", biosA0n[0xab], a0);
+ ret = 0x0302;
+ break;
+ }
+
+ if (McdDisable[0] && McdDisable[1])
+ ret = 0x0100;
+
+ if (ret == 4) {
+ // deliver from card_vint_handler()
+ storeRam8(A_CARD_STATUS1 + port, 8); // busy/info
+ storeRam32(A_CARD_HANDLER, CARD_HARDLER_INFO);
+ } else {
+ DeliverEvent(0xf4000001, ret);
+ DeliverEvent(0xf0000011, 0x0004); // ?
+ }
+ mips_return(1);
+}
+
+static void psxBios__card_load() { // A ac
+ PSXBIOS_LOG("psxBios_%s %02x\n", biosA0n[0xac], a0);
+
+ storeRam32(A_CARD_ACHAN, a0);
+
+// DeliverEvent(0xf0000011, 0x0004);
+ DeliverEvent(0xf4000001, 0x0004);
+
+ mips_return(1);
+}
+
+static void card_vint_handler(void) {
+ u8 select, status;
+ u32 handler;
+
+ if (card_io_delay) {
+ card_io_delay--;
+ return;
+ }
+ UnDeliverEvent(0xf0000011, 0x0004);
+ UnDeliverEvent(0xf0000011, 0x8000);
+ UnDeliverEvent(0xf0000011, 0x0100);
+ UnDeliverEvent(0xf0000011, 0x0200);
+ UnDeliverEvent(0xf0000011, 0x2000);
+
+#if 0
+ select = loadRam8(A_CARD_ISLOT);
+ select = (select ^ 1) & 1;
+ storeRam8(A_CARD_ISLOT, select);
+#else
+ select = loadRam8(A_CARD_ACHAN) >> 4;
+ storeRam8(A_CARD_ISLOT, select);
+#endif
+ status = loadRam8(A_CARD_STATUS1 + select);
+ if (status & 1)
+ return; // done
+
+ //psxBios_SysDeqIntRP_(0, 0x7540);
+ //psxBios_SysDeqIntRP_(0, 0x7540);
+ //card_state_machine = 0;
+ //card_error_flag = 0;
+ handler = loadRam32(A_CARD_HANDLER);
+ switch (handler) {
+ case CARD_HARDLER_INFO:
+ DeliverEvent(0xf4000001, 4);
+ DeliverEvent(0xf0000011, 4);
+ storeRam8(A_CARD_STATUS1 + select, 1);
+ storeRam32(A_CARD_HANDLER, 0);
+ break;
+ case CARD_HARDLER_WRITEM:
+ case CARD_HARDLER_READM:
+ DeliverEvent(0xf4000001, 4);
+ // fallthrough
+ case CARD_HARDLER_WRITE:
+ case CARD_HARDLER_READ:
+ DeliverEvent(0xf0000011, 4);
+ storeRam8(A_CARD_STATUS1 + select, 1);
+ storeRam32(A_CARD_HANDLER, 0);
+ break;
+ case 0:
+ break;
+ default:
+ log_unhandled("%s: unhandled handler %x\n", __func__, handler);
+ DeliverEvent(0xf0000011, 0x8000);
+ storeRam8(A_CARD_STATUS1 + select, 1);
+ storeRam32(A_CARD_HANDLER, 0);
+ }
}
/* System calls C0 */
psxHwWrite16(0x1f801100 + i*0x10 + 8, 0);
psxHwWrite16(0x1f801100 + i*0x10 + 0, 0);
}
- psxBios_SysEnqIntRP_(a0, 0x6d88);
+ for (i = 0; i < 4; i++)
+ psxBios_SysEnqIntRP_(a0, 0x6d58 + i * 0x10);
mips_return_c(0, 9);
}
{ 0x1920, hleop_exc1_3_1 },
{ 0x1794, hleop_exc1_3_2 },
{ 0x2458, hleop_exc3_0_2 },
- { 0x49bc, hleop_exc_padcard1 },
+ { 0x49bc, hleop_exc_padcard1 }, // hleExcPadCard1
{ 0x4a4c, hleop_exc_padcard2 },
};
ram32[0x0150/4] = SWAPu32(0x6ee0); // DCB - device control
ram32[0x0154/4] = SWAPu32(0x0320); // DCB size
- storeRam32(p_excb + 0*4, 0x91e0); // chain0
+ storeRam32(p_excb + 0*4, 0x0000); // chain0
storeRam32(p_excb + 2*4, 0x6d88); // chain1
storeRam32(p_excb + 4*4, 0x0000); // chain2
storeRam32(p_excb + 6*4, 0x6d98); // chain3
for (i = 1; i < tcb_cnt; i++)
storeRam32(p_tcb + sizeof(TCB) * i, 0x1000);
- // default events
- storeRam32(A_CD_EVENTS + 0x00, OpenEvent(0xf0000003, 0x0010, EvMdMARK, 0));
- storeRam32(A_CD_EVENTS + 0x04, OpenEvent(0xf0000003, 0x0020, EvMdMARK, 0));
- storeRam32(A_CD_EVENTS + 0x08, OpenEvent(0xf0000003, 0x0040, EvMdMARK, 0));
- storeRam32(A_CD_EVENTS + 0x0c, OpenEvent(0xf0000003, 0x0080, EvMdMARK, 0));
- storeRam32(A_CD_EVENTS + 0x10, OpenEvent(0xf0000003, 0x8000, EvMdMARK, 0));
+ psxBios_SysEnqIntRP_(0, 0x6da8);
+ setup_cd_irq_and_events();
storeRam32(A_CONF_EvCB, evcb_cnt);
storeRam32(A_CONF_TCB, tcb_cnt);
biosA0[0x51] = psxBios_LoadExec;
//biosA0[0x52] = psxBios_GetSysSp;
//biosA0[0x53] = psxBios_sys_a0_53;
- //biosA0[0x54] = psxBios__96_init_a54;
- //biosA0[0x55] = psxBios__bu_init_a55;
+ biosA0[0x54] = psxBios_CdInit;
+ biosA0[0x55] = psxBios__bu_init;
biosA0[0x56] = psxBios_CdRemove;
//biosA0[0x57] = psxBios_sys_a0_57;
//biosA0[0x58] = psxBios_sys_a0_58;
//biosA0[0x6e] = psxBios_dev_card_rename;
//biosA0[0x6f] = psxBios_dev_card_6f;
biosA0[0x70] = psxBios__bu_init;
- biosA0[0x71] = psxBios__96_init;
+ biosA0[0x71] = psxBios_CdInit;
biosA0[0x72] = psxBios_CdRemove;
//biosA0[0x73] = psxBios_sys_a0_73;
//biosA0[0x74] = psxBios_sys_a0_74;
biosA0[0x92] = hleExc0_1_1;
biosA0[0x93] = hleExc0_0_1;
//biosA0[0x94] = psxBios_sys_a0_94;
- //biosA0[0x95] = psxBios_sys_a0_95;
+ biosA0[0x95] = psxBios_CdReset;
//biosA0[0x96] = psxBios_AddCDROMDevice;
//biosA0[0x97] = psxBios_AddMemCardDevide;
//biosA0[0x98] = psxBios_DisableKernelIORedirection;
biosA0[0x9f] = psxBios_SetMem;
//biosA0[0xa0] = psxBios__boot;
//biosA0[0xa1] = psxBios_SystemError;
- //biosA0[0xa2] = psxBios_EnqueueCdIntr;
+ biosA0[0xa2] = psxBios_EnqueueCdIntr;
biosA0[0xa3] = psxBios_DequeueCdIntr;
//biosA0[0xa4] = psxBios_sys_a0_a4;
//biosA0[0xa5] = psxBios_ReadSector;
//biosB0[0x37] = psxBios_ioctl;
//biosB0[0x38] = psxBios_exit;
//biosB0[0x39] = psxBios_sys_b0_39;
- //biosB0[0x3a] = psxBios_getc;
- //biosB0[0x3b] = psxBios_putc;
+ biosB0[0x3a] = psxBios_getc;
+ biosB0[0x3b] = psxBios_putc;
biosB0[0x3c] = psxBios_getchar;
biosB0[0x3d] = psxBios_putchar;
//biosB0[0x3e] = psxBios_gets;
strcpy((char *)&ram32[0xeff0/4], "bu");
// default exception handler chains
+ // see also setup_cd_irq_and_events()
write_chain(&ram32[0x91e0/4], 0x91d0, 0xbfc050a4, 0xbfc04fbc); // chain0.e0
write_chain(&ram32[0x91d0/4], 0x6da8, 0xbfc0506c, 0xbfc04dec); // chain0.e1
write_chain(&ram32[0x6da8/4], 0, 0, 0x1a00); // chain0.e2
}
if (loadRam32(A_PAD_ACK_VBL))
psxHwWrite16(0x1f801070, ~1);
- if (loadRam32(A_CARD_IRQR_ENA)) {
- // todo, maybe
- }
+ if (loadRam32(A_CARD_IRQR_ENA))
+ card_vint_handler();
mips_return_c(0, 18);
}
bfreezes(ffile);
bfreezel(&nfile);
bfreezes(cdir);
+ bfreezel(&card_io_delay);
}
notaz.gp2x.de / pcsx_rearmed.git / blobdiff