frontend: generic: preliminary SDL support
[pcsx_rearmed.git] / libpcsxcore / psxcounters.c
index 6781c29..8b8fea8 100644 (file)
@@ -22,6 +22,7 @@
  */
 
 #include "psxcounters.h"
+#include "gpu.h"
 #include "debug.h"
 
 /******************************************************************************/
@@ -59,9 +60,9 @@ static const u32 CountToOverflow  = 0;
 static const u32 CountToTarget    = 1;
 
 static const u32 FrameRate[]      = { 60, 50 };
-static const u32 VBlankStart[]    = { 240, 256 };
 static const u32 HSyncTotal[]     = { 263, 313 };
 static const u32 SpuUpdInterval[] = { 32, 32 };
+#define VBlankStart 240
 
 #define VERBOSE_LEVEL 0
 static const s32 VerboseLevel     = VERBOSE_LEVEL;
@@ -70,10 +71,11 @@ static const s32 VerboseLevel     = VERBOSE_LEVEL;
 
 Rcnt rcnts[ CounterQuantity ];
 
-static u32 hSyncCount = 0;
+u32 hSyncCount = 0;
+u32 frame_counter = 0;
 static u32 spuSyncCount = 0;
 static u32 hsync_steps = 0;
-static u32 gpu_wants_hcnt = 0;
+static u32 base_cycle = 0;
 
 u32 psxNextCounter = 0, psxNextsCounter = 0;
 
@@ -176,6 +178,9 @@ void psxRcntSet()
             psxNextCounter = countToUpdate;
         }
     }
+
+    psxRegs.interrupt |= (1 << PSXINT_RCNT);
+    new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
 }
 
 /******************************************************************************/
@@ -185,20 +190,16 @@ void psxRcntReset( u32 index )
 {
     u32 count;
 
+    rcnts[index].mode |= RcUnknown10;
+
     if( rcnts[index].counterState == CountToTarget )
     {
+        count  = psxRegs.cycle;
+        count -= rcnts[index].cycleStart;
+        if( rcnts[index].rate > 1 )
+            count /= rcnts[index].rate;
         if( rcnts[index].mode & RcCountToTarget )
-        {
-            count  = psxRegs.cycle;
-            count -= rcnts[index].cycleStart;
-            if (rcnts[index].rate > 1)
-                count /= rcnts[index].rate;
             count -= rcnts[index].target;
-        }
-        else
-        {
-            count = _psxRcntRcount( index );
-        }
 
         _psxRcntWcount( index, count );
 
@@ -213,8 +214,12 @@ void psxRcntReset( u32 index )
         }
 
         rcnts[index].mode |= RcCountEqTarget;
+
+        if( count < 0xffff ) // special case, overflow too?
+            return;
     }
-    else if( rcnts[index].counterState == CountToOverflow )
+
+    if( rcnts[index].counterState == CountToOverflow )
     {
         count  = psxRegs.cycle;
         count -= rcnts[index].cycleStart;
@@ -236,10 +241,6 @@ void psxRcntReset( u32 index )
 
         rcnts[index].mode |= RcOverflow;
     }
-
-    rcnts[index].mode |= RcUnknown10;
-
-    psxRcntSet();
 }
 
 void psxRcntUpdate()
@@ -287,42 +288,50 @@ void psxRcntUpdate()
         }
         
         // VSync irq.
-        if( hSyncCount == VBlankStart[Config.PsxType] )
+        if( hSyncCount == VBlankStart )
         {
-            GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
-            
-            // For the best times. :D
-            //setIrq( 0x01 );
+            HW_GPU_STATUS &= ~PSXGPU_LCF;
+            GPU_vBlank( 1, 0 );
+            setIrq( 0x01 );
+
+            EmuUpdate();
+            GPU_updateLace();
         }
         
         // Update lace. (with InuYasha fix)
         if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
         {
             hSyncCount = 0;
+            frame_counter++;
 
-            GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
-            setIrq( 0x01 );
-
-            EmuUpdate();
-            GPU_updateLace();
+            gpuSyncPluginSR();
+            if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
+                HW_GPU_STATUS |= frame_counter << 31;
+            GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
         }
 
         // Schedule next call, in hsyncs
         hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
-        next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
+        next_vsync = VBlankStart - hSyncCount; // ok to overflow
         next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
         if( next_vsync && next_vsync < hsync_steps )
             hsync_steps = next_vsync;
         if( next_lace && next_lace < hsync_steps )
             hsync_steps = next_lace;
-        if( gpu_wants_hcnt )
-            hsync_steps = 1;
 
         rcnts[3].cycleStart = cycle - leftover_cycles;
-        rcnts[3].cycle = hsync_steps * rcnts[3].target;
-        psxRcntSet();
+        if (Config.PsxType)
+                // 20.12 precision, clk / 50 / 313 ~= 2164.14
+                base_cycle += hsync_steps * 8864320;
+        else
+                // clk / 60 / 263 ~= 2146.31
+                base_cycle += hsync_steps * 8791293;
+        rcnts[3].cycle = base_cycle >> 12;
+        base_cycle &= 0xfff;
     }
 
+    psxRcntSet();
+
 #ifndef NDEBUG
     DebugVSync();
 #endif
@@ -491,6 +500,8 @@ s32 psxRcntFreeze( gzFile f, s32 Mode )
     if (Mode == 0)
         hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
 
+    base_cycle = 0;
+
     return 0;
 }