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spu: rework synchronization
[pcsx_rearmed.git] / libpcsxcore / psxcounters.c
diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
index 2ea7c63..b25674c 100644 (file)
--- a/libpcsxcore/psxcounters.c
+++ b/libpcsxcore/psxcounters.c
@@ -60,9 +60,9 @@ static const u32 CountToOverflow  = 0;
 static const u32 CountToTarget    = 1;
 
 static const u32 FrameRate[]      = { 60, 50 };
-static const u32 VBlankStart[]    = { 240, 256 };
 static const u32 HSyncTotal[]     = { 263, 313 };
 static const u32 SpuUpdInterval[] = { 32, 32 };
+#define VBlankStart 240
 
 #define VERBOSE_LEVEL 0
 static const s32 VerboseLevel     = VERBOSE_LEVEL;
@@ -128,7 +128,7 @@ void _psxRcntWcount( u32 index, u32 value )
     }
     else
     {
-        rcnts[index].cycle = 0xffff * rcnts[index].rate;
+        rcnts[index].cycle = 0x10000 * rcnts[index].rate;
         rcnts[index].counterState = CountToOverflow;
     }
 }
@@ -143,15 +143,61 @@ u32 _psxRcntRcount( u32 index )
     if (rcnts[index].rate > 1)
         count /= rcnts[index].rate;
 
-    if( count > 0xffff )
+    if( count > 0x10000 )
     {
-        verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
-        count &= 0xffff;
+        verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
     }
+    count &= 0xffff;
 
     return count;
 }
 
+static
+void _psxRcntWmode( u32 index, u32 value )
+{
+    rcnts[index].mode = value;
+
+    switch( index )
+    {
+        case 0:
+            if( value & Rc0PixelClock )
+            {
+                rcnts[index].rate = 5;
+            }
+            else
+            {
+                rcnts[index].rate = 1;
+            }
+        break;
+        case 1:
+            if( value & Rc1HSyncClock )
+            {
+                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
+            }
+            else
+            {
+                rcnts[index].rate = 1;
+            }
+        break;
+        case 2:
+            if( value & Rc2OneEighthClock )
+            {
+                rcnts[index].rate = 8;
+            }
+            else
+            {
+                rcnts[index].rate = 1;
+            }
+
+            // TODO: wcount must work.
+            if( value & Rc2Disable )
+            {
+                rcnts[index].rate = 0xffffffff;
+            }
+        break;
+    }
+}
+
 /******************************************************************************/
 
 static
@@ -188,32 +234,29 @@ void psxRcntSet()
 static
 void psxRcntReset( u32 index )
 {
-    u32 count;
+    u32 rcycles;
 
     rcnts[index].mode |= RcUnknown10;
 
     if( rcnts[index].counterState == CountToTarget )
     {
+        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
         if( rcnts[index].mode & RcCountToTarget )
         {
-            count  = psxRegs.cycle;
-            count -= rcnts[index].cycleStart;
-            if (rcnts[index].rate > 1)
-                count /= rcnts[index].rate;
-            count -= rcnts[index].target;
+            rcycles -= rcnts[index].target * rcnts[index].rate;
+            rcnts[index].cycleStart = psxRegs.cycle - rcycles;
         }
         else
         {
-            count = _psxRcntRcount( index );
+            rcnts[index].cycle = 0x10000 * rcnts[index].rate;
+            rcnts[index].counterState = CountToOverflow;
         }
 
-        _psxRcntWcount( index, count );
-
         if( rcnts[index].mode & RcIrqOnTarget )
         {
             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
             {
-                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
+                verboseLog( 3, "[RCNT %i] irq\n", index );
                 setIrq( rcnts[index].irq );
                 rcnts[index].irqState = 1;
             }
@@ -221,27 +264,28 @@ void psxRcntReset( u32 index )
 
         rcnts[index].mode |= RcCountEqTarget;
 
-        psxRcntSet();
-
-        if( count < 0xffff ) // special case, overflow too?
+        if( rcycles < 0x10000 * rcnts[index].rate )
             return;
     }
 
     if( rcnts[index].counterState == CountToOverflow )
     {
-        count  = psxRegs.cycle;
-        count -= rcnts[index].cycleStart;
-        if (rcnts[index].rate > 1)
-            count /= rcnts[index].rate;
-        count -= 0xffff;
+        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
+        rcycles -= 0x10000 * rcnts[index].rate;
+
+        rcnts[index].cycleStart = psxRegs.cycle - rcycles;
 
-        _psxRcntWcount( index, count );
+        if( rcycles < rcnts[index].target * rcnts[index].rate )
+        {
+            rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
+            rcnts[index].counterState = CountToTarget;
+        }
 
         if( rcnts[index].mode & RcIrqOnOverflow )
         {
             if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
             {
-                verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
+                verboseLog( 3, "[RCNT %i] irq\n", index );
                 setIrq( rcnts[index].irq );
                 rcnts[index].irqState = 1;
             }
@@ -249,8 +293,6 @@ void psxRcntReset( u32 index )
 
         rcnts[index].mode |= RcOverflow;
     }
-
-    psxRcntSet();
 }
 
 void psxRcntUpdate()
@@ -293,16 +335,15 @@ void psxRcntUpdate()
 
             if( SPU_async )
             {
-                SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
+                SPU_async( cycle, 1 );
             }
         }
         
         // VSync irq.
-        if( hSyncCount == VBlankStart[Config.PsxType] )
+        if( hSyncCount == VBlankStart )
         {
-            if( !(HW_GPU_STATUS & PSXGPU_ILACE) )
-                HW_GPU_STATUS |= PSXGPU_LCF;
-
+            HW_GPU_STATUS &= ~PSXGPU_LCF;
+            GPU_vBlank( 1, 0 );
             setIrq( 0x01 );
 
             EmuUpdate();
@@ -315,14 +356,15 @@ void psxRcntUpdate()
             hSyncCount = 0;
             frame_counter++;
 
-            HW_GPU_STATUS &= ~PSXGPU_LCF;
-            if( HW_GPU_STATUS & PSXGPU_ILACE )
+            gpuSyncPluginSR();
+            if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
                 HW_GPU_STATUS |= frame_counter << 31;
+            GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
         }
 
         // Schedule next call, in hsyncs
         hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
-        next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
+        next_vsync = VBlankStart - hSyncCount; // ok to overflow
         next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
         if( next_vsync && next_vsync < hsync_steps )
             hsync_steps = next_vsync;
@@ -338,9 +380,10 @@ void psxRcntUpdate()
                 base_cycle += hsync_steps * 8791293;
         rcnts[3].cycle = base_cycle >> 12;
         base_cycle &= 0xfff;
-        psxRcntSet();
     }
 
+    psxRcntSet();
+
 #ifndef NDEBUG
     DebugVSync();
 #endif
@@ -360,50 +403,10 @@ void psxRcntWmode( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
 
-    rcnts[index].mode = value;
-    rcnts[index].irqState = 0;
-
-    switch( index )
-    {
-        case 0:
-            if( value & Rc0PixelClock )
-            {
-                rcnts[index].rate = 5;
-            }
-            else
-            {
-                rcnts[index].rate = 1;
-            }
-        break;
-        case 1:
-            if( value & Rc1HSyncClock )
-            {
-                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
-            }
-            else
-            {
-                rcnts[index].rate = 1;
-            }
-        break;
-        case 2:
-            if( value & Rc2OneEighthClock )
-            {
-                rcnts[index].rate = 8;
-            }
-            else
-            {
-                rcnts[index].rate = 1;
-            }
-
-            // TODO: wcount must work.
-            if( value & Rc2Disable )
-            {
-                rcnts[index].rate = 0xffffffff;
-            }
-        break;
-    }
-
+    _psxRcntWmode( index, value );
     _psxRcntWcount( index, 0 );
+
+    rcnts[index].irqState = 0;
     psxRcntSet();
 }
 
@@ -498,8 +501,11 @@ void psxRcntInit()
 
 /******************************************************************************/
 
-s32 psxRcntFreeze( gzFile f, s32 Mode )
+s32 psxRcntFreeze( void *f, s32 Mode )
 {
+    u32 count;
+    s32 i;
+
     gzfreeze( &rcnts, sizeof(rcnts) );
     gzfreeze( &hSyncCount, sizeof(hSyncCount) );
     gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
@@ -507,9 +513,19 @@ s32 psxRcntFreeze( gzFile f, s32 Mode )
     gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
 
     if (Mode == 0)
+    {
+        // don't trust things from a savestate
+        for( i = 0; i < CounterQuantity; ++i )
+        {
+            _psxRcntWmode( i, rcnts[i].mode );
+            count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
+            _psxRcntWcount( i, count );
+        }
         hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
+        psxRcntSet();
 
-    base_cycle = 0;
+        base_cycle = 0;
+    }
 
     return 0;
 }
ARM optimized PCSX fork