fix build on some ARM toolchains

[pcsx_rearmed.git] / libpcsxcore / psxinterpreter.c

diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 3736b23..33616e5 100644 (file)
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -25,6 +25,7 @@
 #include "r3000a.h"
 #include "gte.h"
 #include "psxhle.h"
+#include "debug.h"
 
 static int branch = 0;
 static int branch2 = 0;
@@ -59,13 +60,13 @@ static void delayRead(int reg, u32 bpc) {
 
        psxRegs.pc = bpc;
 
-       psxBranchTest();
+       branch = 0;
 
        psxRegs.GPR.r[reg] = rold;
        execI(); // first branch opcode
        psxRegs.GPR.r[reg] = rnew;
 
-       branch = 0;
+       psxBranchTest();
 }
 
 static void delayWrite(int reg, u32 bpc) {
@@ -153,8 +154,12 @@ int psxTestLoadDelay(int reg, u32 tmp) {
 
                case 0x01: // REGIMM
                        switch (_tRt_) {
-                               case 0x00: case 0x02:
-                               case 0x10: case 0x12: // BLTZ/BGEZ...
+                               case 0x00: case 0x01:
+                               case 0x10: case 0x11: // BLTZ/BGEZ...
+                                       // Xenogears - lbu v0 / beq v0
+                                       // - no load delay (fixes battle loading)
+                                       break;
+
                                        if (_tRs_ == reg) return 2;
                                        break;
                        }
@@ -166,10 +171,18 @@ int psxTestLoadDelay(int reg, u32 tmp) {
                        break;
 
                case 0x04: case 0x05: // BEQ/BNE
+                       // Xenogears - lbu v0 / beq v0
+                       // - no load delay (fixes battle loading)
+                       break;
+
                        if (_tRs_ == reg || _tRt_ == reg) return 2;
                        break;
 
                case 0x06: case 0x07: // BLEZ/BGTZ
+                       // Xenogears - lbu v0 / beq v0
+                       // - no load delay (fixes battle loading)
+                       break;
+
                        if (_tRs_ == reg) return 2;
                        break;
 
@@ -492,6 +505,10 @@ void psxDIV() {
                _i32(_rLo_) = _i32(_rRs_) / _i32(_rRt_);
                _i32(_rHi_) = _i32(_rRs_) % _i32(_rRt_);
        }
+       else {
+               _i32(_rLo_) = _i32(_rRs_) >= 0 ? 0xffffffff : 1;
+               _i32(_rHi_) = _i32(_rRs_);
+       }
 }
 
 void psxDIVU() {
@@ -499,6 +516,10 @@ void psxDIVU() {
                _rLo_ = _rRs_ / _rRt_;
                _rHi_ = _rRs_ % _rRt_;
        }
+       else {
+               _i32(_rLo_) = 0xffffffff;
+               _i32(_rHi_) = _i32(_rRs_);
+       }
 }
 
 void psxMULT() {