cdrom: change pause timing again

[pcsx_rearmed.git] / libpcsxcore / psxinterpreter.c

diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index be15f78..3060853 100644 (file)
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -112,7 +112,8 @@ static void intException(psxRegisters *regs, u32 pc, u32 cause)
        if (cause != 0x20) {
                //FILE *f = fopen("/tmp/psx_ram.bin", "wb");
                //fwrite(psxM, 1, 0x200000, f); fclose(f);
-               log_unhandled("exception %08x @%08x\n", cause, pc);
+               log_unhandled("exception %08x @%08x ra=%08x\n",
+                       cause, pc, regs->GPR.n.ra);
        }
        dloadFlush(regs);
        regs->pc = pc;
@@ -127,6 +128,19 @@ static void intExceptionInsn(psxRegisters *regs, u32 cause)
        intException(regs, regs->pc - 4, cause);
 }
 
+static noinline void intExceptionReservedInsn(psxRegisters *regs)
+{
+#ifdef DO_EXCEPTION_RESERVEDI
+       static u32 ppc_ = ~0u;
+       if (regs->pc != ppc_) {
+               SysPrintf("reserved instruction %08x @%08x ra=%08x\n",
+                       regs->code, regs->pc - 4, regs->GPR.n.ra);
+               ppc_ = regs->pc;
+       }
+       intExceptionInsn(regs, R3000E_RI << 2);
+#endif
+}
+
 // 29  Enable for 80000000-ffffffff
 // 30  Enable for 00000000-7fffffff
 // 31  Enable exception
@@ -162,25 +176,21 @@ static int execBreakCheck(psxRegisters *regs, u32 pc)
 // get an opcode without triggering exceptions or affecting cache
 u32 intFakeFetch(u32 pc)
 {
-       u8 *base = psxMemRLUT[pc >> 16];
-       u32 *code;
-       if (unlikely(base == INVALID_PTR))
+       u32 *code = (u32 *)psxm(pc & ~0x3, 0);
+       if (unlikely(code == INVALID_PTR))
                return 0; // nop
-       code = (u32 *)(base + (pc & 0xfffc));
        return SWAP32(*code);
 
 }
 
 static u32 INT_ATTR fetchNoCache(psxRegisters *regs, u8 **memRLUT, u32 pc)
 {
-       u8 *base = memRLUT[pc >> 16];
-       u32 *code;
-       if (unlikely(base == INVALID_PTR)) {
+       u32 *code = (u32 *)psxm_lut(pc & ~0x3, 0, memRLUT);
+       if (unlikely(code == INVALID_PTR)) {
                SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
                intException(regs, pc, R3000E_IBE << 2);
                return 0; // execute as nop
        }
-       code = (u32 *)(base + (pc & 0xfffc));
        return SWAP32(*code);
 }
 
@@ -203,14 +213,12 @@ static u32 INT_ATTR fetchICache(psxRegisters *regs, u8 **memRLUT, u32 pc)
 
                if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag)
                {
-                       const u8 *base = memRLUT[pc >> 16];
-                       const u32 *code;
-                       if (unlikely(base == INVALID_PTR)) {
+                       const u32 *code = (u32 *)psxm_lut(pc & ~0xf, 0, memRLUT);
+                       if (unlikely(code == INVALID_PTR)) {
                                SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
                                intException(regs, pc, R3000E_IBE << 2);
                                return 0; // execute as nop
                        }
-                       code = (u32 *)(base + (pc & 0xfff0));
 
                        entry->tag = pc;
                        // treat as 4 words, although other configurations are said to be possible
@@ -454,14 +462,6 @@ static void doBranchRegE(psxRegisters *regs, u32 tar) {
        doBranch(regs, tar, R3000A_BRANCH_TAKEN);
 }
 
-#if __has_builtin(__builtin_add_overflow) || (defined(__GNUC__) && __GNUC__ >= 5)
-#define add_overflow(a, b, r) __builtin_add_overflow(a, b, &(r))
-#define sub_overflow(a, b, r) __builtin_sub_overflow(a, b, &(r))
-#else
-#define add_overflow(a, b, r) ({r = (u32)a + (u32)b; (a ^ ~b) & (a ^ r) & (1u<<31);})
-#define sub_overflow(a, b, r) ({r = (u32)a - (u32)b; (a ^  b) & (a ^ r) & (1u<<31);})
-#endif
-
 static void addExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) {
        s32 val;
        if (add_overflow(a1, a2, val)) {
@@ -869,12 +869,12 @@ OP(psxLWR) { doLWR(regs_, _Rt_, _oB_); }
 OP(psxLWLe) { if (checkLD(regs_, _oB_ & ~3, 0)) doLWL(regs_, _Rt_, _oB_); }
 OP(psxLWRe) { if (checkLD(regs_, _oB_     , 0)) doLWR(regs_, _Rt_, _oB_); }
 
-OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ &   0xff); }
-OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); }
+OP(psxSB) { psxMemWrite8 (_oB_, _rRt_); }
+OP(psxSH) { psxMemWrite16(_oB_, _rRt_); }
 OP(psxSW) { psxMemWrite32(_oB_, _rRt_); }
 
-OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_ &   0xff); }
-OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_ & 0xffff); }
+OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_); }
+OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_); }
 OP(psxSWe) { if (checkST(regs_, _oB_, 3)) psxMemWrite32(_oB_, _rRt_); }
 
 static void doSWL(psxRegisters *regs, u32 rt, u32 addr) {
@@ -930,10 +930,8 @@ OP(psxSWRe) { if (checkST(regs_, _oB_     , 0)) doSWR(regs_, _Rt_, _oB_); }
 *********************************************************/
 OP(psxMFC0) {
        u32 r = _Rd_;
-#ifdef DO_EXCEPTION_RESERVEDI
        if (unlikely(0x00000417u & (1u << r)))
-               intExceptionInsn(regs_, R3000E_RI << 2);
-#endif
+               intExceptionReservedInsn(regs_);
        doLoad(regs_, _Rt_, regs_->CP0.r[r]);
 }
 
@@ -960,8 +958,14 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
                case 7:
                        if ((regs_->CP0.n.DCIC ^ val) & 0xff800000)
                                log_unhandled("DCIC: %08x->%08x\n", regs_->CP0.n.DCIC, val);
-                       // fallthrough
+                       goto default_;
+               case 3:
+                       if (regs_->CP0.n.BPC != val)
+                               log_unhandled("BPC: %08x->%08x\n", regs_->CP0.n.BPC, val);
+                       goto default_;
+
                default:
+               default_:
                        regs_->CP0.r[reg] = val;
                        break;
        }
@@ -981,9 +985,7 @@ static inline void psxNULLne(psxRegisters *regs) {
 
 OP(psxNULL) {
        psxNULLne(regs_);
-#ifdef DO_EXCEPTION_RESERVEDI
-       intExceptionInsn(regs_, R3000E_RI << 2);
-#endif
+       intExceptionReservedInsn(regs_);
 }
 
 void gteNULL(struct psxCP2Regs *regs) {
@@ -1125,7 +1127,9 @@ OP(psxHLE) {
                psxSWCx(regs_, code);
                return;
        }
+       dloadFlush(regs_);
        psxHLEt[hleCode]();
+       branchSeen = 1;
 }
 
 static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
@@ -1344,12 +1348,15 @@ void intApplyConfig() {
 }
 
 static void intShutdown() {
+       dloadClear(&psxRegs);
 }
 
-// single step (may do several ops in case of a branch)
+// single step (may do several ops in case of a branch or load delay)
+// called by asm/dynarec
 void execI(psxRegisters *regs) {
-       execI_(psxMemRLUT, regs);
-       dloadFlush(regs);
+       do {
+               execIbp(psxMemRLUT, regs);
+       } while (regs->dloadReg[0] || regs->dloadReg[1]);
 }
 
 R3000Acpu psxInt = {