make icache implementation play nice with the dynarec

[pcsx_rearmed.git] / libpcsxcore / r3000a.c

diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index 1e8d0b0..7e6f16b 100644 (file)
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -25,18 +25,22 @@
 #include "cdrom.h"
 #include "mdec.h"
 #include "gte.h"
+#include "psxinterpreter.h"
 
 R3000Acpu *psxCpu = NULL;
+#ifdef DRC_DISABLE
 psxRegisters psxRegs;
+#endif
 
 int psxInit() {
        SysPrintf(_("Running PCSX Version %s (%s).\n"), PACKAGE_VERSION, __DATE__);
 
-#ifdef PSXREC
+#ifndef DRC_DISABLE
        if (Config.Cpu == CPU_INTERPRETER) {
                psxCpu = &psxInt;
        } else psxCpu = &psxRec;
 #else
+       Config.Cpu = CPU_INTERPRETER;
        psxCpu = &psxInt;
 #endif
 
@@ -79,24 +83,25 @@ void psxShutdown() {
 }
 
 void psxException(u32 code, u32 bd) {
-       if (!Config.HLE && (((PSXMu32(psxRegs.pc) >> 24) & 0xfe) == 0x4a)) {
+       psxRegs.code = fetch(psxRegs.pc);
+       
+       if (!Config.HLE && ((((psxRegs.code) >> 24) & 0xfe) == 0x4a)) {
                // "hokuto no ken" / "Crash Bandicot 2" ...
                // BIOS does not allow to return to GTE instructions
                // (just skips it, supposedly because it's scheduled already)
-               // so we step over it with the interpreter
-               extern void execI();
-               execI();
+               // so we execute it here
+               extern void (*psxCP2[64])(void *cp2regs);
+               psxCP2[psxRegs.code & 0x3f](&psxRegs.CP2D);
        }
 
        // Set the Cause
-       psxRegs.CP0.n.Cause = code;
+       psxRegs.CP0.n.Cause = (psxRegs.CP0.n.Cause & 0x300) | code;
 
        // Set the EPC & PC
        if (bd) {
 #ifdef PSXCPU_LOG
                PSXCPU_LOG("bd set!!!\n");
 #endif
-               SysPrintf("bd set!!!\n");
                psxRegs.CP0.n.Cause |= 0x80000000;
                psxRegs.CP0.n.EPC = (psxRegs.pc - 4);
        } else
@@ -185,6 +190,12 @@ void psxBranchTest() {
                                cdrLidSeekInterrupt();
                        }
                }
+               if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
+                       if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
+                               psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
+                               spuUpdate();
+                       }
+               }
        }
 
        if (psxHu32(0x1070) & psxHu32(0x1074)) {