gpu: a bit better idle bit handling

[pcsx_rearmed.git] / libpcsxcore / r3000a.c

diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index 8351c94..8035dfd 100644 (file)
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -26,6 +26,7 @@
 #include "mdec.h"
 #include "gte.h"
 #include "psxinterpreter.h"
+#include "psxbios.h"
 #include "../include/compiler_features.h"
 
 R3000Acpu *psxCpu = NULL;
@@ -53,6 +54,7 @@ int psxInit() {
 }
 
 void psxReset() {
+       boolean introBypassed = FALSE;
        psxMemReset();
 
        memset(&psxRegs, 0, sizeof(psxRegs));
@@ -72,13 +74,15 @@ void psxReset() {
        psxHwReset();
        psxBiosInit();
 
-       BiosLikeGPUSetup(); // a bit of a hack but whatever
-
        if (!Config.HLE) {
                psxExecuteBios();
-               if (psxRegs.pc == 0x80030000 && !Config.SlowBoot)
+               if (psxRegs.pc == 0x80030000 && !Config.SlowBoot) {
                        BiosBootBypass();
+                       introBypassed = TRUE;
+               }
        }
+       if (Config.HLE || introBypassed)
+               psxBiosSetupBootState();
 
 #ifdef EMU_LOG
        EMU_LOG("*BIOS END*\n");
@@ -109,7 +113,7 @@ void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
        }
 
        // Set the Cause
-       cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x300) | cause;
+       cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x700) | cause;
 
        // Set the EPC & PC
        cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;
@@ -188,6 +192,12 @@ void psxBranchTest() {
                                cdrLidSeekInterrupt();
                        }
                }
+               if (psxRegs.interrupt & (1 << PSXINT_IRQ10)) { // irq10 - controller port pin8
+                       if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_IRQ10].sCycle) >= psxRegs.intCycle[PSXINT_IRQ10].cycle) {
+                               psxRegs.interrupt &= ~(1 << PSXINT_IRQ10);
+                               irq10Interrupt();
+                       }
+               }
                if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
                        if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
                                psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
@@ -196,15 +206,13 @@ void psxBranchTest() {
                }
        }
 
-       if (psxHu32(0x1070) & psxHu32(0x1074)) {
-               if ((psxRegs.CP0.n.SR & 0x401) == 0x401) {
-#ifdef PSXCPU_LOG
-                       PSXCPU_LOG("Interrupt: %x %x\n", psxHu32(0x1070), psxHu32(0x1074));
-#endif
-//                     SysPrintf("Interrupt (%x): %x %x\n", psxRegs.cycle, psxHu32(0x1070), psxHu32(0x1074));
-                       psxException(0x400, 0, &psxRegs.CP0);
-               }
-       }
+       psxRegs.CP0.n.Cause &= ~0x400;
+       if (psxHu32(0x1070) & psxHu32(0x1074))
+               psxRegs.CP0.n.Cause |= 0x400;
+       if (((psxRegs.CP0.n.Cause | 1) & psxRegs.CP0.n.SR & 0x401) == 0x401)
+               psxException(0, 0, &psxRegs.CP0);
+       else if (unlikely(psxRegs.pc == psxRegs.biosBranchCheck))
+               psxBiosCheckBranch();
 }
 
 void psxJumpTest() {
@@ -249,3 +257,45 @@ void psxExecuteBios() {
                SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
 }
 
+// irq10 stuff, very preliminary
+static int irq10count;
+
+static void psxScheduleIrq10One(u32 cycles_abs) {
+       // schedule relative to frame start
+       u32 c = cycles_abs - rcnts[3].cycleStart;
+       assert((s32)c >= 0);
+       psxRegs.interrupt |= 1 << PSXINT_IRQ10;
+       psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
+       psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
+       new_dyna_set_event_abs(PSXINT_IRQ10, cycles_abs);
+}
+
+void irq10Interrupt() {
+       u32 prevc = psxRegs.intCycle[PSXINT_IRQ10].sCycle
+               + psxRegs.intCycle[PSXINT_IRQ10].cycle;
+
+       psxHu32ref(0x1070) |= SWAPu32(0x400);
+
+#if 0
+       s32 framec = psxRegs.cycle - rcnts[3].cycleStart;
+       printf("%d:%03d irq10 #%d %3d m=%d,%d\n", frame_counter,
+               (s32)((float)framec / (PSXCLK / 60 / 263.0f)),
+               irq10count, psxRegs.cycle - prevc,
+               (psxRegs.CP0.n.SR & 0x401) != 0x401, !(psxHu32(0x1074) & 0x400));
+#endif
+       if (--irq10count > 0) {
+               u32 cycles_per_line = Config.PsxType
+                       ? PSXCLK / 50 / 314 : PSXCLK / 60 / 263;
+               psxScheduleIrq10One(prevc + cycles_per_line);
+       }
+}
+
+void psxScheduleIrq10(int irq_count, int x_cycles, int y) {
+       //printf("%s %d, %d, %d\n", __func__, irq_count, x_cycles, y);
+       u32 cycles_per_frame = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
+       u32 cycles = rcnts[3].cycleStart + cycles_per_frame;
+       cycles += y * cycles_per_frame / (Config.PsxType ? 314 : 263);
+       cycles += x_cycles;
+       psxScheduleIrq10One(cycles);
+       irq10count = irq_count;
+}