ARM build fixes. (Should fix building on ARM/GCC10) (#210)

[pcsx_rearmed.git] / libpcsxcore / r3000a.c

diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index cccfa60..85b77cb 100644 (file)
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -27,12 +27,14 @@
 #include "gte.h"
 
 R3000Acpu *psxCpu = NULL;
+#ifdef DRC_DISABLE
 psxRegisters psxRegs;
+#endif
 
 int psxInit() {
        SysPrintf(_("Running PCSX Version %s (%s).\n"), PACKAGE_VERSION, __DATE__);
 
-#ifdef PSXREC
+#ifndef DRC_DISABLE
        if (Config.Cpu == CPU_INTERPRETER) {
                psxCpu = &psxInt;
        } else psxCpu = &psxRec;
@@ -89,7 +91,7 @@ void psxException(u32 code, u32 bd) {
        }
 
        // Set the Cause
-       psxRegs.CP0.n.Cause = code;
+       psxRegs.CP0.n.Cause = (psxRegs.CP0.n.Cause & 0x300) | code;
 
        // Set the EPC & PC
        if (bd) {
@@ -185,6 +187,12 @@ void psxBranchTest() {
                                cdrLidSeekInterrupt();
                        }
                }
+               if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
+                       if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
+                               psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
+                               spuUpdate();
+                       }
+               }
        }
 
        if (psxHu32(0x1070) & psxHu32(0x1074)) {