psxinterpreter: use cycle_multiplier also

[pcsx_rearmed.git] / libpcsxcore / r3000a.c

diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index 1e8d0b0..d8268e2 100644 (file)
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -25,18 +25,22 @@
 #include "cdrom.h"
 #include "mdec.h"
 #include "gte.h"
+#include "psxinterpreter.h"
 
 R3000Acpu *psxCpu = NULL;
+#ifdef DRC_DISABLE
 psxRegisters psxRegs;
+#endif
 
 int psxInit() {
        SysPrintf(_("Running PCSX Version %s (%s).\n"), PACKAGE_VERSION, __DATE__);
 
-#ifdef PSXREC
+#ifndef DRC_DISABLE
        if (Config.Cpu == CPU_INTERPRETER) {
                psxCpu = &psxInt;
        } else psxCpu = &psxRec;
 #else
+       Config.Cpu = CPU_INTERPRETER;
        psxCpu = &psxInt;
 #endif
 
@@ -57,6 +61,7 @@ void psxReset() {
        psxRegs.CP0.r[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
        psxRegs.CP0.r[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 
+       psxCpu->ApplyConfig();
        psxCpu->Reset();
 
        psxHwReset();
@@ -79,24 +84,24 @@ void psxShutdown() {
 }
 
 void psxException(u32 code, u32 bd) {
-       if (!Config.HLE && (((PSXMu32(psxRegs.pc) >> 24) & 0xfe) == 0x4a)) {
+       psxRegs.code = PSXMu32(psxRegs.pc);
+       
+       if (!Config.HLE && ((((psxRegs.code) >> 24) & 0xfe) == 0x4a)) {
                // "hokuto no ken" / "Crash Bandicot 2" ...
                // BIOS does not allow to return to GTE instructions
                // (just skips it, supposedly because it's scheduled already)
-               // so we step over it with the interpreter
-               extern void execI();
-               execI();
+               // so we execute it here
+               psxCP2[psxRegs.code & 0x3f](&psxRegs.CP2);
        }
 
        // Set the Cause
-       psxRegs.CP0.n.Cause = code;
+       psxRegs.CP0.n.Cause = (psxRegs.CP0.n.Cause & 0x300) | code;
 
        // Set the EPC & PC
        if (bd) {
 #ifdef PSXCPU_LOG
                PSXCPU_LOG("bd set!!!\n");
 #endif
-               SysPrintf("bd set!!!\n");
                psxRegs.CP0.n.Cause |= 0x80000000;
                psxRegs.CP0.n.EPC = (psxRegs.pc - 4);
        } else
@@ -119,7 +124,7 @@ void psxBranchTest() {
                psxRcntUpdate();
 
        if (psxRegs.interrupt) {
-               if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio
+               if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
                        if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
                                psxRegs.interrupt &= ~(1 << PSXINT_SIO);
                                sioInterrupt();
@@ -134,7 +139,7 @@ void psxBranchTest() {
                if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
                        if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
                                psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
-                               cdrReadInterrupt();
+                               cdrPlayReadInterrupt();
                        }
                }
                if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
@@ -173,18 +178,18 @@ void psxBranchTest() {
                                cdrDmaInterrupt();
                        }
                }
-               if (psxRegs.interrupt & (1 << PSXINT_CDRPLAY)) { // cdr play timing
-                       if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRPLAY].sCycle) >= psxRegs.intCycle[PSXINT_CDRPLAY].cycle) {
-                               psxRegs.interrupt &= ~(1 << PSXINT_CDRPLAY);
-                               cdrPlayInterrupt();
-                       }
-               }
                if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
                        if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
                                psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
                                cdrLidSeekInterrupt();
                        }
                }
+               if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
+                       if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
+                               psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
+                               spuUpdate();
+                       }
+               }
        }
 
        if (psxHu32(0x1070) & psxHu32(0x1074)) {