drc: starting arm64 support

[pcsx_rearmed.git] / libpcsxcore / r3000a.h

diff --git a/libpcsxcore/r3000a.h b/libpcsxcore/r3000a.h
index a2fcca3..4b1ec9e 100644 (file)
--- a/libpcsxcore/r3000a.h
+++ b/libpcsxcore/r3000a.h
@@ -29,21 +29,30 @@ extern "C" {
 #include "psxcounters.h"
 #include "psxbios.h"
 
+#ifdef ICACHE_EMULATION
+enum {
+       R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
+       R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
+       R3000ACPU_NOTIFY_DMA3_EXE_LOAD = 2
+};
+extern uint32_t *Read_ICache(uint32_t pc);
+#endif
+
 typedef struct {
        int  (*Init)();
        void (*Reset)();
        void (*Execute)();              /* executes up to a break */
        void (*ExecuteBlock)(); /* executes up to a jump */
        void (*Clear)(u32 Addr, u32 Size);
+#ifdef ICACHE_EMULATION
+       void (*Notify)(int note, void *data);
+#endif
        void (*Shutdown)();
 } R3000Acpu;
 
 extern R3000Acpu *psxCpu;
 extern R3000Acpu psxInt;
-#if (defined(__x86_64__) || defined(__i386__) || defined(__sh__) || defined(__ppc__) || defined(__arm__)) && !defined(NOPSXREC)
 extern R3000Acpu psxRec;
-#define PSXREC
-#endif
 
 typedef union {
 #if defined(__BIGENDIAN__)
@@ -152,15 +161,33 @@ enum {
        PSXINT_GPUDMA,
        PSXINT_MDECOUTDMA,
        PSXINT_SPUDMA,
+       PSXINT_GPUBUSY,
+       PSXINT_MDECINDMA,
+       PSXINT_GPUOTCDMA,
+       PSXINT_CDRDMA,
        PSXINT_NEWDRC_CHECK,
+       PSXINT_RCNT,
+       PSXINT_CDRLID,
+       PSXINT_CDRPLAY,
+       PSXINT_SPU_UPDATE,
        PSXINT_COUNT
 };
 
+typedef struct psxCP2Regs {
+       psxCP2Data CP2D;        /* Cop2 data registers */
+       psxCP2Ctrl CP2C;        /* Cop2 control registers */
+} psxCP2Regs;
+
 typedef struct {
        psxGPRRegs GPR;         /* General Purpose Registers */
        psxCP0Regs CP0;         /* Coprocessor0 Registers */
-       psxCP2Data CP2D;        /* Cop2 data registers */
-       psxCP2Ctrl CP2C;        /* Cop2 control registers */
+       union {
+               struct {
+                       psxCP2Data CP2D;        /* Cop2 data registers */
+                       psxCP2Ctrl CP2C;        /* Cop2 control registers */
+               };
+               psxCP2Regs CP2;
+       };
     u32 pc;                            /* Program counter */
     u32 code;                  /* The instruction */
        u32 cycle;
@@ -174,6 +201,10 @@ extern psxRegisters psxRegs;
 extern u32 event_cycles[PSXINT_COUNT];
 extern u32 next_interupt;
 
+void new_dyna_before_save(void);
+void new_dyna_after_save(void);
+void new_dyna_freeze(void *f, int mode);
+
 #define new_dyna_set_event(e, c) { \
        s32 c_ = c; \
        u32 abs_ = psxRegs.cycle + c_; \