spu: threaded implementation

[pcsx_rearmed.git] / plugins / dfsound / arm_utils.S

diff --git a/plugins/dfsound/arm_utils.S b/plugins/dfsound/arm_utils.S
index cbcc7f7..1726389 100644 (file)
--- a/plugins/dfsound/arm_utils.S
+++ b/plugins/dfsound/arm_utils.S
@@ -13,9 +13,8 @@
 #ifdef __MACH__
 .data
 .align 2
-ptr_ChanBuf:   .word _ChanBuf
-ptr_SSumLR:    .word _SSumLR
-ptr_sRVBStart: .word _sRVBStart
+ptr_ChanBuf:   .word ESYM(ChanBuf)
+ptr_SSumLR:    .word ESYM(SSumLR)
 #endif
 
 .text
@@ -26,8 +25,8 @@ ptr_sRVBStart: .word _sRVBStart
        movw    \reg, #:lower16:ESYM(\var)
        movt    \reg, #:upper16:ESYM(\var)
 #elif defined(__ARM_ARCH_7A__) && defined(__MACH__)
-       movw    \reg, #:lower16:(ptr_\var-(1678f+4))
-       movt    \reg, #:upper16:(ptr_\var-(1678f+4))
+       movw    \reg, #:lower16:(ptr_\var-(1678f+8))
+       movt    \reg, #:upper16:(ptr_\var-(1678f+8))
 1678:
        ldr     \reg, [pc, \reg]
 #else
@@ -70,14 +69,13 @@ mc_finish:
     bx          lr
 
 
-FUNCTION(mix_chan_rvb): @ (int start, int count, int lv, int rv)
+FUNCTION(mix_chan_rvb): @ (int start, int count, int lv, int rv, int *rvb)
     vmov.32     d14[0], r2
     vmov.32     d14[1], r3             @ multipliers
     mov         r12, r0
     load_varadr r0, ChanBuf
-    load_varadr r3, sRVBStart
+    ldr         r3, [sp]               @ rvb
     load_varadr r2, SSumLR
-    ldr         r3, [r3]
     add         r0, r12, lsl #2
     add         r2, r12, lsl #3
     add         r3, r12, lsl #3
@@ -143,14 +141,13 @@ mc_finish:
     ldmfd       sp!, {r4-r8,pc}
 
 
-FUNCTION(mix_chan_rvb): @ (int start, int count, int lv, int rv)
+FUNCTION(mix_chan_rvb): @ (int start, int count, int lv, int rv, int *rvb)
     stmfd       sp!, {r4-r8,lr}
     orr         lr, r2, r3, lsl #16
     lsl         lr, #1
-    load_varadr r3, sRVBStart
+    ldr         r3, [sp]               @ rvb
     load_varadr r2, SSumLR
     load_varadr r4, ChanBuf
-    ldr         r3, [r3]
     add         r2, r2, r0, lsl #3
     add         r3, r3, r0, lsl #3
     add         r0, r4, r0, lsl #2