struct psx_gpu gpu __attribute__((aligned(2048)));
static noinline int do_cmd_buffer(uint32_t *data, int count);
struct psx_gpu gpu __attribute__((aligned(2048)));
static noinline int do_cmd_buffer(uint32_t *data, int count);
static noinline void do_cmd_reset(void)
{
if (unlikely(gpu.cmd_len > 0))
do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len);
static noinline void do_cmd_reset(void)
{
if (unlikely(gpu.cmd_len > 0))
do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len);
do_vram_line(x, y, sdata, w, is_read);
}
do_vram_line(x, y, sdata, w, is_read);
}
- if (h > 0 && count > 0) {
- y &= 511;
- do_vram_line(x, y, sdata, count, is_read);
- o = count;
- count = 0;
+ if (h > 0) {
+ if (count > 0) {
+ y &= 511;
+ do_vram_line(x, y, sdata, count, is_read);
+ o = count;
+ count = 0;
+ }
memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4);
gpu.state.last_vram_read_frame = *gpu.state.frame_count;
}
memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4);
gpu.state.last_vram_read_frame = *gpu.state.frame_count;
}
log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
}
log_io("start_vram_transfer %c (%d, %d) %dx%d\n", is_read ? 'r' : 'w',
gpu.dma.x, gpu.dma.y, gpu.dma.w, gpu.dma.h);
}
+static void finish_vram_transfer(int is_read)
+{
+ if (is_read)
+ gpu.status.img = 0;
+ else
+ renderer_update_caches(gpu.dma_start.x, gpu.dma_start.y,
+ gpu.dma_start.w, gpu.dma_start.h);
+}
+
static noinline int do_cmd_buffer(uint32_t *data, int count)
{
int len, cmd, start, pos;
static noinline int do_cmd_buffer(uint32_t *data, int count)
{
int len, cmd, start, pos;
memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram));
memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));
memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram));
memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));