case 0x02:
case 0x03:
case 0x04:
- case 0x05:
gpu.gp0 = gpu.ex_regs[data & 7] & 0xfffff;
break;
- case 0x06:
- gpu.gp0 = gpu.ex_regs[5] & 0xfffff;
+ case 0x05:
+ gpu.gp0 = gpu.ex_regs[5] & 0x3fffff;
break;
case 0x07:
gpu.gp0 = 2;
break;
default:
- gpu.gp0 = 0;
+ // gpu.gp0 unchanged
break;
}
}
if (is_read) {
gpu.status |= PSX_GPU_STATUS_IMG;
// XXX: wrong for width 1
- memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4);
+ gpu.gp0 = LE32TOH(*(uint32_t *) VRAM_MEM_XY(gpu.dma.x, gpu.dma.y));
gpu.state.last_vram_read_frame = *gpu.state.frame_count;
}
flush_cmd_buffer();
ret = gpu.gp0;
- if (gpu.dma.h)
+ if (gpu.dma.h) {
+ ret = HTOLE32(ret);
do_vram_io(&ret, 1, 1);
+ ret = LE32TOH(ret);
+ }
log_io("gpu_read %08x\n", ret);
return ret;