clean up cache isolation handling

also ari64 drc now handles unmapped io same as interpreter

diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c
index 33319ba..aac9f78 100644 (file)
--- a/libpcsxcore/new_dynarec/emu_if.c
+++ b/libpcsxcore/new_dynarec/emu_if.c
@@ -370,19 +370,15 @@ static void ari64_clear(u32 addr, u32 size)
 }
 
 static void ari64_notify(int note, void *data) {
-       /*
-       Should be fixed when ARM dynarec has proper icache emulation.
        switch (note)
        {
-               case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
-                       break;
-               case R3000ACPU_NOTIFY_CACHE_ISOLATED:
-               Sent from psxDma3().
-               case R3000ACPU_NOTIFY_DMA3_EXE_LOAD:
-               default:
-                       break;
+       case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
+       case R3000ACPU_NOTIFY_CACHE_ISOLATED:
+               new_dyna_pcsx_mem_isolate(note == R3000ACPU_NOTIFY_CACHE_ISOLATED);
+               break;
+       default:
+               break;
        }
-       */
 }
 
 static void ari64_apply_config()
@@ -430,7 +426,7 @@ int new_dynarec_hacks_old;
 int new_dynarec_hacks;
 void *psxH_ptr;
 void *zeromem_ptr;
-u8 zero_mem[0x1000];
+u32 zero_mem[0x1000/4];
 void *mem_rtab;
 void *scratch_buf_ptr;
 void new_dynarec_init() {}
@@ -442,6 +438,7 @@ void new_dynarec_invalidate_range(unsigned int start, unsigned int end) {}
 void new_dyna_pcsx_mem_init(void) {}
 void new_dyna_pcsx_mem_reset(void) {}
 void new_dyna_pcsx_mem_load_state(void) {}
+void new_dyna_pcsx_mem_isolate(int enable) {}
 void new_dyna_pcsx_mem_shutdown(void) {}
 int  new_dynarec_save_blocks(void *save, int size) { return 0; }
 void new_dynarec_load_blocks(const void *save, int size) {}

diff --git a/libpcsxcore/new_dynarec/linkage_offsets.h b/libpcsxcore/new_dynarec/linkage_offsets.h
index 0c189d7..23935b8 100644 (file)
--- a/libpcsxcore/new_dynarec/linkage_offsets.h
+++ b/libpcsxcore/new_dynarec/linkage_offsets.h
@@ -24,8 +24,10 @@
 #define LO_intCycle            (LO_interrupt + 4)
 #define LO_gteBusyCycle                (LO_intCycle + 256)
 #define LO_muldivBusyCycle     (LO_gteBusyCycle + 4)
-#define LO_psxRegs_reserved    (LO_muldivBusyCycle + 4)
-#define LO_psxRegs_end         (LO_psxRegs_reserved + 4*2)
+#define LO_psxRegs_subCycle    (LO_muldivBusyCycle + 4)
+#define LO_psxRegs_biuReg      (LO_psxRegs_subCycle + 4*2)
+#define LO_psxRegs_reserved    (LO_psxRegs_biuReg + 4)
+#define LO_psxRegs_end         (LO_psxRegs_reserved + 4*3)
 #define LO_rcnts               (LO_psxRegs_end)
 #define LO_rcnts_end           (LO_rcnts + 7*4*4)
 #define LO_inv_code_start      (LO_rcnts_end)

diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index a32b418..8057b7e 100644 (file)
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -26,6 +26,7 @@ static uintptr_t *mem_readtab;
 static uintptr_t *mem_writetab;
 static uintptr_t mem_iortab[(1+2+4) * 0x1000 / 4];
 static uintptr_t mem_iowtab[(1+2+4) * 0x1000 / 4];
+static uintptr_t mem_ffrtab[(1+2+4) * 0x1000 / 4];
 static uintptr_t mem_ffwtab[(1+2+4) * 0x1000 / 4];
 //static uintptr_t mem_unmrtab[(1+2+4) * 0x1000 / 4];
 static uintptr_t mem_unmwtab[(1+2+4) * 0x1000 / 4];
@@ -47,23 +48,28 @@ void map_item(uintptr_t *out, const void *h, uintptr_t flag)
 
 // size must be power of 2, at least 4k
 #define map_l1_mem(tab, i, addr, size, base) \
-       map_item(&tab[((addr)>>12) + i], \
+       map_item(&tab[((u32)(addr) >> 12) + i], \
                 (u8 *)(base) - (u32)((addr) + ((i << 12) & ~(size - 1))), 0)
 
 #define IOMEM32(a) (((a) & 0xfff) / 4)
 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
 #define IOMEM8(a)  (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
 
-u8 zero_mem[0x1000];
+u32 zero_mem[0x1000/4];
+static u32 ffff_mem[0x1000/4];
 
-u32 read_mem_dummy()
+static u32 read_mem_dummy(u32 addr)
 {
-       return 0;
+       // use 'addr' and not 'address', yes the api is weird...
+       memprintf("unmapped r %08x @%08x %u\n", addr, psxRegs.pc, psxRegs.cycle);
+       return 0xffffffff;
 }
 
 static void write_mem_dummy(u32 data)
 {
-       memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
+       if (!(psxRegs.CP0.n.Status & (1 << 16)))
+               memprintf("unmapped w %08x, %08x @%08x %u\n",
+                         address, data, psxRegs.pc, psxRegs.cycle);
 }
 
 /* IO handlers */
@@ -240,46 +246,51 @@ static void io_gpu_write_status(u32 value)
        gpuSyncPluginSR();
 }
 
-static void map_ram_write(void)
+void new_dyna_pcsx_mem_isolate(int enable)
 {
        int i;
 
-       for (i = 0; i < (0x800000 >> 12); i++) {
-               map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
-               map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
-               map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
+       // note: apparently 0xa0000000 uncached access still works,
+       // at least read does for sure, so assume write does too
+       memprintf("mem isolate %d\n", enable);
+       if (enable) {
+               for (i = 0; i < (0x800000 >> 12); i++) {
+                       map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
+                       map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
+                       //map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
+               }
+       }
+       else {
+               for (i = 0; i < (0x800000 >> 12); i++) {
+                       map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
+                       map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
+                       map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
+               }
        }
 }
 
-static void unmap_ram_write(void)
+static u32 read_biu(u32 addr)
 {
-       int i;
-
-       for (i = 0; i < (0x800000 >> 12); i++) {
-               map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
-               map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
-               map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
-       }
+       if (addr != 0xfffe0130)
+               return read_mem_dummy(addr);
+
+ FILE *f = fopen("/tmp/psxbiu.bin", "wb");
+ fwrite(psxM, 1, 0x200000, f);
+ fclose(f);
+       memprintf("read_biu  %08x @%08x %u\n",
+               psxRegs.biuReg, psxRegs.pc, psxRegs.cycle);
+       return psxRegs.biuReg;
 }
 
 static void write_biu(u32 value)
 {
-       memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
-
-       if (address != 0xfffe0130)
+       if (address != 0xfffe0130) {
+               write_mem_dummy(value);
                return;
-
-       switch (value) {
-       case 0x800: case 0x804:
-               unmap_ram_write();
-               break;
-       case 0: case 0x1e988:
-               map_ram_write();
-               break;
-       default:
-               printf("write_biu: unexpected val: %08x\n", value);
-               break;
        }
+
+       memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
+       psxRegs.biuReg = value;
 }
 
 void new_dyna_pcsx_mem_load_state(void)
@@ -302,6 +313,8 @@ void new_dyna_pcsx_mem_init(void)
 {
        int i;
 
+       memset(ffff_mem, 0xff, sizeof(ffff_mem));
+
        // have to map these further to keep tcache close to .text
        mem_readtab = psxMap(0x08000000, 0x200000 * sizeof(mem_readtab[0]), 0, MAP_TAG_LUTS);
        if (mem_readtab == NULL) {
@@ -320,7 +333,7 @@ void new_dyna_pcsx_mem_init(void)
        // default/unmapped memhandlers
        for (i = 0; i < 0x100000; i++) {
                //map_item(&mem_readtab[i], mem_unmrtab, 1);
-               map_l1_mem(mem_readtab, i, 0, 0x1000, zero_mem);
+               map_l1_mem(mem_readtab, i, 0, 0x1000, ffff_mem);
                map_item(&mem_writetab[i], mem_unmwtab, 1);
        }
 
@@ -330,7 +343,7 @@ void new_dyna_pcsx_mem_init(void)
                map_l1_mem(mem_readtab,  i, 0x00000000, 0x200000, psxM);
                map_l1_mem(mem_readtab,  i, 0xa0000000, 0x200000, psxM);
        }
-       map_ram_write();
+       new_dyna_pcsx_mem_isolate(0);
 
        // BIOS and it's mirrors
        for (i = 0; i < (0x80000 >> 12); i++) {
@@ -345,12 +358,12 @@ void new_dyna_pcsx_mem_init(void)
        map_l1_mem(mem_writetab, 0, 0x9f800000, 0x1000, psxH);
 
        // I/O
-       map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
-       map_item(&mem_readtab[0x9f801000 >> 12], mem_iortab, 1);
-       map_item(&mem_readtab[0xbf801000 >> 12], mem_iortab, 1);
-       map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
-       map_item(&mem_writetab[0x9f801000 >> 12], mem_iowtab, 1);
-       map_item(&mem_writetab[0xbf801000 >> 12], mem_iowtab, 1);
+       map_item(&mem_readtab[0x1f801000u >> 12], mem_iortab, 1);
+       map_item(&mem_readtab[0x9f801000u >> 12], mem_iortab, 1);
+       map_item(&mem_readtab[0xbf801000u >> 12], mem_iortab, 1);
+       map_item(&mem_writetab[0x1f801000u >> 12], mem_iowtab, 1);
+       map_item(&mem_writetab[0x9f801000u >> 12], mem_iowtab, 1);
+       map_item(&mem_writetab[0xbf801000u >> 12], mem_iowtab, 1);
 
        // L2
        // unmapped tables
@@ -461,9 +474,12 @@ void new_dyna_pcsx_mem_init(void)
        }
 
        // misc
-       map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
-       for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
+       map_item(&mem_readtab[0xfffe0130u >> 12], mem_ffrtab, 1);
+       map_item(&mem_writetab[0xfffe0130u >> 12], mem_ffwtab, 1);
+       for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
+               map_item(&mem_ffrtab[i], read_biu, 1);
                map_item(&mem_ffwtab[i], write_biu, 1);
+       }
 
        mem_rtab = mem_readtab;
        mem_wtab = mem_writetab;

diff --git a/libpcsxcore/new_dynarec/pcsxmem.h b/libpcsxcore/new_dynarec/pcsxmem.h
index 72892a8..7f8283d 100644 (file)
--- a/libpcsxcore/new_dynarec/pcsxmem.h
+++ b/libpcsxcore/new_dynarec/pcsxmem.h
@@ -1,9 +1,10 @@
 
-extern u8 zero_mem[0x1000];
+extern u32 zero_mem[0x1000/4];
 
 void new_dyna_pcsx_mem_init(void);
 void new_dyna_pcsx_mem_reset(void);
 void new_dyna_pcsx_mem_load_state(void);
+void new_dyna_pcsx_mem_isolate(int enable);
 void new_dyna_pcsx_mem_shutdown(void);
 
 int pcsxmem_is_handler_dynamic(unsigned int addr);

diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 3d08364..9ece259 100644 (file)
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -911,7 +911,9 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
 //     SysPrintf("MTC0 %d: %x\n", reg, val);
        switch (reg) {
                case 12: // Status
-                       regs_->CP0.r[12] = val;
+                       if ((regs_->CP0.n.Status ^ val) & (1 << 16))
+                               psxMemOnIsolate((val >> 16) & 1);
+                       regs_->CP0.n.Status = val;
                        psxTestSWInts(regs_);
                        break;
 
@@ -1114,7 +1116,7 @@ static void intClear(u32 Addr, u32 Size) {
 }
 
 void intNotify (int note, void *data) {
-       /* Gameblabla - Only clear the icache if it's isolated */
+       /* Armored Core won't boot without this */
        if (note == R3000ACPU_NOTIFY_CACHE_ISOLATED)
        {
                memset(&ICache, 0xff, sizeof(ICache));

diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c
index 37a0efd..fb48f77 100644 (file)
--- a/libpcsxcore/psxmem.c
+++ b/libpcsxcore/psxmem.c
@@ -195,8 +195,8 @@ int psxMemInit(void)
                return -1;
        }
 
-       memset(psxMemRLUT, (uintptr_t)INVALID_PTR, 0x10000 * sizeof(void *));
-       memset(psxMemWLUT, (uintptr_t)INVALID_PTR, 0x10000 * sizeof(void *));
+       memset(psxMemRLUT, (int)(uintptr_t)INVALID_PTR, 0x10000 * sizeof(void *));
+       memset(psxMemWLUT, (int)(uintptr_t)INVALID_PTR, 0x10000 * sizeof(void *));
 
 // MemR
        for (i = 0; i < 0x80; i++) psxMemRLUT[i + 0x0000] = (u8 *)&psxM[(i & 0x1f) << 16];
@@ -265,7 +265,22 @@ void psxMemShutdown() {
        free(psxMemWLUT); psxMemWLUT = NULL;
 }
 
-static int writeok = 1;
+void psxMemOnIsolate(int enable)
+{
+       if (enable) {
+               memset(psxMemWLUT + 0x0000, (int)(uintptr_t)INVALID_PTR, 0x80 * sizeof(void *));
+               memset(psxMemWLUT + 0x8000, (int)(uintptr_t)INVALID_PTR, 0x80 * sizeof(void *));
+               //memset(psxMemWLUT + 0xa000, (int)(uintptr_t)INVALID_PTR, 0x80 * sizeof(void *));
+       } else {
+               int i;
+               for (i = 0; i < 0x80; i++)
+                       psxMemWLUT[i + 0x0000] = (void *)&psxM[(i & 0x1f) << 16];
+               memcpy(psxMemWLUT + 0x8000, psxMemWLUT, 0x80 * sizeof(void *));
+               memcpy(psxMemWLUT + 0xa000, psxMemWLUT, 0x80 * sizeof(void *));
+       }
+       psxCpu->Notify(enable ? R3000ACPU_NOTIFY_CACHE_ISOLATED
+                       : R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
+}
 
 u8 psxMemRead8(u32 mem) {
        char *p;
@@ -334,8 +349,10 @@ u32 psxMemRead32(u32 mem) {
                                DebugCheckBP((mem & 0xffffff) | 0x80000000, R4);
                        return SWAPu32(*(u32 *)(p + (mem & 0xffff)));
                } else {
+                       if (mem == 0xfffe0130)
+                               return psxRegs.biuReg;
 #ifdef PSXMEM_LOG
-                       if (writeok) { PSXMEM_LOG("err lw %8.8lx\n", mem); }
+                       PSXMEM_LOG("err lw %8.8lx\n", mem);
 #endif
                        return 0xFFFFFFFF;
                }
@@ -417,44 +434,13 @@ void psxMemWrite32(u32 mem, u32 value) {
                        psxCpu->Clear(mem, 1);
 #endif
                } else {
-                       if (mem != 0xfffe0130) {
-#ifndef DRC_DISABLE
-                               if (!writeok)
-                                       psxCpu->Clear(mem, 1);
-#endif
-
-#ifdef PSXMEM_LOG
-                               if (writeok) { PSXMEM_LOG("err sw %8.8lx\n", mem); }
-#endif
-                       } else {
-                               int i;
-
-                               switch (value) {
-                                       case 0x800: case 0x804:
-                                               if (writeok == 0) break;
-                                               writeok = 0;
-                                               memset(psxMemWLUT + 0x0000, (uintptr_t)INVALID_PTR, 0x80 * sizeof(void *));
-                                               memset(psxMemWLUT + 0x8000, (uintptr_t)INVALID_PTR, 0x80 * sizeof(void *));
-                                               memset(psxMemWLUT + 0xa000, (uintptr_t)INVALID_PTR, 0x80 * sizeof(void *));
-                                               /* Required for icache interpreter otherwise Armored Core won't boot on icache interpreter */
-                                               psxCpu->Notify(R3000ACPU_NOTIFY_CACHE_ISOLATED, NULL);
-                                               break;
-                                       case 0x00: case 0x1e988:
-                                               if (writeok == 1) break;
-                                               writeok = 1;
-                                               for (i = 0; i < 0x80; i++) psxMemWLUT[i + 0x0000] = (void *)&psxM[(i & 0x1f) << 16];
-                                               memcpy(psxMemWLUT + 0x8000, psxMemWLUT, 0x80 * sizeof(void *));
-                                               memcpy(psxMemWLUT + 0xa000, psxMemWLUT, 0x80 * sizeof(void *));
-                                               /* Dynarecs might take this opportunity to flush their code cache */
-                                               psxCpu->Notify(R3000ACPU_NOTIFY_CACHE_UNISOLATED, NULL);
-                                               break;
-                                       default:
+                       if (mem == 0xfffe0130) {
+                               psxRegs.biuReg = value;
+                               return;
+                       }
 #ifdef PSXMEM_LOG
-                                               PSXMEM_LOG("unk %8.8lx = %x\n", mem, value);
+                       PSXMEM_LOG("err sw %8.8lx\n", mem);
 #endif
-                                               break;
-                               }
-                       }
                }
        }
 }

diff --git a/libpcsxcore/psxmem.h b/libpcsxcore/psxmem.h
index 14ff003..129973c 100644 (file)
--- a/libpcsxcore/psxmem.h
+++ b/libpcsxcore/psxmem.h
@@ -127,6 +127,7 @@ extern u8 **psxMemRLUT;
 
 int psxMemInit();
 void psxMemReset();
+void psxMemOnIsolate(int enable);
 void psxMemShutdown();
 
 u8 psxMemRead8 (u32 mem);

diff --git a/libpcsxcore/r3000a.h b/libpcsxcore/r3000a.h
index a052a59..6973afe 100644 (file)
--- a/libpcsxcore/r3000a.h
+++ b/libpcsxcore/r3000a.h
@@ -192,6 +192,8 @@ typedef struct {
        u32 muldivBusyCycle;
        u32 subCycle;           /* interpreter cycle counting */
        u32 subCycleStep;
+       u32 biuReg;
+       u32 reserved[3];
        // warning: changing anything in psxRegisters requires update of all
        // asm in libpcsxcore/new_dynarec/
 } psxRegisters;