drc: fix an old memhandler oversight

accidentally got it right when doing arm64 port though

diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S
index 1d8cefa..6371731 100644 (file)
--- a/libpcsxcore/new_dynarec/linkage_arm.S
+++ b/libpcsxcore/new_dynarec/linkage_arm.S
@@ -661,6 +661,13 @@ FUNCTION(jump_handler_read32):
        pcsx_read_mem ldrcc, 2
 
 
        pcsx_read_mem ldrcc, 2
 
 

+.macro memhandler_post
+       ldr     r0, [fp, #LO_next_interupt]
+       ldr     r2, [fp, #LO_cycle]        @ memhandlers can modify cc, like dma
+       str     r0, [fp, #LO_last_count]
+       sub     r0, r2, r0
+.endm
+

 .macro pcsx_write_mem wrtop tab_shift
        /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
        lsl     r12,r0, #20
 .macro pcsx_write_mem wrtop tab_shift
        /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
        lsl     r12,r0, #20


@@ -668,7 +675,7 @@ FUNCTION(jump_handler_read32):
        ldr     r3, [r3, r12, lsl #2]
        str     r0, [fp, #LO_address]      @ some handlers still need it..
        lsls    r3, #1
        ldr     r3, [r3, r12, lsl #2]
        str     r0, [fp, #LO_address]      @ some handlers still need it..
        lsls    r3, #1

-       mov     r0, r2                                @ cycle return in case of direct store
+       mov     r0, r2                     @ cycle return in case of direct store

 .if \tab_shift == 1
        lsl     r12, #1
        \wrtop  r1, [r3, r12]
 .if \tab_shift == 1
        lsl     r12, #1
        \wrtop  r1, [r3, r12]


@@ -679,14 +686,13 @@ FUNCTION(jump_handler_read32):
        ldr     r12, [fp, #LO_last_count]
        mov     r0, r1
        add     r2, r2, r12
        ldr     r12, [fp, #LO_last_count]
        mov     r0, r1
        add     r2, r2, r12

-       push    {r2, lr}

        str     r2, [fp, #LO_cycle]
        str     r2, [fp, #LO_cycle]

+
+       str     lr, [fp, #LO_saved_lr]

        blx     r3
        blx     r3

+       ldr     lr, [fp, #LO_saved_lr]

 
 

-       ldr     r0, [fp, #LO_next_interupt]
-       pop     {r2, lr}
-       str     r0, [fp, #LO_last_count]
-       sub     r0, r2, r0
+       memhandler_post

        bx      lr
 .endm
 
        bx      lr
 .endm
 


@@ -707,14 +713,13 @@ FUNCTION(jump_handler_write_h):
        str     r0, [fp, #LO_address]      @ some handlers still need it..
        add     r2, r2, r12
        mov     r0, r1
        str     r0, [fp, #LO_address]      @ some handlers still need it..
        add     r2, r2, r12
        mov     r0, r1

-       push    {r2, lr}

        str     r2, [fp, #LO_cycle]
        str     r2, [fp, #LO_cycle]

+
+       str     lr, [fp, #LO_saved_lr]

        blx     r3
        blx     r3

+       ldr     lr, [fp, #LO_saved_lr]

 
 

-       ldr     r0, [fp, #LO_next_interupt]
-       pop     {r2, lr}
-       str     r0, [fp, #LO_last_count]
-       sub     r0, r2, r0
+       memhandler_post

        bx      lr
 
 FUNCTION(jump_handle_swl):
        bx      lr
 
 FUNCTION(jump_handle_swl):

diff --git a/libpcsxcore/new_dynarec/linkage_arm64.S b/libpcsxcore/new_dynarec/linkage_arm64.S
index 7df82b4..7075ebd 100644 (file)
--- a/libpcsxcore/new_dynarec/linkage_arm64.S
+++ b/libpcsxcore/new_dynarec/linkage_arm64.S
@@ -253,10 +253,10 @@ FUNCTION(new_dyna_leave):
 .endm
 
 .macro memhandler_post
 .endm
 
 .macro memhandler_post

-       ldr     w2, [rFP, #LO_next_interupt]
-       ldr     w1, [rFP, #LO_cycle]
-       sub     w0, w1, w2
-       str     w2, [rFP, #LO_last_count]
+       ldr     w0, [rFP, #LO_next_interupt]
+       ldr     w2, [rFP, #LO_cycle]        // memhandlers can modify cc, like dma
+       str     w0, [rFP, #LO_last_count]
+       sub     w0, w2, w0

 .endm
 
 FUNCTION(do_memhandler_pre):
 .endm
 
 FUNCTION(do_memhandler_pre):