asm code updated, Bass Masters fix
[picodrive.git] / Pico / MemoryCmn.c
CommitLineData
6cadc2da 1// common code for Memory.c and cd/Memory.c
2// (c) Copyright 2006-2007, Grazvydas "notaz" Ignotas
fa1e5e29 3
eff55556 4#ifndef UTYPES_DEFINED
5typedef unsigned char u8;
6typedef unsigned short u16;
7typedef unsigned int u32;
8#define UTYPES_DEFINED
9#endif
10
fa1e5e29 11
12#ifndef _ASM_MEMORY_C
13static
14#endif
15u8 z80Read8(u32 a)
16{
17 if(Pico.m.z80Run&1) return 0;
18
19 a&=0x1fff;
20
21 if(!(PicoOpt&4)) {
22 // Z80 disabled, do some faking
23 static u8 zerosent = 0;
24 if(a == Pico.m.z80_lastaddr) { // probably polling something
25 u8 d = Pico.m.z80_fakeval;
26 if((d & 0xf) == 0xf && !zerosent) {
27 d = 0; zerosent = 1;
28 } else {
29 Pico.m.z80_fakeval++;
30 zerosent = 0;
31 }
32 return d;
33 } else {
34 Pico.m.z80_fakeval = 0;
35 }
36 }
37
38 Pico.m.z80_lastaddr = (u16) a;
39 return Pico.zram[a];
40}
41
fa1e5e29 42#ifndef _ASM_MEMORY_C
43static
44#endif
e5503e2f 45u32 z80ReadBusReq(void)
fa1e5e29 46{
e5503e2f 47 u32 d=Pico.m.z80Run&1;
f58f05d2 48 if (!d && Pico.m.scanline != -1) {
e5503e2f 49 // needed by buggy Terminator (Sega CD)
50 int stop_before = SekCyclesDone() - z80stopCycle;
69996cb7 51 //elprintf(EL_BUSREQ, "get_zrun: stop before: %i", stop_before);
52 // note: if we use 20 or more here, Barkley Shut Up and Jam! will purposedly crash itself.
5f20bb80 53 // but CD Terminator needs at least 32, so it only works because next frame cycle wrap.
69996cb7 54 if (stop_before > 0 && stop_before < 20) // Gens uses 16 here
e5503e2f 55 d = 1; // bus not yet available
56 }
57 // |=0x80 for Shadow of the Beast & Super Offroad
69996cb7 58 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d|0x80, SekCyclesDone(), SekPc);
e5503e2f 59 return d|0x80;
60}
fa1e5e29 61
e5503e2f 62#ifndef _ASM_MEMORY_C
63static
64#endif
65void z80WriteBusReq(u32 d)
66{
67 d&=1; d^=1;
f58f05d2 68 {
b542be46 69 if (!d)
70 {
f58f05d2 71 // this is for a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
72 if (Pico.m.z80Run) {
73 int lineCycles;
74 z80stopCycle = SekCyclesDone();
9a8ffeee 75 if ((Pico.m.z80Run&2) && Pico.m.scanline != -1)
f58f05d2 76 lineCycles=(488-SekCyclesLeft)&0x1ff;
77 else lineCycles=z80stopCycle-z80startCycle; // z80 was started at current line
9a8ffeee 78 if (lineCycles > 0) { // && lineCycles <= 488) {
69996cb7 79 //dprintf("zrun: %i/%i cycles", lineCycles, (lineCycles>>1)-(lineCycles>>5));
f58f05d2 80 lineCycles=(lineCycles>>1)-(lineCycles>>5);
b542be46 81 z80_run_nr(lineCycles);
f58f05d2 82 }
e5503e2f 83 }
f58f05d2 84 } else {
69996cb7 85 if (!Pico.m.z80Run)
86 z80startCycle = SekCyclesDone();
87 else
88 d|=Pico.m.z80Run;
fa1e5e29 89 }
fa1e5e29 90 }
69996cb7 91 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
e5503e2f 92 Pico.m.z80Run=(u8)d;
93}
94
95#ifndef _ASM_MEMORY_C
96static
97#endif
98u32 OtherRead16(u32 a, int realsize)
99{
100 u32 d=0;
fa1e5e29 101
102 if ((a&0xffffe0)==0xa10000) { // I/O ports
103 a=(a>>1)&0xf;
104 switch(a) {
105 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
e5503e2f 106 case 1: d=PadRead(0); break;
107 case 2: d=PadRead(1); break;
fa1e5e29 108 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
109 }
110 d|=d<<8;
111 goto end;
112 }
113
f58f05d2 114 // rotate fakes next fetched instruction for Time Killers
fa1e5e29 115 if (a==0xa11100) { // z80 busreq
e5503e2f 116 d=(z80ReadBusReq()<<8)|Pico.m.rotate++;
fa1e5e29 117 goto end;
118 }
119
e5503e2f 120 if ((a&0xff0000)==0xa00000) {
121 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
122 if ((a&0x6000)==0x4000) { // 0x4000-0x5fff, Fudge if disabled
123 if(PicoOpt&1) d=YM2612Read();
124 else d=Pico.m.rotate++&3;
69996cb7 125 elprintf(EL_YM2612R, "read ym2612: %02x", d);
e5503e2f 126 goto end;
127 }
128 d=0xffff;
129 goto end;
130 }
131
f53f286a 132 d = PicoRead16Hook(a, realsize);
fa1e5e29 133
134end:
135 return d;
136}
137
e5503e2f 138static void IoWrite8(u32 a, u32 d)
139{
140 a=(a>>1)&0xf;
141 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
142 if(PicoOpt&0x20) {
143 if(a==1) {
144 Pico.m.padDelay[0] = 0;
145 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
146 }
147 else if(a==2) {
148 Pico.m.padDelay[1] = 0;
149 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
150 }
151 }
152 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
153}
fa1e5e29 154
4ff2d527 155#ifndef _ASM_CD_MEMORY_C
156static
157#endif
e5503e2f 158void OtherWrite8(u32 a,u32 d)
fa1e5e29 159{
3ec29f01 160#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)
fa1e5e29 161 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
162 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
fa283c9a 163 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d)&1; return; } // FM Sound
e5503e2f 164 if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
165#endif
166 if (a==0xa11100) { z80WriteBusReq(d); return; }
fa1e5e29 167 if (a==0xa11200) {
5f20bb80 168 elprintf(EL_BUSREQ, "write z80Reset: %02x", d);
fa1e5e29 169 if(!(d&1)) z80_reset();
170 return;
171 }
3ec29f01 172#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)
fa1e5e29 173 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
174 {
175 Pico.m.z80_bank68k>>=1;
176 Pico.m.z80_bank68k|=(d&1)<<8;
177 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
178 return;
179 }
e5503e2f 180#endif
fa1e5e29 181 if ((a&0xe700e0)==0xc00000) {
f58f05d2 182 d&=0xff;
fa1e5e29 183 PicoVideoWrite(a,(u16)(d|(d<<8))); // Byte access gets mirrored
184 return;
185 }
186
f53f286a 187 PicoWrite8Hook(a, d, 8);
fa1e5e29 188}
189
190
4ff2d527 191#ifndef _ASM_CD_MEMORY_C
192static
193#endif
194void OtherWrite16(u32 a,u32 d)
fa1e5e29 195{
e5503e2f 196 if (a==0xa11100) { z80WriteBusReq(d>>8); return; }
ca61ee42 197 if (a==0xa11200) { elprintf(EL_BUSREQ, "write z80reset: %04x", d); if(!(d&0x100)) z80_reset(); return; }
e5503e2f 198 if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
fa1e5e29 199 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
e5503e2f 200 if ((a&0xe700f8)==0xc00010||(a&0xff7ff8)==0xa07f10) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
fa283c9a 201 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d)&1; return; } // FM Sound (??)
e5503e2f 202 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
203 {
204 Pico.m.z80_bank68k>>=1;
205 Pico.m.z80_bank68k|=(d&1)<<8;
206 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
fa1e5e29 207 return;
208 }
fa1e5e29 209
69996cb7 210#ifndef _CD_MEMORY_C
7969166e 211 if (a >= SRam.start && a <= SRam.end) {
1dceadae 212 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d, SekPc);
9dc09829 213 if ((Pico.m.sram_reg&0x16)==0x10) { // detected, not EEPROM, write not disabled
7969166e 214 u8 *pm=(u8 *)(SRam.data-SRam.start+a);
215 *pm++=d>>8;
216 *pm++=d;
217 SRam.changed = 1;
218 }
219 else
1dceadae 220 SRAMWrite(a, d);
7969166e 221 return;
222 }
69996cb7 223#endif
f53f286a 224
f8ef8ff7 225 PicoWrite16Hook(a, d, 16);
fa1e5e29 226}
227