[picodrive.git] / Pico / carthw / svp / ssp16.h


// register names
enum {
	SSP_GR0, SSP_X,     SSP_Y,   SSP_A,
	SSP_ST,  SSP_STACK, SSP_PC,  SSP_P,
	SSP_PM0, SSP_PM1,   SSP_PM2, SSP_XST,
	SSP_PM4, SSP_gr13,  SSP_PMC, SSP_AL
};

typedef union
{
	unsigned int v;
	struct {
		unsigned short l;
		unsigned short h;
	};
} ssp_reg_t;

typedef struct
{
	union {
		unsigned short RAM[256*2];	// 2 internal RAM banks
		struct {
			unsigned short RAM0[256];
			unsigned short RAM1[256];
		};
	};
	ssp_reg_t gr[16];	// general registers
	union {
		unsigned char r[8];	// BANK pointers
		struct {
			unsigned char r0[4];
			unsigned char r1[4];
		};
	};
	unsigned short stack[6];
	unsigned int pmac_read[6];	// read modes/addrs for PM0-PM5
	unsigned int pmac_write[6];	// write ...
	//
	#define SSP_PMC_HAVE_ADDR	0x0001	// address written to PMAC, waiting for mode
	#define SSP_PMC_SET		0x0002	// PMAC is set
	#define SSP_WAIT_PM0		0x2000	// bit1 in PM0
	#define SSP_WAIT_30FE06		0x4000	// ssp tight loops on 30FE08 to become non-zero
	#define SSP_WAIT_30FE08		0x8000	// same for 30FE06
	#define SSP_WAIT_MASK		0xe000
	unsigned int emu_status;
	unsigned int pad[30];
} ssp1601_t;


void ssp1601_reset(ssp1601_t *ssp);
void ssp1601_run(int cycles);
Commit	Line	Data
f8ef8ff7	1
	2	// register names
	3	enum {
	4	SSP_GR0, SSP_X, SSP_Y, SSP_A,
	5	SSP_ST, SSP_STACK, SSP_PC, SSP_P,
	6	SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
	7	SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
	8	};
	9
	10	typedef union
	11	{
	12	unsigned int v;
	13	struct {
	14	unsigned short l;
	15	unsigned short h;
	16	};
	17	} ssp_reg_t;
	18
	19	typedef struct
	20	{
	21	union {
	22	unsigned short RAM[256*2]; // 2 internal RAM banks
	23	struct {
	24	unsigned short RAM0[256];
	25	unsigned short RAM1[256];
	26	};
	27	};
	28	ssp_reg_t gr[16]; // general registers
	29	union {
	30	unsigned char r[8]; // BANK pointers
	31	struct {
	32	unsigned char r0[4];
	33	unsigned char r1[4];
	34	};
	35	};
	36	unsigned short stack[6];
017512f2	37	unsigned int pmac_read[6]; // read modes/addrs for PM0-PM5
017512f2	38	unsigned int pmac_write[6]; // write ...
f8ef8ff7	39	//
30752975	40	#define SSP_PMC_HAVE_ADDR 0x0001 // address written to PMAC, waiting for mode
30752975	41	#define SSP_PMC_SET 0x0002 // PMAC is set
d26dc685	42	#define SSP_WAIT_PM0 0x2000 // bit1 in PM0
	43	#define SSP_WAIT_30FE06 0x4000 // ssp tight loops on 30FE08 to become non-zero
	44	#define SSP_WAIT_30FE08 0x8000 // same for 30FE06
	45	#define SSP_WAIT_MASK 0xe000
f8ef8ff7	46	unsigned int emu_status;
017512f2	47	unsigned int pad[30];
f8ef8ff7	48	} ssp1601_t;
	49
	50
	51	void ssp1601_reset(ssp1601_t *ssp);
017512f2	52	void ssp1601_run(int cycles);
f8ef8ff7	53